5 files changed, 27 insertions, 148 deletions

diff --git a/arch/mips/au1000/common/dbdma.c b/arch/mips/au1000/common/dbdma.c
index c4fae8ff4671..626de44bd888 100644
--- a/arch/mips/au1000/common/dbdma.c
+++ b/arch/mips/au1000/common/dbdma.c
@@ -849,7 +849,7 @@ au1xxx_dbdma_chan_free(u32 chanid)
 EXPORT_SYMBOL(au1xxx_dbdma_chan_free);
 
 static irqreturn_t
-dbdma_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+dbdma_interrupt(int irq, void *dev_id)
 {
         u32 intstat;
         u32 chan_index;
diff --git a/arch/mips/au1000/common/irq.c b/arch/mips/au1000/common/irq.c
index 2abe132bb07d..9cf7b6715836 100644
--- a/arch/mips/au1000/common/irq.c
+++ b/arch/mips/au1000/common/irq.c
@@ -70,7 +70,6 @@ extern irq_cpustat_t irq_stat [NR_CPUS];
 extern void mips_timer_interrupt(void);
 
 static void setup_local_irq(unsigned int irq, int type, int int_req);
-static unsigned int startup_irq(unsigned int irq);
 static void end_irq(unsigned int irq_nr);
 static inline void mask_and_ack_level_irq(unsigned int irq_nr);
 static inline void mask_and_ack_rise_edge_irq(unsigned int irq_nr);
@@ -84,20 +83,6 @@ void	(*board_init_irq)(void);
 static DEFINE_SPINLOCK(irq_lock);
 
 
-static unsigned int startup_irq(unsigned int irq_nr)
-{
-        local_enable_irq(irq_nr);
-        return 0;
-}
-
-
-static void shutdown_irq(unsigned int irq_nr)
-{
-        local_disable_irq(irq_nr);
-        return;
-}
-
-
 inline void local_enable_irq(unsigned int irq_nr)
 {
         if (irq_nr > AU1000_LAST_INTC0_INT) {
@@ -249,41 +234,37 @@ void restore_local_and_enable(int controller, unsigned long mask)
 
 static struct irq_chip rise_edge_irq_type = {
         .typename = "Au1000 Rise Edge",
-        .startup = startup_irq,
-        .shutdown = shutdown_irq,
-        .enable = local_enable_irq,
-        .disable = local_disable_irq,
         .ack = mask_and_ack_rise_edge_irq,
+        .mask = local_disable_irq,
+        .mask_ack = mask_and_ack_rise_edge_irq,
+        .unmask = local_enable_irq,
         .end = end_irq,
 };
 
 static struct irq_chip fall_edge_irq_type = {
         .typename = "Au1000 Fall Edge",
-        .startup = startup_irq,
-        .shutdown = shutdown_irq,
-        .enable = local_enable_irq,
-        .disable = local_disable_irq,
         .ack = mask_and_ack_fall_edge_irq,
+        .mask = local_disable_irq,
+        .mask_ack = mask_and_ack_fall_edge_irq,
+        .unmask = local_enable_irq,
         .end = end_irq,
 };
 
 static struct irq_chip either_edge_irq_type = {
         .typename = "Au1000 Rise or Fall Edge",
-        .startup = startup_irq,
-        .shutdown = shutdown_irq,
-        .enable = local_enable_irq,
-        .disable = local_disable_irq,
         .ack = mask_and_ack_either_edge_irq,
+        .mask = local_disable_irq,
+        .mask_ack = mask_and_ack_either_edge_irq,
+        .unmask = local_enable_irq,
         .end = end_irq,
 };
 
 static struct irq_chip level_irq_type = {
         .typename = "Au1000 Level",
-        .startup = startup_irq,
-        .shutdown = shutdown_irq,
-        .enable = local_enable_irq,
-        .disable = local_disable_irq,
         .ack = mask_and_ack_level_irq,
+        .mask = local_disable_irq,
+        .mask_ack = mask_and_ack_level_irq,
+        .unmask = local_enable_irq,
         .end = end_irq,
 };
 
@@ -328,31 +309,31 @@ static void setup_local_irq(unsigned int irq_nr, int type, int int_req)
                                 au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
                                 au_writel(1<<(irq_nr-32), IC1_CFG1CLR);
                                 au_writel(1<<(irq_nr-32), IC1_CFG0SET);
-                                irq_desc[irq_nr].chip = &rise_edge_irq_type;
+                                set_irq_chip(irq_nr, &rise_edge_irq_type);
                                 break;
                         case INTC_INT_FALL_EDGE: /* 0:1:0 */
                                 au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
                                 au_writel(1<<(irq_nr-32), IC1_CFG1SET);
                                 au_writel(1<<(irq_nr-32), IC1_CFG0CLR);
-                                irq_desc[irq_nr].chip = &fall_edge_irq_type;
+                                set_irq_chip(irq_nr, &fall_edge_irq_type);
                                 break;
                         case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */
                                 au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
                                 au_writel(1<<(irq_nr-32), IC1_CFG1SET);
                                 au_writel(1<<(irq_nr-32), IC1_CFG0SET);
-                                irq_desc[irq_nr].chip = &either_edge_irq_type;
+                                set_irq_chip(irq_nr, &either_edge_irq_type);
                                 break;
                         case INTC_INT_HIGH_LEVEL: /* 1:0:1 */
                                 au_writel(1<<(irq_nr-32), IC1_CFG2SET);
                                 au_writel(1<<(irq_nr-32), IC1_CFG1CLR);
                                 au_writel(1<<(irq_nr-32), IC1_CFG0SET);
-                                irq_desc[irq_nr].chip = &level_irq_type;
+                                set_irq_chip(irq_nr, &level_irq_type);
                                 break;
                         case INTC_INT_LOW_LEVEL: /* 1:1:0 */
                                 au_writel(1<<(irq_nr-32), IC1_CFG2SET);
                                 au_writel(1<<(irq_nr-32), IC1_CFG1SET);
                                 au_writel(1<<(irq_nr-32), IC1_CFG0CLR);
-                                irq_desc[irq_nr].chip = &level_irq_type;
+                                set_irq_chip(irq_nr, &level_irq_type);
                                 break;
                         case INTC_INT_DISABLED: /* 0:0:0 */
                                 au_writel(1<<(irq_nr-32), IC1_CFG0CLR);
@@ -380,31 +361,31 @@ static void setup_local_irq(unsigned int irq_nr, int type, int int_req)
                                 au_writel(1<<irq_nr, IC0_CFG2CLR);
                                 au_writel(1<<irq_nr, IC0_CFG1CLR);
                                 au_writel(1<<irq_nr, IC0_CFG0SET);
-                                irq_desc[irq_nr].chip = &rise_edge_irq_type;
+                                set_irq_chip(irq_nr, &rise_edge_irq_type);
                                 break;
                         case INTC_INT_FALL_EDGE: /* 0:1:0 */
                                 au_writel(1<<irq_nr, IC0_CFG2CLR);
                                 au_writel(1<<irq_nr, IC0_CFG1SET);
                                 au_writel(1<<irq_nr, IC0_CFG0CLR);
-                                irq_desc[irq_nr].chip = &fall_edge_irq_type;
+                                set_irq_chip(irq_nr, &fall_edge_irq_type);
                                 break;
                         case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */
                                 au_writel(1<<irq_nr, IC0_CFG2CLR);
                                 au_writel(1<<irq_nr, IC0_CFG1SET);
                                 au_writel(1<<irq_nr, IC0_CFG0SET);
-                                irq_desc[irq_nr].chip = &either_edge_irq_type;
+                                set_irq_chip(irq_nr, &either_edge_irq_type);
                                 break;
                         case INTC_INT_HIGH_LEVEL: /* 1:0:1 */
                                 au_writel(1<<irq_nr, IC0_CFG2SET);
                                 au_writel(1<<irq_nr, IC0_CFG1CLR);
                                 au_writel(1<<irq_nr, IC0_CFG0SET);
-                                irq_desc[irq_nr].chip = &level_irq_type;
+                                set_irq_chip(irq_nr, &level_irq_type);
                                 break;
                         case INTC_INT_LOW_LEVEL: /* 1:1:0 */
                                 au_writel(1<<irq_nr, IC0_CFG2SET);
                                 au_writel(1<<irq_nr, IC0_CFG1SET);
                                 au_writel(1<<irq_nr, IC0_CFG0CLR);
-                                irq_desc[irq_nr].chip = &level_irq_type;
+                                set_irq_chip(irq_nr, &level_irq_type);
                                 break;
                         case INTC_INT_DISABLED: /* 0:0:0 */
                                 au_writel(1<<irq_nr, IC0_CFG0CLR);
diff --git a/arch/mips/au1000/common/prom.c b/arch/mips/au1000/common/prom.c
index b4b010a2fe36..6fce60af005d 100644
--- a/arch/mips/au1000/common/prom.c
+++ b/arch/mips/au1000/common/prom.c
@@ -47,7 +47,7 @@ extern int prom_argc;
 extern char **prom_argv, **prom_envp;
 
 
-char * prom_getcmdline(void)
+char * __init_or_module prom_getcmdline(void)
 {
         return &(arcs_cmdline[0]);
 }
diff --git a/arch/mips/au1000/common/setup.c b/arch/mips/au1000/common/setup.c
index 377ae0d8ff00..919172db560c 100644
--- a/arch/mips/au1000/common/setup.c
+++ b/arch/mips/au1000/common/setup.c
@@ -43,7 +43,7 @@
 #include <asm/mach-au1x00/au1000.h>
 #include <asm/time.h>
 
-extern char * __init prom_getcmdline(void);
+extern char * prom_getcmdline(void);
 extern void __init board_setup(void);
 extern void au1000_restart(char *);
 extern void au1000_halt(void);
diff --git a/arch/mips/au1000/common/time.c b/arch/mips/au1000/common/time.c
index 94f09194d63d..fa1c62f05515 100644
--- a/arch/mips/au1000/common/time.c
+++ b/arch/mips/au1000/common/time.c
@@ -53,9 +53,6 @@ static unsigned long r4k_cur;    /* What counter should be at next timer irq */
 int     no_au1xxx_32khz;
 extern int allow_au1k_wait; /* default off for CP0 Counter */
 
-/* Cycle counter value at the previous timer interrupt.. */
-static unsigned int timerhi = 0, timerlo = 0;
-
 #ifdef CONFIG_PM
 #if HZ < 100 || HZ > 1000
 #error "unsupported HZ value! Must be in [100,1000]"
@@ -82,7 +79,6 @@ unsigned long wtimer;
 void mips_timer_interrupt(void)
 {
         int irq = 63;
-        unsigned long count;
 
         irq_enter();
         kstat_this_cpu.irqs[irq]++;
@@ -91,10 +87,6 @@ void mips_timer_interrupt(void)
                 goto null;
 
         do {
-                count = read_c0_count();
-                timerhi += (count < timerlo);   /* Wrap around */
-                timerlo = count;
-
                 kstat_this_cpu.irqs[irq]++;
                 do_timer(1);
 #ifndef CONFIG_SMP
@@ -231,7 +223,6 @@ wakeup_counter0_set(int ticks)
  */
 unsigned long cal_r4koff(void)
 {
-        unsigned long count;
         unsigned long cpu_speed;
         unsigned long flags;
         unsigned long counter;
@@ -258,7 +249,7 @@ unsigned long cal_r4koff(void)
 
 #if defined(CONFIG_AU1000_USE32K)
                 {
-                        unsigned long start, end;
+                        unsigned long start, end, count;
 
                         start = au_readl(SYS_RTCREAD);
                         start += 2;
@@ -282,7 +273,6 @@ unsigned long cal_r4koff(void)
 #else
                 cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) *
                         AU1000_SRC_CLK;
-                count = cpu_speed / 2;
 #endif
         }
         else {
@@ -291,98 +281,15 @@ unsigned long cal_r4koff(void)
                  * NOTE: some old silicon doesn't allow reading the PLL.
                  */
                 cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) * AU1000_SRC_CLK;
-                count = cpu_speed / 2;
                 no_au1xxx_32khz = 1;
         }
-        mips_hpt_frequency = count;
+        mips_hpt_frequency = cpu_speed;
         // Equation: Baudrate = CPU / (SD * 2 * CLKDIV * 16)
         set_au1x00_uart_baud_base(cpu_speed / (2 * ((int)(au_readl(SYS_POWERCTRL)&0x03) + 2) * 16));
         spin_unlock_irqrestore(&time_lock, flags);
         return (cpu_speed / HZ);
 }
 
-/* This is for machines which generate the exact clock. */
-#define USECS_PER_JIFFY (1000000/HZ)
-#define USECS_PER_JIFFY_FRAC (0x100000000LL*1000000/HZ&0xffffffff)
-
-static unsigned long
-div64_32(unsigned long v1, unsigned long v2, unsigned long v3)
-{
-        unsigned long r0;
-        do_div64_32(r0, v1, v2, v3);
-        return r0;
-}
-
-static unsigned long do_fast_cp0_gettimeoffset(void)
-{
-        u32 count;
-        unsigned long res, tmp;
-        unsigned long r0;
-
-        /* Last jiffy when do_fast_gettimeoffset() was called. */
-        static unsigned long last_jiffies=0;
-        unsigned long quotient;
-
-        /*
-         * Cached "1/(clocks per usec)*2^32" value.
-         * It has to be recalculated once each jiffy.
-         */
-        static unsigned long cached_quotient=0;
-
-        tmp = jiffies;
-
-        quotient = cached_quotient;
-
-        if (tmp && last_jiffies != tmp) {
-                last_jiffies = tmp;
-                if (last_jiffies != 0) {
-                        r0 = div64_32(timerhi, timerlo, tmp);
-                        quotient = div64_32(USECS_PER_JIFFY, USECS_PER_JIFFY_FRAC, r0);
-                        cached_quotient = quotient;
-                }
-        }
-
-        /* Get last timer tick in absolute kernel time */
-        count = read_c0_count();
-
-        /* .. relative to previous jiffy (32 bits is enough) */
-        count -= timerlo;
-
-        __asm__("multu\t%1,%2\n\t"
-                "mfhi\t%0"
-                : "=r" (res)
-                : "r" (count), "r" (quotient)
-                : "hi", "lo", GCC_REG_ACCUM);
-
-        /*
-         * Due to possible jiffies inconsistencies, we need to check
-         * the result so that we'll get a timer that is monotonic.
-         */
-        if (res >= USECS_PER_JIFFY)
-                res = USECS_PER_JIFFY-1;
-
-        return res;
-}
-
-#ifdef CONFIG_PM
-static unsigned long do_fast_pm_gettimeoffset(void)
-{
-        unsigned long pc0;
-        unsigned long offset;
-
-        pc0 = au_readl(SYS_TOYREAD);
-        au_sync();
-        offset = pc0 - last_pc0;
-        if (offset > 2*MATCH20_INC) {
-                printk("huge offset %x, last_pc0 %x last_match20 %x pc0 %x\n",
-                                (unsigned)offset, (unsigned)last_pc0,
-                                (unsigned)last_match20, (unsigned)pc0);
-        }
-        offset = (unsigned long)((offset * 305) / 10);
-        return offset;
-}
-#endif
-
 void __init plat_timer_setup(struct irqaction *irq)
 {
         unsigned int est_freq;
@@ -420,7 +327,6 @@ void __init plat_timer_setup(struct irqaction *irq)
                 unsigned int c0_status;
 
                 printk("WARNING: no 32KHz clock found.\n");
-                do_gettimeoffset = do_fast_cp0_gettimeoffset;
 
                 /* Ensure we get CPO_COUNTER interrupts.
                 */
@@ -445,19 +351,11 @@ void __init plat_timer_setup(struct irqaction *irq)
                 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20);
                 startup_match20_interrupt(counter0_irq);
 
-                do_gettimeoffset = do_fast_pm_gettimeoffset;
-
                 /* We can use the real 'wait' instruction.
                 */
                 allow_au1k_wait = 1;
         }
 
-#else
-        /* We have to do this here instead of in timer_init because
-         * the generic code in arch/mips/kernel/time.c will write
-         * over our function pointer.
-         */
-        do_gettimeoffset = do_fast_cp0_gettimeoffset;
 #endif
 }