diff options
Diffstat (limited to 'arch/mips/au1000/common/time.c')
-rw-r--r-- | arch/mips/au1000/common/time.c | 29 |
1 files changed, 0 insertions, 29 deletions
diff --git a/arch/mips/au1000/common/time.c b/arch/mips/au1000/common/time.c index fa1c62f05515..8fc29982d700 100644 --- a/arch/mips/au1000/common/time.c +++ b/arch/mips/au1000/common/time.c | |||
@@ -203,11 +203,7 @@ wakeup_counter0_set(int ticks) | |||
203 | /* I haven't found anyone that doesn't use a 12 MHz source clock, | 203 | /* I haven't found anyone that doesn't use a 12 MHz source clock, |
204 | * but just in case..... | 204 | * but just in case..... |
205 | */ | 205 | */ |
206 | #ifdef CONFIG_AU1000_SRC_CLK | ||
207 | #define AU1000_SRC_CLK CONFIG_AU1000_SRC_CLK | ||
208 | #else | ||
209 | #define AU1000_SRC_CLK 12000000 | 206 | #define AU1000_SRC_CLK 12000000 |
210 | #endif | ||
211 | 207 | ||
212 | /* | 208 | /* |
213 | * We read the real processor speed from the PLL. This is important | 209 | * We read the real processor speed from the PLL. This is important |
@@ -247,33 +243,8 @@ unsigned long cal_r4koff(void) | |||
247 | au_writel (0, SYS_TOYWRITE); | 243 | au_writel (0, SYS_TOYWRITE); |
248 | while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S); | 244 | while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S); |
249 | 245 | ||
250 | #if defined(CONFIG_AU1000_USE32K) | ||
251 | { | ||
252 | unsigned long start, end, count; | ||
253 | |||
254 | start = au_readl(SYS_RTCREAD); | ||
255 | start += 2; | ||
256 | /* wait for the beginning of a new tick | ||
257 | */ | ||
258 | while (au_readl(SYS_RTCREAD) < start); | ||
259 | |||
260 | /* Start r4k counter. | ||
261 | */ | ||
262 | write_c0_count(0); | ||
263 | |||
264 | /* Wait 0.5 seconds. | ||
265 | */ | ||
266 | end = start + (32768 / trim_divide)/2; | ||
267 | |||
268 | while (end > au_readl(SYS_RTCREAD)); | ||
269 | |||
270 | count = read_c0_count(); | ||
271 | cpu_speed = count * 2; | ||
272 | } | ||
273 | #else | ||
274 | cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) * | 246 | cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) * |
275 | AU1000_SRC_CLK; | 247 | AU1000_SRC_CLK; |
276 | #endif | ||
277 | } | 248 | } |
278 | else { | 249 | else { |
279 | /* The 32KHz oscillator isn't running, so assume there | 250 | /* The 32KHz oscillator isn't running, so assume there |