aboutsummaryrefslogtreecommitdiffstats
path: root/arch/mips/au1000/common/setup.c
diff options
context:
space:
mode:
Diffstat (limited to 'arch/mips/au1000/common/setup.c')
-rw-r--r--arch/mips/au1000/common/setup.c60
1 files changed, 28 insertions, 32 deletions
diff --git a/arch/mips/au1000/common/setup.c b/arch/mips/au1000/common/setup.c
index 0e86f7a6b4a7..1ac6b06f42a3 100644
--- a/arch/mips/au1000/common/setup.c
+++ b/arch/mips/au1000/common/setup.c
@@ -1,7 +1,6 @@
1/* 1/*
2 * Copyright 2000 MontaVista Software Inc. 2 * Copyright 2000, 2007-2008 MontaVista Software Inc.
3 * Author: MontaVista Software, Inc. 3 * Author: MontaVista Software, Inc. <source@mvista.com
4 * ppopov@mvista.com or source@mvista.com
5 * 4 *
6 * Updates to 2.6, Pete Popov, Embedded Alley Solutions, Inc. 5 * Updates to 2.6, Pete Popov, Embedded Alley Solutions, Inc.
7 * 6 *
@@ -48,7 +47,7 @@ void __init plat_mem_setup(void)
48{ 47{
49 struct cpu_spec *sp; 48 struct cpu_spec *sp;
50 char *argptr; 49 char *argptr;
51 unsigned long prid, cpufreq, bclk = 1; 50 unsigned long prid, cpufreq, bclk;
52 51
53 set_cpuspec(); 52 set_cpuspec();
54 sp = cur_cpu_spec[0]; 53 sp = cur_cpu_spec[0];
@@ -66,42 +65,39 @@ void __init plat_mem_setup(void)
66 cpufreq = (au_readl(SYS_CPUPLL) & 0x3F) * 12; 65 cpufreq = (au_readl(SYS_CPUPLL) & 0x3F) * 12;
67 printk(KERN_INFO "(PRID %08lx) @ %ld MHz\n", prid, cpufreq); 66 printk(KERN_INFO "(PRID %08lx) @ %ld MHz\n", prid, cpufreq);
68 67
69 bclk = sp->cpu_bclk; 68 if (sp->cpu_bclk) {
70 if (bclk)
71 {
72 /* Enable BCLK switching */ 69 /* Enable BCLK switching */
73 bclk = au_readl(0xB190003C); 70 bclk = au_readl(SYS_POWERCTRL);
74 au_writel(bclk | 0x60, 0xB190003C); 71 au_writel(bclk | 0x60, SYS_POWERCTRL);
75 printk("BCLK switching enabled!\n"); 72 printk(KERN_INFO "BCLK switching enabled!\n");
76 } 73 }
77 74
78 if (sp->cpu_od) { 75 if (sp->cpu_od)
79 /* Various early Au1000 Errata corrected by this */ 76 /* Various early Au1xx0 errata corrected by this */
80 set_c0_config(1<<19); /* Set Config[OD] */ 77 set_c0_config(1 << 19); /* Set Config[OD] */
81 } 78 else
82 else {
83 /* Clear to obtain best system bus performance */ 79 /* Clear to obtain best system bus performance */
84 clear_c0_config(1<<19); /* Clear Config[OD] */ 80 clear_c0_config(1 << 19); /* Clear Config[OD] */
85 }
86 81
87 argptr = prom_getcmdline(); 82 argptr = prom_getcmdline();
88 83
89#ifdef CONFIG_SERIAL_8250_CONSOLE 84#ifdef CONFIG_SERIAL_8250_CONSOLE
90 if ((argptr = strstr(argptr, "console=")) == NULL) { 85 argptr = strstr(argptr, "console=");
86 if (argptr == NULL) {
91 argptr = prom_getcmdline(); 87 argptr = prom_getcmdline();
92 strcat(argptr, " console=ttyS0,115200"); 88 strcat(argptr, " console=ttyS0,115200");
93 } 89 }
94#endif 90#endif
95 91
96#ifdef CONFIG_FB_AU1100 92#ifdef CONFIG_FB_AU1100
97 if ((argptr = strstr(argptr, "video=")) == NULL) { 93 argptr = strstr(argptr, "video=");
98 argptr = prom_getcmdline(); 94 if (argptr == NULL) {
99 /* default panel */ 95 argptr = prom_getcmdline();
100 /*strcat(argptr, " video=au1100fb:panel:Sharp_320x240_16");*/ 96 /* default panel */
101 } 97 /*strcat(argptr, " video=au1100fb:panel:Sharp_320x240_16");*/
98 }
102#endif 99#endif
103 100
104
105#if defined(CONFIG_SOUND_AU1X00) && !defined(CONFIG_SOC_AU1000) 101#if defined(CONFIG_SOUND_AU1X00) && !defined(CONFIG_SOC_AU1000)
106 /* au1000 does not support vra, au1500 and au1100 do */ 102 /* au1000 does not support vra, au1500 and au1100 do */
107 strcat(argptr, " au1000_audio=vra"); 103 strcat(argptr, " au1000_audio=vra");
@@ -129,7 +125,7 @@ void __init plat_mem_setup(void)
129/* This routine should be valid for all Au1x based boards */ 125/* This routine should be valid for all Au1x based boards */
130phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size) 126phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size)
131{ 127{
132 /* Don't fixup 36 bit addresses */ 128 /* Don't fixup 36-bit addresses */
133 if ((phys_addr >> 32) != 0) 129 if ((phys_addr >> 32) != 0)
134 return phys_addr; 130 return phys_addr;
135 131
@@ -145,17 +141,17 @@ phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size)
145 } 141 }
146#endif 142#endif
147 143
148 /* All Au1x SOCs have a pcmcia controller */ 144 /*
149 /* We setup our 32 bit pseudo addresses to be equal to the 145 * All Au1xx0 SOCs have a PCMCIA controller.
150 * 36 bit addr >> 4, to make it easier to check the address 146 * We setup our 32-bit pseudo addresses to be equal to the
147 * 36-bit addr >> 4, to make it easier to check the address
151 * and fix it. 148 * and fix it.
152 * The Au1x socket 0 phys attribute address is 0xF 4000 0000. 149 * The PCMCIA socket 0 physical attribute address is 0xF 4000 0000.
153 * The pseudo address we use is 0xF400 0000. Any address over 150 * The pseudo address we use is 0xF400 0000. Any address over
154 * 0xF400 0000 is a pcmcia pseudo address. 151 * 0xF400 0000 is a PCMCIA pseudo address.
155 */ 152 */
156 if ((phys_addr >= 0xF4000000) && (phys_addr < 0xFFFFFFFF)) { 153 if ((phys_addr >= 0xF4000000) && (phys_addr < 0xFFFFFFFF))
157 return (phys_t)(phys_addr << 4); 154 return (phys_t)(phys_addr << 4);
158 }
159 155
160 /* default nop */ 156 /* default nop */
161 return phys_addr; 157 return phys_addr;