diff options
Diffstat (limited to 'arch/mips/au1000/common/int-handler.S')
| -rw-r--r-- | arch/mips/au1000/common/int-handler.S | 68 |
1 files changed, 0 insertions, 68 deletions
diff --git a/arch/mips/au1000/common/int-handler.S b/arch/mips/au1000/common/int-handler.S deleted file mode 100644 index 1c4ca883321e..000000000000 --- a/arch/mips/au1000/common/int-handler.S +++ /dev/null | |||
| @@ -1,68 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2001 MontaVista Software Inc. | ||
| 3 | * Author: ppopov@mvista.com | ||
| 4 | * | ||
| 5 | * Interrupt dispatcher for Au1000 boards. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify it | ||
| 8 | * under the terms of the GNU General Public License as published by the | ||
| 9 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 10 | * option) any later version. | ||
| 11 | */ | ||
| 12 | #include <asm/asm.h> | ||
| 13 | #include <asm/mipsregs.h> | ||
| 14 | #include <asm/addrspace.h> | ||
| 15 | #include <asm/regdef.h> | ||
| 16 | #include <asm/stackframe.h> | ||
| 17 | |||
| 18 | .text | ||
| 19 | .set macro | ||
| 20 | .set noat | ||
| 21 | .align 5 | ||
| 22 | |||
| 23 | NESTED(au1000_IRQ, PT_SIZE, sp) | ||
| 24 | SAVE_ALL | ||
| 25 | CLI # Important: mark KERNEL mode ! | ||
| 26 | |||
| 27 | mfc0 t0,CP0_CAUSE # get pending interrupts | ||
| 28 | mfc0 t1,CP0_STATUS # get enabled interrupts | ||
| 29 | and t0,t1 # isolate allowed ones | ||
| 30 | |||
| 31 | andi t0,0xff00 # isolate pending bits | ||
| 32 | beqz t0, 3f # spurious interrupt | ||
| 33 | |||
| 34 | andi a0, t0, CAUSEF_IP7 | ||
| 35 | beq a0, zero, 1f | ||
| 36 | move a0, sp | ||
| 37 | jal mips_timer_interrupt | ||
| 38 | j ret_from_irq | ||
| 39 | |||
| 40 | 1: | ||
| 41 | andi a0, t0, CAUSEF_IP2 # Interrupt Controller 0, Request 0 | ||
| 42 | beq a0, zero, 2f | ||
| 43 | move a0,sp | ||
| 44 | jal intc0_req0_irqdispatch | ||
| 45 | j ret_from_irq | ||
| 46 | 2: | ||
| 47 | andi a0, t0, CAUSEF_IP3 # Interrupt Controller 0, Request 1 | ||
| 48 | beq a0, zero, 3f | ||
| 49 | move a0,sp | ||
| 50 | jal intc0_req1_irqdispatch | ||
| 51 | j ret_from_irq | ||
| 52 | 3: | ||
| 53 | andi a0, t0, CAUSEF_IP4 # Interrupt Controller 1, Request 0 | ||
| 54 | beq a0, zero, 4f | ||
| 55 | move a0,sp | ||
| 56 | jal intc1_req0_irqdispatch | ||
| 57 | j ret_from_irq | ||
| 58 | 4: | ||
| 59 | andi a0, t0, CAUSEF_IP5 # Interrupt Controller 1, Request 1 | ||
| 60 | beq a0, zero, 5f | ||
| 61 | move a0, sp | ||
| 62 | jal intc1_req1_irqdispatch | ||
| 63 | j ret_from_irq | ||
| 64 | |||
| 65 | 5: | ||
| 66 | move a0, sp | ||
| 67 | j spurious_interrupt | ||
| 68 | END(au1000_IRQ) | ||
