aboutsummaryrefslogtreecommitdiffstats
path: root/arch/mips/ath79
diff options
context:
space:
mode:
Diffstat (limited to 'arch/mips/ath79')
-rw-r--r--arch/mips/ath79/Kconfig20
-rw-r--r--arch/mips/ath79/Makefile1
-rw-r--r--arch/mips/ath79/clock.c80
-rw-r--r--arch/mips/ath79/common.c4
-rw-r--r--arch/mips/ath79/dev-common.c9
-rw-r--r--arch/mips/ath79/dev-usb.c126
-rw-r--r--arch/mips/ath79/dev-wmac.c30
-rw-r--r--arch/mips/ath79/early_printk.c2
-rw-r--r--arch/mips/ath79/gpio.c52
-rw-r--r--arch/mips/ath79/irq.c187
-rw-r--r--arch/mips/ath79/mach-ap121.c2
-rw-r--r--arch/mips/ath79/mach-ap136.c156
-rw-r--r--arch/mips/ath79/mach-ap81.c2
-rw-r--r--arch/mips/ath79/mach-db120.c2
-rw-r--r--arch/mips/ath79/mach-pb44.c6
-rw-r--r--arch/mips/ath79/machtypes.h1
-rw-r--r--arch/mips/ath79/pci.c165
-rw-r--r--arch/mips/ath79/pci.h1
-rw-r--r--arch/mips/ath79/setup.c18
19 files changed, 689 insertions, 175 deletions
diff --git a/arch/mips/ath79/Kconfig b/arch/mips/ath79/Kconfig
index f44feee2d67f..3995e31a73e2 100644
--- a/arch/mips/ath79/Kconfig
+++ b/arch/mips/ath79/Kconfig
@@ -14,6 +14,18 @@ config ATH79_MACH_AP121
14 Say 'Y' here if you want your kernel to support the 14 Say 'Y' here if you want your kernel to support the
15 Atheros AP121 reference board. 15 Atheros AP121 reference board.
16 16
17config ATH79_MACH_AP136
18 bool "Atheros AP136 reference board"
19 select SOC_QCA955X
20 select ATH79_DEV_GPIO_BUTTONS
21 select ATH79_DEV_LEDS_GPIO
22 select ATH79_DEV_SPI
23 select ATH79_DEV_USB
24 select ATH79_DEV_WMAC
25 help
26 Say 'Y' here if you want your kernel to support the
27 Atheros AP136 reference board.
28
17config ATH79_MACH_AP81 29config ATH79_MACH_AP81
18 bool "Atheros AP81 reference board" 30 bool "Atheros AP81 reference board"
19 select SOC_AR913X 31 select SOC_AR913X
@@ -88,6 +100,12 @@ config SOC_AR934X
88 select PCI_AR724X if PCI 100 select PCI_AR724X if PCI
89 def_bool n 101 def_bool n
90 102
103config SOC_QCA955X
104 select USB_ARCH_HAS_EHCI
105 select HW_HAS_PCI
106 select PCI_AR724X if PCI
107 def_bool n
108
91config PCI_AR724X 109config PCI_AR724X
92 def_bool n 110 def_bool n
93 111
@@ -104,7 +122,7 @@ config ATH79_DEV_USB
104 def_bool n 122 def_bool n
105 123
106config ATH79_DEV_WMAC 124config ATH79_DEV_WMAC
107 depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X) 125 depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA955X)
108 def_bool n 126 def_bool n
109 127
110endif 128endif
diff --git a/arch/mips/ath79/Makefile b/arch/mips/ath79/Makefile
index 2b54d98263f3..5c9ff692ff3c 100644
--- a/arch/mips/ath79/Makefile
+++ b/arch/mips/ath79/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_ATH79_DEV_WMAC) += dev-wmac.o
27# Machines 27# Machines
28# 28#
29obj-$(CONFIG_ATH79_MACH_AP121) += mach-ap121.o 29obj-$(CONFIG_ATH79_MACH_AP121) += mach-ap121.o
30obj-$(CONFIG_ATH79_MACH_AP136) += mach-ap136.o
30obj-$(CONFIG_ATH79_MACH_AP81) += mach-ap81.o 31obj-$(CONFIG_ATH79_MACH_AP81) += mach-ap81.o
31obj-$(CONFIG_ATH79_MACH_DB120) += mach-db120.o 32obj-$(CONFIG_ATH79_MACH_DB120) += mach-db120.o
32obj-$(CONFIG_ATH79_MACH_PB44) += mach-pb44.o 33obj-$(CONFIG_ATH79_MACH_PB44) += mach-pb44.o
diff --git a/arch/mips/ath79/clock.c b/arch/mips/ath79/clock.c
index 579f452c0b45..765ef30e3e1c 100644
--- a/arch/mips/ath79/clock.c
+++ b/arch/mips/ath79/clock.c
@@ -198,7 +198,7 @@ static void __init ar934x_clocks_init(void)
198 dpll_base = ioremap(AR934X_SRIF_BASE, AR934X_SRIF_SIZE); 198 dpll_base = ioremap(AR934X_SRIF_BASE, AR934X_SRIF_SIZE);
199 199
200 bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP); 200 bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
201 if (bootstrap & AR934X_BOOTSTRAP_REF_CLK_40) 201 if (bootstrap & AR934X_BOOTSTRAP_REF_CLK_40)
202 ath79_ref_clk.rate = 40 * 1000 * 1000; 202 ath79_ref_clk.rate = 40 * 1000 * 1000;
203 else 203 else
204 ath79_ref_clk.rate = 25 * 1000 * 1000; 204 ath79_ref_clk.rate = 25 * 1000 * 1000;
@@ -295,6 +295,82 @@ static void __init ar934x_clocks_init(void)
295 iounmap(dpll_base); 295 iounmap(dpll_base);
296} 296}
297 297
298static void __init qca955x_clocks_init(void)
299{
300 u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
301 u32 cpu_pll, ddr_pll;
302 u32 bootstrap;
303
304 bootstrap = ath79_reset_rr(QCA955X_RESET_REG_BOOTSTRAP);
305 if (bootstrap & QCA955X_BOOTSTRAP_REF_CLK_40)
306 ath79_ref_clk.rate = 40 * 1000 * 1000;
307 else
308 ath79_ref_clk.rate = 25 * 1000 * 1000;
309
310 pll = ath79_pll_rr(QCA955X_PLL_CPU_CONFIG_REG);
311 out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
312 QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK;
313 ref_div = (pll >> QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
314 QCA955X_PLL_CPU_CONFIG_REFDIV_MASK;
315 nint = (pll >> QCA955X_PLL_CPU_CONFIG_NINT_SHIFT) &
316 QCA955X_PLL_CPU_CONFIG_NINT_MASK;
317 frac = (pll >> QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
318 QCA955X_PLL_CPU_CONFIG_NFRAC_MASK;
319
320 cpu_pll = nint * ath79_ref_clk.rate / ref_div;
321 cpu_pll += frac * ath79_ref_clk.rate / (ref_div * (1 << 6));
322 cpu_pll /= (1 << out_div);
323
324 pll = ath79_pll_rr(QCA955X_PLL_DDR_CONFIG_REG);
325 out_div = (pll >> QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
326 QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK;
327 ref_div = (pll >> QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
328 QCA955X_PLL_DDR_CONFIG_REFDIV_MASK;
329 nint = (pll >> QCA955X_PLL_DDR_CONFIG_NINT_SHIFT) &
330 QCA955X_PLL_DDR_CONFIG_NINT_MASK;
331 frac = (pll >> QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
332 QCA955X_PLL_DDR_CONFIG_NFRAC_MASK;
333
334 ddr_pll = nint * ath79_ref_clk.rate / ref_div;
335 ddr_pll += frac * ath79_ref_clk.rate / (ref_div * (1 << 10));
336 ddr_pll /= (1 << out_div);
337
338 clk_ctrl = ath79_pll_rr(QCA955X_PLL_CLK_CTRL_REG);
339
340 postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
341 QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
342
343 if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
344 ath79_cpu_clk.rate = ath79_ref_clk.rate;
345 else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL)
346 ath79_cpu_clk.rate = ddr_pll / (postdiv + 1);
347 else
348 ath79_cpu_clk.rate = cpu_pll / (postdiv + 1);
349
350 postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
351 QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
352
353 if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
354 ath79_ddr_clk.rate = ath79_ref_clk.rate;
355 else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
356 ath79_ddr_clk.rate = cpu_pll / (postdiv + 1);
357 else
358 ath79_ddr_clk.rate = ddr_pll / (postdiv + 1);
359
360 postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
361 QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
362
363 if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
364 ath79_ahb_clk.rate = ath79_ref_clk.rate;
365 else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
366 ath79_ahb_clk.rate = ddr_pll / (postdiv + 1);
367 else
368 ath79_ahb_clk.rate = cpu_pll / (postdiv + 1);
369
370 ath79_wdt_clk.rate = ath79_ref_clk.rate;
371 ath79_uart_clk.rate = ath79_ref_clk.rate;
372}
373
298void __init ath79_clocks_init(void) 374void __init ath79_clocks_init(void)
299{ 375{
300 if (soc_is_ar71xx()) 376 if (soc_is_ar71xx())
@@ -307,6 +383,8 @@ void __init ath79_clocks_init(void)
307 ar933x_clocks_init(); 383 ar933x_clocks_init();
308 else if (soc_is_ar934x()) 384 else if (soc_is_ar934x())
309 ar934x_clocks_init(); 385 ar934x_clocks_init();
386 else if (soc_is_qca955x())
387 qca955x_clocks_init();
310 else 388 else
311 BUG(); 389 BUG();
312 390
diff --git a/arch/mips/ath79/common.c b/arch/mips/ath79/common.c
index 5a4adfc9d79d..eb3966cd8cfc 100644
--- a/arch/mips/ath79/common.c
+++ b/arch/mips/ath79/common.c
@@ -72,6 +72,8 @@ void ath79_device_reset_set(u32 mask)
72 reg = AR933X_RESET_REG_RESET_MODULE; 72 reg = AR933X_RESET_REG_RESET_MODULE;
73 else if (soc_is_ar934x()) 73 else if (soc_is_ar934x())
74 reg = AR934X_RESET_REG_RESET_MODULE; 74 reg = AR934X_RESET_REG_RESET_MODULE;
75 else if (soc_is_qca955x())
76 reg = QCA955X_RESET_REG_RESET_MODULE;
75 else 77 else
76 BUG(); 78 BUG();
77 79
@@ -98,6 +100,8 @@ void ath79_device_reset_clear(u32 mask)
98 reg = AR933X_RESET_REG_RESET_MODULE; 100 reg = AR933X_RESET_REG_RESET_MODULE;
99 else if (soc_is_ar934x()) 101 else if (soc_is_ar934x())
100 reg = AR934X_RESET_REG_RESET_MODULE; 102 reg = AR934X_RESET_REG_RESET_MODULE;
103 else if (soc_is_qca955x())
104 reg = QCA955X_RESET_REG_RESET_MODULE;
101 else 105 else
102 BUG(); 106 BUG();
103 107
diff --git a/arch/mips/ath79/dev-common.c b/arch/mips/ath79/dev-common.c
index 45efc63b08b6..9516aab27139 100644
--- a/arch/mips/ath79/dev-common.c
+++ b/arch/mips/ath79/dev-common.c
@@ -36,7 +36,7 @@ static struct resource ath79_uart_resources[] = {
36static struct plat_serial8250_port ath79_uart_data[] = { 36static struct plat_serial8250_port ath79_uart_data[] = {
37 { 37 {
38 .mapbase = AR71XX_UART_BASE, 38 .mapbase = AR71XX_UART_BASE,
39 .irq = ATH79_MISC_IRQ_UART, 39 .irq = ATH79_MISC_IRQ(3),
40 .flags = AR71XX_UART_FLAGS, 40 .flags = AR71XX_UART_FLAGS,
41 .iotype = UPIO_MEM32, 41 .iotype = UPIO_MEM32,
42 .regshift = 2, 42 .regshift = 2,
@@ -62,8 +62,8 @@ static struct resource ar933x_uart_resources[] = {
62 .flags = IORESOURCE_MEM, 62 .flags = IORESOURCE_MEM,
63 }, 63 },
64 { 64 {
65 .start = ATH79_MISC_IRQ_UART, 65 .start = ATH79_MISC_IRQ(3),
66 .end = ATH79_MISC_IRQ_UART, 66 .end = ATH79_MISC_IRQ(3),
67 .flags = IORESOURCE_IRQ, 67 .flags = IORESOURCE_IRQ,
68 }, 68 },
69}; 69};
@@ -90,7 +90,8 @@ void __init ath79_register_uart(void)
90 if (soc_is_ar71xx() || 90 if (soc_is_ar71xx() ||
91 soc_is_ar724x() || 91 soc_is_ar724x() ||
92 soc_is_ar913x() || 92 soc_is_ar913x() ||
93 soc_is_ar934x()) { 93 soc_is_ar934x() ||
94 soc_is_qca955x()) {
94 ath79_uart_data[0].uartclk = clk_get_rate(clk); 95 ath79_uart_data[0].uartclk = clk_get_rate(clk);
95 platform_device_register(&ath79_uart_device); 96 platform_device_register(&ath79_uart_device);
96 } else if (soc_is_ar933x()) { 97 } else if (soc_is_ar933x()) {
diff --git a/arch/mips/ath79/dev-usb.c b/arch/mips/ath79/dev-usb.c
index bd2bc108e1b5..8227265bcc2d 100644
--- a/arch/mips/ath79/dev-usb.c
+++ b/arch/mips/ath79/dev-usb.c
@@ -25,29 +25,11 @@
25#include "common.h" 25#include "common.h"
26#include "dev-usb.h" 26#include "dev-usb.h"
27 27
28static struct resource ath79_ohci_resources[2]; 28static u64 ath79_usb_dmamask = DMA_BIT_MASK(32);
29
30static u64 ath79_ohci_dmamask = DMA_BIT_MASK(32);
31 29
32static struct usb_ohci_pdata ath79_ohci_pdata = { 30static struct usb_ohci_pdata ath79_ohci_pdata = {
33}; 31};
34 32
35static struct platform_device ath79_ohci_device = {
36 .name = "ohci-platform",
37 .id = -1,
38 .resource = ath79_ohci_resources,
39 .num_resources = ARRAY_SIZE(ath79_ohci_resources),
40 .dev = {
41 .dma_mask = &ath79_ohci_dmamask,
42 .coherent_dma_mask = DMA_BIT_MASK(32),
43 .platform_data = &ath79_ohci_pdata,
44 },
45};
46
47static struct resource ath79_ehci_resources[2];
48
49static u64 ath79_ehci_dmamask = DMA_BIT_MASK(32);
50
51static struct usb_ehci_pdata ath79_ehci_pdata_v1 = { 33static struct usb_ehci_pdata ath79_ehci_pdata_v1 = {
52 .has_synopsys_hc_bug = 1, 34 .has_synopsys_hc_bug = 1,
53}; 35};
@@ -57,22 +39,16 @@ static struct usb_ehci_pdata ath79_ehci_pdata_v2 = {
57 .has_tt = 1, 39 .has_tt = 1,
58}; 40};
59 41
60static struct platform_device ath79_ehci_device = { 42static void __init ath79_usb_register(const char *name, int id,
61 .name = "ehci-platform", 43 unsigned long base, unsigned long size,
62 .id = -1, 44 int irq, const void *data,
63 .resource = ath79_ehci_resources, 45 size_t data_size)
64 .num_resources = ARRAY_SIZE(ath79_ehci_resources),
65 .dev = {
66 .dma_mask = &ath79_ehci_dmamask,
67 .coherent_dma_mask = DMA_BIT_MASK(32),
68 },
69};
70
71static void __init ath79_usb_init_resource(struct resource res[2],
72 unsigned long base,
73 unsigned long size,
74 int irq)
75{ 46{
47 struct resource res[2];
48 struct platform_device *pdev;
49
50 memset(res, 0, sizeof(res));
51
76 res[0].flags = IORESOURCE_MEM; 52 res[0].flags = IORESOURCE_MEM;
77 res[0].start = base; 53 res[0].start = base;
78 res[0].end = base + size - 1; 54 res[0].end = base + size - 1;
@@ -80,6 +56,19 @@ static void __init ath79_usb_init_resource(struct resource res[2],
80 res[1].flags = IORESOURCE_IRQ; 56 res[1].flags = IORESOURCE_IRQ;
81 res[1].start = irq; 57 res[1].start = irq;
82 res[1].end = irq; 58 res[1].end = irq;
59
60 pdev = platform_device_register_resndata(NULL, name, id,
61 res, ARRAY_SIZE(res),
62 data, data_size);
63
64 if (IS_ERR(pdev)) {
65 pr_err("ath79: unable to register USB at %08lx, err=%d\n",
66 base, (int) PTR_ERR(pdev));
67 return;
68 }
69
70 pdev->dev.dma_mask = &ath79_usb_dmamask;
71 pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
83} 72}
84 73
85#define AR71XX_USB_RESET_MASK (AR71XX_RESET_USB_HOST | \ 74#define AR71XX_USB_RESET_MASK (AR71XX_RESET_USB_HOST | \
@@ -106,14 +95,15 @@ static void __init ath79_usb_setup(void)
106 95
107 mdelay(900); 96 mdelay(900);
108 97
109 ath79_usb_init_resource(ath79_ohci_resources, AR71XX_OHCI_BASE, 98 ath79_usb_register("ohci-platform", -1,
110 AR71XX_OHCI_SIZE, ATH79_MISC_IRQ_OHCI); 99 AR71XX_OHCI_BASE, AR71XX_OHCI_SIZE,
111 platform_device_register(&ath79_ohci_device); 100 ATH79_MISC_IRQ(6),
101 &ath79_ohci_pdata, sizeof(ath79_ohci_pdata));
112 102
113 ath79_usb_init_resource(ath79_ehci_resources, AR71XX_EHCI_BASE, 103 ath79_usb_register("ehci-platform", -1,
114 AR71XX_EHCI_SIZE, ATH79_CPU_IRQ_USB); 104 AR71XX_EHCI_BASE, AR71XX_EHCI_SIZE,
115 ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v1; 105 ATH79_CPU_IRQ(3),
116 platform_device_register(&ath79_ehci_device); 106 &ath79_ehci_pdata_v1, sizeof(ath79_ehci_pdata_v1));
117} 107}
118 108
119static void __init ar7240_usb_setup(void) 109static void __init ar7240_usb_setup(void)
@@ -135,9 +125,10 @@ static void __init ar7240_usb_setup(void)
135 125
136 iounmap(usb_ctrl_base); 126 iounmap(usb_ctrl_base);
137 127
138 ath79_usb_init_resource(ath79_ohci_resources, AR7240_OHCI_BASE, 128 ath79_usb_register("ohci-platform", -1,
139 AR7240_OHCI_SIZE, ATH79_CPU_IRQ_USB); 129 AR7240_OHCI_BASE, AR7240_OHCI_SIZE,
140 platform_device_register(&ath79_ohci_device); 130 ATH79_CPU_IRQ(3),
131 &ath79_ohci_pdata, sizeof(ath79_ohci_pdata));
141} 132}
142 133
143static void __init ar724x_usb_setup(void) 134static void __init ar724x_usb_setup(void)
@@ -151,10 +142,10 @@ static void __init ar724x_usb_setup(void)
151 ath79_device_reset_clear(AR724X_RESET_USB_PHY); 142 ath79_device_reset_clear(AR724X_RESET_USB_PHY);
152 mdelay(10); 143 mdelay(10);
153 144
154 ath79_usb_init_resource(ath79_ehci_resources, AR724X_EHCI_BASE, 145 ath79_usb_register("ehci-platform", -1,
155 AR724X_EHCI_SIZE, ATH79_CPU_IRQ_USB); 146 AR724X_EHCI_BASE, AR724X_EHCI_SIZE,
156 ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2; 147 ATH79_CPU_IRQ(3),
157 platform_device_register(&ath79_ehci_device); 148 &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
158} 149}
159 150
160static void __init ar913x_usb_setup(void) 151static void __init ar913x_usb_setup(void)
@@ -168,10 +159,10 @@ static void __init ar913x_usb_setup(void)
168 ath79_device_reset_clear(AR913X_RESET_USB_PHY); 159 ath79_device_reset_clear(AR913X_RESET_USB_PHY);
169 mdelay(10); 160 mdelay(10);
170 161
171 ath79_usb_init_resource(ath79_ehci_resources, AR913X_EHCI_BASE, 162 ath79_usb_register("ehci-platform", -1,
172 AR913X_EHCI_SIZE, ATH79_CPU_IRQ_USB); 163 AR913X_EHCI_BASE, AR913X_EHCI_SIZE,
173 ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2; 164 ATH79_CPU_IRQ(3),
174 platform_device_register(&ath79_ehci_device); 165 &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
175} 166}
176 167
177static void __init ar933x_usb_setup(void) 168static void __init ar933x_usb_setup(void)
@@ -185,10 +176,10 @@ static void __init ar933x_usb_setup(void)
185 ath79_device_reset_clear(AR933X_RESET_USB_PHY); 176 ath79_device_reset_clear(AR933X_RESET_USB_PHY);
186 mdelay(10); 177 mdelay(10);
187 178
188 ath79_usb_init_resource(ath79_ehci_resources, AR933X_EHCI_BASE, 179 ath79_usb_register("ehci-platform", -1,
189 AR933X_EHCI_SIZE, ATH79_CPU_IRQ_USB); 180 AR933X_EHCI_BASE, AR933X_EHCI_SIZE,
190 ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2; 181 ATH79_CPU_IRQ(3),
191 platform_device_register(&ath79_ehci_device); 182 &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
192} 183}
193 184
194static void __init ar934x_usb_setup(void) 185static void __init ar934x_usb_setup(void)
@@ -211,10 +202,23 @@ static void __init ar934x_usb_setup(void)
211 ath79_device_reset_clear(AR934X_RESET_USB_HOST); 202 ath79_device_reset_clear(AR934X_RESET_USB_HOST);
212 udelay(1000); 203 udelay(1000);
213 204
214 ath79_usb_init_resource(ath79_ehci_resources, AR934X_EHCI_BASE, 205 ath79_usb_register("ehci-platform", -1,
215 AR934X_EHCI_SIZE, ATH79_CPU_IRQ_USB); 206 AR934X_EHCI_BASE, AR934X_EHCI_SIZE,
216 ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2; 207 ATH79_CPU_IRQ(3),
217 platform_device_register(&ath79_ehci_device); 208 &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
209}
210
211static void __init qca955x_usb_setup(void)
212{
213 ath79_usb_register("ehci-platform", 0,
214 QCA955X_EHCI0_BASE, QCA955X_EHCI_SIZE,
215 ATH79_IP3_IRQ(0),
216 &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
217
218 ath79_usb_register("ehci-platform", 1,
219 QCA955X_EHCI1_BASE, QCA955X_EHCI_SIZE,
220 ATH79_IP3_IRQ(1),
221 &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
218} 222}
219 223
220void __init ath79_register_usb(void) 224void __init ath79_register_usb(void)
@@ -231,6 +235,8 @@ void __init ath79_register_usb(void)
231 ar933x_usb_setup(); 235 ar933x_usb_setup();
232 else if (soc_is_ar934x()) 236 else if (soc_is_ar934x())
233 ar934x_usb_setup(); 237 ar934x_usb_setup();
238 else if (soc_is_qca955x())
239 qca955x_usb_setup();
234 else 240 else
235 BUG(); 241 BUG();
236} 242}
diff --git a/arch/mips/ath79/dev-wmac.c b/arch/mips/ath79/dev-wmac.c
index d6d893c16ad4..da190b1b87ce 100644
--- a/arch/mips/ath79/dev-wmac.c
+++ b/arch/mips/ath79/dev-wmac.c
@@ -55,8 +55,8 @@ static void __init ar913x_wmac_setup(void)
55 55
56 ath79_wmac_resources[0].start = AR913X_WMAC_BASE; 56 ath79_wmac_resources[0].start = AR913X_WMAC_BASE;
57 ath79_wmac_resources[0].end = AR913X_WMAC_BASE + AR913X_WMAC_SIZE - 1; 57 ath79_wmac_resources[0].end = AR913X_WMAC_BASE + AR913X_WMAC_SIZE - 1;
58 ath79_wmac_resources[1].start = ATH79_CPU_IRQ_IP2; 58 ath79_wmac_resources[1].start = ATH79_CPU_IRQ(2);
59 ath79_wmac_resources[1].end = ATH79_CPU_IRQ_IP2; 59 ath79_wmac_resources[1].end = ATH79_CPU_IRQ(2);
60} 60}
61 61
62 62
@@ -83,8 +83,8 @@ static void __init ar933x_wmac_setup(void)
83 83
84 ath79_wmac_resources[0].start = AR933X_WMAC_BASE; 84 ath79_wmac_resources[0].start = AR933X_WMAC_BASE;
85 ath79_wmac_resources[0].end = AR933X_WMAC_BASE + AR933X_WMAC_SIZE - 1; 85 ath79_wmac_resources[0].end = AR933X_WMAC_BASE + AR933X_WMAC_SIZE - 1;
86 ath79_wmac_resources[1].start = ATH79_CPU_IRQ_IP2; 86 ath79_wmac_resources[1].start = ATH79_CPU_IRQ(2);
87 ath79_wmac_resources[1].end = ATH79_CPU_IRQ_IP2; 87 ath79_wmac_resources[1].end = ATH79_CPU_IRQ(2);
88 88
89 t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP); 89 t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
90 if (t & AR933X_BOOTSTRAP_REF_CLK_40) 90 if (t & AR933X_BOOTSTRAP_REF_CLK_40)
@@ -107,7 +107,7 @@ static void ar934x_wmac_setup(void)
107 ath79_wmac_resources[0].start = AR934X_WMAC_BASE; 107 ath79_wmac_resources[0].start = AR934X_WMAC_BASE;
108 ath79_wmac_resources[0].end = AR934X_WMAC_BASE + AR934X_WMAC_SIZE - 1; 108 ath79_wmac_resources[0].end = AR934X_WMAC_BASE + AR934X_WMAC_SIZE - 1;
109 ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1); 109 ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1);
110 ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1); 110 ath79_wmac_resources[1].end = ATH79_IP2_IRQ(1);
111 111
112 t = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP); 112 t = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
113 if (t & AR934X_BOOTSTRAP_REF_CLK_40) 113 if (t & AR934X_BOOTSTRAP_REF_CLK_40)
@@ -116,6 +116,24 @@ static void ar934x_wmac_setup(void)
116 ath79_wmac_data.is_clk_25mhz = true; 116 ath79_wmac_data.is_clk_25mhz = true;
117} 117}
118 118
119static void qca955x_wmac_setup(void)
120{
121 u32 t;
122
123 ath79_wmac_device.name = "qca955x_wmac";
124
125 ath79_wmac_resources[0].start = QCA955X_WMAC_BASE;
126 ath79_wmac_resources[0].end = QCA955X_WMAC_BASE + QCA955X_WMAC_SIZE - 1;
127 ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1);
128 ath79_wmac_resources[1].end = ATH79_IP2_IRQ(1);
129
130 t = ath79_reset_rr(QCA955X_RESET_REG_BOOTSTRAP);
131 if (t & QCA955X_BOOTSTRAP_REF_CLK_40)
132 ath79_wmac_data.is_clk_25mhz = false;
133 else
134 ath79_wmac_data.is_clk_25mhz = true;
135}
136
119void __init ath79_register_wmac(u8 *cal_data) 137void __init ath79_register_wmac(u8 *cal_data)
120{ 138{
121 if (soc_is_ar913x()) 139 if (soc_is_ar913x())
@@ -124,6 +142,8 @@ void __init ath79_register_wmac(u8 *cal_data)
124 ar933x_wmac_setup(); 142 ar933x_wmac_setup();
125 else if (soc_is_ar934x()) 143 else if (soc_is_ar934x())
126 ar934x_wmac_setup(); 144 ar934x_wmac_setup();
145 else if (soc_is_qca955x())
146 qca955x_wmac_setup();
127 else 147 else
128 BUG(); 148 BUG();
129 149
diff --git a/arch/mips/ath79/early_printk.c b/arch/mips/ath79/early_printk.c
index dc938cb2ba58..b955fafc58ba 100644
--- a/arch/mips/ath79/early_printk.c
+++ b/arch/mips/ath79/early_printk.c
@@ -74,6 +74,8 @@ static void prom_putchar_init(void)
74 case REV_ID_MAJOR_AR9341: 74 case REV_ID_MAJOR_AR9341:
75 case REV_ID_MAJOR_AR9342: 75 case REV_ID_MAJOR_AR9342:
76 case REV_ID_MAJOR_AR9344: 76 case REV_ID_MAJOR_AR9344:
77 case REV_ID_MAJOR_QCA9556:
78 case REV_ID_MAJOR_QCA9558:
77 _prom_putchar = prom_putchar_ar71xx; 79 _prom_putchar = prom_putchar_ar71xx;
78 break; 80 break;
79 81
diff --git a/arch/mips/ath79/gpio.c b/arch/mips/ath79/gpio.c
index 48fe762d2526..8d025b028bb1 100644
--- a/arch/mips/ath79/gpio.c
+++ b/arch/mips/ath79/gpio.c
@@ -137,49 +137,45 @@ static struct gpio_chip ath79_gpio_chip = {
137 .base = 0, 137 .base = 0,
138}; 138};
139 139
140void ath79_gpio_function_enable(u32 mask) 140static void __iomem *ath79_gpio_get_function_reg(void)
141{ 141{
142 void __iomem *base = ath79_gpio_base; 142 u32 reg = 0;
143 unsigned long flags;
144 143
145 spin_lock_irqsave(&ath79_gpio_lock, flags); 144 if (soc_is_ar71xx() ||
146 145 soc_is_ar724x() ||
147 __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_FUNC) | mask, 146 soc_is_ar913x() ||
148 base + AR71XX_GPIO_REG_FUNC); 147 soc_is_ar933x())
149 /* flush write */ 148 reg = AR71XX_GPIO_REG_FUNC;
150 __raw_readl(base + AR71XX_GPIO_REG_FUNC); 149 else if (soc_is_ar934x())
150 reg = AR934X_GPIO_REG_FUNC;
151 else
152 BUG();
151 153
152 spin_unlock_irqrestore(&ath79_gpio_lock, flags); 154 return ath79_gpio_base + reg;
153} 155}
154 156
155void ath79_gpio_function_disable(u32 mask) 157void ath79_gpio_function_setup(u32 set, u32 clear)
156{ 158{
157 void __iomem *base = ath79_gpio_base; 159 void __iomem *reg = ath79_gpio_get_function_reg();
158 unsigned long flags; 160 unsigned long flags;
159 161
160 spin_lock_irqsave(&ath79_gpio_lock, flags); 162 spin_lock_irqsave(&ath79_gpio_lock, flags);
161 163
162 __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_FUNC) & ~mask, 164 __raw_writel((__raw_readl(reg) & ~clear) | set, reg);
163 base + AR71XX_GPIO_REG_FUNC);
164 /* flush write */ 165 /* flush write */
165 __raw_readl(base + AR71XX_GPIO_REG_FUNC); 166 __raw_readl(reg);
166 167
167 spin_unlock_irqrestore(&ath79_gpio_lock, flags); 168 spin_unlock_irqrestore(&ath79_gpio_lock, flags);
168} 169}
169 170
170void ath79_gpio_function_setup(u32 set, u32 clear) 171void ath79_gpio_function_enable(u32 mask)
171{ 172{
172 void __iomem *base = ath79_gpio_base; 173 ath79_gpio_function_setup(mask, 0);
173 unsigned long flags; 174}
174
175 spin_lock_irqsave(&ath79_gpio_lock, flags);
176
177 __raw_writel((__raw_readl(base + AR71XX_GPIO_REG_FUNC) & ~clear) | set,
178 base + AR71XX_GPIO_REG_FUNC);
179 /* flush write */
180 __raw_readl(base + AR71XX_GPIO_REG_FUNC);
181 175
182 spin_unlock_irqrestore(&ath79_gpio_lock, flags); 176void ath79_gpio_function_disable(u32 mask)
177{
178 ath79_gpio_function_setup(0, mask);
183} 179}
184 180
185void __init ath79_gpio_init(void) 181void __init ath79_gpio_init(void)
@@ -198,12 +194,14 @@ void __init ath79_gpio_init(void)
198 ath79_gpio_count = AR933X_GPIO_COUNT; 194 ath79_gpio_count = AR933X_GPIO_COUNT;
199 else if (soc_is_ar934x()) 195 else if (soc_is_ar934x())
200 ath79_gpio_count = AR934X_GPIO_COUNT; 196 ath79_gpio_count = AR934X_GPIO_COUNT;
197 else if (soc_is_qca955x())
198 ath79_gpio_count = QCA955X_GPIO_COUNT;
201 else 199 else
202 BUG(); 200 BUG();
203 201
204 ath79_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE); 202 ath79_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE);
205 ath79_gpio_chip.ngpio = ath79_gpio_count; 203 ath79_gpio_chip.ngpio = ath79_gpio_count;
206 if (soc_is_ar934x()) { 204 if (soc_is_ar934x() || soc_is_qca955x()) {
207 ath79_gpio_chip.direction_input = ar934x_gpio_direction_input; 205 ath79_gpio_chip.direction_input = ar934x_gpio_direction_input;
208 ath79_gpio_chip.direction_output = ar934x_gpio_direction_output; 206 ath79_gpio_chip.direction_output = ar934x_gpio_direction_output;
209 } 207 }
diff --git a/arch/mips/ath79/irq.c b/arch/mips/ath79/irq.c
index 90d09fc15398..9c0e1761773f 100644
--- a/arch/mips/ath79/irq.c
+++ b/arch/mips/ath79/irq.c
@@ -35,44 +35,17 @@ static void ath79_misc_irq_handler(unsigned int irq, struct irq_desc *desc)
35 pending = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS) & 35 pending = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS) &
36 __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); 36 __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
37 37
38 if (pending & MISC_INT_UART) 38 if (!pending) {
39 generic_handle_irq(ATH79_MISC_IRQ_UART); 39 spurious_interrupt();
40 40 return;
41 else if (pending & MISC_INT_DMA) 41 }
42 generic_handle_irq(ATH79_MISC_IRQ_DMA);
43
44 else if (pending & MISC_INT_PERFC)
45 generic_handle_irq(ATH79_MISC_IRQ_PERFC);
46
47 else if (pending & MISC_INT_TIMER)
48 generic_handle_irq(ATH79_MISC_IRQ_TIMER);
49
50 else if (pending & MISC_INT_TIMER2)
51 generic_handle_irq(ATH79_MISC_IRQ_TIMER2);
52
53 else if (pending & MISC_INT_TIMER3)
54 generic_handle_irq(ATH79_MISC_IRQ_TIMER3);
55
56 else if (pending & MISC_INT_TIMER4)
57 generic_handle_irq(ATH79_MISC_IRQ_TIMER4);
58
59 else if (pending & MISC_INT_OHCI)
60 generic_handle_irq(ATH79_MISC_IRQ_OHCI);
61
62 else if (pending & MISC_INT_ERROR)
63 generic_handle_irq(ATH79_MISC_IRQ_ERROR);
64
65 else if (pending & MISC_INT_GPIO)
66 generic_handle_irq(ATH79_MISC_IRQ_GPIO);
67
68 else if (pending & MISC_INT_WDOG)
69 generic_handle_irq(ATH79_MISC_IRQ_WDOG);
70 42
71 else if (pending & MISC_INT_ETHSW) 43 while (pending) {
72 generic_handle_irq(ATH79_MISC_IRQ_ETHSW); 44 int bit = __ffs(pending);
73 45
74 else 46 generic_handle_irq(ATH79_MISC_IRQ(bit));
75 spurious_interrupt(); 47 pending &= ~BIT(bit);
48 }
76} 49}
77 50
78static void ar71xx_misc_irq_unmask(struct irq_data *d) 51static void ar71xx_misc_irq_unmask(struct irq_data *d)
@@ -130,7 +103,10 @@ static void __init ath79_misc_irq_init(void)
130 103
131 if (soc_is_ar71xx() || soc_is_ar913x()) 104 if (soc_is_ar71xx() || soc_is_ar913x())
132 ath79_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask; 105 ath79_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask;
133 else if (soc_is_ar724x() || soc_is_ar933x() || soc_is_ar934x()) 106 else if (soc_is_ar724x() ||
107 soc_is_ar933x() ||
108 soc_is_ar934x() ||
109 soc_is_qca955x())
134 ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack; 110 ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
135 else 111 else
136 BUG(); 112 BUG();
@@ -141,7 +117,7 @@ static void __init ath79_misc_irq_init(void)
141 handle_level_irq); 117 handle_level_irq);
142 } 118 }
143 119
144 irq_set_chained_handler(ATH79_CPU_IRQ_MISC, ath79_misc_irq_handler); 120 irq_set_chained_handler(ATH79_CPU_IRQ(6), ath79_misc_irq_handler);
145} 121}
146 122
147static void ar934x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc) 123static void ar934x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc)
@@ -174,7 +150,89 @@ static void ar934x_ip2_irq_init(void)
174 irq_set_chip_and_handler(i, &dummy_irq_chip, 150 irq_set_chip_and_handler(i, &dummy_irq_chip,
175 handle_level_irq); 151 handle_level_irq);
176 152
177 irq_set_chained_handler(ATH79_CPU_IRQ_IP2, ar934x_ip2_irq_dispatch); 153 irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch);
154}
155
156static void qca955x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc)
157{
158 u32 status;
159
160 disable_irq_nosync(irq);
161
162 status = ath79_reset_rr(QCA955X_RESET_REG_EXT_INT_STATUS);
163 status &= QCA955X_EXT_INT_PCIE_RC1_ALL | QCA955X_EXT_INT_WMAC_ALL;
164
165 if (status == 0) {
166 spurious_interrupt();
167 goto enable;
168 }
169
170 if (status & QCA955X_EXT_INT_PCIE_RC1_ALL) {
171 /* TODO: flush DDR? */
172 generic_handle_irq(ATH79_IP2_IRQ(0));
173 }
174
175 if (status & QCA955X_EXT_INT_WMAC_ALL) {
176 /* TODO: flush DDR? */
177 generic_handle_irq(ATH79_IP2_IRQ(1));
178 }
179
180enable:
181 enable_irq(irq);
182}
183
184static void qca955x_ip3_irq_dispatch(unsigned int irq, struct irq_desc *desc)
185{
186 u32 status;
187
188 disable_irq_nosync(irq);
189
190 status = ath79_reset_rr(QCA955X_RESET_REG_EXT_INT_STATUS);
191 status &= QCA955X_EXT_INT_PCIE_RC2_ALL |
192 QCA955X_EXT_INT_USB1 |
193 QCA955X_EXT_INT_USB2;
194
195 if (status == 0) {
196 spurious_interrupt();
197 goto enable;
198 }
199
200 if (status & QCA955X_EXT_INT_USB1) {
201 /* TODO: flush DDR? */
202 generic_handle_irq(ATH79_IP3_IRQ(0));
203 }
204
205 if (status & QCA955X_EXT_INT_USB2) {
206 /* TODO: flush DDR? */
207 generic_handle_irq(ATH79_IP3_IRQ(1));
208 }
209
210 if (status & QCA955X_EXT_INT_PCIE_RC2_ALL) {
211 /* TODO: flush DDR? */
212 generic_handle_irq(ATH79_IP3_IRQ(2));
213 }
214
215enable:
216 enable_irq(irq);
217}
218
219static void qca955x_irq_init(void)
220{
221 int i;
222
223 for (i = ATH79_IP2_IRQ_BASE;
224 i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
225 irq_set_chip_and_handler(i, &dummy_irq_chip,
226 handle_level_irq);
227
228 irq_set_chained_handler(ATH79_CPU_IRQ(2), qca955x_ip2_irq_dispatch);
229
230 for (i = ATH79_IP3_IRQ_BASE;
231 i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++)
232 irq_set_chip_and_handler(i, &dummy_irq_chip,
233 handle_level_irq);
234
235 irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch);
178} 236}
179 237
180asmlinkage void plat_irq_dispatch(void) 238asmlinkage void plat_irq_dispatch(void)
@@ -184,22 +242,22 @@ asmlinkage void plat_irq_dispatch(void)
184 pending = read_c0_status() & read_c0_cause() & ST0_IM; 242 pending = read_c0_status() & read_c0_cause() & ST0_IM;
185 243
186 if (pending & STATUSF_IP7) 244 if (pending & STATUSF_IP7)
187 do_IRQ(ATH79_CPU_IRQ_TIMER); 245 do_IRQ(ATH79_CPU_IRQ(7));
188 246
189 else if (pending & STATUSF_IP2) 247 else if (pending & STATUSF_IP2)
190 ath79_ip2_handler(); 248 ath79_ip2_handler();
191 249
192 else if (pending & STATUSF_IP4) 250 else if (pending & STATUSF_IP4)
193 do_IRQ(ATH79_CPU_IRQ_GE0); 251 do_IRQ(ATH79_CPU_IRQ(4));
194 252
195 else if (pending & STATUSF_IP5) 253 else if (pending & STATUSF_IP5)
196 do_IRQ(ATH79_CPU_IRQ_GE1); 254 do_IRQ(ATH79_CPU_IRQ(5));
197 255
198 else if (pending & STATUSF_IP3) 256 else if (pending & STATUSF_IP3)
199 ath79_ip3_handler(); 257 ath79_ip3_handler();
200 258
201 else if (pending & STATUSF_IP6) 259 else if (pending & STATUSF_IP6)
202 do_IRQ(ATH79_CPU_IRQ_MISC); 260 do_IRQ(ATH79_CPU_IRQ(6));
203 261
204 else 262 else
205 spurious_interrupt(); 263 spurious_interrupt();
@@ -212,63 +270,69 @@ asmlinkage void plat_irq_dispatch(void)
212 * Issue a flush in the handlers to ensure that the driver sees 270 * Issue a flush in the handlers to ensure that the driver sees
213 * the update. 271 * the update.
214 */ 272 */
273
274static void ath79_default_ip2_handler(void)
275{
276 do_IRQ(ATH79_CPU_IRQ(2));
277}
278
279static void ath79_default_ip3_handler(void)
280{
281 do_IRQ(ATH79_CPU_IRQ(3));
282}
283
215static void ar71xx_ip2_handler(void) 284static void ar71xx_ip2_handler(void)
216{ 285{
217 ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_PCI); 286 ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_PCI);
218 do_IRQ(ATH79_CPU_IRQ_IP2); 287 do_IRQ(ATH79_CPU_IRQ(2));
219} 288}
220 289
221static void ar724x_ip2_handler(void) 290static void ar724x_ip2_handler(void)
222{ 291{
223 ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_PCIE); 292 ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_PCIE);
224 do_IRQ(ATH79_CPU_IRQ_IP2); 293 do_IRQ(ATH79_CPU_IRQ(2));
225} 294}
226 295
227static void ar913x_ip2_handler(void) 296static void ar913x_ip2_handler(void)
228{ 297{
229 ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_WMAC); 298 ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_WMAC);
230 do_IRQ(ATH79_CPU_IRQ_IP2); 299 do_IRQ(ATH79_CPU_IRQ(2));
231} 300}
232 301
233static void ar933x_ip2_handler(void) 302static void ar933x_ip2_handler(void)
234{ 303{
235 ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_WMAC); 304 ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_WMAC);
236 do_IRQ(ATH79_CPU_IRQ_IP2); 305 do_IRQ(ATH79_CPU_IRQ(2));
237}
238
239static void ar934x_ip2_handler(void)
240{
241 do_IRQ(ATH79_CPU_IRQ_IP2);
242} 306}
243 307
244static void ar71xx_ip3_handler(void) 308static void ar71xx_ip3_handler(void)
245{ 309{
246 ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_USB); 310 ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_USB);
247 do_IRQ(ATH79_CPU_IRQ_USB); 311 do_IRQ(ATH79_CPU_IRQ(3));
248} 312}
249 313
250static void ar724x_ip3_handler(void) 314static void ar724x_ip3_handler(void)
251{ 315{
252 ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_USB); 316 ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_USB);
253 do_IRQ(ATH79_CPU_IRQ_USB); 317 do_IRQ(ATH79_CPU_IRQ(3));
254} 318}
255 319
256static void ar913x_ip3_handler(void) 320static void ar913x_ip3_handler(void)
257{ 321{
258 ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_USB); 322 ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_USB);
259 do_IRQ(ATH79_CPU_IRQ_USB); 323 do_IRQ(ATH79_CPU_IRQ(3));
260} 324}
261 325
262static void ar933x_ip3_handler(void) 326static void ar933x_ip3_handler(void)
263{ 327{
264 ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_USB); 328 ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_USB);
265 do_IRQ(ATH79_CPU_IRQ_USB); 329 do_IRQ(ATH79_CPU_IRQ(3));
266} 330}
267 331
268static void ar934x_ip3_handler(void) 332static void ar934x_ip3_handler(void)
269{ 333{
270 ath79_ddr_wb_flush(AR934X_DDR_REG_FLUSH_USB); 334 ath79_ddr_wb_flush(AR934X_DDR_REG_FLUSH_USB);
271 do_IRQ(ATH79_CPU_IRQ_USB); 335 do_IRQ(ATH79_CPU_IRQ(3));
272} 336}
273 337
274void __init arch_init_irq(void) 338void __init arch_init_irq(void)
@@ -286,16 +350,21 @@ void __init arch_init_irq(void)
286 ath79_ip2_handler = ar933x_ip2_handler; 350 ath79_ip2_handler = ar933x_ip2_handler;
287 ath79_ip3_handler = ar933x_ip3_handler; 351 ath79_ip3_handler = ar933x_ip3_handler;
288 } else if (soc_is_ar934x()) { 352 } else if (soc_is_ar934x()) {
289 ath79_ip2_handler = ar934x_ip2_handler; 353 ath79_ip2_handler = ath79_default_ip2_handler;
290 ath79_ip3_handler = ar934x_ip3_handler; 354 ath79_ip3_handler = ar934x_ip3_handler;
355 } else if (soc_is_qca955x()) {
356 ath79_ip2_handler = ath79_default_ip2_handler;
357 ath79_ip3_handler = ath79_default_ip3_handler;
291 } else { 358 } else {
292 BUG(); 359 BUG();
293 } 360 }
294 361
295 cp0_perfcount_irq = ATH79_MISC_IRQ_PERFC; 362 cp0_perfcount_irq = ATH79_MISC_IRQ(5);
296 mips_cpu_irq_init(); 363 mips_cpu_irq_init();
297 ath79_misc_irq_init(); 364 ath79_misc_irq_init();
298 365
299 if (soc_is_ar934x()) 366 if (soc_is_ar934x())
300 ar934x_ip2_irq_init(); 367 ar934x_ip2_irq_init();
368 else if (soc_is_qca955x())
369 qca955x_irq_init();
301} 370}
diff --git a/arch/mips/ath79/mach-ap121.c b/arch/mips/ath79/mach-ap121.c
index 4c20200d7c72..1bf73f2a069d 100644
--- a/arch/mips/ath79/mach-ap121.c
+++ b/arch/mips/ath79/mach-ap121.c
@@ -69,7 +69,7 @@ static struct spi_board_info ap121_spi_info[] = {
69 69
70static struct ath79_spi_platform_data ap121_spi_data = { 70static struct ath79_spi_platform_data ap121_spi_data = {
71 .bus_num = 0, 71 .bus_num = 0,
72 .num_chipselect = 1, 72 .num_chipselect = 1,
73}; 73};
74 74
75static void __init ap121_setup(void) 75static void __init ap121_setup(void)
diff --git a/arch/mips/ath79/mach-ap136.c b/arch/mips/ath79/mach-ap136.c
new file mode 100644
index 000000000000..479dd4b1d0d2
--- /dev/null
+++ b/arch/mips/ath79/mach-ap136.c
@@ -0,0 +1,156 @@
1/*
2 * Qualcomm Atheros AP136 reference board support
3 *
4 * Copyright (c) 2012 Qualcomm Atheros
5 * Copyright (c) 2012-2013 Gabor Juhos <juhosg@openwrt.org>
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 *
19 */
20
21#include <linux/pci.h>
22#include <linux/ath9k_platform.h>
23
24#include "machtypes.h"
25#include "dev-gpio-buttons.h"
26#include "dev-leds-gpio.h"
27#include "dev-spi.h"
28#include "dev-usb.h"
29#include "dev-wmac.h"
30#include "pci.h"
31
32#define AP136_GPIO_LED_STATUS_RED 14
33#define AP136_GPIO_LED_STATUS_GREEN 19
34#define AP136_GPIO_LED_USB 4
35#define AP136_GPIO_LED_WLAN_2G 13
36#define AP136_GPIO_LED_WLAN_5G 12
37#define AP136_GPIO_LED_WPS_RED 15
38#define AP136_GPIO_LED_WPS_GREEN 20
39
40#define AP136_GPIO_BTN_WPS 16
41#define AP136_GPIO_BTN_RFKILL 21
42
43#define AP136_KEYS_POLL_INTERVAL 20 /* msecs */
44#define AP136_KEYS_DEBOUNCE_INTERVAL (3 * AP136_KEYS_POLL_INTERVAL)
45
46#define AP136_WMAC_CALDATA_OFFSET 0x1000
47#define AP136_PCIE_CALDATA_OFFSET 0x5000
48
49static struct gpio_led ap136_leds_gpio[] __initdata = {
50 {
51 .name = "qca:green:status",
52 .gpio = AP136_GPIO_LED_STATUS_GREEN,
53 .active_low = 1,
54 },
55 {
56 .name = "qca:red:status",
57 .gpio = AP136_GPIO_LED_STATUS_RED,
58 .active_low = 1,
59 },
60 {
61 .name = "qca:green:wps",
62 .gpio = AP136_GPIO_LED_WPS_GREEN,
63 .active_low = 1,
64 },
65 {
66 .name = "qca:red:wps",
67 .gpio = AP136_GPIO_LED_WPS_RED,
68 .active_low = 1,
69 },
70 {
71 .name = "qca:red:wlan-2g",
72 .gpio = AP136_GPIO_LED_WLAN_2G,
73 .active_low = 1,
74 },
75 {
76 .name = "qca:red:usb",
77 .gpio = AP136_GPIO_LED_USB,
78 .active_low = 1,
79 }
80};
81
82static struct gpio_keys_button ap136_gpio_keys[] __initdata = {
83 {
84 .desc = "WPS button",
85 .type = EV_KEY,
86 .code = KEY_WPS_BUTTON,
87 .debounce_interval = AP136_KEYS_DEBOUNCE_INTERVAL,
88 .gpio = AP136_GPIO_BTN_WPS,
89 .active_low = 1,
90 },
91 {
92 .desc = "RFKILL button",
93 .type = EV_KEY,
94 .code = KEY_RFKILL,
95 .debounce_interval = AP136_KEYS_DEBOUNCE_INTERVAL,
96 .gpio = AP136_GPIO_BTN_RFKILL,
97 .active_low = 1,
98 },
99};
100
101static struct spi_board_info ap136_spi_info[] = {
102 {
103 .bus_num = 0,
104 .chip_select = 0,
105 .max_speed_hz = 25000000,
106 .modalias = "mx25l6405d",
107 }
108};
109
110static struct ath79_spi_platform_data ap136_spi_data = {
111 .bus_num = 0,
112 .num_chipselect = 1,
113};
114
115#ifdef CONFIG_PCI
116static struct ath9k_platform_data ap136_ath9k_data;
117
118static int ap136_pci_plat_dev_init(struct pci_dev *dev)
119{
120 if (dev->bus->number == 1 && (PCI_SLOT(dev->devfn)) == 0)
121 dev->dev.platform_data = &ap136_ath9k_data;
122
123 return 0;
124}
125
126static void __init ap136_pci_init(u8 *eeprom)
127{
128 memcpy(ap136_ath9k_data.eeprom_data, eeprom,
129 sizeof(ap136_ath9k_data.eeprom_data));
130
131 ath79_pci_set_plat_dev_init(ap136_pci_plat_dev_init);
132 ath79_register_pci();
133}
134#else
135static inline void ap136_pci_init(void) {}
136#endif /* CONFIG_PCI */
137
138static void __init ap136_setup(void)
139{
140 u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
141
142 ath79_register_leds_gpio(-1, ARRAY_SIZE(ap136_leds_gpio),
143 ap136_leds_gpio);
144 ath79_register_gpio_keys_polled(-1, AP136_KEYS_POLL_INTERVAL,
145 ARRAY_SIZE(ap136_gpio_keys),
146 ap136_gpio_keys);
147 ath79_register_spi(&ap136_spi_data, ap136_spi_info,
148 ARRAY_SIZE(ap136_spi_info));
149 ath79_register_usb();
150 ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET);
151 ap136_pci_init(art + AP136_PCIE_CALDATA_OFFSET);
152}
153
154MIPS_MACHINE(ATH79_MACH_AP136_010, "AP136-010",
155 "Atheros AP136-010 reference board",
156 ap136_setup);
diff --git a/arch/mips/ath79/mach-ap81.c b/arch/mips/ath79/mach-ap81.c
index abe19836331c..1c78d497f930 100644
--- a/arch/mips/ath79/mach-ap81.c
+++ b/arch/mips/ath79/mach-ap81.c
@@ -78,7 +78,7 @@ static struct spi_board_info ap81_spi_info[] = {
78 78
79static struct ath79_spi_platform_data ap81_spi_data = { 79static struct ath79_spi_platform_data ap81_spi_data = {
80 .bus_num = 0, 80 .bus_num = 0,
81 .num_chipselect = 1, 81 .num_chipselect = 1,
82}; 82};
83 83
84static void __init ap81_setup(void) 84static void __init ap81_setup(void)
diff --git a/arch/mips/ath79/mach-db120.c b/arch/mips/ath79/mach-db120.c
index 42f540a724f4..4d661a1d2dae 100644
--- a/arch/mips/ath79/mach-db120.c
+++ b/arch/mips/ath79/mach-db120.c
@@ -87,7 +87,7 @@ static struct spi_board_info db120_spi_info[] = {
87 87
88static struct ath79_spi_platform_data db120_spi_data = { 88static struct ath79_spi_platform_data db120_spi_data = {
89 .bus_num = 0, 89 .bus_num = 0,
90 .num_chipselect = 1, 90 .num_chipselect = 1,
91}; 91};
92 92
93#ifdef CONFIG_PCI 93#ifdef CONFIG_PCI
diff --git a/arch/mips/ath79/mach-pb44.c b/arch/mips/ath79/mach-pb44.c
index c5f0ea5e00c3..67b980d94fb7 100644
--- a/arch/mips/ath79/mach-pb44.c
+++ b/arch/mips/ath79/mach-pb44.c
@@ -34,8 +34,8 @@
34#define PB44_KEYS_DEBOUNCE_INTERVAL (3 * PB44_KEYS_POLL_INTERVAL) 34#define PB44_KEYS_DEBOUNCE_INTERVAL (3 * PB44_KEYS_POLL_INTERVAL)
35 35
36static struct i2c_gpio_platform_data pb44_i2c_gpio_data = { 36static struct i2c_gpio_platform_data pb44_i2c_gpio_data = {
37 .sda_pin = PB44_GPIO_I2C_SDA, 37 .sda_pin = PB44_GPIO_I2C_SDA,
38 .scl_pin = PB44_GPIO_I2C_SCL, 38 .scl_pin = PB44_GPIO_I2C_SCL,
39}; 39};
40 40
41static struct platform_device pb44_i2c_gpio_device = { 41static struct platform_device pb44_i2c_gpio_device = {
@@ -53,7 +53,7 @@ static struct pcf857x_platform_data pb44_pcf857x_data = {
53static struct i2c_board_info pb44_i2c_board_info[] __initdata = { 53static struct i2c_board_info pb44_i2c_board_info[] __initdata = {
54 { 54 {
55 I2C_BOARD_INFO("pcf8575", 0x20), 55 I2C_BOARD_INFO("pcf8575", 0x20),
56 .platform_data = &pb44_pcf857x_data, 56 .platform_data = &pb44_pcf857x_data,
57 }, 57 },
58}; 58};
59 59
diff --git a/arch/mips/ath79/machtypes.h b/arch/mips/ath79/machtypes.h
index af92e5c30d66..26254058c545 100644
--- a/arch/mips/ath79/machtypes.h
+++ b/arch/mips/ath79/machtypes.h
@@ -17,6 +17,7 @@
17enum ath79_mach_type { 17enum ath79_mach_type {
18 ATH79_MACH_GENERIC = 0, 18 ATH79_MACH_GENERIC = 0,
19 ATH79_MACH_AP121, /* Atheros AP121 reference board */ 19 ATH79_MACH_AP121, /* Atheros AP121 reference board */
20 ATH79_MACH_AP136_010, /* Atheros AP136-010 reference board */
20 ATH79_MACH_AP81, /* Atheros AP81 reference board */ 21 ATH79_MACH_AP81, /* Atheros AP81 reference board */
21 ATH79_MACH_DB120, /* Atheros DB120 reference board */ 22 ATH79_MACH_DB120, /* Atheros DB120 reference board */
22 ATH79_MACH_PB44, /* Atheros PB44 reference board */ 23 ATH79_MACH_PB44, /* Atheros PB44 reference board */
diff --git a/arch/mips/ath79/pci.c b/arch/mips/ath79/pci.c
index ca83abd9d31e..730c0b03060d 100644
--- a/arch/mips/ath79/pci.c
+++ b/arch/mips/ath79/pci.c
@@ -14,10 +14,11 @@
14 14
15#include <linux/init.h> 15#include <linux/init.h>
16#include <linux/pci.h> 16#include <linux/pci.h>
17#include <linux/resource.h>
18#include <linux/platform_device.h>
17#include <asm/mach-ath79/ar71xx_regs.h> 19#include <asm/mach-ath79/ar71xx_regs.h>
18#include <asm/mach-ath79/ath79.h> 20#include <asm/mach-ath79/ath79.h>
19#include <asm/mach-ath79/irq.h> 21#include <asm/mach-ath79/irq.h>
20#include <asm/mach-ath79/pci.h>
21#include "pci.h" 22#include "pci.h"
22 23
23static int (*ath79_pci_plat_dev_init)(struct pci_dev *dev); 24static int (*ath79_pci_plat_dev_init)(struct pci_dev *dev);
@@ -48,6 +49,21 @@ static const struct ath79_pci_irq ar724x_pci_irq_map[] __initconst = {
48 } 49 }
49}; 50};
50 51
52static const struct ath79_pci_irq qca955x_pci_irq_map[] __initconst = {
53 {
54 .bus = 0,
55 .slot = 0,
56 .pin = 1,
57 .irq = ATH79_PCI_IRQ(0),
58 },
59 {
60 .bus = 1,
61 .slot = 0,
62 .pin = 1,
63 .irq = ATH79_PCI_IRQ(1),
64 },
65};
66
51int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin) 67int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin)
52{ 68{
53 int irq = -1; 69 int irq = -1;
@@ -63,6 +79,9 @@ int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin)
63 soc_is_ar9344()) { 79 soc_is_ar9344()) {
64 ath79_pci_irq_map = ar724x_pci_irq_map; 80 ath79_pci_irq_map = ar724x_pci_irq_map;
65 ath79_pci_nr_irqs = ARRAY_SIZE(ar724x_pci_irq_map); 81 ath79_pci_nr_irqs = ARRAY_SIZE(ar724x_pci_irq_map);
82 } else if (soc_is_qca955x()) {
83 ath79_pci_irq_map = qca955x_pci_irq_map;
84 ath79_pci_nr_irqs = ARRAY_SIZE(qca955x_pci_irq_map);
66 } else { 85 } else {
67 pr_crit("pci %s: invalid irq map\n", 86 pr_crit("pci %s: invalid irq map\n",
68 pci_name((struct pci_dev *) dev)); 87 pci_name((struct pci_dev *) dev));
@@ -74,7 +93,9 @@ int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin)
74 const struct ath79_pci_irq *entry; 93 const struct ath79_pci_irq *entry;
75 94
76 entry = &ath79_pci_irq_map[i]; 95 entry = &ath79_pci_irq_map[i];
77 if (entry->slot == slot && entry->pin == pin) { 96 if (entry->bus == dev->bus->number &&
97 entry->slot == slot &&
98 entry->pin == pin) {
78 irq = entry->irq; 99 irq = entry->irq;
79 break; 100 break;
80 } 101 }
@@ -110,21 +131,143 @@ void __init ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *dev))
110 ath79_pci_plat_dev_init = func; 131 ath79_pci_plat_dev_init = func;
111} 132}
112 133
113int __init ath79_register_pci(void) 134static struct platform_device *
135ath79_register_pci_ar71xx(void)
136{
137 struct platform_device *pdev;
138 struct resource res[4];
139
140 memset(res, 0, sizeof(res));
141
142 res[0].name = "cfg_base";
143 res[0].flags = IORESOURCE_MEM;
144 res[0].start = AR71XX_PCI_CFG_BASE;
145 res[0].end = AR71XX_PCI_CFG_BASE + AR71XX_PCI_CFG_SIZE - 1;
146
147 res[1].flags = IORESOURCE_IRQ;
148 res[1].start = ATH79_CPU_IRQ(2);
149 res[1].end = ATH79_CPU_IRQ(2);
150
151 res[2].name = "io_base";
152 res[2].flags = IORESOURCE_IO;
153 res[2].start = 0;
154 res[2].end = 0;
155
156 res[3].name = "mem_base";
157 res[3].flags = IORESOURCE_MEM;
158 res[3].start = AR71XX_PCI_MEM_BASE;
159 res[3].end = AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1;
160
161 pdev = platform_device_register_simple("ar71xx-pci", -1,
162 res, ARRAY_SIZE(res));
163 return pdev;
164}
165
166static struct platform_device *
167ath79_register_pci_ar724x(int id,
168 unsigned long cfg_base,
169 unsigned long ctrl_base,
170 unsigned long crp_base,
171 unsigned long mem_base,
172 unsigned long mem_size,
173 unsigned long io_base,
174 int irq)
114{ 175{
115 if (soc_is_ar71xx()) 176 struct platform_device *pdev;
116 return ar71xx_pcibios_init(); 177 struct resource res[6];
178
179 memset(res, 0, sizeof(res));
180
181 res[0].name = "cfg_base";
182 res[0].flags = IORESOURCE_MEM;
183 res[0].start = cfg_base;
184 res[0].end = cfg_base + AR724X_PCI_CFG_SIZE - 1;
185
186 res[1].name = "ctrl_base";
187 res[1].flags = IORESOURCE_MEM;
188 res[1].start = ctrl_base;
189 res[1].end = ctrl_base + AR724X_PCI_CTRL_SIZE - 1;
190
191 res[2].flags = IORESOURCE_IRQ;
192 res[2].start = irq;
193 res[2].end = irq;
194
195 res[3].name = "mem_base";
196 res[3].flags = IORESOURCE_MEM;
197 res[3].start = mem_base;
198 res[3].end = mem_base + mem_size - 1;
199
200 res[4].name = "io_base";
201 res[4].flags = IORESOURCE_IO;
202 res[4].start = io_base;
203 res[4].end = io_base;
117 204
118 if (soc_is_ar724x()) 205 res[5].name = "crp_base";
119 return ar724x_pcibios_init(ATH79_CPU_IRQ_IP2); 206 res[5].flags = IORESOURCE_MEM;
207 res[5].start = crp_base;
208 res[5].end = crp_base + AR724X_PCI_CRP_SIZE - 1;
120 209
121 if (soc_is_ar9342() || soc_is_ar9344()) { 210 pdev = platform_device_register_simple("ar724x-pci", id,
211 res, ARRAY_SIZE(res));
212 return pdev;
213}
214
215int __init ath79_register_pci(void)
216{
217 struct platform_device *pdev = NULL;
218
219 if (soc_is_ar71xx()) {
220 pdev = ath79_register_pci_ar71xx();
221 } else if (soc_is_ar724x()) {
222 pdev = ath79_register_pci_ar724x(-1,
223 AR724X_PCI_CFG_BASE,
224 AR724X_PCI_CTRL_BASE,
225 AR724X_PCI_CRP_BASE,
226 AR724X_PCI_MEM_BASE,
227 AR724X_PCI_MEM_SIZE,
228 0,
229 ATH79_CPU_IRQ(2));
230 } else if (soc_is_ar9342() ||
231 soc_is_ar9344()) {
122 u32 bootstrap; 232 u32 bootstrap;
123 233
124 bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP); 234 bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
125 if (bootstrap & AR934X_BOOTSTRAP_PCIE_RC) 235 if ((bootstrap & AR934X_BOOTSTRAP_PCIE_RC) == 0)
126 return ar724x_pcibios_init(ATH79_IP2_IRQ(0)); 236 return -ENODEV;
237
238 pdev = ath79_register_pci_ar724x(-1,
239 AR724X_PCI_CFG_BASE,
240 AR724X_PCI_CTRL_BASE,
241 AR724X_PCI_CRP_BASE,
242 AR724X_PCI_MEM_BASE,
243 AR724X_PCI_MEM_SIZE,
244 0,
245 ATH79_IP2_IRQ(0));
246 } else if (soc_is_qca9558()) {
247 pdev = ath79_register_pci_ar724x(0,
248 QCA955X_PCI_CFG_BASE0,
249 QCA955X_PCI_CTRL_BASE0,
250 QCA955X_PCI_CRP_BASE0,
251 QCA955X_PCI_MEM_BASE0,
252 QCA955X_PCI_MEM_SIZE,
253 0,
254 ATH79_IP2_IRQ(0));
255
256 pdev = ath79_register_pci_ar724x(1,
257 QCA955X_PCI_CFG_BASE1,
258 QCA955X_PCI_CTRL_BASE1,
259 QCA955X_PCI_CRP_BASE1,
260 QCA955X_PCI_MEM_BASE1,
261 QCA955X_PCI_MEM_SIZE,
262 1,
263 ATH79_IP3_IRQ(2));
264 } else {
265 /* No PCI support */
266 return -ENODEV;
127 } 267 }
128 268
129 return -ENODEV; 269 if (!pdev)
270 pr_err("unable to register PCI controller device\n");
271
272 return pdev ? 0 : -ENODEV;
130} 273}
diff --git a/arch/mips/ath79/pci.h b/arch/mips/ath79/pci.h
index 51c6625dcc6d..1d00a3803c37 100644
--- a/arch/mips/ath79/pci.h
+++ b/arch/mips/ath79/pci.h
@@ -14,6 +14,7 @@
14#define _ATH79_PCI_H 14#define _ATH79_PCI_H
15 15
16struct ath79_pci_irq { 16struct ath79_pci_irq {
17 int bus;
17 u8 slot; 18 u8 slot;
18 u8 pin; 19 u8 pin;
19 int irq; 20 int irq;
diff --git a/arch/mips/ath79/setup.c b/arch/mips/ath79/setup.c
index 60d212ef8629..d5b3c9057018 100644
--- a/arch/mips/ath79/setup.c
+++ b/arch/mips/ath79/setup.c
@@ -164,13 +164,29 @@ static void __init ath79_detect_sys_type(void)
164 rev = id & AR934X_REV_ID_REVISION_MASK; 164 rev = id & AR934X_REV_ID_REVISION_MASK;
165 break; 165 break;
166 166
167 case REV_ID_MAJOR_QCA9556:
168 ath79_soc = ATH79_SOC_QCA9556;
169 chip = "9556";
170 rev = id & QCA955X_REV_ID_REVISION_MASK;
171 break;
172
173 case REV_ID_MAJOR_QCA9558:
174 ath79_soc = ATH79_SOC_QCA9558;
175 chip = "9558";
176 rev = id & QCA955X_REV_ID_REVISION_MASK;
177 break;
178
167 default: 179 default:
168 panic("ath79: unknown SoC, id:0x%08x", id); 180 panic("ath79: unknown SoC, id:0x%08x", id);
169 } 181 }
170 182
171 ath79_soc_rev = rev; 183 ath79_soc_rev = rev;
172 184
173 sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev); 185 if (soc_is_qca955x())
186 sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u",
187 chip, rev);
188 else
189 sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
174 pr_info("SoC: %s\n", ath79_sys_type); 190 pr_info("SoC: %s\n", ath79_sys_type);
175} 191}
176 192
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-05 21:48:00 -0500