1 files changed, 17 insertions, 6 deletions

diff --git a/arch/mips/ath79/setup.c b/arch/mips/ath79/setup.c
index 80f4ecd42b0d..64807a4809d0 100644
--- a/arch/mips/ath79/setup.c
+++ b/arch/mips/ath79/setup.c
@@ -200,7 +200,6 @@ void __init plat_mem_setup(void)
 
         ath79_detect_sys_type();
         detect_memory_region(0, ATH79_MEM_SIZE_MIN, ATH79_MEM_SIZE_MAX);
-        ath79_clocks_init();
 
         _machine_restart = ath79_restart;
         _machine_halt = ath79_halt;
@@ -209,13 +208,25 @@ void __init plat_mem_setup(void)
 
 void __init plat_time_init(void)
 {
-        struct clk *clk;
+        unsigned long cpu_clk_rate;
+        unsigned long ahb_clk_rate;
+        unsigned long ddr_clk_rate;
+        unsigned long ref_clk_rate;
+
+        ath79_clocks_init();
+
+        cpu_clk_rate = ath79_get_sys_clk_rate("cpu");
+        ahb_clk_rate = ath79_get_sys_clk_rate("ahb");
+        ddr_clk_rate = ath79_get_sys_clk_rate("ddr");
+        ref_clk_rate = ath79_get_sys_clk_rate("ref");
 
-        clk = clk_get(NULL, "cpu");
-        if (IS_ERR(clk))
-                panic("unable to get CPU clock, err=%ld", PTR_ERR(clk));
+        pr_info("Clocks: CPU:%lu.%03luMHz, DDR:%lu.%03luMHz, AHB:%lu.%03luMHz, Ref:%lu.%03luMHz",
+                cpu_clk_rate / 1000000, (cpu_clk_rate / 1000) % 1000,
+                ddr_clk_rate / 1000000, (ddr_clk_rate / 1000) % 1000,
+                ahb_clk_rate / 1000000, (ahb_clk_rate / 1000) % 1000,
+                ref_clk_rate / 1000000, (ref_clk_rate / 1000) % 1000);
 
-        mips_hpt_frequency = clk_get_rate(clk) / 2;
+        mips_hpt_frequency = cpu_clk_rate / 2;
 }
 
 static int __init ath79_setup(void)