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-rw-r--r--arch/mips/ath25/Kconfig16
-rw-r--r--arch/mips/ath25/Makefile16
-rw-r--r--arch/mips/ath25/Platform6
-rw-r--r--arch/mips/ath25/ar2315.c364
-rw-r--r--arch/mips/ath25/ar2315.h22
-rw-r--r--arch/mips/ath25/ar2315_regs.h410
-rw-r--r--arch/mips/ath25/ar5312.c393
-rw-r--r--arch/mips/ath25/ar5312.h22
-rw-r--r--arch/mips/ath25/ar5312_regs.h224
-rw-r--r--arch/mips/ath25/board.c234
-rw-r--r--arch/mips/ath25/devices.c125
-rw-r--r--arch/mips/ath25/devices.h43
-rw-r--r--arch/mips/ath25/early_printk.c44
-rw-r--r--arch/mips/ath25/prom.c26
14 files changed, 1945 insertions, 0 deletions
diff --git a/arch/mips/ath25/Kconfig b/arch/mips/ath25/Kconfig
new file mode 100644
index 000000000000..fc19dd57e42d
--- /dev/null
+++ b/arch/mips/ath25/Kconfig
@@ -0,0 +1,16 @@
1config SOC_AR5312
2 bool "Atheros AR5312/AR2312+ SoC support"
3 depends on ATH25
4 default y
5
6config SOC_AR2315
7 bool "Atheros AR2315+ SoC support"
8 depends on ATH25
9 default y
10
11config PCI_AR2315
12 bool "Atheros AR2315 PCI controller support"
13 depends on SOC_AR2315
14 select HW_HAS_PCI
15 select PCI
16 default y
diff --git a/arch/mips/ath25/Makefile b/arch/mips/ath25/Makefile
new file mode 100644
index 000000000000..eabad7da446a
--- /dev/null
+++ b/arch/mips/ath25/Makefile
@@ -0,0 +1,16 @@
1#
2# This file is subject to the terms and conditions of the GNU General Public
3# License. See the file "COPYING" in the main directory of this archive
4# for more details.
5#
6# Copyright (C) 2006 FON Technology, SL.
7# Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
8# Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
9#
10
11obj-y += board.o prom.o devices.o
12
13obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
14
15obj-$(CONFIG_SOC_AR5312) += ar5312.o
16obj-$(CONFIG_SOC_AR2315) += ar2315.o
diff --git a/arch/mips/ath25/Platform b/arch/mips/ath25/Platform
new file mode 100644
index 000000000000..ef3f81fa080b
--- /dev/null
+++ b/arch/mips/ath25/Platform
@@ -0,0 +1,6 @@
1#
2# Atheros AR531X/AR231X WiSoC
3#
4platform-$(CONFIG_ATH25) += ath25/
5cflags-$(CONFIG_ATH25) += -I$(srctree)/arch/mips/include/asm/mach-ath25
6load-$(CONFIG_ATH25) += 0xffffffff80041000
diff --git a/arch/mips/ath25/ar2315.c b/arch/mips/ath25/ar2315.c
new file mode 100644
index 000000000000..2befa7d766a6
--- /dev/null
+++ b/arch/mips/ath25/ar2315.c
@@ -0,0 +1,364 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
7 * Copyright (C) 2006 FON Technology, SL.
8 * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
9 * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
10 * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
11 */
12
13/*
14 * Platform devices for Atheros AR2315 SoCs
15 */
16
17#include <linux/init.h>
18#include <linux/kernel.h>
19#include <linux/bitops.h>
20#include <linux/irqdomain.h>
21#include <linux/interrupt.h>
22#include <linux/platform_device.h>
23#include <linux/reboot.h>
24#include <asm/bootinfo.h>
25#include <asm/reboot.h>
26#include <asm/time.h>
27
28#include <ath25_platform.h>
29
30#include "devices.h"
31#include "ar2315.h"
32#include "ar2315_regs.h"
33
34static void __iomem *ar2315_rst_base;
35static struct irq_domain *ar2315_misc_irq_domain;
36
37static inline u32 ar2315_rst_reg_read(u32 reg)
38{
39 return __raw_readl(ar2315_rst_base + reg);
40}
41
42static inline void ar2315_rst_reg_write(u32 reg, u32 val)
43{
44 __raw_writel(val, ar2315_rst_base + reg);
45}
46
47static inline void ar2315_rst_reg_mask(u32 reg, u32 mask, u32 val)
48{
49 u32 ret = ar2315_rst_reg_read(reg);
50
51 ret &= ~mask;
52 ret |= val;
53 ar2315_rst_reg_write(reg, ret);
54}
55
56static irqreturn_t ar2315_ahb_err_handler(int cpl, void *dev_id)
57{
58 ar2315_rst_reg_write(AR2315_AHB_ERR0, AR2315_AHB_ERROR_DET);
59 ar2315_rst_reg_read(AR2315_AHB_ERR1);
60
61 pr_emerg("AHB fatal error\n");
62 machine_restart("AHB error"); /* Catastrophic failure */
63
64 return IRQ_HANDLED;
65}
66
67static struct irqaction ar2315_ahb_err_interrupt = {
68 .handler = ar2315_ahb_err_handler,
69 .name = "ar2315-ahb-error",
70};
71
72static void ar2315_misc_irq_handler(unsigned irq, struct irq_desc *desc)
73{
74 u32 pending = ar2315_rst_reg_read(AR2315_ISR) &
75 ar2315_rst_reg_read(AR2315_IMR);
76 unsigned nr, misc_irq = 0;
77
78 if (pending) {
79 struct irq_domain *domain = irq_get_handler_data(irq);
80
81 nr = __ffs(pending);
82 misc_irq = irq_find_mapping(domain, nr);
83 }
84
85 if (misc_irq) {
86 if (nr == AR2315_MISC_IRQ_GPIO)
87 ar2315_rst_reg_write(AR2315_ISR, AR2315_ISR_GPIO);
88 else if (nr == AR2315_MISC_IRQ_WATCHDOG)
89 ar2315_rst_reg_write(AR2315_ISR, AR2315_ISR_WD);
90 generic_handle_irq(misc_irq);
91 } else {
92 spurious_interrupt();
93 }
94}
95
96static void ar2315_misc_irq_unmask(struct irq_data *d)
97{
98 ar2315_rst_reg_mask(AR2315_IMR, 0, BIT(d->hwirq));
99}
100
101static void ar2315_misc_irq_mask(struct irq_data *d)
102{
103 ar2315_rst_reg_mask(AR2315_IMR, BIT(d->hwirq), 0);
104}
105
106static struct irq_chip ar2315_misc_irq_chip = {
107 .name = "ar2315-misc",
108 .irq_unmask = ar2315_misc_irq_unmask,
109 .irq_mask = ar2315_misc_irq_mask,
110};
111
112static int ar2315_misc_irq_map(struct irq_domain *d, unsigned irq,
113 irq_hw_number_t hw)
114{
115 irq_set_chip_and_handler(irq, &ar2315_misc_irq_chip, handle_level_irq);
116 return 0;
117}
118
119static struct irq_domain_ops ar2315_misc_irq_domain_ops = {
120 .map = ar2315_misc_irq_map,
121};
122
123/*
124 * Called when an interrupt is received, this function
125 * determines exactly which interrupt it was, and it
126 * invokes the appropriate handler.
127 *
128 * Implicitly, we also define interrupt priority by
129 * choosing which to dispatch first.
130 */
131static void ar2315_irq_dispatch(void)
132{
133 u32 pending = read_c0_status() & read_c0_cause();
134
135 if (pending & CAUSEF_IP3)
136 do_IRQ(AR2315_IRQ_WLAN0);
137#ifdef CONFIG_PCI_AR2315
138 else if (pending & CAUSEF_IP5)
139 do_IRQ(AR2315_IRQ_LCBUS_PCI);
140#endif
141 else if (pending & CAUSEF_IP2)
142 do_IRQ(AR2315_IRQ_MISC);
143 else if (pending & CAUSEF_IP7)
144 do_IRQ(ATH25_IRQ_CPU_CLOCK);
145 else
146 spurious_interrupt();
147}
148
149void __init ar2315_arch_init_irq(void)
150{
151 struct irq_domain *domain;
152 unsigned irq;
153
154 ath25_irq_dispatch = ar2315_irq_dispatch;
155
156 domain = irq_domain_add_linear(NULL, AR2315_MISC_IRQ_COUNT,
157 &ar2315_misc_irq_domain_ops, NULL);
158 if (!domain)
159 panic("Failed to add IRQ domain");
160
161 irq = irq_create_mapping(domain, AR2315_MISC_IRQ_AHB);
162 setup_irq(irq, &ar2315_ahb_err_interrupt);
163
164 irq_set_chained_handler(AR2315_IRQ_MISC, ar2315_misc_irq_handler);
165 irq_set_handler_data(AR2315_IRQ_MISC, domain);
166
167 ar2315_misc_irq_domain = domain;
168}
169
170void __init ar2315_init_devices(void)
171{
172 /* Find board configuration */
173 ath25_find_config(AR2315_SPI_READ_BASE, AR2315_SPI_READ_SIZE);
174
175 ath25_add_wmac(0, AR2315_WLAN0_BASE, AR2315_IRQ_WLAN0);
176}
177
178static void ar2315_restart(char *command)
179{
180 void (*mips_reset_vec)(void) = (void *)0xbfc00000;
181
182 local_irq_disable();
183
184 /* try reset the system via reset control */
185 ar2315_rst_reg_write(AR2315_COLD_RESET, AR2317_RESET_SYSTEM);
186
187 /* Cold reset does not work on the AR2315/6, use the GPIO reset bits
188 * a workaround. Give it some time to attempt a gpio based hardware
189 * reset (atheros reference design workaround) */
190
191 /* TODO: implement the GPIO reset workaround */
192
193 /* Some boards (e.g. Senao EOC-2610) don't implement the reset logic
194 * workaround. Attempt to jump to the mips reset location -
195 * the boot loader itself might be able to recover the system */
196 mips_reset_vec();
197}
198
199/*
200 * This table is indexed by bits 5..4 of the CLOCKCTL1 register
201 * to determine the predevisor value.
202 */
203static int clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
204static int pllc_divide_table[5] __initdata = { 2, 3, 4, 6, 3 };
205
206static unsigned __init ar2315_sys_clk(u32 clock_ctl)
207{
208 unsigned int pllc_ctrl, cpu_div;
209 unsigned int pllc_out, refdiv, fdiv, divby2;
210 unsigned int clk_div;
211
212 pllc_ctrl = ar2315_rst_reg_read(AR2315_PLLC_CTL);
213 refdiv = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_REF_DIV);
214 refdiv = clockctl1_predivide_table[refdiv];
215 fdiv = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_FDBACK_DIV);
216 divby2 = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_ADD_FDBACK_DIV) + 1;
217 pllc_out = (40000000 / refdiv) * (2 * divby2) * fdiv;
218
219 /* clkm input selected */
220 switch (clock_ctl & AR2315_CPUCLK_CLK_SEL_M) {
221 case 0:
222 case 1:
223 clk_div = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_CLKM_DIV);
224 clk_div = pllc_divide_table[clk_div];
225 break;
226 case 2:
227 clk_div = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_CLKC_DIV);
228 clk_div = pllc_divide_table[clk_div];
229 break;
230 default:
231 pllc_out = 40000000;
232 clk_div = 1;
233 break;
234 }
235
236 cpu_div = ATH25_REG_MS(clock_ctl, AR2315_CPUCLK_CLK_DIV);
237 cpu_div = cpu_div * 2 ?: 1;
238
239 return pllc_out / (clk_div * cpu_div);
240}
241
242static inline unsigned ar2315_cpu_frequency(void)
243{
244 return ar2315_sys_clk(ar2315_rst_reg_read(AR2315_CPUCLK));
245}
246
247static inline unsigned ar2315_apb_frequency(void)
248{
249 return ar2315_sys_clk(ar2315_rst_reg_read(AR2315_AMBACLK));
250}
251
252void __init ar2315_plat_time_init(void)
253{
254 mips_hpt_frequency = ar2315_cpu_frequency() / 2;
255}
256
257void __init ar2315_plat_mem_setup(void)
258{
259 void __iomem *sdram_base;
260 u32 memsize, memcfg;
261 u32 devid;
262 u32 config;
263
264 /* Detect memory size */
265 sdram_base = ioremap_nocache(AR2315_SDRAMCTL_BASE,
266 AR2315_SDRAMCTL_SIZE);
267 memcfg = __raw_readl(sdram_base + AR2315_MEM_CFG);
268 memsize = 1 + ATH25_REG_MS(memcfg, AR2315_MEM_CFG_DATA_WIDTH);
269 memsize <<= 1 + ATH25_REG_MS(memcfg, AR2315_MEM_CFG_COL_WIDTH);
270 memsize <<= 1 + ATH25_REG_MS(memcfg, AR2315_MEM_CFG_ROW_WIDTH);
271 memsize <<= 3;
272 add_memory_region(0, memsize, BOOT_MEM_RAM);
273 iounmap(sdram_base);
274
275 ar2315_rst_base = ioremap_nocache(AR2315_RST_BASE, AR2315_RST_SIZE);
276
277 /* Detect the hardware based on the device ID */
278 devid = ar2315_rst_reg_read(AR2315_SREV) & AR2315_REV_CHIP;
279 switch (devid) {
280 case 0x91: /* Need to check */
281 ath25_soc = ATH25_SOC_AR2318;
282 break;
283 case 0x90:
284 ath25_soc = ATH25_SOC_AR2317;
285 break;
286 case 0x87:
287 ath25_soc = ATH25_SOC_AR2316;
288 break;
289 case 0x86:
290 default:
291 ath25_soc = ATH25_SOC_AR2315;
292 break;
293 }
294 ath25_board.devid = devid;
295
296 /* Clear any lingering AHB errors */
297 config = read_c0_config();
298 write_c0_config(config & ~0x3);
299 ar2315_rst_reg_write(AR2315_AHB_ERR0, AR2315_AHB_ERROR_DET);
300 ar2315_rst_reg_read(AR2315_AHB_ERR1);
301 ar2315_rst_reg_write(AR2315_WDT_CTRL, AR2315_WDT_CTRL_IGNORE);
302
303 _machine_restart = ar2315_restart;
304}
305
306#ifdef CONFIG_PCI_AR2315
307static struct resource ar2315_pci_res[] = {
308 {
309 .name = "ar2315-pci-ctrl",
310 .flags = IORESOURCE_MEM,
311 .start = AR2315_PCI_BASE,
312 .end = AR2315_PCI_BASE + AR2315_PCI_SIZE - 1,
313 },
314 {
315 .name = "ar2315-pci-ext",
316 .flags = IORESOURCE_MEM,
317 .start = AR2315_PCI_EXT_BASE,
318 .end = AR2315_PCI_EXT_BASE + AR2315_PCI_EXT_SIZE - 1,
319 },
320 {
321 .name = "ar2315-pci",
322 .flags = IORESOURCE_IRQ,
323 .start = AR2315_IRQ_LCBUS_PCI,
324 .end = AR2315_IRQ_LCBUS_PCI,
325 },
326};
327#endif
328
329void __init ar2315_arch_init(void)
330{
331 unsigned irq = irq_create_mapping(ar2315_misc_irq_domain,
332 AR2315_MISC_IRQ_UART0);
333
334 ath25_serial_setup(AR2315_UART0_BASE, irq, ar2315_apb_frequency());
335
336#ifdef CONFIG_PCI_AR2315
337 if (ath25_soc == ATH25_SOC_AR2315) {
338 /* Reset PCI DMA logic */
339 ar2315_rst_reg_mask(AR2315_RESET, 0, AR2315_RESET_PCIDMA);
340 msleep(20);
341 ar2315_rst_reg_mask(AR2315_RESET, AR2315_RESET_PCIDMA, 0);
342 msleep(20);
343
344 /* Configure endians */
345 ar2315_rst_reg_mask(AR2315_ENDIAN_CTL, 0, AR2315_CONFIG_PCIAHB |
346 AR2315_CONFIG_PCIAHB_BRIDGE);
347
348 /* Configure as PCI host with DMA */
349 ar2315_rst_reg_write(AR2315_PCICLK, AR2315_PCICLK_PLLC_CLKM |
350 (AR2315_PCICLK_IN_FREQ_DIV_6 <<
351 AR2315_PCICLK_DIV_S));
352 ar2315_rst_reg_mask(AR2315_AHB_ARB_CTL, 0, AR2315_ARB_PCI);
353 ar2315_rst_reg_mask(AR2315_IF_CTL, AR2315_IF_PCI_CLK_MASK |
354 AR2315_IF_MASK, AR2315_IF_PCI |
355 AR2315_IF_PCI_HOST | AR2315_IF_PCI_INTR |
356 (AR2315_IF_PCI_CLK_OUTPUT_CLK <<
357 AR2315_IF_PCI_CLK_SHIFT));
358
359 platform_device_register_simple("ar2315-pci", -1,
360 ar2315_pci_res,
361 ARRAY_SIZE(ar2315_pci_res));
362 }
363#endif
364}
diff --git a/arch/mips/ath25/ar2315.h b/arch/mips/ath25/ar2315.h
new file mode 100644
index 000000000000..877afe63eed5
--- /dev/null
+++ b/arch/mips/ath25/ar2315.h
@@ -0,0 +1,22 @@
1#ifndef __AR2315_H
2#define __AR2315_H
3
4#ifdef CONFIG_SOC_AR2315
5
6void ar2315_arch_init_irq(void);
7void ar2315_init_devices(void);
8void ar2315_plat_time_init(void);
9void ar2315_plat_mem_setup(void);
10void ar2315_arch_init(void);
11
12#else
13
14static inline void ar2315_arch_init_irq(void) {}
15static inline void ar2315_init_devices(void) {}
16static inline void ar2315_plat_time_init(void) {}
17static inline void ar2315_plat_mem_setup(void) {}
18static inline void ar2315_arch_init(void) {}
19
20#endif
21
22#endif /* __AR2315_H */
diff --git a/arch/mips/ath25/ar2315_regs.h b/arch/mips/ath25/ar2315_regs.h
new file mode 100644
index 000000000000..16e86149cb74
--- /dev/null
+++ b/arch/mips/ath25/ar2315_regs.h
@@ -0,0 +1,410 @@
1/*
2 * Register definitions for AR2315+
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
9 * Copyright (C) 2006 FON Technology, SL.
10 * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
11 * Copyright (C) 2006-2008 Felix Fietkau <nbd@openwrt.org>
12 */
13
14#ifndef __ASM_MACH_ATH25_AR2315_REGS_H
15#define __ASM_MACH_ATH25_AR2315_REGS_H
16
17/*
18 * IRQs
19 */
20#define AR2315_IRQ_MISC (MIPS_CPU_IRQ_BASE + 2) /* C0_CAUSE: 0x0400 */
21#define AR2315_IRQ_WLAN0 (MIPS_CPU_IRQ_BASE + 3) /* C0_CAUSE: 0x0800 */
22#define AR2315_IRQ_ENET0 (MIPS_CPU_IRQ_BASE + 4) /* C0_CAUSE: 0x1000 */
23#define AR2315_IRQ_LCBUS_PCI (MIPS_CPU_IRQ_BASE + 5) /* C0_CAUSE: 0x2000 */
24#define AR2315_IRQ_WLAN0_POLL (MIPS_CPU_IRQ_BASE + 6) /* C0_CAUSE: 0x4000 */
25
26/*
27 * Miscellaneous interrupts, which share IP2.
28 */
29#define AR2315_MISC_IRQ_UART0 0
30#define AR2315_MISC_IRQ_I2C_RSVD 1
31#define AR2315_MISC_IRQ_SPI 2
32#define AR2315_MISC_IRQ_AHB 3
33#define AR2315_MISC_IRQ_APB 4
34#define AR2315_MISC_IRQ_TIMER 5
35#define AR2315_MISC_IRQ_GPIO 6
36#define AR2315_MISC_IRQ_WATCHDOG 7
37#define AR2315_MISC_IRQ_IR_RSVD 8
38#define AR2315_MISC_IRQ_COUNT 9
39
40/*
41 * Address map
42 */
43#define AR2315_SPI_READ_BASE 0x08000000 /* SPI flash */
44#define AR2315_SPI_READ_SIZE 0x01000000
45#define AR2315_WLAN0_BASE 0x10000000 /* Wireless MMR */
46#define AR2315_PCI_BASE 0x10100000 /* PCI MMR */
47#define AR2315_PCI_SIZE 0x00001000
48#define AR2315_SDRAMCTL_BASE 0x10300000 /* SDRAM MMR */
49#define AR2315_SDRAMCTL_SIZE 0x00000020
50#define AR2315_LOCAL_BASE 0x10400000 /* Local bus MMR */
51#define AR2315_ENET0_BASE 0x10500000 /* Ethernet MMR */
52#define AR2315_RST_BASE 0x11000000 /* Reset control MMR */
53#define AR2315_RST_SIZE 0x00000100
54#define AR2315_UART0_BASE 0x11100000 /* UART MMR */
55#define AR2315_SPI_MMR_BASE 0x11300000 /* SPI flash MMR */
56#define AR2315_SPI_MMR_SIZE 0x00000010
57#define AR2315_PCI_EXT_BASE 0x80000000 /* PCI external */
58#define AR2315_PCI_EXT_SIZE 0x40000000
59
60/*
61 * Configuration registers
62 */
63
64/* Cold reset register */
65#define AR2315_COLD_RESET 0x0000
66
67#define AR2315_RESET_COLD_AHB 0x00000001
68#define AR2315_RESET_COLD_APB 0x00000002
69#define AR2315_RESET_COLD_CPU 0x00000004
70#define AR2315_RESET_COLD_CPUWARM 0x00000008
71#define AR2315_RESET_SYSTEM (RESET_COLD_CPU |\
72 RESET_COLD_APB |\
73 RESET_COLD_AHB) /* full system */
74#define AR2317_RESET_SYSTEM 0x00000010
75
76/* Reset register */
77#define AR2315_RESET 0x0004
78
79#define AR2315_RESET_WARM_WLAN0_MAC 0x00000001 /* warm reset WLAN0 MAC */
80#define AR2315_RESET_WARM_WLAN0_BB 0x00000002 /* warm reset WLAN0 BB */
81#define AR2315_RESET_MPEGTS_RSVD 0x00000004 /* warm reset MPEG-TS */
82#define AR2315_RESET_PCIDMA 0x00000008 /* warm reset PCI ahb/dma */
83#define AR2315_RESET_MEMCTL 0x00000010 /* warm reset mem control */
84#define AR2315_RESET_LOCAL 0x00000020 /* warm reset local bus */
85#define AR2315_RESET_I2C_RSVD 0x00000040 /* warm reset I2C bus */
86#define AR2315_RESET_SPI 0x00000080 /* warm reset SPI iface */
87#define AR2315_RESET_UART0 0x00000100 /* warm reset UART0 */
88#define AR2315_RESET_IR_RSVD 0x00000200 /* warm reset IR iface */
89#define AR2315_RESET_EPHY0 0x00000400 /* cold reset ENET0 phy */
90#define AR2315_RESET_ENET0 0x00000800 /* cold reset ENET0 MAC */
91
92/* AHB master arbitration control */
93#define AR2315_AHB_ARB_CTL 0x0008
94
95#define AR2315_ARB_CPU 0x00000001 /* CPU, default */
96#define AR2315_ARB_WLAN 0x00000002 /* WLAN */
97#define AR2315_ARB_MPEGTS_RSVD 0x00000004 /* MPEG-TS */
98#define AR2315_ARB_LOCAL 0x00000008 /* Local bus */
99#define AR2315_ARB_PCI 0x00000010 /* PCI bus */
100#define AR2315_ARB_ETHERNET 0x00000020 /* Ethernet */
101#define AR2315_ARB_RETRY 0x00000100 /* Retry policy (debug) */
102
103/* Config Register */
104#define AR2315_ENDIAN_CTL 0x000c
105
106#define AR2315_CONFIG_AHB 0x00000001 /* EC-AHB bridge endian */
107#define AR2315_CONFIG_WLAN 0x00000002 /* WLAN byteswap */
108#define AR2315_CONFIG_MPEGTS_RSVD 0x00000004 /* MPEG-TS byteswap */
109#define AR2315_CONFIG_PCI 0x00000008 /* PCI byteswap */
110#define AR2315_CONFIG_MEMCTL 0x00000010 /* Mem controller endian */
111#define AR2315_CONFIG_LOCAL 0x00000020 /* Local bus byteswap */
112#define AR2315_CONFIG_ETHERNET 0x00000040 /* Ethernet byteswap */
113#define AR2315_CONFIG_MERGE 0x00000200 /* CPU write buffer merge */
114#define AR2315_CONFIG_CPU 0x00000400 /* CPU big endian */
115#define AR2315_CONFIG_BIG 0x00000400
116#define AR2315_CONFIG_PCIAHB 0x00000800
117#define AR2315_CONFIG_PCIAHB_BRIDGE 0x00001000
118#define AR2315_CONFIG_SPI 0x00008000 /* SPI byteswap */
119#define AR2315_CONFIG_CPU_DRAM 0x00010000
120#define AR2315_CONFIG_CPU_PCI 0x00020000
121#define AR2315_CONFIG_CPU_MMR 0x00040000
122
123/* NMI control */
124#define AR2315_NMI_CTL 0x0010
125
126#define AR2315_NMI_EN 1
127
128/* Revision Register - Initial value is 0x3010 (WMAC 3.0, AR231X 1.0). */
129#define AR2315_SREV 0x0014
130
131#define AR2315_REV_MAJ 0x000000f0
132#define AR2315_REV_MAJ_S 4
133#define AR2315_REV_MIN 0x0000000f
134#define AR2315_REV_MIN_S 0
135#define AR2315_REV_CHIP (AR2315_REV_MAJ | AR2315_REV_MIN)
136
137/* Interface Enable */
138#define AR2315_IF_CTL 0x0018
139
140#define AR2315_IF_MASK 0x00000007
141#define AR2315_IF_DISABLED 0 /* Disable all */
142#define AR2315_IF_PCI 1 /* PCI */
143#define AR2315_IF_TS_LOCAL 2 /* Local bus */
144#define AR2315_IF_ALL 3 /* Emulation only */
145#define AR2315_IF_LOCAL_HOST 0x00000008
146#define AR2315_IF_PCI_HOST 0x00000010
147#define AR2315_IF_PCI_INTR 0x00000020
148#define AR2315_IF_PCI_CLK_MASK 0x00030000
149#define AR2315_IF_PCI_CLK_INPUT 0
150#define AR2315_IF_PCI_CLK_OUTPUT_LOW 1
151#define AR2315_IF_PCI_CLK_OUTPUT_CLK 2
152#define AR2315_IF_PCI_CLK_OUTPUT_HIGH 3
153#define AR2315_IF_PCI_CLK_SHIFT 16
154
155/* APB Interrupt control */
156#define AR2315_ISR 0x0020
157#define AR2315_IMR 0x0024
158#define AR2315_GISR 0x0028
159
160#define AR2315_ISR_UART0 0x00000001 /* high speed UART */
161#define AR2315_ISR_I2C_RSVD 0x00000002 /* I2C bus */
162#define AR2315_ISR_SPI 0x00000004 /* SPI bus */
163#define AR2315_ISR_AHB 0x00000008 /* AHB error */
164#define AR2315_ISR_APB 0x00000010 /* APB error */
165#define AR2315_ISR_TIMER 0x00000020 /* Timer */
166#define AR2315_ISR_GPIO 0x00000040 /* GPIO */
167#define AR2315_ISR_WD 0x00000080 /* Watchdog */
168#define AR2315_ISR_IR_RSVD 0x00000100 /* IR */
169
170#define AR2315_GISR_MISC 0x00000001 /* Misc */
171#define AR2315_GISR_WLAN0 0x00000002 /* WLAN0 */
172#define AR2315_GISR_MPEGTS_RSVD 0x00000004 /* MPEG-TS */
173#define AR2315_GISR_LOCALPCI 0x00000008 /* Local/PCI bus */
174#define AR2315_GISR_WMACPOLL 0x00000010
175#define AR2315_GISR_TIMER 0x00000020
176#define AR2315_GISR_ETHERNET 0x00000040 /* Ethernet */
177
178/* Generic timer */
179#define AR2315_TIMER 0x0030
180#define AR2315_RELOAD 0x0034
181
182/* Watchdog timer */
183#define AR2315_WDT_TIMER 0x0038
184#define AR2315_WDT_CTRL 0x003c
185
186#define AR2315_WDT_CTRL_IGNORE 0x00000000 /* ignore expiration */
187#define AR2315_WDT_CTRL_NMI 0x00000001 /* NMI on watchdog */
188#define AR2315_WDT_CTRL_RESET 0x00000002 /* reset on watchdog */
189
190/* CPU Performance Counters */
191#define AR2315_PERFCNT0 0x0048
192#define AR2315_PERFCNT1 0x004c
193
194#define AR2315_PERF0_DATAHIT 0x00000001 /* Count Data Cache Hits */
195#define AR2315_PERF0_DATAMISS 0x00000002 /* Count Data Cache Misses */
196#define AR2315_PERF0_INSTHIT 0x00000004 /* Count Instruction Cache Hits */
197#define AR2315_PERF0_INSTMISS 0x00000008 /* Count Instruction Cache Misses */
198#define AR2315_PERF0_ACTIVE 0x00000010 /* Count Active Processor Cycles */
199#define AR2315_PERF0_WBHIT 0x00000020 /* Count CPU Write Buffer Hits */
200#define AR2315_PERF0_WBMISS 0x00000040 /* Count CPU Write Buffer Misses */
201
202#define AR2315_PERF1_EB_ARDY 0x00000001 /* Count EB_ARdy signal */
203#define AR2315_PERF1_EB_AVALID 0x00000002 /* Count EB_AValid signal */
204#define AR2315_PERF1_EB_WDRDY 0x00000004 /* Count EB_WDRdy signal */
205#define AR2315_PERF1_EB_RDVAL 0x00000008 /* Count EB_RdVal signal */
206#define AR2315_PERF1_VRADDR 0x00000010 /* Count valid read address cycles*/
207#define AR2315_PERF1_VWADDR 0x00000020 /* Count valid write address cycl.*/
208#define AR2315_PERF1_VWDATA 0x00000040 /* Count valid write data cycles */
209
210/* AHB Error Reporting */
211#define AR2315_AHB_ERR0 0x0050 /* error */
212#define AR2315_AHB_ERR1 0x0054 /* haddr */
213#define AR2315_AHB_ERR2 0x0058 /* hwdata */
214#define AR2315_AHB_ERR3 0x005c /* hrdata */
215#define AR2315_AHB_ERR4 0x0060 /* status */
216
217#define AR2315_AHB_ERROR_DET 1 /* AHB Error has been detected, */
218 /* write 1 to clear all bits in ERR0 */
219#define AR2315_AHB_ERROR_OVR 2 /* AHB Error overflow has been detected */
220#define AR2315_AHB_ERROR_WDT 4 /* AHB Error due to wdt instead of hresp */
221
222#define AR2315_PROCERR_HMAST 0x0000000f
223#define AR2315_PROCERR_HMAST_DFLT 0
224#define AR2315_PROCERR_HMAST_WMAC 1
225#define AR2315_PROCERR_HMAST_ENET 2
226#define AR2315_PROCERR_HMAST_PCIENDPT 3
227#define AR2315_PROCERR_HMAST_LOCAL 4
228#define AR2315_PROCERR_HMAST_CPU 5
229#define AR2315_PROCERR_HMAST_PCITGT 6
230#define AR2315_PROCERR_HMAST_S 0
231#define AR2315_PROCERR_HWRITE 0x00000010
232#define AR2315_PROCERR_HSIZE 0x00000060
233#define AR2315_PROCERR_HSIZE_S 5
234#define AR2315_PROCERR_HTRANS 0x00000180
235#define AR2315_PROCERR_HTRANS_S 7
236#define AR2315_PROCERR_HBURST 0x00000e00
237#define AR2315_PROCERR_HBURST_S 9
238
239/* Clock Control */
240#define AR2315_PLLC_CTL 0x0064
241#define AR2315_PLLV_CTL 0x0068
242#define AR2315_CPUCLK 0x006c
243#define AR2315_AMBACLK 0x0070
244#define AR2315_SYNCCLK 0x0074
245#define AR2315_DSL_SLEEP_CTL 0x0080
246#define AR2315_DSL_SLEEP_DUR 0x0084
247
248/* PLLc Control fields */
249#define AR2315_PLLC_REF_DIV_M 0x00000003
250#define AR2315_PLLC_REF_DIV_S 0
251#define AR2315_PLLC_FDBACK_DIV_M 0x0000007c
252#define AR2315_PLLC_FDBACK_DIV_S 2
253#define AR2315_PLLC_ADD_FDBACK_DIV_M 0x00000080
254#define AR2315_PLLC_ADD_FDBACK_DIV_S 7
255#define AR2315_PLLC_CLKC_DIV_M 0x0001c000
256#define AR2315_PLLC_CLKC_DIV_S 14
257#define AR2315_PLLC_CLKM_DIV_M 0x00700000
258#define AR2315_PLLC_CLKM_DIV_S 20
259
260/* CPU CLK Control fields */
261#define AR2315_CPUCLK_CLK_SEL_M 0x00000003
262#define AR2315_CPUCLK_CLK_SEL_S 0
263#define AR2315_CPUCLK_CLK_DIV_M 0x0000000c
264#define AR2315_CPUCLK_CLK_DIV_S 2
265
266/* AMBA CLK Control fields */
267#define AR2315_AMBACLK_CLK_SEL_M 0x00000003
268#define AR2315_AMBACLK_CLK_SEL_S 0
269#define AR2315_AMBACLK_CLK_DIV_M 0x0000000c
270#define AR2315_AMBACLK_CLK_DIV_S 2
271
272/* PCI Clock Control */
273#define AR2315_PCICLK 0x00a4
274
275#define AR2315_PCICLK_INPUT_M 0x00000003
276#define AR2315_PCICLK_INPUT_S 0
277#define AR2315_PCICLK_PLLC_CLKM 0
278#define AR2315_PCICLK_PLLC_CLKM1 1
279#define AR2315_PCICLK_PLLC_CLKC 2
280#define AR2315_PCICLK_REF_CLK 3
281#define AR2315_PCICLK_DIV_M 0x0000000c
282#define AR2315_PCICLK_DIV_S 2
283#define AR2315_PCICLK_IN_FREQ 0
284#define AR2315_PCICLK_IN_FREQ_DIV_6 1
285#define AR2315_PCICLK_IN_FREQ_DIV_8 2
286#define AR2315_PCICLK_IN_FREQ_DIV_10 3
287
288/* Observation Control Register */
289#define AR2315_OCR 0x00b0
290
291#define AR2315_OCR_GPIO0_IRIN 0x00000040
292#define AR2315_OCR_GPIO1_IROUT 0x00000080
293#define AR2315_OCR_GPIO3_RXCLR 0x00000200
294
295/* General Clock Control */
296#define AR2315_MISCCLK 0x00b4
297
298#define AR2315_MISCCLK_PLLBYPASS_EN 0x00000001
299#define AR2315_MISCCLK_PROCREFCLK 0x00000002
300
301/*
302 * SDRAM Controller
303 * - No read or write buffers are included.
304 */
305#define AR2315_MEM_CFG 0x0000
306#define AR2315_MEM_CTRL 0x000c
307#define AR2315_MEM_REF 0x0010
308
309#define AR2315_MEM_CFG_DATA_WIDTH_M 0x00006000
310#define AR2315_MEM_CFG_DATA_WIDTH_S 13
311#define AR2315_MEM_CFG_COL_WIDTH_M 0x00001e00
312#define AR2315_MEM_CFG_COL_WIDTH_S 9
313#define AR2315_MEM_CFG_ROW_WIDTH_M 0x000001e0
314#define AR2315_MEM_CFG_ROW_WIDTH_S 5
315#define AR2315_MEM_CFG_BANKADDR_BITS_M 0x00000018
316#define AR2315_MEM_CFG_BANKADDR_BITS_S 3
317
318/*
319 * Local Bus Interface Registers
320 */
321#define AR2315_LB_CONFIG 0x0000
322
323#define AR2315_LBCONF_OE 0x00000001 /* =1 OE is low-true */
324#define AR2315_LBCONF_CS0 0x00000002 /* =1 first CS is low-true */
325#define AR2315_LBCONF_CS1 0x00000004 /* =1 2nd CS is low-true */
326#define AR2315_LBCONF_RDY 0x00000008 /* =1 RDY is low-true */
327#define AR2315_LBCONF_WE 0x00000010 /* =1 Write En is low-true */
328#define AR2315_LBCONF_WAIT 0x00000020 /* =1 WAIT is low-true */
329#define AR2315_LBCONF_ADS 0x00000040 /* =1 Adr Strobe is low-true */
330#define AR2315_LBCONF_MOT 0x00000080 /* =0 Intel, =1 Motorola */
331#define AR2315_LBCONF_8CS 0x00000100 /* =1 8 bits CS, 0= 16bits */
332#define AR2315_LBCONF_8DS 0x00000200 /* =1 8 bits Data S, 0=16bits */
333#define AR2315_LBCONF_ADS_EN 0x00000400 /* =1 Enable ADS */
334#define AR2315_LBCONF_ADR_OE 0x00000800 /* =1 Adr cap on OE, WE or DS */
335#define AR2315_LBCONF_ADDT_MUX 0x00001000 /* =1 Adr and Data share bus */
336#define AR2315_LBCONF_DATA_OE 0x00002000 /* =1 Data cap on OE, WE, DS */
337#define AR2315_LBCONF_16DATA 0x00004000 /* =1 Data is 16 bits wide */
338#define AR2315_LBCONF_SWAPDT 0x00008000 /* =1 Byte swap data */
339#define AR2315_LBCONF_SYNC 0x00010000 /* =1 Bus synchronous to clk */
340#define AR2315_LBCONF_INT 0x00020000 /* =1 Intr is low true */
341#define AR2315_LBCONF_INT_CTR0 0x00000000 /* GND high-Z, Vdd is high-Z */
342#define AR2315_LBCONF_INT_CTR1 0x00040000 /* GND drive, Vdd is high-Z */
343#define AR2315_LBCONF_INT_CTR2 0x00080000 /* GND high-Z, Vdd drive */
344#define AR2315_LBCONF_INT_CTR3 0x000c0000 /* GND drive, Vdd drive */
345#define AR2315_LBCONF_RDY_WAIT 0x00100000 /* =1 RDY is negative of WAIT */
346#define AR2315_LBCONF_INT_PULSE 0x00200000 /* =1 Interrupt is a pulse */
347#define AR2315_LBCONF_ENABLE 0x00400000 /* =1 Falcon respond to LB */
348
349#define AR2315_LB_CLKSEL 0x0004
350
351#define AR2315_LBCLK_EXT 0x00000001 /* use external clk for lb */
352
353#define AR2315_LB_1MS 0x0008
354
355#define AR2315_LB1MS_MASK 0x0003ffff /* # of AHB clk cycles in 1ms */
356
357#define AR2315_LB_MISCCFG 0x000c
358
359#define AR2315_LBM_TXD_EN 0x00000001 /* Enable TXD for fragments */
360#define AR2315_LBM_RX_INTEN 0x00000002 /* Enable LB ints on RX ready */
361#define AR2315_LBM_MBOXWR_INTEN 0x00000004 /* Enable LB ints on mbox wr */
362#define AR2315_LBM_MBOXRD_INTEN 0x00000008 /* Enable LB ints on mbox rd */
363#define AR2315_LMB_DESCSWAP_EN 0x00000010 /* Byte swap desc enable */
364#define AR2315_LBM_TIMEOUT_M 0x00ffff80
365#define AR2315_LBM_TIMEOUT_S 7
366#define AR2315_LBM_PORTMUX 0x07000000
367
368#define AR2315_LB_RXTSOFF 0x0010
369
370#define AR2315_LB_TX_CHAIN_EN 0x0100
371
372#define AR2315_LB_TXEN_0 0x00000001
373#define AR2315_LB_TXEN_1 0x00000002
374#define AR2315_LB_TXEN_2 0x00000004
375#define AR2315_LB_TXEN_3 0x00000008
376
377#define AR2315_LB_TX_CHAIN_DIS 0x0104
378#define AR2315_LB_TX_DESC_PTR 0x0200
379
380#define AR2315_LB_RX_CHAIN_EN 0x0400
381
382#define AR2315_LB_RXEN 0x00000001
383
384#define AR2315_LB_RX_CHAIN_DIS 0x0404
385#define AR2315_LB_RX_DESC_PTR 0x0408
386
387#define AR2315_LB_INT_STATUS 0x0500
388
389#define AR2315_LB_INT_TX_DESC 0x00000001
390#define AR2315_LB_INT_TX_OK 0x00000002
391#define AR2315_LB_INT_TX_ERR 0x00000004
392#define AR2315_LB_INT_TX_EOF 0x00000008
393#define AR2315_LB_INT_RX_DESC 0x00000010
394#define AR2315_LB_INT_RX_OK 0x00000020
395#define AR2315_LB_INT_RX_ERR 0x00000040
396#define AR2315_LB_INT_RX_EOF 0x00000080
397#define AR2315_LB_INT_TX_TRUNC 0x00000100
398#define AR2315_LB_INT_TX_STARVE 0x00000200
399#define AR2315_LB_INT_LB_TIMEOUT 0x00000400
400#define AR2315_LB_INT_LB_ERR 0x00000800
401#define AR2315_LB_INT_MBOX_WR 0x00001000
402#define AR2315_LB_INT_MBOX_RD 0x00002000
403
404/* Bit definitions for INT MASK are the same as INT_STATUS */
405#define AR2315_LB_INT_MASK 0x0504
406
407#define AR2315_LB_INT_EN 0x0508
408#define AR2315_LB_MBOX 0x0600
409
410#endif /* __ASM_MACH_ATH25_AR2315_REGS_H */
diff --git a/arch/mips/ath25/ar5312.c b/arch/mips/ath25/ar5312.c
new file mode 100644
index 000000000000..b6887f75144c
--- /dev/null
+++ b/arch/mips/ath25/ar5312.c
@@ -0,0 +1,393 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
7 * Copyright (C) 2006 FON Technology, SL.
8 * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
9 * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
10 * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
11 */
12
13/*
14 * Platform devices for Atheros AR5312 SoCs
15 */
16
17#include <linux/init.h>
18#include <linux/kernel.h>
19#include <linux/bitops.h>
20#include <linux/irqdomain.h>
21#include <linux/interrupt.h>
22#include <linux/platform_device.h>
23#include <linux/mtd/physmap.h>
24#include <linux/reboot.h>
25#include <asm/bootinfo.h>
26#include <asm/reboot.h>
27#include <asm/time.h>
28
29#include <ath25_platform.h>
30
31#include "devices.h"
32#include "ar5312.h"
33#include "ar5312_regs.h"
34
35static void __iomem *ar5312_rst_base;
36static struct irq_domain *ar5312_misc_irq_domain;
37
38static inline u32 ar5312_rst_reg_read(u32 reg)
39{
40 return __raw_readl(ar5312_rst_base + reg);
41}
42
43static inline void ar5312_rst_reg_write(u32 reg, u32 val)
44{
45 __raw_writel(val, ar5312_rst_base + reg);
46}
47
48static inline void ar5312_rst_reg_mask(u32 reg, u32 mask, u32 val)
49{
50 u32 ret = ar5312_rst_reg_read(reg);
51
52 ret &= ~mask;
53 ret |= val;
54 ar5312_rst_reg_write(reg, ret);
55}
56
57static irqreturn_t ar5312_ahb_err_handler(int cpl, void *dev_id)
58{
59 u32 proc1 = ar5312_rst_reg_read(AR5312_PROC1);
60 u32 proc_addr = ar5312_rst_reg_read(AR5312_PROCADDR); /* clears error */
61 u32 dma1 = ar5312_rst_reg_read(AR5312_DMA1);
62 u32 dma_addr = ar5312_rst_reg_read(AR5312_DMAADDR); /* clears error */
63
64 pr_emerg("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x DMAADDR=0x%8.8x DMA1=0x%8.8x\n",
65 proc_addr, proc1, dma_addr, dma1);
66
67 machine_restart("AHB error"); /* Catastrophic failure */
68 return IRQ_HANDLED;
69}
70
71static struct irqaction ar5312_ahb_err_interrupt = {
72 .handler = ar5312_ahb_err_handler,
73 .name = "ar5312-ahb-error",
74};
75
76static void ar5312_misc_irq_handler(unsigned irq, struct irq_desc *desc)
77{
78 u32 pending = ar5312_rst_reg_read(AR5312_ISR) &
79 ar5312_rst_reg_read(AR5312_IMR);
80 unsigned nr, misc_irq = 0;
81
82 if (pending) {
83 struct irq_domain *domain = irq_get_handler_data(irq);
84
85 nr = __ffs(pending);
86 misc_irq = irq_find_mapping(domain, nr);
87 }
88
89 if (misc_irq) {
90 generic_handle_irq(misc_irq);
91 if (nr == AR5312_MISC_IRQ_TIMER)
92 ar5312_rst_reg_read(AR5312_TIMER);
93 } else {
94 spurious_interrupt();
95 }
96}
97
98/* Enable the specified AR5312_MISC_IRQ interrupt */
99static void ar5312_misc_irq_unmask(struct irq_data *d)
100{
101 ar5312_rst_reg_mask(AR5312_IMR, 0, BIT(d->hwirq));
102}
103
104/* Disable the specified AR5312_MISC_IRQ interrupt */
105static void ar5312_misc_irq_mask(struct irq_data *d)
106{
107 ar5312_rst_reg_mask(AR5312_IMR, BIT(d->hwirq), 0);
108 ar5312_rst_reg_read(AR5312_IMR); /* flush write buffer */
109}
110
111static struct irq_chip ar5312_misc_irq_chip = {
112 .name = "ar5312-misc",
113 .irq_unmask = ar5312_misc_irq_unmask,
114 .irq_mask = ar5312_misc_irq_mask,
115};
116
117static int ar5312_misc_irq_map(struct irq_domain *d, unsigned irq,
118 irq_hw_number_t hw)
119{
120 irq_set_chip_and_handler(irq, &ar5312_misc_irq_chip, handle_level_irq);
121 return 0;
122}
123
124static struct irq_domain_ops ar5312_misc_irq_domain_ops = {
125 .map = ar5312_misc_irq_map,
126};
127
128static void ar5312_irq_dispatch(void)
129{
130 u32 pending = read_c0_status() & read_c0_cause();
131
132 if (pending & CAUSEF_IP2)
133 do_IRQ(AR5312_IRQ_WLAN0);
134 else if (pending & CAUSEF_IP5)
135 do_IRQ(AR5312_IRQ_WLAN1);
136 else if (pending & CAUSEF_IP6)
137 do_IRQ(AR5312_IRQ_MISC);
138 else if (pending & CAUSEF_IP7)
139 do_IRQ(ATH25_IRQ_CPU_CLOCK);
140 else
141 spurious_interrupt();
142}
143
144void __init ar5312_arch_init_irq(void)
145{
146 struct irq_domain *domain;
147 unsigned irq;
148
149 ath25_irq_dispatch = ar5312_irq_dispatch;
150
151 domain = irq_domain_add_linear(NULL, AR5312_MISC_IRQ_COUNT,
152 &ar5312_misc_irq_domain_ops, NULL);
153 if (!domain)
154 panic("Failed to add IRQ domain");
155
156 irq = irq_create_mapping(domain, AR5312_MISC_IRQ_AHB_PROC);
157 setup_irq(irq, &ar5312_ahb_err_interrupt);
158
159 irq_set_chained_handler(AR5312_IRQ_MISC, ar5312_misc_irq_handler);
160 irq_set_handler_data(AR5312_IRQ_MISC, domain);
161
162 ar5312_misc_irq_domain = domain;
163}
164
165static struct physmap_flash_data ar5312_flash_data = {
166 .width = 2,
167};
168
169static struct resource ar5312_flash_resource = {
170 .start = AR5312_FLASH_BASE,
171 .end = AR5312_FLASH_BASE + AR5312_FLASH_SIZE - 1,
172 .flags = IORESOURCE_MEM,
173};
174
175static struct platform_device ar5312_physmap_flash = {
176 .name = "physmap-flash",
177 .id = 0,
178 .dev.platform_data = &ar5312_flash_data,
179 .resource = &ar5312_flash_resource,
180 .num_resources = 1,
181};
182
183static void __init ar5312_flash_init(void)
184{
185 void __iomem *flashctl_base;
186 u32 ctl;
187
188 flashctl_base = ioremap_nocache(AR5312_FLASHCTL_BASE,
189 AR5312_FLASHCTL_SIZE);
190
191 ctl = __raw_readl(flashctl_base + AR5312_FLASHCTL0);
192 ctl &= AR5312_FLASHCTL_MW;
193
194 /* fixup flash width */
195 switch (ctl) {
196 case AR5312_FLASHCTL_MW16:
197 ar5312_flash_data.width = 2;
198 break;
199 case AR5312_FLASHCTL_MW8:
200 default:
201 ar5312_flash_data.width = 1;
202 break;
203 }
204
205 /*
206 * Configure flash bank 0.
207 * Assume 8M window size. Flash will be aliased if it's smaller
208 */
209 ctl |= AR5312_FLASHCTL_E | AR5312_FLASHCTL_AC_8M | AR5312_FLASHCTL_RBLE;
210 ctl |= 0x01 << AR5312_FLASHCTL_IDCY_S;
211 ctl |= 0x07 << AR5312_FLASHCTL_WST1_S;
212 ctl |= 0x07 << AR5312_FLASHCTL_WST2_S;
213 __raw_writel(ctl, flashctl_base + AR5312_FLASHCTL0);
214
215 /* Disable other flash banks */
216 ctl = __raw_readl(flashctl_base + AR5312_FLASHCTL1);
217 ctl &= ~(AR5312_FLASHCTL_E | AR5312_FLASHCTL_AC);
218 __raw_writel(ctl, flashctl_base + AR5312_FLASHCTL1);
219 ctl = __raw_readl(flashctl_base + AR5312_FLASHCTL2);
220 ctl &= ~(AR5312_FLASHCTL_E | AR5312_FLASHCTL_AC);
221 __raw_writel(ctl, flashctl_base + AR5312_FLASHCTL2);
222
223 iounmap(flashctl_base);
224}
225
226void __init ar5312_init_devices(void)
227{
228 struct ath25_boarddata *config;
229
230 ar5312_flash_init();
231
232 /* Locate board/radio config data */
233 ath25_find_config(AR5312_FLASH_BASE, AR5312_FLASH_SIZE);
234 config = ath25_board.config;
235
236 /* AR2313 has CPU minor rev. 10 */
237 if ((current_cpu_data.processor_id & 0xff) == 0x0a)
238 ath25_soc = ATH25_SOC_AR2313;
239
240 /* AR2312 shares the same Silicon ID as AR5312 */
241 else if (config->flags & BD_ISCASPER)
242 ath25_soc = ATH25_SOC_AR2312;
243
244 /* Everything else is probably AR5312 or compatible */
245 else
246 ath25_soc = ATH25_SOC_AR5312;
247
248 platform_device_register(&ar5312_physmap_flash);
249
250 switch (ath25_soc) {
251 case ATH25_SOC_AR5312:
252 if (!ath25_board.radio)
253 return;
254
255 if (!(config->flags & BD_WLAN0))
256 break;
257
258 ath25_add_wmac(0, AR5312_WLAN0_BASE, AR5312_IRQ_WLAN0);
259 break;
260 case ATH25_SOC_AR2312:
261 case ATH25_SOC_AR2313:
262 if (!ath25_board.radio)
263 return;
264 break;
265 default:
266 break;
267 }
268
269 if (config->flags & BD_WLAN1)
270 ath25_add_wmac(1, AR5312_WLAN1_BASE, AR5312_IRQ_WLAN1);
271}
272
273static void ar5312_restart(char *command)
274{
275 /* reset the system */
276 local_irq_disable();
277 while (1)
278 ar5312_rst_reg_write(AR5312_RESET, AR5312_RESET_SYSTEM);
279}
280
281/*
282 * This table is indexed by bits 5..4 of the CLOCKCTL1 register
283 * to determine the predevisor value.
284 */
285static unsigned clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
286
287static unsigned __init ar5312_cpu_frequency(void)
288{
289 u32 scratch, devid, clock_ctl1;
290 u32 predivide_mask, multiplier_mask, doubler_mask;
291 unsigned predivide_shift, multiplier_shift;
292 unsigned predivide_select, predivisor, multiplier;
293
294 /* Trust the bootrom's idea of cpu frequency. */
295 scratch = ar5312_rst_reg_read(AR5312_SCRATCH);
296 if (scratch)
297 return scratch;
298
299 devid = ar5312_rst_reg_read(AR5312_REV);
300 devid = (devid & AR5312_REV_MAJ) >> AR5312_REV_MAJ_S;
301 if (devid == AR5312_REV_MAJ_AR2313) {
302 predivide_mask = AR2313_CLOCKCTL1_PREDIVIDE_MASK;
303 predivide_shift = AR2313_CLOCKCTL1_PREDIVIDE_SHIFT;
304 multiplier_mask = AR2313_CLOCKCTL1_MULTIPLIER_MASK;
305 multiplier_shift = AR2313_CLOCKCTL1_MULTIPLIER_SHIFT;
306 doubler_mask = AR2313_CLOCKCTL1_DOUBLER_MASK;
307 } else { /* AR5312 and AR2312 */
308 predivide_mask = AR5312_CLOCKCTL1_PREDIVIDE_MASK;
309 predivide_shift = AR5312_CLOCKCTL1_PREDIVIDE_SHIFT;
310 multiplier_mask = AR5312_CLOCKCTL1_MULTIPLIER_MASK;
311 multiplier_shift = AR5312_CLOCKCTL1_MULTIPLIER_SHIFT;
312 doubler_mask = AR5312_CLOCKCTL1_DOUBLER_MASK;
313 }
314
315 /*
316 * Clocking is derived from a fixed 40MHz input clock.
317 *
318 * cpu_freq = input_clock * MULT (where MULT is PLL multiplier)
319 * sys_freq = cpu_freq / 4 (used for APB clock, serial,
320 * flash, Timer, Watchdog Timer)
321 *
322 * cnt_freq = cpu_freq / 2 (use for CPU count/compare)
323 *
324 * So, for example, with a PLL multiplier of 5, we have
325 *
326 * cpu_freq = 200MHz
327 * sys_freq = 50MHz
328 * cnt_freq = 100MHz
329 *
330 * We compute the CPU frequency, based on PLL settings.
331 */
332
333 clock_ctl1 = ar5312_rst_reg_read(AR5312_CLOCKCTL1);
334 predivide_select = (clock_ctl1 & predivide_mask) >> predivide_shift;
335 predivisor = clockctl1_predivide_table[predivide_select];
336 multiplier = (clock_ctl1 & multiplier_mask) >> multiplier_shift;
337
338 if (clock_ctl1 & doubler_mask)
339 multiplier <<= 1;
340
341 return (40000000 / predivisor) * multiplier;
342}
343
344static inline unsigned ar5312_sys_frequency(void)
345{
346 return ar5312_cpu_frequency() / 4;
347}
348
349void __init ar5312_plat_time_init(void)
350{
351 mips_hpt_frequency = ar5312_cpu_frequency() / 2;
352}
353
354void __init ar5312_plat_mem_setup(void)
355{
356 void __iomem *sdram_base;
357 u32 memsize, memcfg, bank0_ac, bank1_ac;
358 u32 devid;
359
360 /* Detect memory size */
361 sdram_base = ioremap_nocache(AR5312_SDRAMCTL_BASE,
362 AR5312_SDRAMCTL_SIZE);
363 memcfg = __raw_readl(sdram_base + AR5312_MEM_CFG1);
364 bank0_ac = ATH25_REG_MS(memcfg, AR5312_MEM_CFG1_AC0);
365 bank1_ac = ATH25_REG_MS(memcfg, AR5312_MEM_CFG1_AC1);
366 memsize = (bank0_ac ? (1 << (bank0_ac + 1)) : 0) +
367 (bank1_ac ? (1 << (bank1_ac + 1)) : 0);
368 memsize <<= 20;
369 add_memory_region(0, memsize, BOOT_MEM_RAM);
370 iounmap(sdram_base);
371
372 ar5312_rst_base = ioremap_nocache(AR5312_RST_BASE, AR5312_RST_SIZE);
373
374 devid = ar5312_rst_reg_read(AR5312_REV);
375 devid >>= AR5312_REV_WMAC_MIN_S;
376 devid &= AR5312_REV_CHIP;
377 ath25_board.devid = (u16)devid;
378
379 /* Clear any lingering AHB errors */
380 ar5312_rst_reg_read(AR5312_PROCADDR);
381 ar5312_rst_reg_read(AR5312_DMAADDR);
382 ar5312_rst_reg_write(AR5312_WDT_CTRL, AR5312_WDT_CTRL_IGNORE);
383
384 _machine_restart = ar5312_restart;
385}
386
387void __init ar5312_arch_init(void)
388{
389 unsigned irq = irq_create_mapping(ar5312_misc_irq_domain,
390 AR5312_MISC_IRQ_UART0);
391
392 ath25_serial_setup(AR5312_UART0_BASE, irq, ar5312_sys_frequency());
393}
diff --git a/arch/mips/ath25/ar5312.h b/arch/mips/ath25/ar5312.h
new file mode 100644
index 000000000000..470abb0052bd
--- /dev/null
+++ b/arch/mips/ath25/ar5312.h
@@ -0,0 +1,22 @@
1#ifndef __AR5312_H
2#define __AR5312_H
3
4#ifdef CONFIG_SOC_AR5312
5
6void ar5312_arch_init_irq(void);
7void ar5312_init_devices(void);
8void ar5312_plat_time_init(void);
9void ar5312_plat_mem_setup(void);
10void ar5312_arch_init(void);
11
12#else
13
14static inline void ar5312_arch_init_irq(void) {}
15static inline void ar5312_init_devices(void) {}
16static inline void ar5312_plat_time_init(void) {}
17static inline void ar5312_plat_mem_setup(void) {}
18static inline void ar5312_arch_init(void) {}
19
20#endif
21
22#endif /* __AR5312_H */
diff --git a/arch/mips/ath25/ar5312_regs.h b/arch/mips/ath25/ar5312_regs.h
new file mode 100644
index 000000000000..4b947f967439
--- /dev/null
+++ b/arch/mips/ath25/ar5312_regs.h
@@ -0,0 +1,224 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
7 * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
8 * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
9 */
10
11#ifndef __ASM_MACH_ATH25_AR5312_REGS_H
12#define __ASM_MACH_ATH25_AR5312_REGS_H
13
14/*
15 * IRQs
16 */
17#define AR5312_IRQ_WLAN0 (MIPS_CPU_IRQ_BASE + 2) /* C0_CAUSE: 0x0400 */
18#define AR5312_IRQ_ENET0 (MIPS_CPU_IRQ_BASE + 3) /* C0_CAUSE: 0x0800 */
19#define AR5312_IRQ_ENET1 (MIPS_CPU_IRQ_BASE + 4) /* C0_CAUSE: 0x1000 */
20#define AR5312_IRQ_WLAN1 (MIPS_CPU_IRQ_BASE + 5) /* C0_CAUSE: 0x2000 */
21#define AR5312_IRQ_MISC (MIPS_CPU_IRQ_BASE + 6) /* C0_CAUSE: 0x4000 */
22
23/*
24 * Miscellaneous interrupts, which share IP6.
25 */
26#define AR5312_MISC_IRQ_TIMER 0
27#define AR5312_MISC_IRQ_AHB_PROC 1
28#define AR5312_MISC_IRQ_AHB_DMA 2
29#define AR5312_MISC_IRQ_GPIO 3
30#define AR5312_MISC_IRQ_UART0 4
31#define AR5312_MISC_IRQ_UART0_DMA 5
32#define AR5312_MISC_IRQ_WATCHDOG 6
33#define AR5312_MISC_IRQ_LOCAL 7
34#define AR5312_MISC_IRQ_SPI 8
35#define AR5312_MISC_IRQ_COUNT 9
36
37/*
38 * Address Map
39 *
40 * The AR5312 supports 2 enet MACS, even though many reference boards only
41 * actually use 1 of them (i.e. Only MAC 0 is actually connected to an enet
42 * PHY or PHY switch. The AR2312 supports 1 enet MAC.
43 */
44#define AR5312_WLAN0_BASE 0x18000000
45#define AR5312_ENET0_BASE 0x18100000
46#define AR5312_ENET1_BASE 0x18200000
47#define AR5312_SDRAMCTL_BASE 0x18300000
48#define AR5312_SDRAMCTL_SIZE 0x00000010
49#define AR5312_FLASHCTL_BASE 0x18400000
50#define AR5312_FLASHCTL_SIZE 0x00000010
51#define AR5312_WLAN1_BASE 0x18500000
52#define AR5312_UART0_BASE 0x1c000000 /* UART MMR */
53#define AR5312_GPIO_BASE 0x1c002000
54#define AR5312_GPIO_SIZE 0x00000010
55#define AR5312_RST_BASE 0x1c003000
56#define AR5312_RST_SIZE 0x00000100
57#define AR5312_FLASH_BASE 0x1e000000
58#define AR5312_FLASH_SIZE 0x00800000
59
60/*
61 * Need these defines to determine true number of ethernet MACs
62 */
63#define AR5312_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */
64#define AR5312_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */
65#define AR5312_AR2313_REV8 0x0058 /* AR2313 WMAC (AP43-030) */
66
67/* Reset/Timer Block Address Map */
68#define AR5312_TIMER 0x0000 /* countdown timer */
69#define AR5312_RELOAD 0x0004 /* timer reload value */
70#define AR5312_WDT_CTRL 0x0008 /* watchdog cntrl */
71#define AR5312_WDT_TIMER 0x000c /* watchdog timer */
72#define AR5312_ISR 0x0010 /* Intr Status Reg */
73#define AR5312_IMR 0x0014 /* Intr Mask Reg */
74#define AR5312_RESET 0x0020
75#define AR5312_CLOCKCTL1 0x0064
76#define AR5312_SCRATCH 0x006c
77#define AR5312_PROCADDR 0x0070
78#define AR5312_PROC1 0x0074
79#define AR5312_DMAADDR 0x0078
80#define AR5312_DMA1 0x007c
81#define AR5312_ENABLE 0x0080 /* interface enb */
82#define AR5312_REV 0x0090 /* revision */
83
84/* AR5312_WDT_CTRL register bit field definitions */
85#define AR5312_WDT_CTRL_IGNORE 0x00000000 /* ignore expiration */
86#define AR5312_WDT_CTRL_NMI 0x00000001
87#define AR5312_WDT_CTRL_RESET 0x00000002
88
89/* AR5312_ISR register bit field definitions */
90#define AR5312_ISR_TIMER 0x00000001
91#define AR5312_ISR_AHBPROC 0x00000002
92#define AR5312_ISR_AHBDMA 0x00000004
93#define AR5312_ISR_GPIO 0x00000008
94#define AR5312_ISR_UART0 0x00000010
95#define AR5312_ISR_UART0DMA 0x00000020
96#define AR5312_ISR_WD 0x00000040
97#define AR5312_ISR_LOCAL 0x00000080
98
99/* AR5312_RESET register bit field definitions */
100#define AR5312_RESET_SYSTEM 0x00000001 /* cold reset full system */
101#define AR5312_RESET_PROC 0x00000002 /* cold reset MIPS core */
102#define AR5312_RESET_WLAN0 0x00000004 /* cold reset WLAN MAC/BB */
103#define AR5312_RESET_EPHY0 0x00000008 /* cold reset ENET0 phy */
104#define AR5312_RESET_EPHY1 0x00000010 /* cold reset ENET1 phy */
105#define AR5312_RESET_ENET0 0x00000020 /* cold reset ENET0 MAC */
106#define AR5312_RESET_ENET1 0x00000040 /* cold reset ENET1 MAC */
107#define AR5312_RESET_UART0 0x00000100 /* cold reset UART0 */
108#define AR5312_RESET_WLAN1 0x00000200 /* cold reset WLAN MAC/BB */
109#define AR5312_RESET_APB 0x00000400 /* cold reset APB ar5312 */
110#define AR5312_RESET_WARM_PROC 0x00001000 /* warm reset MIPS core */
111#define AR5312_RESET_WARM_WLAN0_MAC 0x00002000 /* warm reset WLAN0 MAC */
112#define AR5312_RESET_WARM_WLAN0_BB 0x00004000 /* warm reset WLAN0 BB */
113#define AR5312_RESET_NMI 0x00010000 /* send an NMI to the CPU */
114#define AR5312_RESET_WARM_WLAN1_MAC 0x00020000 /* warm reset WLAN1 MAC */
115#define AR5312_RESET_WARM_WLAN1_BB 0x00040000 /* warm reset WLAN1 BB */
116#define AR5312_RESET_LOCAL_BUS 0x00080000 /* reset local bus */
117#define AR5312_RESET_WDOG 0x00100000 /* last reset was a wdt */
118
119#define AR5312_RESET_WMAC0_BITS (AR5312_RESET_WLAN0 |\
120 AR5312_RESET_WARM_WLAN0_MAC |\
121 AR5312_RESET_WARM_WLAN0_BB)
122
123#define AR5312_RESET_WMAC1_BITS (AR5312_RESET_WLAN1 |\
124 AR5312_RESET_WARM_WLAN1_MAC |\
125 AR5312_RESET_WARM_WLAN1_BB)
126
127/* AR5312_CLOCKCTL1 register bit field definitions */
128#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
129#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
130#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
131#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
132#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
133
134/* Valid for AR5312 and AR2312 */
135#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
136#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
137#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
138#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
139#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
140
141/* Valid for AR2313 */
142#define AR2313_CLOCKCTL1_PREDIVIDE_MASK 0x00003000
143#define AR2313_CLOCKCTL1_PREDIVIDE_SHIFT 12
144#define AR2313_CLOCKCTL1_MULTIPLIER_MASK 0x001f0000
145#define AR2313_CLOCKCTL1_MULTIPLIER_SHIFT 16
146#define AR2313_CLOCKCTL1_DOUBLER_MASK 0x00000000
147
148/* AR5312_ENABLE register bit field definitions */
149#define AR5312_ENABLE_WLAN0 0x00000001
150#define AR5312_ENABLE_ENET0 0x00000002
151#define AR5312_ENABLE_ENET1 0x00000004
152#define AR5312_ENABLE_UART_AND_WLAN1_PIO 0x00000008/* UART & WLAN1 PIO */
153#define AR5312_ENABLE_WLAN1_DMA 0x00000010/* WLAN1 DMAs */
154#define AR5312_ENABLE_WLAN1 (AR5312_ENABLE_UART_AND_WLAN1_PIO |\
155 AR5312_ENABLE_WLAN1_DMA)
156
157/* AR5312_REV register bit field definitions */
158#define AR5312_REV_WMAC_MAJ 0x0000f000
159#define AR5312_REV_WMAC_MAJ_S 12
160#define AR5312_REV_WMAC_MIN 0x00000f00
161#define AR5312_REV_WMAC_MIN_S 8
162#define AR5312_REV_MAJ 0x000000f0
163#define AR5312_REV_MAJ_S 4
164#define AR5312_REV_MIN 0x0000000f
165#define AR5312_REV_MIN_S 0
166#define AR5312_REV_CHIP (AR5312_REV_MAJ|AR5312_REV_MIN)
167
168/* Major revision numbers, bits 7..4 of Revision ID register */
169#define AR5312_REV_MAJ_AR5312 0x4
170#define AR5312_REV_MAJ_AR2313 0x5
171
172/* Minor revision numbers, bits 3..0 of Revision ID register */
173#define AR5312_REV_MIN_DUAL 0x0 /* Dual WLAN version */
174#define AR5312_REV_MIN_SINGLE 0x1 /* Single WLAN version */
175
176/*
177 * ARM Flash Controller -- 3 flash banks with either x8 or x16 devices
178 */
179#define AR5312_FLASHCTL0 0x0000
180#define AR5312_FLASHCTL1 0x0004
181#define AR5312_FLASHCTL2 0x0008
182
183/* AR5312_FLASHCTL register bit field definitions */
184#define AR5312_FLASHCTL_IDCY 0x0000000f /* Idle cycle turnaround time */
185#define AR5312_FLASHCTL_IDCY_S 0
186#define AR5312_FLASHCTL_WST1 0x000003e0 /* Wait state 1 */
187#define AR5312_FLASHCTL_WST1_S 5
188#define AR5312_FLASHCTL_RBLE 0x00000400 /* Read byte lane enable */
189#define AR5312_FLASHCTL_WST2 0x0000f800 /* Wait state 2 */
190#define AR5312_FLASHCTL_WST2_S 11
191#define AR5312_FLASHCTL_AC 0x00070000 /* Flash addr check (added) */
192#define AR5312_FLASHCTL_AC_S 16
193#define AR5312_FLASHCTL_AC_128K 0x00000000
194#define AR5312_FLASHCTL_AC_256K 0x00010000
195#define AR5312_FLASHCTL_AC_512K 0x00020000
196#define AR5312_FLASHCTL_AC_1M 0x00030000
197#define AR5312_FLASHCTL_AC_2M 0x00040000
198#define AR5312_FLASHCTL_AC_4M 0x00050000
199#define AR5312_FLASHCTL_AC_8M 0x00060000
200#define AR5312_FLASHCTL_AC_RES 0x00070000 /* 16MB is not supported */
201#define AR5312_FLASHCTL_E 0x00080000 /* Flash bank enable (added) */
202#define AR5312_FLASHCTL_BUSERR 0x01000000 /* Bus transfer error flag */
203#define AR5312_FLASHCTL_WPERR 0x02000000 /* Write protect error flag */
204#define AR5312_FLASHCTL_WP 0x04000000 /* Write protect */
205#define AR5312_FLASHCTL_BM 0x08000000 /* Burst mode */
206#define AR5312_FLASHCTL_MW 0x30000000 /* Mem width */
207#define AR5312_FLASHCTL_MW8 0x00000000 /* Mem width x8 */
208#define AR5312_FLASHCTL_MW16 0x10000000 /* Mem width x16 */
209#define AR5312_FLASHCTL_MW32 0x20000000 /* Mem width x32 (not supp) */
210#define AR5312_FLASHCTL_ATNR 0x00000000 /* Access == no retry */
211#define AR5312_FLASHCTL_ATR 0x80000000 /* Access == retry every */
212#define AR5312_FLASHCTL_ATR4 0xc0000000 /* Access == retry every 4 */
213
214/*
215 * ARM SDRAM Controller -- just enough to determine memory size
216 */
217#define AR5312_MEM_CFG1 0x0004
218
219#define AR5312_MEM_CFG1_AC0_M 0x00000700 /* bank 0: SDRAM addr check */
220#define AR5312_MEM_CFG1_AC0_S 8
221#define AR5312_MEM_CFG1_AC1_M 0x00007000 /* bank 1: SDRAM addr check */
222#define AR5312_MEM_CFG1_AC1_S 12
223
224#endif /* __ASM_MACH_ATH25_AR5312_REGS_H */
diff --git a/arch/mips/ath25/board.c b/arch/mips/ath25/board.c
new file mode 100644
index 000000000000..b8bb78282d6a
--- /dev/null
+++ b/arch/mips/ath25/board.c
@@ -0,0 +1,234 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
7 * Copyright (C) 2006 FON Technology, SL.
8 * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
9 * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
10 */
11
12#include <linux/init.h>
13#include <linux/interrupt.h>
14#include <asm/irq_cpu.h>
15#include <asm/reboot.h>
16#include <asm/bootinfo.h>
17#include <asm/time.h>
18
19#include <ath25_platform.h>
20#include "devices.h"
21#include "ar5312.h"
22#include "ar2315.h"
23
24void (*ath25_irq_dispatch)(void);
25
26static inline bool check_radio_magic(const void __iomem *addr)
27{
28 addr += 0x7a; /* offset for flash magic */
29 return (__raw_readb(addr) == 0x5a) && (__raw_readb(addr + 1) == 0xa5);
30}
31
32static inline bool check_notempty(const void __iomem *addr)
33{
34 return __raw_readl(addr) != 0xffffffff;
35}
36
37static inline bool check_board_data(const void __iomem *addr, bool broken)
38{
39 /* config magic found */
40 if (__raw_readl(addr) == ATH25_BD_MAGIC)
41 return true;
42
43 if (!broken)
44 return false;
45
46 /* broken board data detected, use radio data to find the
47 * offset, user will fix this */
48
49 if (check_radio_magic(addr + 0x1000))
50 return true;
51 if (check_radio_magic(addr + 0xf8))
52 return true;
53
54 return false;
55}
56
57static const void __iomem * __init find_board_config(const void __iomem *limit,
58 const bool broken)
59{
60 const void __iomem *addr;
61 const void __iomem *begin = limit - 0x1000;
62 const void __iomem *end = limit - 0x30000;
63
64 for (addr = begin; addr >= end; addr -= 0x1000)
65 if (check_board_data(addr, broken))
66 return addr;
67
68 return NULL;
69}
70
71static const void __iomem * __init find_radio_config(const void __iomem *limit,
72 const void __iomem *bcfg)
73{
74 const void __iomem *rcfg, *begin, *end;
75
76 /*
77 * Now find the start of Radio Configuration data, using heuristics:
78 * Search forward from Board Configuration data by 0x1000 bytes
79 * at a time until we find non-0xffffffff.
80 */
81 begin = bcfg + 0x1000;
82 end = limit;
83 for (rcfg = begin; rcfg < end; rcfg += 0x1000)
84 if (check_notempty(rcfg) && check_radio_magic(rcfg))
85 return rcfg;
86
87 /* AR2316 relocates radio config to new location */
88 begin = bcfg + 0xf8;
89 end = limit - 0x1000 + 0xf8;
90 for (rcfg = begin; rcfg < end; rcfg += 0x1000)
91 if (check_notempty(rcfg) && check_radio_magic(rcfg))
92 return rcfg;
93
94 return NULL;
95}
96
97/*
98 * NB: Search region size could be larger than the actual flash size,
99 * but this shouldn't be a problem here, because the flash
100 * will simply be mapped multiple times.
101 */
102int __init ath25_find_config(phys_addr_t base, unsigned long size)
103{
104 const void __iomem *flash_base, *flash_limit;
105 struct ath25_boarddata *config;
106 unsigned int rcfg_size;
107 int broken_boarddata = 0;
108 const void __iomem *bcfg, *rcfg;
109 u8 *board_data;
110 u8 *radio_data;
111 u8 *mac_addr;
112 u32 offset;
113
114 flash_base = ioremap_nocache(base, size);
115 flash_limit = flash_base + size;
116
117 ath25_board.config = NULL;
118 ath25_board.radio = NULL;
119
120 /* Copy the board and radio data to RAM, because accessing the mapped
121 * memory of the flash directly after booting is not safe */
122
123 /* Try to find valid board and radio data */
124 bcfg = find_board_config(flash_limit, false);
125
126 /* If that fails, try to at least find valid radio data */
127 if (!bcfg) {
128 bcfg = find_board_config(flash_limit, true);
129 broken_boarddata = 1;
130 }
131
132 if (!bcfg) {
133 pr_warn("WARNING: No board configuration data found!\n");
134 goto error;
135 }
136
137 board_data = kzalloc(BOARD_CONFIG_BUFSZ, GFP_KERNEL);
138 ath25_board.config = (struct ath25_boarddata *)board_data;
139 memcpy_fromio(board_data, bcfg, 0x100);
140 if (broken_boarddata) {
141 pr_warn("WARNING: broken board data detected\n");
142 config = ath25_board.config;
143 if (is_zero_ether_addr(config->enet0_mac)) {
144 pr_info("Fixing up empty mac addresses\n");
145 config->reset_config_gpio = 0xffff;
146 config->sys_led_gpio = 0xffff;
147 random_ether_addr(config->wlan0_mac);
148 config->wlan0_mac[0] &= ~0x06;
149 random_ether_addr(config->enet0_mac);
150 random_ether_addr(config->enet1_mac);
151 }
152 }
153
154 /* Radio config starts 0x100 bytes after board config, regardless
155 * of what the physical layout on the flash chip looks like */
156
157 rcfg = find_radio_config(flash_limit, bcfg);
158 if (!rcfg) {
159 pr_warn("WARNING: Could not find Radio Configuration data\n");
160 goto error;
161 }
162
163 radio_data = board_data + 0x100 + ((rcfg - bcfg) & 0xfff);
164 ath25_board.radio = radio_data;
165 offset = radio_data - board_data;
166 pr_info("Radio config found at offset 0x%x (0x%x)\n", rcfg - bcfg,
167 offset);
168 rcfg_size = BOARD_CONFIG_BUFSZ - offset;
169 memcpy_fromio(radio_data, rcfg, rcfg_size);
170
171 mac_addr = &radio_data[0x1d * 2];
172 if (is_broadcast_ether_addr(mac_addr)) {
173 pr_info("Radio MAC is blank; using board-data\n");
174 ether_addr_copy(mac_addr, ath25_board.config->wlan0_mac);
175 }
176
177 iounmap(flash_base);
178
179 return 0;
180
181error:
182 iounmap(flash_base);
183 return -ENODEV;
184}
185
186static void ath25_halt(void)
187{
188 local_irq_disable();
189 unreachable();
190}
191
192void __init plat_mem_setup(void)
193{
194 _machine_halt = ath25_halt;
195 pm_power_off = ath25_halt;
196
197 if (is_ar5312())
198 ar5312_plat_mem_setup();
199 else
200 ar2315_plat_mem_setup();
201
202 /* Disable data watchpoints */
203 write_c0_watchlo0(0);
204}
205
206asmlinkage void plat_irq_dispatch(void)
207{
208 ath25_irq_dispatch();
209}
210
211void __init plat_time_init(void)
212{
213 if (is_ar5312())
214 ar5312_plat_time_init();
215 else
216 ar2315_plat_time_init();
217}
218
219unsigned int __cpuinit get_c0_compare_int(void)
220{
221 return CP0_LEGACY_COMPARE_IRQ;
222}
223
224void __init arch_init_irq(void)
225{
226 clear_c0_status(ST0_IM);
227 mips_cpu_irq_init();
228
229 /* Initialize interrupt controllers */
230 if (is_ar5312())
231 ar5312_arch_init_irq();
232 else
233 ar2315_arch_init_irq();
234}
diff --git a/arch/mips/ath25/devices.c b/arch/mips/ath25/devices.c
new file mode 100644
index 000000000000..7a64567d1ac3
--- /dev/null
+++ b/arch/mips/ath25/devices.c
@@ -0,0 +1,125 @@
1#include <linux/kernel.h>
2#include <linux/init.h>
3#include <linux/serial_8250.h>
4#include <linux/platform_device.h>
5#include <asm/bootinfo.h>
6
7#include <ath25_platform.h>
8#include "devices.h"
9#include "ar5312.h"
10#include "ar2315.h"
11
12struct ar231x_board_config ath25_board;
13enum ath25_soc_type ath25_soc = ATH25_SOC_UNKNOWN;
14
15static struct resource ath25_wmac0_res[] = {
16 {
17 .name = "wmac0_membase",
18 .flags = IORESOURCE_MEM,
19 },
20 {
21 .name = "wmac0_irq",
22 .flags = IORESOURCE_IRQ,
23 }
24};
25
26static struct resource ath25_wmac1_res[] = {
27 {
28 .name = "wmac1_membase",
29 .flags = IORESOURCE_MEM,
30 },
31 {
32 .name = "wmac1_irq",
33 .flags = IORESOURCE_IRQ,
34 }
35};
36
37static struct platform_device ath25_wmac[] = {
38 {
39 .id = 0,
40 .name = "ar231x-wmac",
41 .resource = ath25_wmac0_res,
42 .num_resources = ARRAY_SIZE(ath25_wmac0_res),
43 .dev.platform_data = &ath25_board,
44 },
45 {
46 .id = 1,
47 .name = "ar231x-wmac",
48 .resource = ath25_wmac1_res,
49 .num_resources = ARRAY_SIZE(ath25_wmac1_res),
50 .dev.platform_data = &ath25_board,
51 },
52};
53
54static const char * const soc_type_strings[] = {
55 [ATH25_SOC_AR5312] = "Atheros AR5312",
56 [ATH25_SOC_AR2312] = "Atheros AR2312",
57 [ATH25_SOC_AR2313] = "Atheros AR2313",
58 [ATH25_SOC_AR2315] = "Atheros AR2315",
59 [ATH25_SOC_AR2316] = "Atheros AR2316",
60 [ATH25_SOC_AR2317] = "Atheros AR2317",
61 [ATH25_SOC_AR2318] = "Atheros AR2318",
62 [ATH25_SOC_UNKNOWN] = "Atheros (unknown)",
63};
64
65const char *get_system_type(void)
66{
67 if ((ath25_soc >= ARRAY_SIZE(soc_type_strings)) ||
68 !soc_type_strings[ath25_soc])
69 return soc_type_strings[ATH25_SOC_UNKNOWN];
70 return soc_type_strings[ath25_soc];
71}
72
73void __init ath25_serial_setup(u32 mapbase, int irq, unsigned int uartclk)
74{
75 struct uart_port s;
76
77 memset(&s, 0, sizeof(s));
78
79 s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP;
80 s.iotype = UPIO_MEM32;
81 s.irq = irq;
82 s.regshift = 2;
83 s.mapbase = mapbase;
84 s.uartclk = uartclk;
85
86 early_serial_setup(&s);
87}
88
89int __init ath25_add_wmac(int nr, u32 base, int irq)
90{
91 struct resource *res;
92
93 ath25_wmac[nr].dev.platform_data = &ath25_board;
94 res = &ath25_wmac[nr].resource[0];
95 res->start = base;
96 res->end = base + 0x10000 - 1;
97 res++;
98 res->start = irq;
99 res->end = irq;
100 return platform_device_register(&ath25_wmac[nr]);
101}
102
103static int __init ath25_register_devices(void)
104{
105 if (is_ar5312())
106 ar5312_init_devices();
107 else
108 ar2315_init_devices();
109
110 return 0;
111}
112
113device_initcall(ath25_register_devices);
114
115static int __init ath25_arch_init(void)
116{
117 if (is_ar5312())
118 ar5312_arch_init();
119 else
120 ar2315_arch_init();
121
122 return 0;
123}
124
125arch_initcall(ath25_arch_init);
diff --git a/arch/mips/ath25/devices.h b/arch/mips/ath25/devices.h
new file mode 100644
index 000000000000..04d414115356
--- /dev/null
+++ b/arch/mips/ath25/devices.h
@@ -0,0 +1,43 @@
1#ifndef __ATH25_DEVICES_H
2#define __ATH25_DEVICES_H
3
4#include <linux/cpu.h>
5
6#define ATH25_REG_MS(_val, _field) (((_val) & _field##_M) >> _field##_S)
7
8#define ATH25_IRQ_CPU_CLOCK (MIPS_CPU_IRQ_BASE + 7) /* C0_CAUSE: 0x8000 */
9
10enum ath25_soc_type {
11 /* handled by ar5312.c */
12 ATH25_SOC_AR2312,
13 ATH25_SOC_AR2313,
14 ATH25_SOC_AR5312,
15
16 /* handled by ar2315.c */
17 ATH25_SOC_AR2315,
18 ATH25_SOC_AR2316,
19 ATH25_SOC_AR2317,
20 ATH25_SOC_AR2318,
21
22 ATH25_SOC_UNKNOWN
23};
24
25extern enum ath25_soc_type ath25_soc;
26extern struct ar231x_board_config ath25_board;
27extern void (*ath25_irq_dispatch)(void);
28
29int ath25_find_config(phys_addr_t offset, unsigned long size);
30void ath25_serial_setup(u32 mapbase, int irq, unsigned int uartclk);
31int ath25_add_wmac(int nr, u32 base, int irq);
32
33static inline bool is_ar2315(void)
34{
35 return (current_cpu_data.cputype == CPU_4KEC);
36}
37
38static inline bool is_ar5312(void)
39{
40 return !is_ar2315();
41}
42
43#endif
diff --git a/arch/mips/ath25/early_printk.c b/arch/mips/ath25/early_printk.c
new file mode 100644
index 000000000000..36035b628161
--- /dev/null
+++ b/arch/mips/ath25/early_printk.c
@@ -0,0 +1,44 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org>
7 */
8
9#include <linux/mm.h>
10#include <linux/io.h>
11#include <linux/serial_reg.h>
12
13#include "devices.h"
14#include "ar2315_regs.h"
15#include "ar5312_regs.h"
16
17static inline void prom_uart_wr(void __iomem *base, unsigned reg,
18 unsigned char ch)
19{
20 __raw_writel(ch, base + 4 * reg);
21}
22
23static inline unsigned char prom_uart_rr(void __iomem *base, unsigned reg)
24{
25 return __raw_readl(base + 4 * reg);
26}
27
28void prom_putchar(unsigned char ch)
29{
30 static void __iomem *base;
31
32 if (unlikely(base == NULL)) {
33 if (is_ar2315())
34 base = (void __iomem *)(KSEG1ADDR(AR2315_UART0_BASE));
35 else
36 base = (void __iomem *)(KSEG1ADDR(AR5312_UART0_BASE));
37 }
38
39 while ((prom_uart_rr(base, UART_LSR) & UART_LSR_THRE) == 0)
40 ;
41 prom_uart_wr(base, UART_TX, ch);
42 while ((prom_uart_rr(base, UART_LSR) & UART_LSR_THRE) == 0)
43 ;
44}
diff --git a/arch/mips/ath25/prom.c b/arch/mips/ath25/prom.c
new file mode 100644
index 000000000000..edf82be8870d
--- /dev/null
+++ b/arch/mips/ath25/prom.c
@@ -0,0 +1,26 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright MontaVista Software Inc
7 * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
8 * Copyright (C) 2006 FON Technology, SL.
9 * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
10 * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
11 */
12
13/*
14 * Prom setup file for AR5312/AR231x SoCs
15 */
16
17#include <linux/init.h>
18#include <asm/bootinfo.h>
19
20void __init prom_init(void)
21{
22}
23
24void __init prom_free_prom_memory(void)
25{
26}
generated by cgit v1.2.2 (git 2.25.0) at 2025-05-31 19:56:17 -0400