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-rw-r--r--arch/mips/ar7/clock.c109
-rw-r--r--arch/mips/ar7/gpio.c113
-rw-r--r--arch/mips/ar7/memory.c3
-rw-r--r--arch/mips/ar7/platform.c713
-rw-r--r--arch/mips/ar7/prom.c78
-rw-r--r--arch/mips/ar7/setup.c15
-rw-r--r--arch/mips/ar7/time.c12
7 files changed, 610 insertions, 433 deletions
diff --git a/arch/mips/ar7/clock.c b/arch/mips/ar7/clock.c
index cc65c8eb391b..fc0e7154e8d6 100644
--- a/arch/mips/ar7/clock.c
+++ b/arch/mips/ar7/clock.c
@@ -1,6 +1,7 @@
1/* 1/*
2 * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org> 2 * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
3 * Copyright (C) 2007 Eugene Konev <ejka@openwrt.org> 3 * Copyright (C) 2007 Eugene Konev <ejka@openwrt.org>
4 * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
4 * 5 *
5 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by 7 * it under the terms of the GNU General Public License as published by
@@ -24,6 +25,8 @@
24#include <linux/delay.h> 25#include <linux/delay.h>
25#include <linux/gcd.h> 26#include <linux/gcd.h>
26#include <linux/io.h> 27#include <linux/io.h>
28#include <linux/err.h>
29#include <linux/clk.h>
27 30
28#include <asm/addrspace.h> 31#include <asm/addrspace.h>
29#include <asm/mach-ar7/ar7.h> 32#include <asm/mach-ar7/ar7.h>
@@ -94,12 +97,16 @@ struct tnetd7200_clocks {
94 struct tnetd7200_clock usb; 97 struct tnetd7200_clock usb;
95}; 98};
96 99
97int ar7_cpu_clock = 150000000; 100static struct clk bus_clk = {
98EXPORT_SYMBOL(ar7_cpu_clock); 101 .rate = 125000000,
99int ar7_bus_clock = 125000000; 102};
100EXPORT_SYMBOL(ar7_bus_clock); 103
101int ar7_dsp_clock; 104static struct clk cpu_clk = {
102EXPORT_SYMBOL(ar7_dsp_clock); 105 .rate = 150000000,
106};
107
108static struct clk dsp_clk;
109static struct clk vbus_clk;
103 110
104static void approximate(int base, int target, int *prediv, 111static void approximate(int base, int target, int *prediv,
105 int *postdiv, int *mul) 112 int *postdiv, int *mul)
@@ -185,7 +192,7 @@ static int tnetd7300_get_clock(u32 shift, struct tnetd7300_clock *clock,
185 base_clock = AR7_XTAL_CLOCK; 192 base_clock = AR7_XTAL_CLOCK;
186 break; 193 break;
187 case BOOT_PLL_SOURCE_CPU: 194 case BOOT_PLL_SOURCE_CPU:
188 base_clock = ar7_cpu_clock; 195 base_clock = cpu_clk.rate;
189 break; 196 break;
190 } 197 }
191 198
@@ -212,11 +219,11 @@ static void tnetd7300_set_clock(u32 shift, struct tnetd7300_clock *clock,
212 u32 *bootcr, u32 frequency) 219 u32 *bootcr, u32 frequency)
213{ 220{
214 int prediv, postdiv, mul; 221 int prediv, postdiv, mul;
215 int base_clock = ar7_bus_clock; 222 int base_clock = bus_clk.rate;
216 223
217 switch ((*bootcr & (BOOT_PLL_SOURCE_MASK << shift)) >> shift) { 224 switch ((*bootcr & (BOOT_PLL_SOURCE_MASK << shift)) >> shift) {
218 case BOOT_PLL_SOURCE_BUS: 225 case BOOT_PLL_SOURCE_BUS:
219 base_clock = ar7_bus_clock; 226 base_clock = bus_clk.rate;
220 break; 227 break;
221 case BOOT_PLL_SOURCE_REF: 228 case BOOT_PLL_SOURCE_REF:
222 base_clock = AR7_REF_CLOCK; 229 base_clock = AR7_REF_CLOCK;
@@ -225,7 +232,7 @@ static void tnetd7300_set_clock(u32 shift, struct tnetd7300_clock *clock,
225 base_clock = AR7_XTAL_CLOCK; 232 base_clock = AR7_XTAL_CLOCK;
226 break; 233 break;
227 case BOOT_PLL_SOURCE_CPU: 234 case BOOT_PLL_SOURCE_CPU:
228 base_clock = ar7_cpu_clock; 235 base_clock = cpu_clk.rate;
229 break; 236 break;
230 } 237 }
231 238
@@ -247,18 +254,18 @@ static void __init tnetd7300_init_clocks(void)
247 ioremap_nocache(UR8_REGS_CLOCKS, 254 ioremap_nocache(UR8_REGS_CLOCKS,
248 sizeof(struct tnetd7300_clocks)); 255 sizeof(struct tnetd7300_clocks));
249 256
250 ar7_bus_clock = tnetd7300_get_clock(BUS_PLL_SOURCE_SHIFT, 257 bus_clk.rate = tnetd7300_get_clock(BUS_PLL_SOURCE_SHIFT,
251 &clocks->bus, bootcr, AR7_AFE_CLOCK); 258 &clocks->bus, bootcr, AR7_AFE_CLOCK);
252 259
253 if (*bootcr & BOOT_PLL_ASYNC_MODE) 260 if (*bootcr & BOOT_PLL_ASYNC_MODE)
254 ar7_cpu_clock = tnetd7300_get_clock(CPU_PLL_SOURCE_SHIFT, 261 cpu_clk.rate = tnetd7300_get_clock(CPU_PLL_SOURCE_SHIFT,
255 &clocks->cpu, bootcr, AR7_AFE_CLOCK); 262 &clocks->cpu, bootcr, AR7_AFE_CLOCK);
256 else 263 else
257 ar7_cpu_clock = ar7_bus_clock; 264 cpu_clk.rate = bus_clk.rate;
258 265
259 if (ar7_dsp_clock == 250000000) 266 if (dsp_clk.rate == 250000000)
260 tnetd7300_set_clock(DSP_PLL_SOURCE_SHIFT, &clocks->dsp, 267 tnetd7300_set_clock(DSP_PLL_SOURCE_SHIFT, &clocks->dsp,
261 bootcr, ar7_dsp_clock); 268 bootcr, dsp_clk.rate);
262 269
263 iounmap(clocks); 270 iounmap(clocks);
264 iounmap(bootcr); 271 iounmap(bootcr);
@@ -343,20 +350,20 @@ static void __init tnetd7200_init_clocks(void)
343 printk(KERN_INFO "Clocks: Setting DSP clock\n"); 350 printk(KERN_INFO "Clocks: Setting DSP clock\n");
344 calculate(dsp_base, TNETD7200_DEF_DSP_CLK, 351 calculate(dsp_base, TNETD7200_DEF_DSP_CLK,
345 &dsp_prediv, &dsp_postdiv, &dsp_mul); 352 &dsp_prediv, &dsp_postdiv, &dsp_mul);
346 ar7_bus_clock = 353 bus_clk.rate =
347 ((dsp_base / dsp_prediv) * dsp_mul) / dsp_postdiv; 354 ((dsp_base / dsp_prediv) * dsp_mul) / dsp_postdiv;
348 tnetd7200_set_clock(dsp_base, &clocks->dsp, 355 tnetd7200_set_clock(dsp_base, &clocks->dsp,
349 dsp_prediv, dsp_postdiv * 2, dsp_postdiv, dsp_mul * 2, 356 dsp_prediv, dsp_postdiv * 2, dsp_postdiv, dsp_mul * 2,
350 ar7_bus_clock); 357 bus_clk.rate);
351 358
352 printk(KERN_INFO "Clocks: Setting CPU clock\n"); 359 printk(KERN_INFO "Clocks: Setting CPU clock\n");
353 calculate(cpu_base, TNETD7200_DEF_CPU_CLK, &cpu_prediv, 360 calculate(cpu_base, TNETD7200_DEF_CPU_CLK, &cpu_prediv,
354 &cpu_postdiv, &cpu_mul); 361 &cpu_postdiv, &cpu_mul);
355 ar7_cpu_clock = 362 cpu_clk.rate =
356 ((cpu_base / cpu_prediv) * cpu_mul) / cpu_postdiv; 363 ((cpu_base / cpu_prediv) * cpu_mul) / cpu_postdiv;
357 tnetd7200_set_clock(cpu_base, &clocks->cpu, 364 tnetd7200_set_clock(cpu_base, &clocks->cpu,
358 cpu_prediv, cpu_postdiv, -1, cpu_mul, 365 cpu_prediv, cpu_postdiv, -1, cpu_mul,
359 ar7_cpu_clock); 366 cpu_clk.rate);
360 367
361 } else 368 } else
362 if (*bootcr & BOOT_PLL_2TO1_MODE) { 369 if (*bootcr & BOOT_PLL_2TO1_MODE) {
@@ -365,48 +372,90 @@ static void __init tnetd7200_init_clocks(void)
365 printk(KERN_INFO "Clocks: Setting CPU clock\n"); 372 printk(KERN_INFO "Clocks: Setting CPU clock\n");
366 calculate(cpu_base, TNETD7200_DEF_CPU_CLK, &cpu_prediv, 373 calculate(cpu_base, TNETD7200_DEF_CPU_CLK, &cpu_prediv,
367 &cpu_postdiv, &cpu_mul); 374 &cpu_postdiv, &cpu_mul);
368 ar7_cpu_clock = ((cpu_base / cpu_prediv) * cpu_mul) 375 cpu_clk.rate = ((cpu_base / cpu_prediv) * cpu_mul)
369 / cpu_postdiv; 376 / cpu_postdiv;
370 tnetd7200_set_clock(cpu_base, &clocks->cpu, 377 tnetd7200_set_clock(cpu_base, &clocks->cpu,
371 cpu_prediv, cpu_postdiv, -1, cpu_mul, 378 cpu_prediv, cpu_postdiv, -1, cpu_mul,
372 ar7_cpu_clock); 379 cpu_clk.rate);
373 380
374 printk(KERN_INFO "Clocks: Setting DSP clock\n"); 381 printk(KERN_INFO "Clocks: Setting DSP clock\n");
375 calculate(dsp_base, TNETD7200_DEF_DSP_CLK, &dsp_prediv, 382 calculate(dsp_base, TNETD7200_DEF_DSP_CLK, &dsp_prediv,
376 &dsp_postdiv, &dsp_mul); 383 &dsp_postdiv, &dsp_mul);
377 ar7_bus_clock = ar7_cpu_clock / 2; 384 bus_clk.rate = cpu_clk.rate / 2;
378 tnetd7200_set_clock(dsp_base, &clocks->dsp, 385 tnetd7200_set_clock(dsp_base, &clocks->dsp,
379 dsp_prediv, dsp_postdiv * 2, dsp_postdiv, 386 dsp_prediv, dsp_postdiv * 2, dsp_postdiv,
380 dsp_mul * 2, ar7_bus_clock); 387 dsp_mul * 2, bus_clk.rate);
381 } else { 388 } else {
382 printk(KERN_INFO "Clocks: Sync 1:1 mode\n"); 389 printk(KERN_INFO "Clocks: Sync 1:1 mode\n");
383 390
384 printk(KERN_INFO "Clocks: Setting DSP clock\n"); 391 printk(KERN_INFO "Clocks: Setting DSP clock\n");
385 calculate(dsp_base, TNETD7200_DEF_DSP_CLK, &dsp_prediv, 392 calculate(dsp_base, TNETD7200_DEF_DSP_CLK, &dsp_prediv,
386 &dsp_postdiv, &dsp_mul); 393 &dsp_postdiv, &dsp_mul);
387 ar7_bus_clock = ((dsp_base / dsp_prediv) * dsp_mul) 394 bus_clk.rate = ((dsp_base / dsp_prediv) * dsp_mul)
388 / dsp_postdiv; 395 / dsp_postdiv;
389 tnetd7200_set_clock(dsp_base, &clocks->dsp, 396 tnetd7200_set_clock(dsp_base, &clocks->dsp,
390 dsp_prediv, dsp_postdiv * 2, dsp_postdiv, 397 dsp_prediv, dsp_postdiv * 2, dsp_postdiv,
391 dsp_mul * 2, ar7_bus_clock); 398 dsp_mul * 2, bus_clk.rate);
392 399
393 ar7_cpu_clock = ar7_bus_clock; 400 cpu_clk.rate = bus_clk.rate;
394 } 401 }
395 402
396 printk(KERN_INFO "Clocks: Setting USB clock\n"); 403 printk(KERN_INFO "Clocks: Setting USB clock\n");
397 usb_base = ar7_bus_clock; 404 usb_base = bus_clk.rate;
398 calculate(usb_base, TNETD7200_DEF_USB_CLK, &usb_prediv, 405 calculate(usb_base, TNETD7200_DEF_USB_CLK, &usb_prediv,
399 &usb_postdiv, &usb_mul); 406 &usb_postdiv, &usb_mul);
400 tnetd7200_set_clock(usb_base, &clocks->usb, 407 tnetd7200_set_clock(usb_base, &clocks->usb,
401 usb_prediv, usb_postdiv, -1, usb_mul, 408 usb_prediv, usb_postdiv, -1, usb_mul,
402 TNETD7200_DEF_USB_CLK); 409 TNETD7200_DEF_USB_CLK);
403 410
404 ar7_dsp_clock = ar7_cpu_clock; 411 dsp_clk.rate = cpu_clk.rate;
405 412
406 iounmap(clocks); 413 iounmap(clocks);
407 iounmap(bootcr); 414 iounmap(bootcr);
408} 415}
409 416
417/*
418 * Linux clock API
419 */
420int clk_enable(struct clk *clk)
421{
422 return 0;
423}
424EXPORT_SYMBOL(clk_enable);
425
426void clk_disable(struct clk *clk)
427{
428}
429EXPORT_SYMBOL(clk_disable);
430
431unsigned long clk_get_rate(struct clk *clk)
432{
433 return clk->rate;
434}
435EXPORT_SYMBOL(clk_get_rate);
436
437struct clk *clk_get(struct device *dev, const char *id)
438{
439 if (!strcmp(id, "bus"))
440 return &bus_clk;
441 /* cpmac and vbus share the same rate */
442 if (!strcmp(id, "cpmac"))
443 return &vbus_clk;
444 if (!strcmp(id, "cpu"))
445 return &cpu_clk;
446 if (!strcmp(id, "dsp"));
447 return &dsp_clk;
448 if (!strcmp(id, "vbus"))
449 return &vbus_clk;
450 return ERR_PTR(-ENOENT);
451}
452EXPORT_SYMBOL(clk_get);
453
454void clk_put(struct clk *clk)
455{
456}
457EXPORT_SYMBOL(clk_put);
458
410int __init ar7_init_clocks(void) 459int __init ar7_init_clocks(void)
411{ 460{
412 switch (ar7_chip_id()) { 461 switch (ar7_chip_id()) {
@@ -415,12 +464,14 @@ int __init ar7_init_clocks(void)
415 tnetd7200_init_clocks(); 464 tnetd7200_init_clocks();
416 break; 465 break;
417 case AR7_CHIP_7300: 466 case AR7_CHIP_7300:
418 ar7_dsp_clock = tnetd7300_dsp_clock(); 467 dsp_clk.rate = tnetd7300_dsp_clock();
419 tnetd7300_init_clocks(); 468 tnetd7300_init_clocks();
420 break; 469 break;
421 default: 470 default:
422 break; 471 break;
423 } 472 }
473 /* adjust vbus clock rate */
474 vbus_clk.rate = bus_clk.rate / 2;
424 475
425 return 0; 476 return 0;
426} 477}
diff --git a/arch/mips/ar7/gpio.c b/arch/mips/ar7/gpio.c
index 74e14a3dbf4a..c32fbb57441a 100644
--- a/arch/mips/ar7/gpio.c
+++ b/arch/mips/ar7/gpio.c
@@ -1,6 +1,7 @@
1/* 1/*
2 * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org> 2 * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
3 * Copyright (C) 2007 Eugene Konev <ejka@openwrt.org> 3 * Copyright (C) 2007 Eugene Konev <ejka@openwrt.org>
4 * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
4 * 5 *
5 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by 7 * it under the terms of the GNU General Public License as published by
@@ -18,31 +19,113 @@
18 */ 19 */
19 20
20#include <linux/module.h> 21#include <linux/module.h>
22#include <linux/gpio.h>
21 23
22#include <asm/mach-ar7/gpio.h> 24#include <asm/mach-ar7/gpio.h>
23 25
24static const char *ar7_gpio_list[AR7_GPIO_MAX]; 26struct ar7_gpio_chip {
27 void __iomem *regs;
28 struct gpio_chip chip;
29};
25 30
26int gpio_request(unsigned gpio, const char *label) 31static int ar7_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
27{ 32{
28 if (gpio >= AR7_GPIO_MAX) 33 struct ar7_gpio_chip *gpch =
29 return -EINVAL; 34 container_of(chip, struct ar7_gpio_chip, chip);
35 void __iomem *gpio_in = gpch->regs + AR7_GPIO_INPUT;
30 36
31 if (ar7_gpio_list[gpio]) 37 return readl(gpio_in) & (1 << gpio);
32 return -EBUSY; 38}
39
40static void ar7_gpio_set_value(struct gpio_chip *chip,
41 unsigned gpio, int value)
42{
43 struct ar7_gpio_chip *gpch =
44 container_of(chip, struct ar7_gpio_chip, chip);
45 void __iomem *gpio_out = gpch->regs + AR7_GPIO_OUTPUT;
46 unsigned tmp;
47
48 tmp = readl(gpio_out) & ~(1 << gpio);
49 if (value)
50 tmp |= 1 << gpio;
51 writel(tmp, gpio_out);
52}
53
54static int ar7_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
55{
56 struct ar7_gpio_chip *gpch =
57 container_of(chip, struct ar7_gpio_chip, chip);
58 void __iomem *gpio_dir = gpch->regs + AR7_GPIO_DIR;
33 59
34 if (label) 60 writel(readl(gpio_dir) | (1 << gpio), gpio_dir);
35 ar7_gpio_list[gpio] = label;
36 else
37 ar7_gpio_list[gpio] = "busy";
38 61
39 return 0; 62 return 0;
40} 63}
41EXPORT_SYMBOL(gpio_request);
42 64
43void gpio_free(unsigned gpio) 65static int ar7_gpio_direction_output(struct gpio_chip *chip,
66 unsigned gpio, int value)
44{ 67{
45 BUG_ON(!ar7_gpio_list[gpio]); 68 struct ar7_gpio_chip *gpch =
46 ar7_gpio_list[gpio] = NULL; 69 container_of(chip, struct ar7_gpio_chip, chip);
70 void __iomem *gpio_dir = gpch->regs + AR7_GPIO_DIR;
71
72 ar7_gpio_set_value(chip, gpio, value);
73 writel(readl(gpio_dir) & ~(1 << gpio), gpio_dir);
74
75 return 0;
76}
77
78static struct ar7_gpio_chip ar7_gpio_chip = {
79 .chip = {
80 .label = "ar7-gpio",
81 .direction_input = ar7_gpio_direction_input,
82 .direction_output = ar7_gpio_direction_output,
83 .set = ar7_gpio_set_value,
84 .get = ar7_gpio_get_value,
85 .base = 0,
86 .ngpio = AR7_GPIO_MAX,
87 }
88};
89
90int ar7_gpio_enable(unsigned gpio)
91{
92 void __iomem *gpio_en = ar7_gpio_chip.regs + AR7_GPIO_ENABLE;
93
94 writel(readl(gpio_en) | (1 << gpio), gpio_en);
95
96 return 0;
97}
98EXPORT_SYMBOL(ar7_gpio_enable);
99
100int ar7_gpio_disable(unsigned gpio)
101{
102 void __iomem *gpio_en = ar7_gpio_chip.regs + AR7_GPIO_ENABLE;
103
104 writel(readl(gpio_en) & ~(1 << gpio), gpio_en);
105
106 return 0;
107}
108EXPORT_SYMBOL(ar7_gpio_disable);
109
110static int __init ar7_gpio_init(void)
111{
112 int ret;
113
114 ar7_gpio_chip.regs = ioremap_nocache(AR7_REGS_GPIO,
115 AR7_REGS_GPIO + 0x10);
116
117 if (!ar7_gpio_chip.regs) {
118 printk(KERN_ERR "ar7-gpio: failed to ioremap regs\n");
119 return -ENOMEM;
120 }
121
122 ret = gpiochip_add(&ar7_gpio_chip.chip);
123 if (ret) {
124 printk(KERN_ERR "ar7-gpio: failed to add gpiochip\n");
125 return ret;
126 }
127 printk(KERN_INFO "ar7-gpio: registered %d GPIOs\n",
128 ar7_gpio_chip.chip.ngpio);
129 return ret;
47} 130}
48EXPORT_SYMBOL(gpio_free); 131arch_initcall(ar7_gpio_init);
diff --git a/arch/mips/ar7/memory.c b/arch/mips/ar7/memory.c
index 696c723dc6d4..28abfeef09d6 100644
--- a/arch/mips/ar7/memory.c
+++ b/arch/mips/ar7/memory.c
@@ -62,8 +62,7 @@ void __init prom_meminit(void)
62 unsigned long pages; 62 unsigned long pages;
63 63
64 pages = memsize() >> PAGE_SHIFT; 64 pages = memsize() >> PAGE_SHIFT;
65 add_memory_region(PHYS_OFFSET, pages << PAGE_SHIFT, 65 add_memory_region(PHYS_OFFSET, pages << PAGE_SHIFT, BOOT_MEM_RAM);
66 BOOT_MEM_RAM);
67} 66}
68 67
69void __init prom_free_prom_memory(void) 68void __init prom_free_prom_memory(void)
diff --git a/arch/mips/ar7/platform.c b/arch/mips/ar7/platform.c
index f70a10a8cc96..246df7aca2e7 100644
--- a/arch/mips/ar7/platform.c
+++ b/arch/mips/ar7/platform.c
@@ -34,45 +34,50 @@
34#include <linux/etherdevice.h> 34#include <linux/etherdevice.h>
35#include <linux/phy.h> 35#include <linux/phy.h>
36#include <linux/phy_fixed.h> 36#include <linux/phy_fixed.h>
37#include <linux/gpio.h>
38#include <linux/clk.h>
37 39
38#include <asm/addrspace.h> 40#include <asm/addrspace.h>
39#include <asm/mach-ar7/ar7.h> 41#include <asm/mach-ar7/ar7.h>
40#include <asm/mach-ar7/gpio.h> 42#include <asm/mach-ar7/gpio.h>
41#include <asm/mach-ar7/prom.h> 43#include <asm/mach-ar7/prom.h>
42 44
45/*****************************************************************************
46 * VLYNQ Bus
47 ****************************************************************************/
43struct plat_vlynq_data { 48struct plat_vlynq_data {
44 struct plat_vlynq_ops ops; 49 struct plat_vlynq_ops ops;
45 int gpio_bit; 50 int gpio_bit;
46 int reset_bit; 51 int reset_bit;
47}; 52};
48 53
49
50static int vlynq_on(struct vlynq_device *dev) 54static int vlynq_on(struct vlynq_device *dev)
51{ 55{
52 int result; 56 int ret;
53 struct plat_vlynq_data *pdata = dev->dev.platform_data; 57 struct plat_vlynq_data *pdata = dev->dev.platform_data;
54 58
55 result = gpio_request(pdata->gpio_bit, "vlynq"); 59 ret = gpio_request(pdata->gpio_bit, "vlynq");
56 if (result) 60 if (ret)
57 goto out; 61 goto out;
58 62
59 ar7_device_reset(pdata->reset_bit); 63 ar7_device_reset(pdata->reset_bit);
60 64
61 result = ar7_gpio_disable(pdata->gpio_bit); 65 ret = ar7_gpio_disable(pdata->gpio_bit);
62 if (result) 66 if (ret)
63 goto out_enabled; 67 goto out_enabled;
64 68
65 result = ar7_gpio_enable(pdata->gpio_bit); 69 ret = ar7_gpio_enable(pdata->gpio_bit);
66 if (result) 70 if (ret)
67 goto out_enabled; 71 goto out_enabled;
68 72
69 result = gpio_direction_output(pdata->gpio_bit, 0); 73 ret = gpio_direction_output(pdata->gpio_bit, 0);
70 if (result) 74 if (ret)
71 goto out_gpio_enabled; 75 goto out_gpio_enabled;
72 76
73 msleep(50); 77 msleep(50);
74 78
75 gpio_set_value(pdata->gpio_bit, 1); 79 gpio_set_value(pdata->gpio_bit, 1);
80
76 msleep(50); 81 msleep(50);
77 82
78 return 0; 83 return 0;
@@ -83,320 +88,384 @@ out_enabled:
83 ar7_device_disable(pdata->reset_bit); 88 ar7_device_disable(pdata->reset_bit);
84 gpio_free(pdata->gpio_bit); 89 gpio_free(pdata->gpio_bit);
85out: 90out:
86 return result; 91 return ret;
87} 92}
88 93
89static void vlynq_off(struct vlynq_device *dev) 94static void vlynq_off(struct vlynq_device *dev)
90{ 95{
91 struct plat_vlynq_data *pdata = dev->dev.platform_data; 96 struct plat_vlynq_data *pdata = dev->dev.platform_data;
97
92 ar7_gpio_disable(pdata->gpio_bit); 98 ar7_gpio_disable(pdata->gpio_bit);
93 gpio_free(pdata->gpio_bit); 99 gpio_free(pdata->gpio_bit);
94 ar7_device_disable(pdata->reset_bit); 100 ar7_device_disable(pdata->reset_bit);
95} 101}
96 102
97static struct resource physmap_flash_resource = { 103static struct resource vlynq_low_res[] = {
98 .name = "mem",
99 .flags = IORESOURCE_MEM,
100 .start = 0x10000000,
101 .end = 0x107fffff,
102};
103
104static struct resource cpmac_low_res[] = {
105 { 104 {
106 .name = "regs", 105 .name = "regs",
107 .flags = IORESOURCE_MEM, 106 .flags = IORESOURCE_MEM,
108 .start = AR7_REGS_MAC0, 107 .start = AR7_REGS_VLYNQ0,
109 .end = AR7_REGS_MAC0 + 0x7ff, 108 .end = AR7_REGS_VLYNQ0 + 0xff,
110 }, 109 },
111 { 110 {
112 .name = "irq", 111 .name = "irq",
113 .flags = IORESOURCE_IRQ, 112 .flags = IORESOURCE_IRQ,
114 .start = 27, 113 .start = 29,
115 .end = 27, 114 .end = 29,
116 }, 115 },
117};
118
119static struct resource cpmac_high_res[] = {
120 { 116 {
121 .name = "regs", 117 .name = "mem",
122 .flags = IORESOURCE_MEM, 118 .flags = IORESOURCE_MEM,
123 .start = AR7_REGS_MAC1, 119 .start = 0x04000000,
124 .end = AR7_REGS_MAC1 + 0x7ff, 120 .end = 0x04ffffff,
125 }, 121 },
126 { 122 {
127 .name = "irq", 123 .name = "devirq",
128 .flags = IORESOURCE_IRQ, 124 .flags = IORESOURCE_IRQ,
129 .start = 41, 125 .start = 80,
130 .end = 41, 126 .end = 111,
131 }, 127 },
132}; 128};
133 129
134static struct resource vlynq_low_res[] = { 130static struct resource vlynq_high_res[] = {
135 { 131 {
136 .name = "regs", 132 .name = "regs",
137 .flags = IORESOURCE_MEM, 133 .flags = IORESOURCE_MEM,
138 .start = AR7_REGS_VLYNQ0, 134 .start = AR7_REGS_VLYNQ1,
139 .end = AR7_REGS_VLYNQ0 + 0xff, 135 .end = AR7_REGS_VLYNQ1 + 0xff,
140 }, 136 },
141 { 137 {
142 .name = "irq", 138 .name = "irq",
143 .flags = IORESOURCE_IRQ, 139 .flags = IORESOURCE_IRQ,
144 .start = 29, 140 .start = 33,
145 .end = 29, 141 .end = 33,
146 }, 142 },
147 { 143 {
148 .name = "mem", 144 .name = "mem",
149 .flags = IORESOURCE_MEM, 145 .flags = IORESOURCE_MEM,
150 .start = 0x04000000, 146 .start = 0x0c000000,
151 .end = 0x04ffffff, 147 .end = 0x0cffffff,
152 }, 148 },
153 { 149 {
154 .name = "devirq", 150 .name = "devirq",
155 .flags = IORESOURCE_IRQ, 151 .flags = IORESOURCE_IRQ,
156 .start = 80, 152 .start = 112,
157 .end = 111, 153 .end = 143,
158 }, 154 },
159}; 155};
160 156
161static struct resource vlynq_high_res[] = { 157static struct plat_vlynq_data vlynq_low_data = {
162 { 158 .ops = {
163 .name = "regs", 159 .on = vlynq_on,
164 .flags = IORESOURCE_MEM, 160 .off = vlynq_off,
165 .start = AR7_REGS_VLYNQ1,
166 .end = AR7_REGS_VLYNQ1 + 0xff,
167 }, 161 },
168 { 162 .reset_bit = 20,
169 .name = "irq", 163 .gpio_bit = 18,
170 .flags = IORESOURCE_IRQ, 164};
171 .start = 33, 165
172 .end = 33, 166static struct plat_vlynq_data vlynq_high_data = {
167 .ops = {
168 .on = vlynq_on,
169 .off = vlynq_off,
173 }, 170 },
174 { 171 .reset_bit = 26,
175 .name = "mem", 172 .gpio_bit = 19,
176 .flags = IORESOURCE_MEM, 173};
177 .start = 0x0c000000, 174
178 .end = 0x0cffffff, 175static struct platform_device vlynq_low = {
176 .id = 0,
177 .name = "vlynq",
178 .dev = {
179 .platform_data = &vlynq_low_data,
179 }, 180 },
180 { 181 .resource = vlynq_low_res,
181 .name = "devirq", 182 .num_resources = ARRAY_SIZE(vlynq_low_res),
182 .flags = IORESOURCE_IRQ, 183};
183 .start = 112, 184
184 .end = 143, 185static struct platform_device vlynq_high = {
186 .id = 1,
187 .name = "vlynq",
188 .dev = {
189 .platform_data = &vlynq_high_data,
185 }, 190 },
191 .resource = vlynq_high_res,
192 .num_resources = ARRAY_SIZE(vlynq_high_res),
186}; 193};
187 194
188static struct resource usb_res[] = { 195/*****************************************************************************
189 { 196 * Flash
190 .name = "regs", 197 ****************************************************************************/
191 .flags = IORESOURCE_MEM, 198static struct resource physmap_flash_resource = {
192 .start = AR7_REGS_USB, 199 .name = "mem",
193 .end = AR7_REGS_USB + 0xff, 200 .flags = IORESOURCE_MEM,
201 .start = 0x10000000,
202 .end = 0x107fffff,
203};
204
205static struct physmap_flash_data physmap_flash_data = {
206 .width = 2,
207};
208
209static struct platform_device physmap_flash = {
210 .name = "physmap-flash",
211 .dev = {
212 .platform_data = &physmap_flash_data,
194 }, 213 },
214 .resource = &physmap_flash_resource,
215 .num_resources = 1,
216};
217
218/*****************************************************************************
219 * Ethernet
220 ****************************************************************************/
221static struct resource cpmac_low_res[] = {
195 { 222 {
196 .name = "irq", 223 .name = "regs",
197 .flags = IORESOURCE_IRQ, 224 .flags = IORESOURCE_MEM,
198 .start = 32, 225 .start = AR7_REGS_MAC0,
199 .end = 32, 226 .end = AR7_REGS_MAC0 + 0x7ff,
200 }, 227 },
201 { 228 {
202 .name = "mem", 229 .name = "irq",
203 .flags = IORESOURCE_MEM, 230 .flags = IORESOURCE_IRQ,
204 .start = 0x03400000, 231 .start = 27,
205 .end = 0x03401fff, 232 .end = 27,
206 }, 233 },
207}; 234};
208 235
209static struct physmap_flash_data physmap_flash_data = { 236static struct resource cpmac_high_res[] = {
210 .width = 2, 237 {
238 .name = "regs",
239 .flags = IORESOURCE_MEM,
240 .start = AR7_REGS_MAC1,
241 .end = AR7_REGS_MAC1 + 0x7ff,
242 },
243 {
244 .name = "irq",
245 .flags = IORESOURCE_IRQ,
246 .start = 41,
247 .end = 41,
248 },
211}; 249};
212 250
213static struct fixed_phy_status fixed_phy_status __initdata = { 251static struct fixed_phy_status fixed_phy_status __initdata = {
214 .link = 1, 252 .link = 1,
215 .speed = 100, 253 .speed = 100,
216 .duplex = 1, 254 .duplex = 1,
217}; 255};
218 256
219static struct plat_cpmac_data cpmac_low_data = { 257static struct plat_cpmac_data cpmac_low_data = {
220 .reset_bit = 17, 258 .reset_bit = 17,
221 .power_bit = 20, 259 .power_bit = 20,
222 .phy_mask = 0x80000000, 260 .phy_mask = 0x80000000,
223}; 261};
224 262
225static struct plat_cpmac_data cpmac_high_data = { 263static struct plat_cpmac_data cpmac_high_data = {
226 .reset_bit = 21, 264 .reset_bit = 21,
227 .power_bit = 22, 265 .power_bit = 22,
228 .phy_mask = 0x7fffffff, 266 .phy_mask = 0x7fffffff,
229};
230
231static struct plat_vlynq_data vlynq_low_data = {
232 .ops.on = vlynq_on,
233 .ops.off = vlynq_off,
234 .reset_bit = 20,
235 .gpio_bit = 18,
236};
237
238static struct plat_vlynq_data vlynq_high_data = {
239 .ops.on = vlynq_on,
240 .ops.off = vlynq_off,
241 .reset_bit = 16,
242 .gpio_bit = 19,
243};
244
245static struct platform_device physmap_flash = {
246 .id = 0,
247 .name = "physmap-flash",
248 .dev.platform_data = &physmap_flash_data,
249 .resource = &physmap_flash_resource,
250 .num_resources = 1,
251}; 267};
252 268
253static u64 cpmac_dma_mask = DMA_BIT_MASK(32); 269static u64 cpmac_dma_mask = DMA_BIT_MASK(32);
270
254static struct platform_device cpmac_low = { 271static struct platform_device cpmac_low = {
255 .id = 0, 272 .id = 0,
256 .name = "cpmac", 273 .name = "cpmac",
257 .dev = { 274 .dev = {
258 .dma_mask = &cpmac_dma_mask, 275 .dma_mask = &cpmac_dma_mask,
259 .coherent_dma_mask = DMA_BIT_MASK(32), 276 .coherent_dma_mask = DMA_BIT_MASK(32),
260 .platform_data = &cpmac_low_data, 277 .platform_data = &cpmac_low_data,
261 }, 278 },
262 .resource = cpmac_low_res, 279 .resource = cpmac_low_res,
263 .num_resources = ARRAY_SIZE(cpmac_low_res), 280 .num_resources = ARRAY_SIZE(cpmac_low_res),
264}; 281};
265 282
266static struct platform_device cpmac_high = { 283static struct platform_device cpmac_high = {
267 .id = 1, 284 .id = 1,
268 .name = "cpmac", 285 .name = "cpmac",
269 .dev = { 286 .dev = {
270 .dma_mask = &cpmac_dma_mask, 287 .dma_mask = &cpmac_dma_mask,
271 .coherent_dma_mask = DMA_BIT_MASK(32), 288 .coherent_dma_mask = DMA_BIT_MASK(32),
272 .platform_data = &cpmac_high_data, 289 .platform_data = &cpmac_high_data,
273 }, 290 },
274 .resource = cpmac_high_res, 291 .resource = cpmac_high_res,
275 .num_resources = ARRAY_SIZE(cpmac_high_res), 292 .num_resources = ARRAY_SIZE(cpmac_high_res),
276}; 293};
277 294
278static struct platform_device vlynq_low = { 295static inline unsigned char char2hex(char h)
279 .id = 0, 296{
280 .name = "vlynq", 297 switch (h) {
281 .dev.platform_data = &vlynq_low_data, 298 case '0': case '1': case '2': case '3': case '4':
282 .resource = vlynq_low_res, 299 case '5': case '6': case '7': case '8': case '9':
283 .num_resources = ARRAY_SIZE(vlynq_low_res), 300 return h - '0';
284}; 301 case 'A': case 'B': case 'C': case 'D': case 'E': case 'F':
302 return h - 'A' + 10;
303 case 'a': case 'b': case 'c': case 'd': case 'e': case 'f':
304 return h - 'a' + 10;
305 default:
306 return 0;
307 }
308}
285 309
286static struct platform_device vlynq_high = { 310static void cpmac_get_mac(int instance, unsigned char *dev_addr)
287 .id = 1, 311{
288 .name = "vlynq", 312 int i;
289 .dev.platform_data = &vlynq_high_data, 313 char name[5], default_mac[ETH_ALEN], *mac;
290 .resource = vlynq_high_res, 314
291 .num_resources = ARRAY_SIZE(vlynq_high_res), 315 mac = NULL;
316 sprintf(name, "mac%c", 'a' + instance);
317 mac = prom_getenv(name);
318 if (!mac) {
319 sprintf(name, "mac%c", 'a');
320 mac = prom_getenv(name);
321 }
322 if (!mac) {
323 random_ether_addr(default_mac);
324 mac = default_mac;
325 }
326 for (i = 0; i < 6; i++)
327 dev_addr[i] = (char2hex(mac[i * 3]) << 4) +
328 char2hex(mac[i * 3 + 1]);
329}
330
331/*****************************************************************************
332 * USB
333 ****************************************************************************/
334static struct resource usb_res[] = {
335 {
336 .name = "regs",
337 .flags = IORESOURCE_MEM,
338 .start = AR7_REGS_USB,
339 .end = AR7_REGS_USB + 0xff,
340 },
341 {
342 .name = "irq",
343 .flags = IORESOURCE_IRQ,
344 .start = 32,
345 .end = 32,
346 },
347 {
348 .name = "mem",
349 .flags = IORESOURCE_MEM,
350 .start = 0x03400000,
351 .end = 0x03401fff,
352 },
292}; 353};
293 354
355static struct platform_device ar7_udc = {
356 .name = "ar7_udc",
357 .resource = usb_res,
358 .num_resources = ARRAY_SIZE(usb_res),
359};
294 360
361/*****************************************************************************
362 * LEDs
363 ****************************************************************************/
295static struct gpio_led default_leds[] = { 364static struct gpio_led default_leds[] = {
296 { 365 {
297 .name = "status", 366 .name = "status",
298 .gpio = 8, 367 .gpio = 8,
299 .active_low = 1, 368 .active_low = 1,
300 }, 369 },
301}; 370};
302 371
303static struct gpio_led dsl502t_leds[] = { 372static struct gpio_led dsl502t_leds[] = {
304 { 373 {
305 .name = "status", 374 .name = "status",
306 .gpio = 9, 375 .gpio = 9,
307 .active_low = 1, 376 .active_low = 1,
308 }, 377 },
309 { 378 {
310 .name = "ethernet", 379 .name = "ethernet",
311 .gpio = 7, 380 .gpio = 7,
312 .active_low = 1, 381 .active_low = 1,
313 }, 382 },
314 { 383 {
315 .name = "usb", 384 .name = "usb",
316 .gpio = 12, 385 .gpio = 12,
317 .active_low = 1, 386 .active_low = 1,
318 }, 387 },
319}; 388};
320 389
321static struct gpio_led dg834g_leds[] = { 390static struct gpio_led dg834g_leds[] = {
322 { 391 {
323 .name = "ppp", 392 .name = "ppp",
324 .gpio = 6, 393 .gpio = 6,
325 .active_low = 1, 394 .active_low = 1,
326 }, 395 },
327 { 396 {
328 .name = "status", 397 .name = "status",
329 .gpio = 7, 398 .gpio = 7,
330 .active_low = 1, 399 .active_low = 1,
331 }, 400 },
332 { 401 {
333 .name = "adsl", 402 .name = "adsl",
334 .gpio = 8, 403 .gpio = 8,
335 .active_low = 1, 404 .active_low = 1,
336 }, 405 },
337 { 406 {
338 .name = "wifi", 407 .name = "wifi",
339 .gpio = 12, 408 .gpio = 12,
340 .active_low = 1, 409 .active_low = 1,
341 }, 410 },
342 { 411 {
343 .name = "power", 412 .name = "power",
344 .gpio = 14, 413 .gpio = 14,
345 .active_low = 1, 414 .active_low = 1,
346 .default_trigger = "default-on", 415 .default_trigger = "default-on",
347 }, 416 },
348}; 417};
349 418
350static struct gpio_led fb_sl_leds[] = { 419static struct gpio_led fb_sl_leds[] = {
351 { 420 {
352 .name = "1", 421 .name = "1",
353 .gpio = 7, 422 .gpio = 7,
354 }, 423 },
355 { 424 {
356 .name = "2", 425 .name = "2",
357 .gpio = 13, 426 .gpio = 13,
358 .active_low = 1, 427 .active_low = 1,
359 }, 428 },
360 { 429 {
361 .name = "3", 430 .name = "3",
362 .gpio = 10, 431 .gpio = 10,
363 .active_low = 1, 432 .active_low = 1,
364 }, 433 },
365 { 434 {
366 .name = "4", 435 .name = "4",
367 .gpio = 12, 436 .gpio = 12,
368 .active_low = 1, 437 .active_low = 1,
369 }, 438 },
370 { 439 {
371 .name = "5", 440 .name = "5",
372 .gpio = 9, 441 .gpio = 9,
373 .active_low = 1, 442 .active_low = 1,
374 }, 443 },
375}; 444};
376 445
377static struct gpio_led fb_fon_leds[] = { 446static struct gpio_led fb_fon_leds[] = {
378 { 447 {
379 .name = "1", 448 .name = "1",
380 .gpio = 8, 449 .gpio = 8,
381 }, 450 },
382 { 451 {
383 .name = "2", 452 .name = "2",
384 .gpio = 3, 453 .gpio = 3,
385 .active_low = 1, 454 .active_low = 1,
386 }, 455 },
387 { 456 {
388 .name = "3", 457 .name = "3",
389 .gpio = 5, 458 .gpio = 5,
390 }, 459 },
391 { 460 {
392 .name = "4", 461 .name = "4",
393 .gpio = 4, 462 .gpio = 4,
394 .active_low = 1, 463 .active_low = 1,
395 }, 464 },
396 { 465 {
397 .name = "5", 466 .name = "5",
398 .gpio = 11, 467 .gpio = 11,
399 .active_low = 1, 468 .active_low = 1,
400 }, 469 },
401}; 470};
402 471
@@ -404,69 +473,11 @@ static struct gpio_led_platform_data ar7_led_data;
404 473
405static struct platform_device ar7_gpio_leds = { 474static struct platform_device ar7_gpio_leds = {
406 .name = "leds-gpio", 475 .name = "leds-gpio",
407 .id = -1,
408 .dev = { 476 .dev = {
409 .platform_data = &ar7_led_data, 477 .platform_data = &ar7_led_data,
410 } 478 }
411}; 479};
412 480
413static struct platform_device ar7_udc = {
414 .id = -1,
415 .name = "ar7_udc",
416 .resource = usb_res,
417 .num_resources = ARRAY_SIZE(usb_res),
418};
419
420static struct resource ar7_wdt_res = {
421 .name = "regs",
422 .start = -1, /* Filled at runtime */
423 .end = -1, /* Filled at runtime */
424 .flags = IORESOURCE_MEM,
425};
426
427static struct platform_device ar7_wdt = {
428 .id = -1,
429 .name = "ar7_wdt",
430 .resource = &ar7_wdt_res,
431 .num_resources = 1,
432};
433
434static inline unsigned char char2hex(char h)
435{
436 switch (h) {
437 case '0': case '1': case '2': case '3': case '4':
438 case '5': case '6': case '7': case '8': case '9':
439 return h - '0';
440 case 'A': case 'B': case 'C': case 'D': case 'E': case 'F':
441 return h - 'A' + 10;
442 case 'a': case 'b': case 'c': case 'd': case 'e': case 'f':
443 return h - 'a' + 10;
444 default:
445 return 0;
446 }
447}
448
449static void cpmac_get_mac(int instance, unsigned char *dev_addr)
450{
451 int i;
452 char name[5], default_mac[ETH_ALEN], *mac;
453
454 mac = NULL;
455 sprintf(name, "mac%c", 'a' + instance);
456 mac = prom_getenv(name);
457 if (!mac) {
458 sprintf(name, "mac%c", 'a');
459 mac = prom_getenv(name);
460 }
461 if (!mac) {
462 random_ether_addr(default_mac);
463 mac = default_mac;
464 }
465 for (i = 0; i < 6; i++)
466 dev_addr[i] = (char2hex(mac[i * 3]) << 4) +
467 char2hex(mac[i * 3 + 1]);
468}
469
470static void __init detect_leds(void) 481static void __init detect_leds(void)
471{ 482{
472 char *prid, *usb_prod; 483 char *prid, *usb_prod;
@@ -499,111 +510,149 @@ static void __init detect_leds(void)
499 } 510 }
500} 511}
501 512
502static int __init ar7_register_devices(void) 513/*****************************************************************************
514 * Watchdog
515 ****************************************************************************/
516static struct resource ar7_wdt_res = {
517 .name = "regs",
518 .flags = IORESOURCE_MEM,
519 .start = -1, /* Filled at runtime */
520 .end = -1, /* Filled at runtime */
521};
522
523static struct platform_device ar7_wdt = {
524 .name = "ar7_wdt",
525 .resource = &ar7_wdt_res,
526 .num_resources = 1,
527};
528
529/*****************************************************************************
530 * Init
531 ****************************************************************************/
532static int __init ar7_register_uarts(void)
503{ 533{
504 u16 chip_id;
505 int res;
506 u32 *bootcr, val;
507#ifdef CONFIG_SERIAL_8250 534#ifdef CONFIG_SERIAL_8250
508 static struct uart_port uart_port[2] __initdata; 535 static struct uart_port uart_port __initdata;
509 536 struct clk *bus_clk;
510 memset(uart_port, 0, sizeof(struct uart_port) * 2); 537 int res;
511 538
512 uart_port[0].type = PORT_16550A; 539 memset(&uart_port, 0, sizeof(struct uart_port));
513 uart_port[0].line = 0; 540
514 uart_port[0].irq = AR7_IRQ_UART0; 541 bus_clk = clk_get(NULL, "bus");
515 uart_port[0].uartclk = ar7_bus_freq() / 2; 542 if (IS_ERR(bus_clk))
516 uart_port[0].iotype = UPIO_MEM32; 543 panic("unable to get bus clk\n");
517 uart_port[0].mapbase = AR7_REGS_UART0; 544
518 uart_port[0].membase = ioremap(uart_port[0].mapbase, 256); 545 uart_port.type = PORT_16550A;
519 uart_port[0].regshift = 2; 546 uart_port.uartclk = clk_get_rate(bus_clk) / 2;
520 res = early_serial_setup(&uart_port[0]); 547 uart_port.iotype = UPIO_MEM32;
548 uart_port.regshift = 2;
549
550 uart_port.line = 0;
551 uart_port.irq = AR7_IRQ_UART0;
552 uart_port.mapbase = AR7_REGS_UART0;
553 uart_port.membase = ioremap(uart_port.mapbase, 256);
554
555 res = early_serial_setup(&uart_port);
521 if (res) 556 if (res)
522 return res; 557 return res;
523 558
524
525 /* Only TNETD73xx have a second serial port */ 559 /* Only TNETD73xx have a second serial port */
526 if (ar7_has_second_uart()) { 560 if (ar7_has_second_uart()) {
527 uart_port[1].type = PORT_16550A; 561 uart_port.line = 1;
528 uart_port[1].line = 1; 562 uart_port.irq = AR7_IRQ_UART1;
529 uart_port[1].irq = AR7_IRQ_UART1; 563 uart_port.mapbase = UR8_REGS_UART1;
530 uart_port[1].uartclk = ar7_bus_freq() / 2; 564 uart_port.membase = ioremap(uart_port.mapbase, 256);
531 uart_port[1].iotype = UPIO_MEM32; 565
532 uart_port[1].mapbase = UR8_REGS_UART1; 566 res = early_serial_setup(&uart_port);
533 uart_port[1].membase = ioremap(uart_port[1].mapbase, 256);
534 uart_port[1].regshift = 2;
535 res = early_serial_setup(&uart_port[1]);
536 if (res) 567 if (res)
537 return res; 568 return res;
538 } 569 }
539#endif /* CONFIG_SERIAL_8250 */ 570#endif
571
572 return 0;
573}
574
575static int __init ar7_register_devices(void)
576{
577 void __iomem *bootcr;
578 u32 val;
579 u16 chip_id;
580 int res;
581
582 res = ar7_register_uarts();
583 if (res)
584 pr_err("unable to setup uart(s): %d\n", res);
585
540 res = platform_device_register(&physmap_flash); 586 res = platform_device_register(&physmap_flash);
541 if (res) 587 if (res)
542 return res; 588 pr_warning("unable to register physmap-flash: %d\n", res);
543 589
544 ar7_device_disable(vlynq_low_data.reset_bit); 590 ar7_device_disable(vlynq_low_data.reset_bit);
545 res = platform_device_register(&vlynq_low); 591 res = platform_device_register(&vlynq_low);
546 if (res) 592 if (res)
547 return res; 593 pr_warning("unable to register vlynq-low: %d\n", res);
548 594
549 if (ar7_has_high_vlynq()) { 595 if (ar7_has_high_vlynq()) {
550 ar7_device_disable(vlynq_high_data.reset_bit); 596 ar7_device_disable(vlynq_high_data.reset_bit);
551 res = platform_device_register(&vlynq_high); 597 res = platform_device_register(&vlynq_high);
552 if (res) 598 if (res)
553 return res; 599 pr_warning("unable to register vlynq-high: %d\n", res);
554 } 600 }
555 601
556 if (ar7_has_high_cpmac()) { 602 if (ar7_has_high_cpmac()) {
557 res = fixed_phy_add(PHY_POLL, cpmac_high.id, &fixed_phy_status); 603 if (!res) {
558 if (res && res != -ENODEV) 604 cpmac_get_mac(1, cpmac_high_data.dev_addr);
559 return res; 605
560 cpmac_get_mac(1, cpmac_high_data.dev_addr); 606 res = platform_device_register(&cpmac_high);
561 res = platform_device_register(&cpmac_high); 607 if (res)
562 if (res) 608 pr_warning("unable to register cpmac-high: %d\n", res);
563 return res; 609 } else
564 } else { 610 pr_warning("unable to add cpmac-high phy: %d\n", res);
611 } else
565 cpmac_low_data.phy_mask = 0xffffffff; 612 cpmac_low_data.phy_mask = 0xffffffff;
566 }
567 613
568 res = fixed_phy_add(PHY_POLL, cpmac_low.id, &fixed_phy_status); 614 res = fixed_phy_add(PHY_POLL, cpmac_low.id, &fixed_phy_status);
569 if (res && res != -ENODEV) 615 if (!res) {
570 return res; 616 cpmac_get_mac(0, cpmac_low_data.dev_addr);
571 617 res = platform_device_register(&cpmac_low);
572 cpmac_get_mac(0, cpmac_low_data.dev_addr); 618 if (res)
573 res = platform_device_register(&cpmac_low); 619 pr_warning("unable to register cpmac-low: %d\n", res);
574 if (res) 620 } else
575 return res; 621 pr_warning("unable to add cpmac-low phy: %d\n", res);
576 622
577 detect_leds(); 623 detect_leds();
578 res = platform_device_register(&ar7_gpio_leds); 624 res = platform_device_register(&ar7_gpio_leds);
579 if (res) 625 if (res)
580 return res; 626 pr_warning("unable to register leds: %d\n", res);
581 627
582 res = platform_device_register(&ar7_udc); 628 res = platform_device_register(&ar7_udc);
583 629 if (res)
584 chip_id = ar7_chip_id(); 630 pr_warning("unable to register usb slave: %d\n", res);
585 switch (chip_id) {
586 case AR7_CHIP_7100:
587 case AR7_CHIP_7200:
588 ar7_wdt_res.start = AR7_REGS_WDT;
589 break;
590 case AR7_CHIP_7300:
591 ar7_wdt_res.start = UR8_REGS_WDT;
592 break;
593 default:
594 break;
595 }
596
597 ar7_wdt_res.end = ar7_wdt_res.start + 0x20;
598
599 bootcr = (u32 *)ioremap_nocache(AR7_REGS_DCL, 4);
600 val = *bootcr;
601 iounmap(bootcr);
602 631
603 /* Register watchdog only if enabled in hardware */ 632 /* Register watchdog only if enabled in hardware */
604 if (val & AR7_WDT_HW_ENA) 633 bootcr = ioremap_nocache(AR7_REGS_DCL, 4);
634 val = readl(bootcr);
635 iounmap(bootcr);
636 if (val & AR7_WDT_HW_ENA) {
637 chip_id = ar7_chip_id();
638 switch (chip_id) {
639 case AR7_CHIP_7100:
640 case AR7_CHIP_7200:
641 ar7_wdt_res.start = AR7_REGS_WDT;
642 break;
643 case AR7_CHIP_7300:
644 ar7_wdt_res.start = UR8_REGS_WDT;
645 break;
646 default:
647 break;
648 }
649
650 ar7_wdt_res.end = ar7_wdt_res.start + 0x20;
605 res = platform_device_register(&ar7_wdt); 651 res = platform_device_register(&ar7_wdt);
652 if (res)
653 pr_warning("unable to register watchdog: %d\n", res);
654 }
606 655
607 return res; 656 return 0;
608} 657}
609arch_initcall(ar7_register_devices); 658arch_initcall(ar7_register_devices);
diff --git a/arch/mips/ar7/prom.c b/arch/mips/ar7/prom.c
index c1fdd3682812..52385790e5c1 100644
--- a/arch/mips/ar7/prom.c
+++ b/arch/mips/ar7/prom.c
@@ -32,8 +32,8 @@
32#define MAX_ENTRY 80 32#define MAX_ENTRY 80
33 33
34struct env_var { 34struct env_var {
35 char *name; 35 char *name;
36 char *value; 36 char *value;
37}; 37};
38 38
39static struct env_var adam2_env[MAX_ENTRY]; 39static struct env_var adam2_env[MAX_ENTRY];
@@ -41,6 +41,7 @@ static struct env_var adam2_env[MAX_ENTRY];
41char *prom_getenv(const char *name) 41char *prom_getenv(const char *name)
42{ 42{
43 int i; 43 int i;
44
44 for (i = 0; (i < MAX_ENTRY) && adam2_env[i].name; i++) 45 for (i = 0; (i < MAX_ENTRY) && adam2_env[i].name; i++)
45 if (!strcmp(name, adam2_env[i].name)) 46 if (!strcmp(name, adam2_env[i].name))
46 return adam2_env[i].value; 47 return adam2_env[i].value;
@@ -49,65 +50,50 @@ char *prom_getenv(const char *name)
49} 50}
50EXPORT_SYMBOL(prom_getenv); 51EXPORT_SYMBOL(prom_getenv);
51 52
52char * __init prom_getcmdline(void)
53{
54 return &(arcs_cmdline[0]);
55}
56
57static void __init ar7_init_cmdline(int argc, char *argv[]) 53static void __init ar7_init_cmdline(int argc, char *argv[])
58{ 54{
59 char *cp; 55 int i;
60 int actr;
61
62 actr = 1; /* Always ignore argv[0] */
63 56
64 cp = &(arcs_cmdline[0]); 57 for (i = 1; i < argc; i++) {
65 while (actr < argc) { 58 strlcat(arcs_cmdline, argv[i], COMMAND_LINE_SIZE);
66 strcpy(cp, argv[actr]); 59 if (i < (argc - 1))
67 cp += strlen(argv[actr]); 60 strlcat(arcs_cmdline, " ", COMMAND_LINE_SIZE);
68 *cp++ = ' ';
69 actr++;
70 }
71 if (cp != &(arcs_cmdline[0])) {
72 /* get rid of trailing space */
73 --cp;
74 *cp = '\0';
75 } 61 }
76} 62}
77 63
78struct psbl_rec { 64struct psbl_rec {
79 u32 psbl_size; 65 u32 psbl_size;
80 u32 env_base; 66 u32 env_base;
81 u32 env_size; 67 u32 env_size;
82 u32 ffs_base; 68 u32 ffs_base;
83 u32 ffs_size; 69 u32 ffs_size;
84}; 70};
85 71
86static __initdata char psp_env_version[] = "TIENV0.8"; 72static __initdata char psp_env_version[] = "TIENV0.8";
87 73
88struct psp_env_chunk { 74struct psp_env_chunk {
89 u8 num; 75 u8 num;
90 u8 ctrl; 76 u8 ctrl;
91 u16 csum; 77 u16 csum;
92 u8 len; 78 u8 len;
93 char data[11]; 79 char data[11];
94} __attribute__ ((packed)); 80} __attribute__ ((packed));
95 81
96struct psp_var_map_entry { 82struct psp_var_map_entry {
97 u8 num; 83 u8 num;
98 char *value; 84 char *value;
99}; 85};
100 86
101static struct psp_var_map_entry psp_var_map[] = { 87static struct psp_var_map_entry psp_var_map[] = {
102 { 1, "cpufrequency" }, 88 { 1, "cpufrequency" },
103 { 2, "memsize" }, 89 { 2, "memsize" },
104 { 3, "flashsize" }, 90 { 3, "flashsize" },
105 { 4, "modetty0" }, 91 { 4, "modetty0" },
106 { 5, "modetty1" }, 92 { 5, "modetty1" },
107 { 8, "maca" }, 93 { 8, "maca" },
108 { 9, "macb" }, 94 { 9, "macb" },
109 { 28, "sysfrequency" }, 95 { 28, "sysfrequency" },
110 { 38, "mipsfrequency" }, 96 { 38, "mipsfrequency" },
111}; 97};
112 98
113/* 99/*
@@ -154,6 +140,7 @@ static char * __init lookup_psp_var_map(u8 num)
154static void __init add_adam2_var(char *name, char *value) 140static void __init add_adam2_var(char *name, char *value)
155{ 141{
156 int i; 142 int i;
143
157 for (i = 0; i < MAX_ENTRY; i++) { 144 for (i = 0; i < MAX_ENTRY; i++) {
158 if (!adam2_env[i].name) { 145 if (!adam2_env[i].name) {
159 adam2_env[i].name = name; 146 adam2_env[i].name = name;
@@ -216,7 +203,7 @@ static void __init console_config(void)
216 char parity = '\0', bits = '\0', flow = '\0'; 203 char parity = '\0', bits = '\0', flow = '\0';
217 char *s, *p; 204 char *s, *p;
218 205
219 if (strstr(prom_getcmdline(), "console=")) 206 if (strstr(arcs_cmdline, "console="))
220 return; 207 return;
221 208
222 s = prom_getenv("modetty0"); 209 s = prom_getenv("modetty0");
@@ -250,7 +237,7 @@ static void __init console_config(void)
250 else 237 else
251 sprintf(console_string, " console=ttyS0,%d%c%c", baud, parity, 238 sprintf(console_string, " console=ttyS0,%d%c%c", baud, parity,
252 bits); 239 bits);
253 strcat(prom_getcmdline(), console_string); 240 strlcat(arcs_cmdline, console_string, COMMAND_LINE_SIZE);
254#endif 241#endif
255} 242}
256 243
@@ -279,4 +266,3 @@ int prom_putchar(char c)
279 serial_out(UART_TX, c); 266 serial_out(UART_TX, c);
280 return 1; 267 return 1;
281} 268}
282
diff --git a/arch/mips/ar7/setup.c b/arch/mips/ar7/setup.c
index 39f6b5b96463..3a801d2cb6e5 100644
--- a/arch/mips/ar7/setup.c
+++ b/arch/mips/ar7/setup.c
@@ -26,8 +26,8 @@
26 26
27static void ar7_machine_restart(char *command) 27static void ar7_machine_restart(char *command)
28{ 28{
29 u32 *softres_reg = ioremap(AR7_REGS_RESET + 29 u32 *softres_reg = ioremap(AR7_REGS_RESET + AR7_RESET_SOFTWARE, 1);
30 AR7_RESET_SOFTWARE, 1); 30
31 writel(1, softres_reg); 31 writel(1, softres_reg);
32} 32}
33 33
@@ -41,6 +41,7 @@ static void ar7_machine_power_off(void)
41{ 41{
42 u32 *power_reg = (u32 *)ioremap(AR7_REGS_POWER, 1); 42 u32 *power_reg = (u32 *)ioremap(AR7_REGS_POWER, 1);
43 u32 power_state = readl(power_reg) | (3 << 30); 43 u32 power_state = readl(power_reg) | (3 << 30);
44
44 writel(power_state, power_reg); 45 writel(power_state, power_reg);
45 ar7_machine_halt(); 46 ar7_machine_halt();
46} 47}
@@ -49,14 +50,14 @@ const char *get_system_type(void)
49{ 50{
50 u16 chip_id = ar7_chip_id(); 51 u16 chip_id = ar7_chip_id();
51 switch (chip_id) { 52 switch (chip_id) {
52 case AR7_CHIP_7300:
53 return "TI AR7 (TNETD7300)";
54 case AR7_CHIP_7100: 53 case AR7_CHIP_7100:
55 return "TI AR7 (TNETD7100)"; 54 return "TI AR7 (TNETD7100)";
56 case AR7_CHIP_7200: 55 case AR7_CHIP_7200:
57 return "TI AR7 (TNETD7200)"; 56 return "TI AR7 (TNETD7200)";
57 case AR7_CHIP_7300:
58 return "TI AR7 (TNETD7300)";
58 default: 59 default:
59 return "TI AR7 (Unknown)"; 60 return "TI AR7 (unknown)";
60 } 61 }
61} 62}
62 63
@@ -70,7 +71,6 @@ console_initcall(ar7_init_console);
70 * Initializes basic routines and structures pointers, memory size (as 71 * Initializes basic routines and structures pointers, memory size (as
71 * given by the bios and saves the command line. 72 * given by the bios and saves the command line.
72 */ 73 */
73
74void __init plat_mem_setup(void) 74void __init plat_mem_setup(void)
75{ 75{
76 unsigned long io_base; 76 unsigned long io_base;
@@ -88,6 +88,5 @@ void __init plat_mem_setup(void)
88 prom_meminit(); 88 prom_meminit();
89 89
90 printk(KERN_INFO "%s, ID: 0x%04x, Revision: 0x%02x\n", 90 printk(KERN_INFO "%s, ID: 0x%04x, Revision: 0x%02x\n",
91 get_system_type(), 91 get_system_type(), ar7_chip_id(), ar7_chip_rev());
92 ar7_chip_id(), ar7_chip_rev());
93} 92}
diff --git a/arch/mips/ar7/time.c b/arch/mips/ar7/time.c
index a1fba894daa2..5fb8a0134085 100644
--- a/arch/mips/ar7/time.c
+++ b/arch/mips/ar7/time.c
@@ -20,11 +20,21 @@
20 20
21#include <linux/init.h> 21#include <linux/init.h>
22#include <linux/time.h> 22#include <linux/time.h>
23#include <linux/err.h>
24#include <linux/clk.h>
23 25
24#include <asm/time.h> 26#include <asm/time.h>
25#include <asm/mach-ar7/ar7.h> 27#include <asm/mach-ar7/ar7.h>
26 28
27void __init plat_time_init(void) 29void __init plat_time_init(void)
28{ 30{
29 mips_hpt_frequency = ar7_cpu_freq() / 2; 31 struct clk *cpu_clk;
32
33 cpu_clk = clk_get(NULL, "cpu");
34 if (IS_ERR(cpu_clk)) {
35 printk(KERN_ERR "unable to get cpu clock\n");
36 return;
37 }
38
39 mips_hpt_frequency = clk_get_rate(cpu_clk) / 2;
30} 40}
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-06 03:51:19 -0500