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-rw-r--r--arch/mips/alchemy/devboards/Makefile7
-rw-r--r--arch/mips/alchemy/devboards/db1000.c120
-rw-r--r--arch/mips/alchemy/devboards/db1200.c37
-rw-r--r--arch/mips/alchemy/devboards/db1235.c94
-rw-r--r--arch/mips/alchemy/devboards/db1300.c12
-rw-r--r--arch/mips/alchemy/devboards/db1550.c192
-rw-r--r--arch/mips/alchemy/devboards/pb1100.c167
-rw-r--r--arch/mips/alchemy/devboards/pb1500.c198
-rw-r--r--arch/mips/alchemy/devboards/pb1550.c244
-rw-r--r--arch/mips/alchemy/devboards/platform.c9
10 files changed, 354 insertions, 726 deletions
diff --git a/arch/mips/alchemy/devboards/Makefile b/arch/mips/alchemy/devboards/Makefile
index c9e747dd9fc2..15bf7306648b 100644
--- a/arch/mips/alchemy/devboards/Makefile
+++ b/arch/mips/alchemy/devboards/Makefile
@@ -4,10 +4,5 @@
4 4
5obj-y += bcsr.o platform.o 5obj-y += bcsr.o platform.o
6obj-$(CONFIG_PM) += pm.o 6obj-$(CONFIG_PM) += pm.o
7obj-$(CONFIG_MIPS_PB1100) += pb1100.o
8obj-$(CONFIG_MIPS_PB1500) += pb1500.o
9obj-$(CONFIG_MIPS_PB1550) += pb1550.o
10obj-$(CONFIG_MIPS_DB1000) += db1000.o 7obj-$(CONFIG_MIPS_DB1000) += db1000.o
11obj-$(CONFIG_MIPS_DB1200) += db1200.o 8obj-$(CONFIG_MIPS_DB1235) += db1235.o db1200.o db1300.o db1550.o
12obj-$(CONFIG_MIPS_DB1300) += db1300.o
13obj-$(CONFIG_MIPS_DB1550) += db1550.o
diff --git a/arch/mips/alchemy/devboards/db1000.c b/arch/mips/alchemy/devboards/db1000.c
index 1b81dbf6b804..8187845650f7 100644
--- a/arch/mips/alchemy/devboards/db1000.c
+++ b/arch/mips/alchemy/devboards/db1000.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * DBAu1000/1500/1100 board support 2 * DBAu1000/1500/1100 PBAu1100/1500 board support
3 * 3 *
4 * Copyright 2000, 2008 MontaVista Software Inc. 4 * Copyright 2000, 2008 MontaVista Software Inc.
5 * Author: MontaVista Software, Inc. <source@mvista.com> 5 * Author: MontaVista Software, Inc. <source@mvista.com>
@@ -52,6 +52,11 @@ static const char *board_type_str(void)
52 return "DB1500"; 52 return "DB1500";
53 case BCSR_WHOAMI_DB1100: 53 case BCSR_WHOAMI_DB1100:
54 return "DB1100"; 54 return "DB1100";
55 case BCSR_WHOAMI_PB1500:
56 case BCSR_WHOAMI_PB1500R2:
57 return "PB1500";
58 case BCSR_WHOAMI_PB1100:
59 return "PB1100";
55 default: 60 default:
56 return "(unknown)"; 61 return "(unknown)";
57 } 62 }
@@ -111,7 +116,9 @@ static struct platform_device db1500_pci_host_dev = {
111 116
112static int __init db1500_pci_init(void) 117static int __init db1500_pci_init(void)
113{ 118{
114 if (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)) == BCSR_WHOAMI_DB1500) 119 int id = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI));
120 if ((id == BCSR_WHOAMI_DB1500) || (id == BCSR_WHOAMI_PB1500) ||
121 (id == BCSR_WHOAMI_PB1500R2))
115 return platform_device_register(&db1500_pci_host_dev); 122 return platform_device_register(&db1500_pci_host_dev);
116 return 0; 123 return 0;
117} 124}
@@ -199,27 +206,37 @@ static irqreturn_t db1100_mmc_cd(int irq, void *ptr)
199 206
200static int db1100_mmc_cd_setup(void *mmc_host, int en) 207static int db1100_mmc_cd_setup(void *mmc_host, int en)
201{ 208{
202 int ret = 0; 209 int ret = 0, irq;
210
211 if (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)) == BCSR_WHOAMI_DB1100)
212 irq = AU1100_GPIO19_INT;
213 else
214 irq = AU1100_GPIO14_INT; /* PB1100 SD0 CD# */
203 215
204 if (en) { 216 if (en) {
205 irq_set_irq_type(AU1100_GPIO19_INT, IRQ_TYPE_EDGE_BOTH); 217 irq_set_irq_type(irq, IRQ_TYPE_EDGE_BOTH);
206 ret = request_irq(AU1100_GPIO19_INT, db1100_mmc_cd, 0, 218 ret = request_irq(irq, db1100_mmc_cd, 0,
207 "sd0_cd", mmc_host); 219 "sd0_cd", mmc_host);
208 } else 220 } else
209 free_irq(AU1100_GPIO19_INT, mmc_host); 221 free_irq(irq, mmc_host);
210 return ret; 222 return ret;
211} 223}
212 224
213static int db1100_mmc1_cd_setup(void *mmc_host, int en) 225static int db1100_mmc1_cd_setup(void *mmc_host, int en)
214{ 226{
215 int ret = 0; 227 int ret = 0, irq;
228
229 if (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)) == BCSR_WHOAMI_DB1100)
230 irq = AU1100_GPIO20_INT;
231 else
232 irq = AU1100_GPIO15_INT; /* PB1100 SD1 CD# */
216 233
217 if (en) { 234 if (en) {
218 irq_set_irq_type(AU1100_GPIO20_INT, IRQ_TYPE_EDGE_BOTH); 235 irq_set_irq_type(irq, IRQ_TYPE_EDGE_BOTH);
219 ret = request_irq(AU1100_GPIO20_INT, db1100_mmc_cd, 0, 236 ret = request_irq(irq, db1100_mmc_cd, 0,
220 "sd1_cd", mmc_host); 237 "sd1_cd", mmc_host);
221 } else 238 } else
222 free_irq(AU1100_GPIO20_INT, mmc_host); 239 free_irq(irq, mmc_host);
223 return ret; 240 return ret;
224} 241}
225 242
@@ -236,11 +253,18 @@ static int db1100_mmc_card_inserted(void *mmc_host)
236 253
237static void db1100_mmc_set_power(void *mmc_host, int state) 254static void db1100_mmc_set_power(void *mmc_host, int state)
238{ 255{
256 int bit;
257
258 if (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)) == BCSR_WHOAMI_DB1100)
259 bit = BCSR_BOARD_SD0PWR;
260 else
261 bit = BCSR_BOARD_PB1100_SD0PWR;
262
239 if (state) { 263 if (state) {
240 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD0PWR); 264 bcsr_mod(BCSR_BOARD, 0, bit);
241 msleep(400); /* stabilization time */ 265 msleep(400); /* stabilization time */
242 } else 266 } else
243 bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD0PWR, 0); 267 bcsr_mod(BCSR_BOARD, bit, 0);
244} 268}
245 269
246static void db1100_mmcled_set(struct led_classdev *led, enum led_brightness b) 270static void db1100_mmcled_set(struct led_classdev *led, enum led_brightness b)
@@ -267,11 +291,18 @@ static int db1100_mmc1_card_inserted(void *mmc_host)
267 291
268static void db1100_mmc1_set_power(void *mmc_host, int state) 292static void db1100_mmc1_set_power(void *mmc_host, int state)
269{ 293{
294 int bit;
295
296 if (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)) == BCSR_WHOAMI_DB1100)
297 bit = BCSR_BOARD_SD1PWR;
298 else
299 bit = BCSR_BOARD_PB1100_SD1PWR;
300
270 if (state) { 301 if (state) {
271 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD1PWR); 302 bcsr_mod(BCSR_BOARD, 0, bit);
272 msleep(400); /* stabilization time */ 303 msleep(400); /* stabilization time */
273 } else 304 } else
274 bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD1PWR, 0); 305 bcsr_mod(BCSR_BOARD, bit, 0);
275} 306}
276 307
277static void db1100_mmc1led_set(struct led_classdev *led, enum led_brightness b) 308static void db1100_mmc1led_set(struct led_classdev *led, enum led_brightness b)
@@ -480,13 +511,12 @@ static struct platform_device *db1100_devs[] = {
480 &db1100_mmc0_dev, 511 &db1100_mmc0_dev,
481 &db1100_mmc1_dev, 512 &db1100_mmc1_dev,
482 &db1000_irda_dev, 513 &db1000_irda_dev,
483 &db1100_spi_dev,
484}; 514};
485 515
486static int __init db1000_dev_init(void) 516static int __init db1000_dev_init(void)
487{ 517{
488 int board = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)); 518 int board = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI));
489 int c0, c1, d0, d1, s0, s1; 519 int c0, c1, d0, d1, s0, s1, flashsize = 32, twosocks = 1;
490 unsigned long pfc; 520 unsigned long pfc;
491 521
492 if (board == BCSR_WHOAMI_DB1500) { 522 if (board == BCSR_WHOAMI_DB1500) {
@@ -522,6 +552,7 @@ static int __init db1000_dev_init(void)
522 ARRAY_SIZE(db1100_spi_info)); 552 ARRAY_SIZE(db1100_spi_info));
523 553
524 platform_add_devices(db1100_devs, ARRAY_SIZE(db1100_devs)); 554 platform_add_devices(db1100_devs, ARRAY_SIZE(db1100_devs));
555 platform_device_register(&db1100_spi_dev);
525 } else if (board == BCSR_WHOAMI_DB1000) { 556 } else if (board == BCSR_WHOAMI_DB1000) {
526 c0 = AU1000_GPIO2_INT; 557 c0 = AU1000_GPIO2_INT;
527 c1 = AU1000_GPIO5_INT; 558 c1 = AU1000_GPIO5_INT;
@@ -530,15 +561,42 @@ static int __init db1000_dev_init(void)
530 s0 = AU1000_GPIO1_INT; 561 s0 = AU1000_GPIO1_INT;
531 s1 = AU1000_GPIO4_INT; 562 s1 = AU1000_GPIO4_INT;
532 platform_add_devices(db1000_devs, ARRAY_SIZE(db1000_devs)); 563 platform_add_devices(db1000_devs, ARRAY_SIZE(db1000_devs));
564 } else if ((board == BCSR_WHOAMI_PB1500) ||
565 (board == BCSR_WHOAMI_PB1500R2)) {
566 c0 = AU1500_GPIO203_INT;
567 d0 = AU1500_GPIO201_INT;
568 s0 = AU1500_GPIO202_INT;
569 twosocks = 0;
570 flashsize = 64;
571 /* RTC and daughtercard irqs */
572 irq_set_irq_type(AU1500_GPIO204_INT, IRQ_TYPE_LEVEL_LOW);
573 irq_set_irq_type(AU1500_GPIO205_INT, IRQ_TYPE_LEVEL_LOW);
574 /* EPSON S1D13806 0x1b000000
575 * SRAM 1MB/2MB 0x1a000000
576 * DS1693 RTC 0x0c000000
577 */
578 } else if (board == BCSR_WHOAMI_PB1100) {
579 c0 = AU1100_GPIO11_INT;
580 d0 = AU1100_GPIO9_INT;
581 s0 = AU1100_GPIO10_INT;
582 twosocks = 0;
583 flashsize = 64;
584 /* pendown, rtc, daughtercard irqs */
585 irq_set_irq_type(AU1100_GPIO8_INT, IRQ_TYPE_LEVEL_LOW);
586 irq_set_irq_type(AU1100_GPIO12_INT, IRQ_TYPE_LEVEL_LOW);
587 irq_set_irq_type(AU1100_GPIO13_INT, IRQ_TYPE_LEVEL_LOW);
588 /* EPSON S1D13806 0x1b000000
589 * SRAM 1MB/2MB 0x1a000000
590 * DiskOnChip 0x0d000000
591 * DS1693 RTC 0x0c000000
592 */
593 platform_add_devices(db1100_devs, ARRAY_SIZE(db1100_devs));
533 } else 594 } else
534 return 0; /* unknown board, no further dev setup to do */ 595 return 0; /* unknown board, no further dev setup to do */
535 596
536 irq_set_irq_type(d0, IRQ_TYPE_EDGE_BOTH); 597 irq_set_irq_type(d0, IRQ_TYPE_EDGE_BOTH);
537 irq_set_irq_type(d1, IRQ_TYPE_EDGE_BOTH);
538 irq_set_irq_type(c0, IRQ_TYPE_LEVEL_LOW); 598 irq_set_irq_type(c0, IRQ_TYPE_LEVEL_LOW);
539 irq_set_irq_type(c1, IRQ_TYPE_LEVEL_LOW);
540 irq_set_irq_type(s0, IRQ_TYPE_LEVEL_LOW); 599 irq_set_irq_type(s0, IRQ_TYPE_LEVEL_LOW);
541 irq_set_irq_type(s1, IRQ_TYPE_LEVEL_LOW);
542 600
543 db1x_register_pcmcia_socket( 601 db1x_register_pcmcia_socket(
544 AU1000_PCMCIA_ATTR_PHYS_ADDR, 602 AU1000_PCMCIA_ATTR_PHYS_ADDR,
@@ -549,17 +607,23 @@ static int __init db1000_dev_init(void)
549 AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1, 607 AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
550 c0, d0, /*s0*/0, 0, 0); 608 c0, d0, /*s0*/0, 0, 0);
551 609
552 db1x_register_pcmcia_socket( 610 if (twosocks) {
553 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000, 611 irq_set_irq_type(d1, IRQ_TYPE_EDGE_BOTH);
554 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1, 612 irq_set_irq_type(c1, IRQ_TYPE_LEVEL_LOW);
555 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004000000, 613 irq_set_irq_type(s1, IRQ_TYPE_LEVEL_LOW);
556 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1, 614
557 AU1000_PCMCIA_IO_PHYS_ADDR + 0x004000000, 615 db1x_register_pcmcia_socket(
558 AU1000_PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1, 616 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000,
559 c1, d1, /*s1*/0, 0, 1); 617 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1,
618 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004000000,
619 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1,
620 AU1000_PCMCIA_IO_PHYS_ADDR + 0x004000000,
621 AU1000_PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1,
622 c1, d1, /*s1*/0, 0, 1);
623 }
560 624
561 platform_add_devices(db1x00_devs, ARRAY_SIZE(db1x00_devs)); 625 platform_add_devices(db1x00_devs, ARRAY_SIZE(db1x00_devs));
562 db1x_register_norflash(32 << 20, 4 /* 32bit */, F_SWAPPED); 626 db1x_register_norflash(flashsize << 20, 4 /* 32bit */, F_SWAPPED);
563 return 0; 627 return 0;
564} 628}
565device_initcall(db1000_dev_init); 629device_initcall(db1000_dev_init);
diff --git a/arch/mips/alchemy/devboards/db1200.c b/arch/mips/alchemy/devboards/db1200.c
index bf2248474fa8..299b7d202bea 100644
--- a/arch/mips/alchemy/devboards/db1200.c
+++ b/arch/mips/alchemy/devboards/db1200.c
@@ -45,25 +45,9 @@
45 45
46#include "platform.h" 46#include "platform.h"
47 47
48static const char *board_type_str(void) 48const char *get_system_type(void);
49{
50 switch (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI))) {
51 case BCSR_WHOAMI_PB1200_DDR1:
52 case BCSR_WHOAMI_PB1200_DDR2:
53 return "PB1200";
54 case BCSR_WHOAMI_DB1200:
55 return "DB1200";
56 default:
57 return "(unknown)";
58 }
59}
60 49
61const char *get_system_type(void) 50static int __init db1200_detect_board(void)
62{
63 return board_type_str();
64}
65
66static int __init detect_board(void)
67{ 51{
68 int bid; 52 int bid;
69 53
@@ -96,19 +80,17 @@ static int __init detect_board(void)
96 return 1; /* it's neither */ 80 return 1; /* it's neither */
97} 81}
98 82
99void __init board_setup(void) 83int __init db1200_board_setup(void)
100{ 84{
101 unsigned long freq0, clksrc, div, pfc; 85 unsigned long freq0, clksrc, div, pfc;
102 unsigned short whoami; 86 unsigned short whoami;
103 87
104 if (detect_board()) { 88 if (db1200_detect_board())
105 printk(KERN_ERR "NOT running on a DB1200/PB1200 board!\n"); 89 return -ENODEV;
106 return;
107 }
108 90
109 whoami = bcsr_read(BCSR_WHOAMI); 91 whoami = bcsr_read(BCSR_WHOAMI);
110 printk(KERN_INFO "Alchemy/AMD/RMI %s Board, CPLD Rev %d" 92 printk(KERN_INFO "Alchemy/AMD/RMI %s Board, CPLD Rev %d"
111 " Board-ID %d Daughtercard ID %d\n", board_type_str(), 93 " Board-ID %d Daughtercard ID %d\n", get_system_type(),
112 (whoami >> 4) & 0xf, (whoami >> 8) & 0xf, whoami & 0xf); 94 (whoami >> 4) & 0xf, (whoami >> 8) & 0xf, whoami & 0xf);
113 95
114 /* SMBus/SPI on PSC0, Audio on PSC1 */ 96 /* SMBus/SPI on PSC0, Audio on PSC1 */
@@ -138,6 +120,8 @@ void __init board_setup(void)
138 clksrc = SYS_CS_MUX_FQ0 << SYS_CS_ME0_BIT; 120 clksrc = SYS_CS_MUX_FQ0 << SYS_CS_ME0_BIT;
139 __raw_writel(clksrc, (void __iomem *)SYS_CLKSRC); 121 __raw_writel(clksrc, (void __iomem *)SYS_CLKSRC);
140 wmb(); 122 wmb();
123
124 return 0;
141} 125}
142 126
143/******************************************************************************/ 127/******************************************************************************/
@@ -796,7 +780,7 @@ static int __init pb1200_res_fixup(void)
796 return 0; 780 return 0;
797} 781}
798 782
799static int __init db1200_dev_init(void) 783int __init db1200_dev_setup(void)
800{ 784{
801 unsigned long pfc; 785 unsigned long pfc;
802 unsigned short sw; 786 unsigned short sw;
@@ -846,7 +830,7 @@ static int __init db1200_dev_init(void)
846 gpio_request(215, "otg-vbus"); 830 gpio_request(215, "otg-vbus");
847 gpio_direction_output(215, 1); 831 gpio_direction_output(215, 1);
848 832
849 printk(KERN_INFO "%s device configuration:\n", board_type_str()); 833 printk(KERN_INFO "%s device configuration:\n", get_system_type());
850 834
851 sw = bcsr_read(BCSR_SWITCHES); 835 sw = bcsr_read(BCSR_SWITCHES);
852 if (sw & BCSR_SWITCHES_DIP_8) { 836 if (sw & BCSR_SWITCHES_DIP_8) {
@@ -922,4 +906,3 @@ static int __init db1200_dev_init(void)
922 906
923 return 0; 907 return 0;
924} 908}
925device_initcall(db1200_dev_init);
diff --git a/arch/mips/alchemy/devboards/db1235.c b/arch/mips/alchemy/devboards/db1235.c
new file mode 100644
index 000000000000..c76a90f78664
--- /dev/null
+++ b/arch/mips/alchemy/devboards/db1235.c
@@ -0,0 +1,94 @@
1/*
2 * DB1200/PB1200 / DB1550 / DB1300 board support.
3 *
4 * These 4 boards can reliably be supported in a single kernel image.
5 */
6
7#include <asm/mach-au1x00/au1000.h>
8#include <asm/mach-db1x00/bcsr.h>
9
10int __init db1200_board_setup(void);
11int __init db1200_dev_setup(void);
12int __init db1300_board_setup(void);
13int __init db1300_dev_setup(void);
14int __init db1550_board_setup(void);
15int __init db1550_dev_setup(void);
16int __init db1550_pci_setup(int);
17
18static const char *board_type_str(void)
19{
20 switch (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI))) {
21 case BCSR_WHOAMI_PB1200_DDR1:
22 case BCSR_WHOAMI_PB1200_DDR2:
23 return "PB1200";
24 case BCSR_WHOAMI_DB1200:
25 return "DB1200";
26 case BCSR_WHOAMI_DB1300:
27 return "DB1300";
28 case BCSR_WHOAMI_DB1550:
29 return "DB1550";
30 case BCSR_WHOAMI_PB1550_SDR:
31 case BCSR_WHOAMI_PB1550_DDR:
32 return "PB1550";
33 default:
34 return "(unknown)";
35 }
36}
37
38const char *get_system_type(void)
39{
40 return board_type_str();
41}
42
43void __init board_setup(void)
44{
45 int ret;
46
47 switch (alchemy_get_cputype()) {
48 case ALCHEMY_CPU_AU1550:
49 ret = db1550_board_setup();
50 break;
51 case ALCHEMY_CPU_AU1200:
52 ret = db1200_board_setup();
53 break;
54 case ALCHEMY_CPU_AU1300:
55 ret = db1300_board_setup();
56 break;
57 default:
58 pr_err("unsupported CPU on board\n");
59 ret = -ENODEV;
60 }
61 if (ret)
62 panic("cannot initialize board support\n");
63}
64
65int __init db1235_arch_init(void)
66{
67 int id = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI));
68 if (id == BCSR_WHOAMI_DB1550)
69 return db1550_pci_setup(0);
70 else if ((id == BCSR_WHOAMI_PB1550_SDR) ||
71 (id == BCSR_WHOAMI_PB1550_DDR))
72 return db1550_pci_setup(1);
73
74 return 0;
75}
76arch_initcall(db1235_arch_init);
77
78int __init db1235_dev_init(void)
79{
80 switch (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI))) {
81 case BCSR_WHOAMI_PB1200_DDR1:
82 case BCSR_WHOAMI_PB1200_DDR2:
83 case BCSR_WHOAMI_DB1200:
84 return db1200_dev_setup();
85 case BCSR_WHOAMI_DB1300:
86 return db1300_dev_setup();
87 case BCSR_WHOAMI_DB1550:
88 case BCSR_WHOAMI_PB1550_SDR:
89 case BCSR_WHOAMI_PB1550_DDR:
90 return db1550_dev_setup();
91 }
92 return 0;
93}
94device_initcall(db1235_dev_init);
diff --git a/arch/mips/alchemy/devboards/db1300.c b/arch/mips/alchemy/devboards/db1300.c
index c56e0246694e..cdf37cbd3d1f 100644
--- a/arch/mips/alchemy/devboards/db1300.c
+++ b/arch/mips/alchemy/devboards/db1300.c
@@ -110,11 +110,6 @@ static void __init db1300_gpio_config(void)
110 au1300_set_dbdma_gpio(1, AU1300_PIN_FG3AUX); 110 au1300_set_dbdma_gpio(1, AU1300_PIN_FG3AUX);
111} 111}
112 112
113char *get_system_type(void)
114{
115 return "DB1300";
116}
117
118/**********************************************************************/ 113/**********************************************************************/
119 114
120static void au1300_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, 115static void au1300_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
@@ -701,7 +696,7 @@ static struct platform_device *db1300_dev[] __initdata = {
701 &db1300_sndi2s_dev, 696 &db1300_sndi2s_dev,
702}; 697};
703 698
704static int __init db1300_device_init(void) 699int __init db1300_dev_setup(void)
705{ 700{
706 int swapped, cpldirq; 701 int swapped, cpldirq;
707 702
@@ -758,10 +753,9 @@ static int __init db1300_device_init(void)
758 753
759 return platform_add_devices(db1300_dev, ARRAY_SIZE(db1300_dev)); 754 return platform_add_devices(db1300_dev, ARRAY_SIZE(db1300_dev));
760} 755}
761device_initcall(db1300_device_init);
762 756
763 757
764void __init board_setup(void) 758int __init db1300_board_setup(void)
765{ 759{
766 unsigned short whoami; 760 unsigned short whoami;
767 761
@@ -779,4 +773,6 @@ void __init board_setup(void)
779 alchemy_uart_enable(AU1300_UART0_PHYS_ADDR); 773 alchemy_uart_enable(AU1300_UART0_PHYS_ADDR);
780 alchemy_uart_enable(AU1300_UART1_PHYS_ADDR); 774 alchemy_uart_enable(AU1300_UART1_PHYS_ADDR);
781 alchemy_uart_enable(AU1300_UART3_PHYS_ADDR); 775 alchemy_uart_enable(AU1300_UART3_PHYS_ADDR);
776
777 return 0;
782} 778}
diff --git a/arch/mips/alchemy/devboards/db1550.c b/arch/mips/alchemy/devboards/db1550.c
index 9eb79062f46e..5a9ae6095428 100644
--- a/arch/mips/alchemy/devboards/db1550.c
+++ b/arch/mips/alchemy/devboards/db1550.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Alchemy Db1550 board support 2 * Alchemy Db1550/Pb1550 board support
3 * 3 *
4 * (c) 2011 Manuel Lauss <manuel.lauss@googlemail.com> 4 * (c) 2011 Manuel Lauss <manuel.lauss@googlemail.com>
5 */ 5 */
@@ -17,34 +17,29 @@
17#include <linux/pm.h> 17#include <linux/pm.h>
18#include <linux/spi/spi.h> 18#include <linux/spi/spi.h>
19#include <linux/spi/flash.h> 19#include <linux/spi/flash.h>
20#include <asm/bootinfo.h>
20#include <asm/mach-au1x00/au1000.h> 21#include <asm/mach-au1x00/au1000.h>
21#include <asm/mach-au1x00/au1xxx_eth.h> 22#include <asm/mach-au1x00/au1xxx_eth.h>
22#include <asm/mach-au1x00/au1xxx_dbdma.h> 23#include <asm/mach-au1x00/au1xxx_dbdma.h>
23#include <asm/mach-au1x00/au1xxx_psc.h> 24#include <asm/mach-au1x00/au1xxx_psc.h>
24#include <asm/mach-au1x00/au1550_spi.h> 25#include <asm/mach-au1x00/au1550_spi.h>
26#include <asm/mach-au1x00/au1550nd.h>
25#include <asm/mach-db1x00/bcsr.h> 27#include <asm/mach-db1x00/bcsr.h>
26#include <prom.h> 28#include <prom.h>
27#include "platform.h" 29#include "platform.h"
28 30
29
30const char *get_system_type(void)
31{
32 return "DB1550";
33}
34
35static void __init db1550_hw_setup(void) 31static void __init db1550_hw_setup(void)
36{ 32{
37 void __iomem *base; 33 void __iomem *base;
38 34
39 alchemy_gpio_direction_output(203, 0); /* red led on */
40
41 /* complete SPI setup: link psc0_intclk to a 48MHz source, 35 /* complete SPI setup: link psc0_intclk to a 48MHz source,
42 * and assign GPIO16 to PSC0_SYNC1 (SPI cs# line) 36 * and assign GPIO16 to PSC0_SYNC1 (SPI cs# line) as well as PSC1_SYNC
37 * for AC97 on PB1550.
43 */ 38 */
44 base = (void __iomem *)SYS_CLKSRC; 39 base = (void __iomem *)SYS_CLKSRC;
45 __raw_writel(__raw_readl(base) | 0x000001e0, base); 40 __raw_writel(__raw_readl(base) | 0x000001e0, base);
46 base = (void __iomem *)SYS_PINFUNC; 41 base = (void __iomem *)SYS_PINFUNC;
47 __raw_writel(__raw_readl(base) | 1, base); 42 __raw_writel(__raw_readl(base) | 1 | SYS_PF_PSC1_S1, base);
48 wmb(); 43 wmb();
49 44
50 /* reset the AC97 codec now, the reset time in the psc-ac97 driver 45 /* reset the AC97 codec now, the reset time in the psc-ac97 driver
@@ -57,23 +52,27 @@ static void __init db1550_hw_setup(void)
57 wmb(); 52 wmb();
58 __raw_writel(PSC_AC97RST_RST, base + PSC_AC97RST_OFFSET); 53 __raw_writel(PSC_AC97RST_RST, base + PSC_AC97RST_OFFSET);
59 wmb(); 54 wmb();
60
61 alchemy_gpio_direction_output(202, 0); /* green led on */
62} 55}
63 56
64void __init board_setup(void) 57int __init db1550_board_setup(void)
65{ 58{
66 unsigned short whoami; 59 unsigned short whoami;
67 60
68 bcsr_init(DB1550_BCSR_PHYS_ADDR, 61 bcsr_init(DB1550_BCSR_PHYS_ADDR,
69 DB1550_BCSR_PHYS_ADDR + DB1550_BCSR_HEXLED_OFS); 62 DB1550_BCSR_PHYS_ADDR + DB1550_BCSR_HEXLED_OFS);
70 63
71 whoami = bcsr_read(BCSR_WHOAMI); 64 whoami = bcsr_read(BCSR_WHOAMI); /* PB1550 hexled offset differs */
72 printk(KERN_INFO "Alchemy/AMD DB1550 Board, CPLD Rev %d" 65 if ((BCSR_WHOAMI_BOARD(whoami) == BCSR_WHOAMI_PB1550_SDR) ||
73 " Board-ID %d Daughtercard ID %d\n", 66 (BCSR_WHOAMI_BOARD(whoami) == BCSR_WHOAMI_PB1550_DDR))
67 bcsr_init(PB1550_BCSR_PHYS_ADDR,
68 PB1550_BCSR_PHYS_ADDR + PB1550_BCSR_HEXLED_OFS);
69
70 pr_info("Alchemy/AMD %s Board, CPLD Rev %d Board-ID %d " \
71 "Daughtercard ID %d\n", get_system_type(),
74 (whoami >> 4) & 0xf, (whoami >> 8) & 0xf, whoami & 0xf); 72 (whoami >> 4) & 0xf, (whoami >> 8) & 0xf, whoami & 0xf);
75 73
76 db1550_hw_setup(); 74 db1550_hw_setup();
75 return 0;
77} 76}
78 77
79/*****************************************************************************/ 78/*****************************************************************************/
@@ -194,6 +193,39 @@ static struct platform_device db1550_nand_dev = {
194 } 193 }
195}; 194};
196 195
196static struct au1550nd_platdata pb1550_nand_pd = {
197 .parts = db1550_nand_parts,
198 .num_parts = ARRAY_SIZE(db1550_nand_parts),
199 .devwidth = 0, /* x8 NAND default, needs fixing up */
200};
201
202static struct platform_device pb1550_nand_dev = {
203 .name = "au1550-nand",
204 .id = -1,
205 .resource = db1550_nand_res,
206 .num_resources = ARRAY_SIZE(db1550_nand_res),
207 .dev = {
208 .platform_data = &pb1550_nand_pd,
209 },
210};
211
212static void __init pb1550_nand_setup(void)
213{
214 int boot_swapboot = (au_readl(MEM_STSTAT) & (0x7 << 1)) |
215 ((bcsr_read(BCSR_STATUS) >> 6) & 0x1);
216
217 gpio_direction_input(206); /* de-assert NAND CS# */
218 switch (boot_swapboot) {
219 case 0: case 2: case 8: case 0xC: case 0xD:
220 /* x16 NAND Flash */
221 pb1550_nand_pd.devwidth = 1;
222 /* fallthrough */
223 case 1: case 3: case 9: case 0xE: case 0xF:
224 /* x8 NAND, already set up */
225 platform_device_register(&pb1550_nand_dev);
226 }
227}
228
197/**********************************************************************/ 229/**********************************************************************/
198 230
199static struct resource au1550_psc0_res[] = { 231static struct resource au1550_psc0_res[] = {
@@ -394,6 +426,29 @@ static int db1550_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
394 return -1; 426 return -1;
395} 427}
396 428
429static int pb1550_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
430{
431 if ((slot < 12) || (slot > 13) || pin == 0)
432 return -1;
433 if (slot == 12) {
434 switch (pin) {
435 case 1: return AU1500_PCI_INTB;
436 case 2: return AU1500_PCI_INTC;
437 case 3: return AU1500_PCI_INTD;
438 case 4: return AU1500_PCI_INTA;
439 }
440 }
441 if (slot == 13) {
442 switch (pin) {
443 case 1: return AU1500_PCI_INTA;
444 case 2: return AU1500_PCI_INTB;
445 case 3: return AU1500_PCI_INTC;
446 case 4: return AU1500_PCI_INTD;
447 }
448 }
449 return -1;
450}
451
397static struct resource alchemy_pci_host_res[] = { 452static struct resource alchemy_pci_host_res[] = {
398 [0] = { 453 [0] = {
399 .start = AU1500_PCI_PHYS_ADDR, 454 .start = AU1500_PCI_PHYS_ADDR,
@@ -417,7 +472,6 @@ static struct platform_device db1550_pci_host_dev = {
417/**********************************************************************/ 472/**********************************************************************/
418 473
419static struct platform_device *db1550_devs[] __initdata = { 474static struct platform_device *db1550_devs[] __initdata = {
420 &db1550_nand_dev,
421 &db1550_i2c_dev, 475 &db1550_i2c_dev,
422 &db1550_ac97_dev, 476 &db1550_ac97_dev,
423 &db1550_spi_dev, 477 &db1550_spi_dev,
@@ -430,15 +484,16 @@ static struct platform_device *db1550_devs[] __initdata = {
430}; 484};
431 485
432/* must be arch_initcall; MIPS PCI scans busses in a subsys_initcall */ 486/* must be arch_initcall; MIPS PCI scans busses in a subsys_initcall */
433static int __init db1550_pci_init(void) 487int __init db1550_pci_setup(int id)
434{ 488{
489 if (id)
490 db1550_pci_pd.board_map_irq = pb1550_map_pci_irq;
435 return platform_device_register(&db1550_pci_host_dev); 491 return platform_device_register(&db1550_pci_host_dev);
436} 492}
437arch_initcall(db1550_pci_init);
438 493
439static int __init db1550_dev_init(void) 494static void __init db1550_devices(void)
440{ 495{
441 int swapped; 496 alchemy_gpio_direction_output(203, 0); /* red led on */
442 497
443 irq_set_irq_type(AU1550_GPIO0_INT, IRQ_TYPE_EDGE_BOTH); /* CD0# */ 498 irq_set_irq_type(AU1550_GPIO0_INT, IRQ_TYPE_EDGE_BOTH); /* CD0# */
444 irq_set_irq_type(AU1550_GPIO1_INT, IRQ_TYPE_EDGE_BOTH); /* CD1# */ 499 irq_set_irq_type(AU1550_GPIO1_INT, IRQ_TYPE_EDGE_BOTH); /* CD1# */
@@ -447,6 +502,75 @@ static int __init db1550_dev_init(void)
447 irq_set_irq_type(AU1550_GPIO21_INT, IRQ_TYPE_LEVEL_LOW); /* STSCHG0# */ 502 irq_set_irq_type(AU1550_GPIO21_INT, IRQ_TYPE_LEVEL_LOW); /* STSCHG0# */
448 irq_set_irq_type(AU1550_GPIO22_INT, IRQ_TYPE_LEVEL_LOW); /* STSCHG1# */ 503 irq_set_irq_type(AU1550_GPIO22_INT, IRQ_TYPE_LEVEL_LOW); /* STSCHG1# */
449 504
505 db1x_register_pcmcia_socket(
506 AU1000_PCMCIA_ATTR_PHYS_ADDR,
507 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
508 AU1000_PCMCIA_MEM_PHYS_ADDR,
509 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
510 AU1000_PCMCIA_IO_PHYS_ADDR,
511 AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
512 AU1550_GPIO3_INT, AU1550_GPIO0_INT,
513 /*AU1550_GPIO21_INT*/0, 0, 0);
514
515 db1x_register_pcmcia_socket(
516 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000,
517 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1,
518 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004000000,
519 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1,
520 AU1000_PCMCIA_IO_PHYS_ADDR + 0x004000000,
521 AU1000_PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1,
522 AU1550_GPIO5_INT, AU1550_GPIO1_INT,
523 /*AU1550_GPIO22_INT*/0, 0, 1);
524
525 platform_device_register(&db1550_nand_dev);
526
527 alchemy_gpio_direction_output(202, 0); /* green led on */
528}
529
530static void __init pb1550_devices(void)
531{
532 irq_set_irq_type(AU1550_GPIO0_INT, IRQ_TYPE_LEVEL_LOW);
533 irq_set_irq_type(AU1550_GPIO1_INT, IRQ_TYPE_LEVEL_LOW);
534 irq_set_irq_type(AU1550_GPIO201_205_INT, IRQ_TYPE_LEVEL_HIGH);
535
536 /* enable both PCMCIA card irqs in the shared line */
537 alchemy_gpio2_enable_int(201); /* socket 0 card irq */
538 alchemy_gpio2_enable_int(202); /* socket 1 card irq */
539
540 /* Pb1550, like all others, also has statuschange irqs; however they're
541 * wired up on one of the Au1550's shared GPIO201_205 line, which also
542 * services the PCMCIA card interrupts. So we ignore statuschange and
543 * use the GPIO201_205 exclusively for card interrupts, since a) pcmcia
544 * drivers are used to shared irqs and b) statuschange isn't really use-
545 * ful anyway.
546 */
547 db1x_register_pcmcia_socket(
548 AU1000_PCMCIA_ATTR_PHYS_ADDR,
549 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
550 AU1000_PCMCIA_MEM_PHYS_ADDR,
551 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
552 AU1000_PCMCIA_IO_PHYS_ADDR,
553 AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
554 AU1550_GPIO201_205_INT, AU1550_GPIO0_INT, 0, 0, 0);
555
556 db1x_register_pcmcia_socket(
557 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x008000000,
558 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x008400000 - 1,
559 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x008000000,
560 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x008400000 - 1,
561 AU1000_PCMCIA_IO_PHYS_ADDR + 0x008000000,
562 AU1000_PCMCIA_IO_PHYS_ADDR + 0x008010000 - 1,
563 AU1550_GPIO201_205_INT, AU1550_GPIO1_INT, 0, 0, 1);
564
565 pb1550_nand_setup();
566}
567
568int __init db1550_dev_setup(void)
569{
570 int swapped, id;
571
572 id = (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)) != BCSR_WHOAMI_DB1550);
573
450 i2c_register_board_info(0, db1550_i2c_devs, 574 i2c_register_board_info(0, db1550_i2c_devs,
451 ARRAY_SIZE(db1550_i2c_devs)); 575 ARRAY_SIZE(db1550_i2c_devs));
452 spi_register_board_info(db1550_spi_devs, 576 spi_register_board_info(db1550_spi_devs,
@@ -467,29 +591,11 @@ static int __init db1550_dev_init(void)
467 (void __iomem *)KSEG1ADDR(AU1550_PSC2_PHYS_ADDR) + PSC_SEL_OFFSET); 591 (void __iomem *)KSEG1ADDR(AU1550_PSC2_PHYS_ADDR) + PSC_SEL_OFFSET);
468 wmb(); 592 wmb();
469 593
470 db1x_register_pcmcia_socket( 594 id ? pb1550_devices() : db1550_devices();
471 AU1000_PCMCIA_ATTR_PHYS_ADDR,
472 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
473 AU1000_PCMCIA_MEM_PHYS_ADDR,
474 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
475 AU1000_PCMCIA_IO_PHYS_ADDR,
476 AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
477 AU1550_GPIO3_INT, AU1550_GPIO0_INT,
478 /*AU1550_GPIO21_INT*/0, 0, 0);
479
480 db1x_register_pcmcia_socket(
481 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000,
482 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1,
483 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004000000,
484 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1,
485 AU1000_PCMCIA_IO_PHYS_ADDR + 0x004000000,
486 AU1000_PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1,
487 AU1550_GPIO5_INT, AU1550_GPIO1_INT,
488 /*AU1550_GPIO22_INT*/0, 0, 1);
489 595
490 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT; 596 swapped = bcsr_read(BCSR_STATUS) &
597 (id ? BCSR_STATUS_PB1550_SWAPBOOT : BCSR_STATUS_DB1000_SWAPBOOT);
491 db1x_register_norflash(128 << 20, 4, swapped); 598 db1x_register_norflash(128 << 20, 4, swapped);
492 599
493 return platform_add_devices(db1550_devs, ARRAY_SIZE(db1550_devs)); 600 return platform_add_devices(db1550_devs, ARRAY_SIZE(db1550_devs));
494} 601}
495device_initcall(db1550_dev_init);
diff --git a/arch/mips/alchemy/devboards/pb1100.c b/arch/mips/alchemy/devboards/pb1100.c
deleted file mode 100644
index 78c77a44a317..000000000000
--- a/arch/mips/alchemy/devboards/pb1100.c
+++ /dev/null
@@ -1,167 +0,0 @@
1/*
2 * Pb1100 board platform device registration
3 *
4 * Copyright (C) 2009 Manuel Lauss
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include <linux/delay.h>
22#include <linux/gpio.h>
23#include <linux/init.h>
24#include <linux/interrupt.h>
25#include <linux/dma-mapping.h>
26#include <linux/platform_device.h>
27#include <asm/mach-au1x00/au1000.h>
28#include <asm/mach-db1x00/bcsr.h>
29#include <prom.h>
30#include "platform.h"
31
32const char *get_system_type(void)
33{
34 return "PB1100";
35}
36
37void __init board_setup(void)
38{
39 volatile void __iomem *base = (volatile void __iomem *)0xac000000UL;
40
41 bcsr_init(DB1000_BCSR_PHYS_ADDR,
42 DB1000_BCSR_PHYS_ADDR + DB1000_BCSR_HEXLED_OFS);
43
44 /* Set AUX clock to 12 MHz * 8 = 96 MHz */
45 au_writel(8, SYS_AUXPLL);
46 alchemy_gpio1_input_enable();
47 udelay(100);
48
49#if IS_ENABLED(CONFIG_USB_OHCI_HCD)
50 {
51 u32 pin_func, sys_freqctrl, sys_clksrc;
52
53 /* Configure pins GPIO[14:9] as GPIO */
54 pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_UR3;
55
56 /* Zero and disable FREQ2 */
57 sys_freqctrl = au_readl(SYS_FREQCTRL0);
58 sys_freqctrl &= ~0xFFF00000;
59 au_writel(sys_freqctrl, SYS_FREQCTRL0);
60
61 /* Zero and disable USBH/USBD/IrDA clock */
62 sys_clksrc = au_readl(SYS_CLKSRC);
63 sys_clksrc &= ~(SYS_CS_CIR | SYS_CS_DIR | SYS_CS_MIR_MASK);
64 au_writel(sys_clksrc, SYS_CLKSRC);
65
66 sys_freqctrl = au_readl(SYS_FREQCTRL0);
67 sys_freqctrl &= ~0xFFF00000;
68
69 sys_clksrc = au_readl(SYS_CLKSRC);
70 sys_clksrc &= ~(SYS_CS_CIR | SYS_CS_DIR | SYS_CS_MIR_MASK);
71
72 /* FREQ2 = aux / 2 = 48 MHz */
73 sys_freqctrl |= (0 << SYS_FC_FRDIV2_BIT) |
74 SYS_FC_FE2 | SYS_FC_FS2;
75 au_writel(sys_freqctrl, SYS_FREQCTRL0);
76
77 /*
78 * Route 48 MHz FREQ2 into USBH/USBD/IrDA
79 */
80 sys_clksrc |= SYS_CS_MUX_FQ2 << SYS_CS_MIR_BIT;
81 au_writel(sys_clksrc, SYS_CLKSRC);
82
83 /* Setup the static bus controller */
84 au_writel(0x00000002, MEM_STCFG3); /* type = PCMCIA */
85 au_writel(0x280E3D07, MEM_STTIME3); /* 250ns cycle time */
86 au_writel(0x10000000, MEM_STADDR3); /* any PCMCIA select */
87
88 /*
89 * Get USB Functionality pin state (device vs host drive pins).
90 */
91 pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_USB;
92 /* 2nd USB port is USB host. */
93 pin_func |= SYS_PF_USB;
94 au_writel(pin_func, SYS_PINFUNC);
95 }
96#endif /* IS_ENABLED(CONFIG_USB_OHCI_HCD) */
97
98 /* Enable sys bus clock divider when IDLE state or no bus activity. */
99 au_writel(au_readl(SYS_POWERCTRL) | (0x3 << 5), SYS_POWERCTRL);
100
101 /* Enable the RTC if not already enabled. */
102 if (!(readb(base + 0x28) & 0x20)) {
103 writeb(readb(base + 0x28) | 0x20, base + 0x28);
104 au_sync();
105 }
106 /* Put the clock in BCD mode. */
107 if (readb(base + 0x2C) & 0x4) { /* reg B */
108 writeb(readb(base + 0x2c) & ~0x4, base + 0x2c);
109 au_sync();
110 }
111}
112
113/******************************************************************************/
114
115static struct resource au1100_lcd_resources[] = {
116 [0] = {
117 .start = AU1100_LCD_PHYS_ADDR,
118 .end = AU1100_LCD_PHYS_ADDR + 0x800 - 1,
119 .flags = IORESOURCE_MEM,
120 },
121 [1] = {
122 .start = AU1100_LCD_INT,
123 .end = AU1100_LCD_INT,
124 .flags = IORESOURCE_IRQ,
125 }
126};
127
128static u64 au1100_lcd_dmamask = DMA_BIT_MASK(32);
129
130static struct platform_device au1100_lcd_device = {
131 .name = "au1100-lcd",
132 .id = 0,
133 .dev = {
134 .dma_mask = &au1100_lcd_dmamask,
135 .coherent_dma_mask = DMA_BIT_MASK(32),
136 },
137 .num_resources = ARRAY_SIZE(au1100_lcd_resources),
138 .resource = au1100_lcd_resources,
139};
140
141static int __init pb1100_dev_init(void)
142{
143 int swapped;
144
145 irq_set_irq_type(AU1100_GPIO9_INT, IRQF_TRIGGER_LOW); /* PCCD# */
146 irq_set_irq_type(AU1100_GPIO10_INT, IRQF_TRIGGER_LOW); /* PCSTSCHG# */
147 irq_set_irq_type(AU1100_GPIO11_INT, IRQF_TRIGGER_LOW); /* PCCard# */
148 irq_set_irq_type(AU1100_GPIO13_INT, IRQF_TRIGGER_LOW); /* DC_IRQ# */
149
150 /* PCMCIA. single socket, identical to Pb1500 */
151 db1x_register_pcmcia_socket(
152 AU1000_PCMCIA_ATTR_PHYS_ADDR,
153 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
154 AU1000_PCMCIA_MEM_PHYS_ADDR,
155 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
156 AU1000_PCMCIA_IO_PHYS_ADDR,
157 AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
158 AU1100_GPIO11_INT, AU1100_GPIO9_INT, /* card / insert */
159 /*AU1100_GPIO10_INT*/0, 0, 0); /* stschg / eject / id */
160
161 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT;
162 db1x_register_norflash(64 * 1024 * 1024, 4, swapped);
163 platform_device_register(&au1100_lcd_device);
164
165 return 0;
166}
167device_initcall(pb1100_dev_init);
diff --git a/arch/mips/alchemy/devboards/pb1500.c b/arch/mips/alchemy/devboards/pb1500.c
deleted file mode 100644
index 232fee942000..000000000000
--- a/arch/mips/alchemy/devboards/pb1500.c
+++ /dev/null
@@ -1,198 +0,0 @@
1/*
2 * Pb1500 board support.
3 *
4 * Copyright (C) 2009 Manuel Lauss
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include <linux/delay.h>
22#include <linux/dma-mapping.h>
23#include <linux/gpio.h>
24#include <linux/init.h>
25#include <linux/interrupt.h>
26#include <linux/platform_device.h>
27#include <asm/mach-au1x00/au1000.h>
28#include <asm/mach-db1x00/bcsr.h>
29#include <prom.h>
30#include "platform.h"
31
32const char *get_system_type(void)
33{
34 return "PB1500";
35}
36
37void __init board_setup(void)
38{
39 u32 pin_func;
40 u32 sys_freqctrl, sys_clksrc;
41
42 bcsr_init(DB1000_BCSR_PHYS_ADDR,
43 DB1000_BCSR_PHYS_ADDR + DB1000_BCSR_HEXLED_OFS);
44
45 sys_clksrc = sys_freqctrl = pin_func = 0;
46 /* Set AUX clock to 12 MHz * 8 = 96 MHz */
47 au_writel(8, SYS_AUXPLL);
48 alchemy_gpio1_input_enable();
49 udelay(100);
50
51 /* GPIO201 is input for PCMCIA card detect */
52 /* GPIO203 is input for PCMCIA interrupt request */
53 alchemy_gpio_direction_input(201);
54 alchemy_gpio_direction_input(203);
55
56#if IS_ENABLED(CONFIG_USB_OHCI_HCD)
57
58 /* Zero and disable FREQ2 */
59 sys_freqctrl = au_readl(SYS_FREQCTRL0);
60 sys_freqctrl &= ~0xFFF00000;
61 au_writel(sys_freqctrl, SYS_FREQCTRL0);
62
63 /* zero and disable USBH/USBD clocks */
64 sys_clksrc = au_readl(SYS_CLKSRC);
65 sys_clksrc &= ~(SYS_CS_CUD | SYS_CS_DUD | SYS_CS_MUD_MASK |
66 SYS_CS_CUH | SYS_CS_DUH | SYS_CS_MUH_MASK);
67 au_writel(sys_clksrc, SYS_CLKSRC);
68
69 sys_freqctrl = au_readl(SYS_FREQCTRL0);
70 sys_freqctrl &= ~0xFFF00000;
71
72 sys_clksrc = au_readl(SYS_CLKSRC);
73 sys_clksrc &= ~(SYS_CS_CUD | SYS_CS_DUD | SYS_CS_MUD_MASK |
74 SYS_CS_CUH | SYS_CS_DUH | SYS_CS_MUH_MASK);
75
76 /* FREQ2 = aux/2 = 48 MHz */
77 sys_freqctrl |= (0 << SYS_FC_FRDIV2_BIT) | SYS_FC_FE2 | SYS_FC_FS2;
78 au_writel(sys_freqctrl, SYS_FREQCTRL0);
79
80 /*
81 * Route 48MHz FREQ2 into USB Host and/or Device
82 */
83 sys_clksrc |= SYS_CS_MUX_FQ2 << SYS_CS_MUH_BIT;
84 au_writel(sys_clksrc, SYS_CLKSRC);
85
86 pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_USB;
87 /* 2nd USB port is USB host */
88 pin_func |= SYS_PF_USB;
89 au_writel(pin_func, SYS_PINFUNC);
90#endif /* IS_ENABLED(CONFIG_USB_OHCI_HCD) */
91
92#ifdef CONFIG_PCI
93 {
94 void __iomem *base =
95 (void __iomem *)KSEG1ADDR(AU1500_PCI_PHYS_ADDR);
96 /* Setup PCI bus controller */
97 __raw_writel(0x00003fff, base + PCI_REG_CMEM);
98 __raw_writel(0xf0000000, base + PCI_REG_MWMASK_DEV);
99 __raw_writel(0, base + PCI_REG_MWBASE_REV_CCL);
100 __raw_writel(0x02a00356, base + PCI_REG_STATCMD);
101 __raw_writel(0x00003c04, base + PCI_REG_PARAM);
102 __raw_writel(0x00000008, base + PCI_REG_MBAR);
103 wmb();
104 }
105#endif
106
107 /* Enable sys bus clock divider when IDLE state or no bus activity. */
108 au_writel(au_readl(SYS_POWERCTRL) | (0x3 << 5), SYS_POWERCTRL);
109
110 /* Enable the RTC if not already enabled */
111 if (!(au_readl(0xac000028) & 0x20)) {
112 printk(KERN_INFO "enabling clock ...\n");
113 au_writel((au_readl(0xac000028) | 0x20), 0xac000028);
114 }
115 /* Put the clock in BCD mode */
116 if (au_readl(0xac00002c) & 0x4) { /* reg B */
117 au_writel(au_readl(0xac00002c) & ~0x4, 0xac00002c);
118 au_sync();
119 }
120}
121
122/******************************************************************************/
123
124static int pb1500_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
125{
126 if ((slot < 12) || (slot > 13) || pin == 0)
127 return -1;
128 if (slot == 12)
129 return (pin == 1) ? AU1500_PCI_INTA : 0xff;
130 if (slot == 13) {
131 switch (pin) {
132 case 1: return AU1500_PCI_INTA;
133 case 2: return AU1500_PCI_INTB;
134 case 3: return AU1500_PCI_INTC;
135 case 4: return AU1500_PCI_INTD;
136 }
137 }
138 return -1;
139}
140
141static struct resource alchemy_pci_host_res[] = {
142 [0] = {
143 .start = AU1500_PCI_PHYS_ADDR,
144 .end = AU1500_PCI_PHYS_ADDR + 0xfff,
145 .flags = IORESOURCE_MEM,
146 },
147};
148
149static struct alchemy_pci_platdata pb1500_pci_pd = {
150 .board_map_irq = pb1500_map_pci_irq,
151 .pci_cfg_set = PCI_CONFIG_AEN | PCI_CONFIG_R2H | PCI_CONFIG_R1H |
152 PCI_CONFIG_CH |
153#if defined(__MIPSEB__)
154 PCI_CONFIG_SIC_HWA_DAT | PCI_CONFIG_SM,
155#else
156 0,
157#endif
158};
159
160static struct platform_device pb1500_pci_host = {
161 .dev.platform_data = &pb1500_pci_pd,
162 .name = "alchemy-pci",
163 .id = 0,
164 .num_resources = ARRAY_SIZE(alchemy_pci_host_res),
165 .resource = alchemy_pci_host_res,
166};
167
168static int __init pb1500_dev_init(void)
169{
170 int swapped;
171
172 irq_set_irq_type(AU1500_GPIO9_INT, IRQF_TRIGGER_LOW); /* CD0# */
173 irq_set_irq_type(AU1500_GPIO10_INT, IRQF_TRIGGER_LOW); /* CARD0 */
174 irq_set_irq_type(AU1500_GPIO11_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
175 irq_set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH);
176 irq_set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW);
177 irq_set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW);
178 irq_set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW);
179 irq_set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW);
180
181 /* PCMCIA. single socket, identical to Pb1100 */
182 db1x_register_pcmcia_socket(
183 AU1000_PCMCIA_ATTR_PHYS_ADDR,
184 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
185 AU1000_PCMCIA_MEM_PHYS_ADDR,
186 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
187 AU1000_PCMCIA_IO_PHYS_ADDR,
188 AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
189 AU1500_GPIO11_INT, AU1500_GPIO9_INT, /* card / insert */
190 /*AU1500_GPIO10_INT*/0, 0, 0); /* stschg / eject / id */
191
192 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT;
193 db1x_register_norflash(64 * 1024 * 1024, 4, swapped);
194 platform_device_register(&pb1500_pci_host);
195
196 return 0;
197}
198arch_initcall(pb1500_dev_init);
diff --git a/arch/mips/alchemy/devboards/pb1550.c b/arch/mips/alchemy/devboards/pb1550.c
deleted file mode 100644
index b37e7de8d920..000000000000
--- a/arch/mips/alchemy/devboards/pb1550.c
+++ /dev/null
@@ -1,244 +0,0 @@
1/*
2 * Pb1550 board support.
3 *
4 * Copyright (C) 2009-2011 Manuel Lauss
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include <linux/dma-mapping.h>
22#include <linux/init.h>
23#include <linux/interrupt.h>
24#include <linux/platform_device.h>
25#include <asm/mach-au1x00/au1000.h>
26#include <asm/mach-au1x00/au1xxx_dbdma.h>
27#include <asm/mach-au1x00/au1550nd.h>
28#include <asm/mach-au1x00/gpio.h>
29#include <asm/mach-db1x00/bcsr.h>
30#include "platform.h"
31
32const char *get_system_type(void)
33{
34 return "PB1550";
35}
36
37void __init board_setup(void)
38{
39 u32 pin_func;
40
41 bcsr_init(PB1550_BCSR_PHYS_ADDR,
42 PB1550_BCSR_PHYS_ADDR + PB1550_BCSR_HEXLED_OFS);
43
44 alchemy_gpio2_enable();
45
46 /*
47 * Enable PSC1 SYNC for AC'97. Normaly done in audio driver,
48 * but it is board specific code, so put it here.
49 */
50 pin_func = au_readl(SYS_PINFUNC);
51 au_sync();
52 pin_func |= SYS_PF_MUST_BE_SET | SYS_PF_PSC1_S1;
53 au_writel(pin_func, SYS_PINFUNC);
54
55 bcsr_write(BCSR_PCMCIA, 0); /* turn off PCMCIA power */
56
57 printk(KERN_INFO "AMD Alchemy Pb1550 Board\n");
58}
59
60/******************************************************************************/
61
62static int pb1550_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
63{
64 if ((slot < 12) || (slot > 13) || pin == 0)
65 return -1;
66 if (slot == 12) {
67 switch (pin) {
68 case 1: return AU1500_PCI_INTB;
69 case 2: return AU1500_PCI_INTC;
70 case 3: return AU1500_PCI_INTD;
71 case 4: return AU1500_PCI_INTA;
72 }
73 }
74 if (slot == 13) {
75 switch (pin) {
76 case 1: return AU1500_PCI_INTA;
77 case 2: return AU1500_PCI_INTB;
78 case 3: return AU1500_PCI_INTC;
79 case 4: return AU1500_PCI_INTD;
80 }
81 }
82 return -1;
83}
84
85static struct resource alchemy_pci_host_res[] = {
86 [0] = {
87 .start = AU1500_PCI_PHYS_ADDR,
88 .end = AU1500_PCI_PHYS_ADDR + 0xfff,
89 .flags = IORESOURCE_MEM,
90 },
91};
92
93static struct alchemy_pci_platdata pb1550_pci_pd = {
94 .board_map_irq = pb1550_map_pci_irq,
95};
96
97static struct platform_device pb1550_pci_host = {
98 .dev.platform_data = &pb1550_pci_pd,
99 .name = "alchemy-pci",
100 .id = 0,
101 .num_resources = ARRAY_SIZE(alchemy_pci_host_res),
102 .resource = alchemy_pci_host_res,
103};
104
105static struct resource au1550_psc2_res[] = {
106 [0] = {
107 .start = AU1550_PSC2_PHYS_ADDR,
108 .end = AU1550_PSC2_PHYS_ADDR + 0xfff,
109 .flags = IORESOURCE_MEM,
110 },
111 [1] = {
112 .start = AU1550_PSC2_INT,
113 .end = AU1550_PSC2_INT,
114 .flags = IORESOURCE_IRQ,
115 },
116 [2] = {
117 .start = AU1550_DSCR_CMD0_PSC2_TX,
118 .end = AU1550_DSCR_CMD0_PSC2_TX,
119 .flags = IORESOURCE_DMA,
120 },
121 [3] = {
122 .start = AU1550_DSCR_CMD0_PSC2_RX,
123 .end = AU1550_DSCR_CMD0_PSC2_RX,
124 .flags = IORESOURCE_DMA,
125 },
126};
127
128static struct platform_device pb1550_i2c_dev = {
129 .name = "au1xpsc_smbus",
130 .id = 0, /* bus number */
131 .num_resources = ARRAY_SIZE(au1550_psc2_res),
132 .resource = au1550_psc2_res,
133};
134
135static struct mtd_partition pb1550_nand_parts[] = {
136 [0] = {
137 .name = "NAND FS 0",
138 .offset = 0,
139 .size = 8 * 1024 * 1024,
140 },
141 [1] = {
142 .name = "NAND FS 1",
143 .offset = MTDPART_OFS_APPEND,
144 .size = MTDPART_SIZ_FULL,
145 },
146};
147
148static struct au1550nd_platdata pb1550_nand_pd = {
149 .parts = pb1550_nand_parts,
150 .num_parts = ARRAY_SIZE(pb1550_nand_parts),
151 .devwidth = 0, /* x8 NAND default, needs fixing up */
152};
153
154static struct resource pb1550_nand_res[] = {
155 [0] = {
156 .start = 0x20000000,
157 .end = 0x20000fff,
158 .flags = IORESOURCE_MEM,
159 },
160};
161
162static struct platform_device pb1550_nand_dev = {
163 .name = "au1550-nand",
164 .id = -1,
165 .resource = pb1550_nand_res,
166 .num_resources = ARRAY_SIZE(pb1550_nand_res),
167 .dev = {
168 .platform_data = &pb1550_nand_pd,
169 },
170};
171
172static void __init pb1550_nand_setup(void)
173{
174 int boot_swapboot = (au_readl(MEM_STSTAT) & (0x7 << 1)) |
175 ((bcsr_read(BCSR_STATUS) >> 6) & 0x1);
176
177 switch (boot_swapboot) {
178 case 0:
179 case 2:
180 case 8:
181 case 0xC:
182 case 0xD:
183 /* x16 NAND Flash */
184 pb1550_nand_pd.devwidth = 1;
185 /* fallthrough */
186 case 1:
187 case 9:
188 case 3:
189 case 0xE:
190 case 0xF:
191 /* x8 NAND, already set up */
192 platform_device_register(&pb1550_nand_dev);
193 }
194}
195
196static int __init pb1550_dev_init(void)
197{
198 int swapped;
199
200 irq_set_irq_type(AU1550_GPIO0_INT, IRQF_TRIGGER_LOW);
201 irq_set_irq_type(AU1550_GPIO1_INT, IRQF_TRIGGER_LOW);
202 irq_set_irq_type(AU1550_GPIO201_205_INT, IRQF_TRIGGER_HIGH);
203
204 /* enable both PCMCIA card irqs in the shared line */
205 alchemy_gpio2_enable_int(201);
206 alchemy_gpio2_enable_int(202);
207
208 /* Pb1550, like all others, also has statuschange irqs; however they're
209 * wired up on one of the Au1550's shared GPIO201_205 line, which also
210 * services the PCMCIA card interrupts. So we ignore statuschange and
211 * use the GPIO201_205 exclusively for card interrupts, since a) pcmcia
212 * drivers are used to shared irqs and b) statuschange isn't really use-
213 * ful anyway.
214 */
215 db1x_register_pcmcia_socket(
216 AU1000_PCMCIA_ATTR_PHYS_ADDR,
217 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
218 AU1000_PCMCIA_MEM_PHYS_ADDR,
219 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
220 AU1000_PCMCIA_IO_PHYS_ADDR,
221 AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
222 AU1550_GPIO201_205_INT, AU1550_GPIO0_INT, 0, 0, 0);
223
224 db1x_register_pcmcia_socket(
225 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x008000000,
226 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x008400000 - 1,
227 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x008000000,
228 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x008400000 - 1,
229 AU1000_PCMCIA_IO_PHYS_ADDR + 0x008000000,
230 AU1000_PCMCIA_IO_PHYS_ADDR + 0x008010000 - 1,
231 AU1550_GPIO201_205_INT, AU1550_GPIO1_INT, 0, 0, 1);
232
233 /* NAND setup */
234 gpio_direction_input(206); /* GPIO206 high */
235 pb1550_nand_setup();
236
237 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_PB1550_SWAPBOOT;
238 db1x_register_norflash(128 * 1024 * 1024, 4, swapped);
239 platform_device_register(&pb1550_pci_host);
240 platform_device_register(&pb1550_i2c_dev);
241
242 return 0;
243}
244arch_initcall(pb1550_dev_init);
diff --git a/arch/mips/alchemy/devboards/platform.c b/arch/mips/alchemy/devboards/platform.c
index f39042e99d0d..8df86eb94972 100644
--- a/arch/mips/alchemy/devboards/platform.c
+++ b/arch/mips/alchemy/devboards/platform.c
@@ -36,11 +36,10 @@ void __init prom_init(void)
36 36
37void prom_putchar(unsigned char c) 37void prom_putchar(unsigned char c)
38{ 38{
39#ifdef CONFIG_MIPS_DB1300 39 if (alchemy_get_cputype() == ALCHEMY_CPU_AU1300)
40 alchemy_uart_putchar(AU1300_UART2_PHYS_ADDR, c); 40 alchemy_uart_putchar(AU1300_UART2_PHYS_ADDR, c);
41#else 41 else
42 alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c); 42 alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c);
43#endif
44} 43}
45 44
46 45
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-23 12:45:28 -0500