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-rw-r--r--arch/mips/alchemy/devboards/pb1100.c167
1 files changed, 0 insertions, 167 deletions
diff --git a/arch/mips/alchemy/devboards/pb1100.c b/arch/mips/alchemy/devboards/pb1100.c
deleted file mode 100644
index 78c77a44a317..000000000000
--- a/arch/mips/alchemy/devboards/pb1100.c
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1/*
2 * Pb1100 board platform device registration
3 *
4 * Copyright (C) 2009 Manuel Lauss
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include <linux/delay.h>
22#include <linux/gpio.h>
23#include <linux/init.h>
24#include <linux/interrupt.h>
25#include <linux/dma-mapping.h>
26#include <linux/platform_device.h>
27#include <asm/mach-au1x00/au1000.h>
28#include <asm/mach-db1x00/bcsr.h>
29#include <prom.h>
30#include "platform.h"
31
32const char *get_system_type(void)
33{
34 return "PB1100";
35}
36
37void __init board_setup(void)
38{
39 volatile void __iomem *base = (volatile void __iomem *)0xac000000UL;
40
41 bcsr_init(DB1000_BCSR_PHYS_ADDR,
42 DB1000_BCSR_PHYS_ADDR + DB1000_BCSR_HEXLED_OFS);
43
44 /* Set AUX clock to 12 MHz * 8 = 96 MHz */
45 au_writel(8, SYS_AUXPLL);
46 alchemy_gpio1_input_enable();
47 udelay(100);
48
49#if IS_ENABLED(CONFIG_USB_OHCI_HCD)
50 {
51 u32 pin_func, sys_freqctrl, sys_clksrc;
52
53 /* Configure pins GPIO[14:9] as GPIO */
54 pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_UR3;
55
56 /* Zero and disable FREQ2 */
57 sys_freqctrl = au_readl(SYS_FREQCTRL0);
58 sys_freqctrl &= ~0xFFF00000;
59 au_writel(sys_freqctrl, SYS_FREQCTRL0);
60
61 /* Zero and disable USBH/USBD/IrDA clock */
62 sys_clksrc = au_readl(SYS_CLKSRC);
63 sys_clksrc &= ~(SYS_CS_CIR | SYS_CS_DIR | SYS_CS_MIR_MASK);
64 au_writel(sys_clksrc, SYS_CLKSRC);
65
66 sys_freqctrl = au_readl(SYS_FREQCTRL0);
67 sys_freqctrl &= ~0xFFF00000;
68
69 sys_clksrc = au_readl(SYS_CLKSRC);
70 sys_clksrc &= ~(SYS_CS_CIR | SYS_CS_DIR | SYS_CS_MIR_MASK);
71
72 /* FREQ2 = aux / 2 = 48 MHz */
73 sys_freqctrl |= (0 << SYS_FC_FRDIV2_BIT) |
74 SYS_FC_FE2 | SYS_FC_FS2;
75 au_writel(sys_freqctrl, SYS_FREQCTRL0);
76
77 /*
78 * Route 48 MHz FREQ2 into USBH/USBD/IrDA
79 */
80 sys_clksrc |= SYS_CS_MUX_FQ2 << SYS_CS_MIR_BIT;
81 au_writel(sys_clksrc, SYS_CLKSRC);
82
83 /* Setup the static bus controller */
84 au_writel(0x00000002, MEM_STCFG3); /* type = PCMCIA */
85 au_writel(0x280E3D07, MEM_STTIME3); /* 250ns cycle time */
86 au_writel(0x10000000, MEM_STADDR3); /* any PCMCIA select */
87
88 /*
89 * Get USB Functionality pin state (device vs host drive pins).
90 */
91 pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_USB;
92 /* 2nd USB port is USB host. */
93 pin_func |= SYS_PF_USB;
94 au_writel(pin_func, SYS_PINFUNC);
95 }
96#endif /* IS_ENABLED(CONFIG_USB_OHCI_HCD) */
97
98 /* Enable sys bus clock divider when IDLE state or no bus activity. */
99 au_writel(au_readl(SYS_POWERCTRL) | (0x3 << 5), SYS_POWERCTRL);
100
101 /* Enable the RTC if not already enabled. */
102 if (!(readb(base + 0x28) & 0x20)) {
103 writeb(readb(base + 0x28) | 0x20, base + 0x28);
104 au_sync();
105 }
106 /* Put the clock in BCD mode. */
107 if (readb(base + 0x2C) & 0x4) { /* reg B */
108 writeb(readb(base + 0x2c) & ~0x4, base + 0x2c);
109 au_sync();
110 }
111}
112
113/******************************************************************************/
114
115static struct resource au1100_lcd_resources[] = {
116 [0] = {
117 .start = AU1100_LCD_PHYS_ADDR,
118 .end = AU1100_LCD_PHYS_ADDR + 0x800 - 1,
119 .flags = IORESOURCE_MEM,
120 },
121 [1] = {
122 .start = AU1100_LCD_INT,
123 .end = AU1100_LCD_INT,
124 .flags = IORESOURCE_IRQ,
125 }
126};
127
128static u64 au1100_lcd_dmamask = DMA_BIT_MASK(32);
129
130static struct platform_device au1100_lcd_device = {
131 .name = "au1100-lcd",
132 .id = 0,
133 .dev = {
134 .dma_mask = &au1100_lcd_dmamask,
135 .coherent_dma_mask = DMA_BIT_MASK(32),
136 },
137 .num_resources = ARRAY_SIZE(au1100_lcd_resources),
138 .resource = au1100_lcd_resources,
139};
140
141static int __init pb1100_dev_init(void)
142{
143 int swapped;
144
145 irq_set_irq_type(AU1100_GPIO9_INT, IRQF_TRIGGER_LOW); /* PCCD# */
146 irq_set_irq_type(AU1100_GPIO10_INT, IRQF_TRIGGER_LOW); /* PCSTSCHG# */
147 irq_set_irq_type(AU1100_GPIO11_INT, IRQF_TRIGGER_LOW); /* PCCard# */
148 irq_set_irq_type(AU1100_GPIO13_INT, IRQF_TRIGGER_LOW); /* DC_IRQ# */
149
150 /* PCMCIA. single socket, identical to Pb1500 */
151 db1x_register_pcmcia_socket(
152 AU1000_PCMCIA_ATTR_PHYS_ADDR,
153 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
154 AU1000_PCMCIA_MEM_PHYS_ADDR,
155 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
156 AU1000_PCMCIA_IO_PHYS_ADDR,
157 AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
158 AU1100_GPIO11_INT, AU1100_GPIO9_INT, /* card / insert */
159 /*AU1100_GPIO10_INT*/0, 0, 0); /* stschg / eject / id */
160
161 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT;
162 db1x_register_norflash(64 * 1024 * 1024, 4, swapped);
163 platform_device_register(&au1100_lcd_device);
164
165 return 0;
166}
167device_initcall(pb1100_dev_init);
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-01 01:23:49 -0400