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-rw-r--r--arch/mips/alchemy/devboards/db1x00/Makefile2
-rw-r--r--arch/mips/alchemy/devboards/db1x00/board_setup.c204
-rw-r--r--arch/mips/alchemy/devboards/db1x00/irqmap.c90
-rw-r--r--arch/mips/alchemy/devboards/db1x00/platform.c118
4 files changed, 274 insertions, 140 deletions
diff --git a/arch/mips/alchemy/devboards/db1x00/Makefile b/arch/mips/alchemy/devboards/db1x00/Makefile
index 432241ab8677..613c0c0c8be9 100644
--- a/arch/mips/alchemy/devboards/db1x00/Makefile
+++ b/arch/mips/alchemy/devboards/db1x00/Makefile
@@ -5,4 +5,4 @@
5# Makefile for the Alchemy Semiconductor DBAu1xx0 boards. 5# Makefile for the Alchemy Semiconductor DBAu1xx0 boards.
6# 6#
7 7
8obj-y := board_setup.o irqmap.o 8obj-y := board_setup.o platform.o
diff --git a/arch/mips/alchemy/devboards/db1x00/board_setup.c b/arch/mips/alchemy/devboards/db1x00/board_setup.c
index de30d8ea7176..50c9bef99daa 100644
--- a/arch/mips/alchemy/devboards/db1x00/board_setup.c
+++ b/arch/mips/alchemy/devboards/db1x00/board_setup.c
@@ -29,59 +29,139 @@
29 29
30#include <linux/gpio.h> 30#include <linux/gpio.h>
31#include <linux/init.h> 31#include <linux/init.h>
32#include <linux/interrupt.h>
33#include <linux/pm.h>
32 34
33#include <asm/mach-au1x00/au1000.h> 35#include <asm/mach-au1x00/au1000.h>
36#include <asm/mach-au1x00/au1xxx_eth.h>
34#include <asm/mach-db1x00/db1x00.h> 37#include <asm/mach-db1x00/db1x00.h>
38#include <asm/mach-db1x00/bcsr.h>
39#include <asm/reboot.h>
35 40
36#include <prom.h> 41#include <prom.h>
37 42
43#ifdef CONFIG_MIPS_DB1500
44char irq_tab_alchemy[][5] __initdata = {
45 [12] = { -1, AU1500_PCI_INTA, 0xff, 0xff, 0xff }, /* IDSEL 12 - HPT371 */
46 [13] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, AU1500_PCI_INTC, AU1500_PCI_INTD }, /* IDSEL 13 - PCI slot */
47};
48
49#endif
38 50
39static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR; 51
52#ifdef CONFIG_MIPS_DB1550
53char irq_tab_alchemy[][5] __initdata = {
54 [11] = { -1, AU1550_PCI_INTC, 0xff, 0xff, 0xff }, /* IDSEL 11 - on-board HPT371 */
55 [12] = { -1, AU1550_PCI_INTB, AU1550_PCI_INTC, AU1550_PCI_INTD, AU1550_PCI_INTA }, /* IDSEL 12 - PCI slot 2 (left) */
56 [13] = { -1, AU1550_PCI_INTA, AU1550_PCI_INTB, AU1550_PCI_INTC, AU1550_PCI_INTD }, /* IDSEL 13 - PCI slot 1 (right) */
57};
58#endif
59
60
61#ifdef CONFIG_MIPS_BOSPORUS
62char irq_tab_alchemy[][5] __initdata = {
63 [11] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, /* IDSEL 11 - miniPCI */
64 [12] = { -1, AU1500_PCI_INTA, 0xff, 0xff, 0xff }, /* IDSEL 12 - SN1741 */
65 [13] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, AU1500_PCI_INTC, AU1500_PCI_INTD }, /* IDSEL 13 - PCI slot */
66};
67
68/*
69 * Micrel/Kendin 5 port switch attached to MAC0,
70 * MAC0 is associated with PHY address 5 (== WAN port)
71 * MAC1 is not associated with any PHY, since it's connected directly
72 * to the switch.
73 * no interrupts are used
74 */
75static struct au1000_eth_platform_data eth0_pdata = {
76 .phy_static_config = 1,
77 .phy_addr = 5,
78};
79
80static void bosporus_power_off(void)
81{
82 printk(KERN_INFO "It's now safe to turn off power\n");
83 while (1)
84 asm volatile (".set mips3 ; wait ; .set mips0");
85}
40 86
41const char *get_system_type(void) 87const char *get_system_type(void)
42{ 88{
43#ifdef CONFIG_MIPS_BOSPORUS
44 return "Alchemy Bosporus Gateway Reference"; 89 return "Alchemy Bosporus Gateway Reference";
45#else 90}
46 return "Alchemy Db1x00";
47#endif 91#endif
92
93
94#ifdef CONFIG_MIPS_MIRAGE
95char irq_tab_alchemy[][5] __initdata = {
96 [11] = { -1, AU1500_PCI_INTD, 0xff, 0xff, 0xff }, /* IDSEL 11 - SMI VGX */
97 [12] = { -1, 0xff, 0xff, AU1500_PCI_INTC, 0xff }, /* IDSEL 12 - PNX1300 */
98 [13] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, /* IDSEL 13 - miniPCI */
99};
100
101static void mirage_power_off(void)
102{
103 alchemy_gpio_direction_output(210, 1);
104}
105
106const char *get_system_type(void)
107{
108 return "Alchemy Mirage";
109}
110#endif
111
112
113#if defined(CONFIG_MIPS_BOSPORUS) || defined(CONFIG_MIPS_MIRAGE)
114static void mips_softreset(void)
115{
116 asm volatile ("jr\t%0" : : "r"(0xbfc00000));
48} 117}
49 118
50void board_reset(void) 119#else
120
121const char *get_system_type(void)
51{ 122{
52 /* Hit BCSR.SW_RESET[RESET] */ 123 return "Alchemy Db1x00";
53 bcsr->swreset = 0x0000;
54} 124}
125#endif
126
55 127
56void __init board_setup(void) 128void __init board_setup(void)
57{ 129{
58 u32 pin_func = 0; 130 unsigned long bcsr1, bcsr2;
59 char *argptr; 131 u32 pin_func;
60 132
61 argptr = prom_getcmdline(); 133 bcsr1 = DB1000_BCSR_PHYS_ADDR;
62#ifdef CONFIG_SERIAL_8250_CONSOLE 134 bcsr2 = DB1000_BCSR_PHYS_ADDR + DB1000_BCSR_HEXLED_OFS;
63 argptr = strstr(argptr, "console="); 135
64 if (argptr == NULL) { 136 pin_func = 0;
65 argptr = prom_getcmdline(); 137
66 strcat(argptr, " console=ttyS0,115200"); 138#ifdef CONFIG_MIPS_DB1000
67 } 139 printk(KERN_INFO "AMD Alchemy Au1000/Db1000 Board\n");
140#endif
141#ifdef CONFIG_MIPS_DB1500
142 printk(KERN_INFO "AMD Alchemy Au1500/Db1500 Board\n");
68#endif 143#endif
144#ifdef CONFIG_MIPS_DB1100
145 printk(KERN_INFO "AMD Alchemy Au1100/Db1100 Board\n");
146#endif
147#ifdef CONFIG_MIPS_BOSPORUS
148 au1xxx_override_eth_cfg(0, &eth0_pdata);
69 149
70#ifdef CONFIG_FB_AU1100 150 printk(KERN_INFO "AMD Alchemy Bosporus Board\n");
71 argptr = strstr(argptr, "video=");
72 if (argptr == NULL) {
73 argptr = prom_getcmdline();
74 /* default panel */
75 /*strcat(argptr, " video=au1100fb:panel:Sharp_320x240_16");*/
76 }
77#endif 151#endif
152#ifdef CONFIG_MIPS_MIRAGE
153 printk(KERN_INFO "AMD Alchemy Mirage Board\n");
154#endif
155#ifdef CONFIG_MIPS_DB1550
156 printk(KERN_INFO "AMD Alchemy Au1550/Db1550 Board\n");
78 157
79#if defined(CONFIG_SOUND_AU1X00) && !defined(CONFIG_SOC_AU1000) 158 bcsr1 = DB1550_BCSR_PHYS_ADDR;
80 /* au1000 does not support vra, au1500 and au1100 do */ 159 bcsr2 = DB1550_BCSR_PHYS_ADDR + DB1550_BCSR_HEXLED_OFS;
81 strcat(argptr, " au1000_audio=vra");
82 argptr = prom_getcmdline();
83#endif 160#endif
84 161
162 /* initialize board register space */
163 bcsr_init(bcsr1, bcsr2);
164
85 /* Not valid for Au1550 */ 165 /* Not valid for Au1550 */
86#if defined(CONFIG_IRDA) && \ 166#if defined(CONFIG_IRDA) && \
87 (defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1100)) 167 (defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1100))
@@ -89,11 +169,10 @@ void __init board_setup(void)
89 pin_func = au_readl(SYS_PINFUNC) | SYS_PF_IRF; 169 pin_func = au_readl(SYS_PINFUNC) | SYS_PF_IRF;
90 au_writel(pin_func, SYS_PINFUNC); 170 au_writel(pin_func, SYS_PINFUNC);
91 /* Power off until the driver is in use */ 171 /* Power off until the driver is in use */
92 bcsr->resets &= ~BCSR_RESETS_IRDA_MODE_MASK; 172 bcsr_mod(BCSR_RESETS, BCSR_RESETS_IRDA_MODE_MASK,
93 bcsr->resets |= BCSR_RESETS_IRDA_MODE_OFF; 173 BCSR_RESETS_IRDA_MODE_OFF);
94 au_sync();
95#endif 174#endif
96 bcsr->pcmcia = 0x0000; /* turn off PCMCIA power */ 175 bcsr_write(BCSR_PCMCIA, 0); /* turn off PCMCIA power */
97 176
98 /* Enable GPIO[31:0] inputs */ 177 /* Enable GPIO[31:0] inputs */
99 alchemy_gpio1_input_enable(); 178 alchemy_gpio1_input_enable();
@@ -120,26 +199,53 @@ void __init board_setup(void)
120 * be part of the audio driver. 199 * be part of the audio driver.
121 */ 200 */
122 alchemy_gpio_direction_output(209, 1); 201 alchemy_gpio_direction_output(209, 1);
123#endif
124
125 au_sync();
126 202
127#ifdef CONFIG_MIPS_DB1000 203 pm_power_off = mirage_power_off;
128 printk(KERN_INFO "AMD Alchemy Au1000/Db1000 Board\n"); 204 _machine_halt = mirage_power_off;
129#endif 205 _machine_restart = (void(*)(char *))mips_softreset;
130#ifdef CONFIG_MIPS_DB1500
131 printk(KERN_INFO "AMD Alchemy Au1500/Db1500 Board\n");
132#endif
133#ifdef CONFIG_MIPS_DB1100
134 printk(KERN_INFO "AMD Alchemy Au1100/Db1100 Board\n");
135#endif 206#endif
207
136#ifdef CONFIG_MIPS_BOSPORUS 208#ifdef CONFIG_MIPS_BOSPORUS
137 printk(KERN_INFO "AMD Alchemy Bosporus Board\n"); 209 pm_power_off = bosporus_power_off;
210 _machine_halt = bosporus_power_off;
211 _machine_restart = (void(*)(char *))mips_softreset;
138#endif 212#endif
139#ifdef CONFIG_MIPS_MIRAGE 213 au_sync();
140 printk(KERN_INFO "AMD Alchemy Mirage Board\n"); 214}
141#endif 215
142#ifdef CONFIG_MIPS_DB1550 216static int __init db1x00_init_irq(void)
143 printk(KERN_INFO "AMD Alchemy Au1550/Db1550 Board\n"); 217{
218#if defined(CONFIG_MIPS_MIRAGE)
219 set_irq_type(AU1500_GPIO7_INT, IRQF_TRIGGER_RISING); /* TS pendown */
220#elif defined(CONFIG_MIPS_DB1550)
221 set_irq_type(AU1550_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
222 set_irq_type(AU1550_GPIO1_INT, IRQF_TRIGGER_LOW); /* CD1# */
223 set_irq_type(AU1550_GPIO3_INT, IRQF_TRIGGER_LOW); /* CARD0# */
224 set_irq_type(AU1550_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
225 set_irq_type(AU1550_GPIO21_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
226 set_irq_type(AU1550_GPIO22_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
227#elif defined(CONFIG_MIPS_DB1500)
228 set_irq_type(AU1500_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
229 set_irq_type(AU1500_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */
230 set_irq_type(AU1500_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */
231 set_irq_type(AU1500_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
232 set_irq_type(AU1500_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
233 set_irq_type(AU1500_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
234#elif defined(CONFIG_MIPS_DB1100)
235 set_irq_type(AU1100_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
236 set_irq_type(AU1100_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */
237 set_irq_type(AU1100_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */
238 set_irq_type(AU1100_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
239 set_irq_type(AU1100_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
240 set_irq_type(AU1100_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
241#elif defined(CONFIG_MIPS_DB1000)
242 set_irq_type(AU1000_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
243 set_irq_type(AU1000_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */
244 set_irq_type(AU1000_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */
245 set_irq_type(AU1000_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
246 set_irq_type(AU1000_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
247 set_irq_type(AU1000_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
144#endif 248#endif
249 return 0;
145} 250}
251arch_initcall(db1x00_init_irq);
diff --git a/arch/mips/alchemy/devboards/db1x00/irqmap.c b/arch/mips/alchemy/devboards/db1x00/irqmap.c
deleted file mode 100644
index 0b09025087c6..000000000000
--- a/arch/mips/alchemy/devboards/db1x00/irqmap.c
+++ /dev/null
@@ -1,90 +0,0 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * Au1xxx irq map table
4 *
5 * Copyright 2003 Embedded Edge, LLC
6 * dan@embeddededge.com
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
16 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
19 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
20 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 *
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 675 Mass Ave, Cambridge, MA 02139, USA.
27 */
28
29#include <linux/init.h>
30#include <linux/interrupt.h>
31
32#include <asm/mach-au1x00/au1000.h>
33
34#ifdef CONFIG_MIPS_DB1500
35char irq_tab_alchemy[][5] __initdata = {
36 [12] = { -1, INTA, INTX, INTX, INTX }, /* IDSEL 12 - HPT371 */
37 [13] = { -1, INTA, INTB, INTC, INTD }, /* IDSEL 13 - PCI slot */
38};
39#endif
40
41#ifdef CONFIG_MIPS_BOSPORUS
42char irq_tab_alchemy[][5] __initdata = {
43 [11] = { -1, INTA, INTB, INTX, INTX }, /* IDSEL 11 - miniPCI */
44 [12] = { -1, INTA, INTX, INTX, INTX }, /* IDSEL 12 - SN1741 */
45 [13] = { -1, INTA, INTB, INTC, INTD }, /* IDSEL 13 - PCI slot */
46};
47#endif
48
49#ifdef CONFIG_MIPS_MIRAGE
50char irq_tab_alchemy[][5] __initdata = {
51 [11] = { -1, INTD, INTX, INTX, INTX }, /* IDSEL 11 - SMI VGX */
52 [12] = { -1, INTX, INTX, INTC, INTX }, /* IDSEL 12 - PNX1300 */
53 [13] = { -1, INTA, INTB, INTX, INTX }, /* IDSEL 13 - miniPCI */
54};
55#endif
56
57#ifdef CONFIG_MIPS_DB1550
58char irq_tab_alchemy[][5] __initdata = {
59 [11] = { -1, INTC, INTX, INTX, INTX }, /* IDSEL 11 - on-board HPT371 */
60 [12] = { -1, INTB, INTC, INTD, INTA }, /* IDSEL 12 - PCI slot 2 (left) */
61 [13] = { -1, INTA, INTB, INTC, INTD }, /* IDSEL 13 - PCI slot 1 (right) */
62};
63#endif
64
65
66struct au1xxx_irqmap __initdata au1xxx_irq_map[] = {
67
68#ifndef CONFIG_MIPS_MIRAGE
69#ifdef CONFIG_MIPS_DB1550
70 { AU1000_GPIO_3, IRQF_TRIGGER_LOW, 0 }, /* PCMCIA Card 0 IRQ# */
71 { AU1000_GPIO_5, IRQF_TRIGGER_LOW, 0 }, /* PCMCIA Card 1 IRQ# */
72#else
73 { AU1000_GPIO_0, IRQF_TRIGGER_LOW, 0 }, /* PCMCIA Card 0 Fully_Interted# */
74 { AU1000_GPIO_1, IRQF_TRIGGER_LOW, 0 }, /* PCMCIA Card 0 STSCHG# */
75 { AU1000_GPIO_2, IRQF_TRIGGER_LOW, 0 }, /* PCMCIA Card 0 IRQ# */
76
77 { AU1000_GPIO_3, IRQF_TRIGGER_LOW, 0 }, /* PCMCIA Card 1 Fully_Interted# */
78 { AU1000_GPIO_4, IRQF_TRIGGER_LOW, 0 }, /* PCMCIA Card 1 STSCHG# */
79 { AU1000_GPIO_5, IRQF_TRIGGER_LOW, 0 }, /* PCMCIA Card 1 IRQ# */
80#endif
81#else
82 { AU1000_GPIO_7, IRQF_TRIGGER_RISING, 0 }, /* touchscreen pen down */
83#endif
84
85};
86
87void __init board_init_irq(void)
88{
89 au1xxx_setup_irqmap(au1xxx_irq_map, ARRAY_SIZE(au1xxx_irq_map));
90}
diff --git a/arch/mips/alchemy/devboards/db1x00/platform.c b/arch/mips/alchemy/devboards/db1x00/platform.c
new file mode 100644
index 000000000000..978d5ab3d678
--- /dev/null
+++ b/arch/mips/alchemy/devboards/db1x00/platform.c
@@ -0,0 +1,118 @@
1/*
2 * DBAu1xxx board platform device registration
3 *
4 * Copyright (C) 2009 Manuel Lauss
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include <linux/init.h>
22#include <linux/platform_device.h>
23
24#include <asm/mach-au1x00/au1xxx.h>
25#include <asm/mach-db1x00/bcsr.h>
26#include "../platform.h"
27
28/* DB1xxx PCMCIA interrupt sources:
29 * CD0/1 GPIO0/3
30 * STSCHG0/1 GPIO1/4
31 * CARD0/1 GPIO2/5
32 * Db1550: 0/1, 21/22, 3/5
33 */
34
35#define DB1XXX_HAS_PCMCIA
36#define F_SWAPPED (bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT)
37
38#if defined(CONFIG_MIPS_DB1000)
39#define DB1XXX_PCMCIA_CD0 AU1000_GPIO0_INT
40#define DB1XXX_PCMCIA_STSCHG0 AU1000_GPIO1_INT
41#define DB1XXX_PCMCIA_CARD0 AU1000_GPIO2_INT
42#define DB1XXX_PCMCIA_CD1 AU1000_GPIO3_INT
43#define DB1XXX_PCMCIA_STSCHG1 AU1000_GPIO4_INT
44#define DB1XXX_PCMCIA_CARD1 AU1000_GPIO5_INT
45#define BOARD_FLASH_SIZE 0x02000000 /* 32MB */
46#define BOARD_FLASH_WIDTH 4 /* 32-bits */
47#elif defined(CONFIG_MIPS_DB1100)
48#define DB1XXX_PCMCIA_CD0 AU1100_GPIO0_INT
49#define DB1XXX_PCMCIA_STSCHG0 AU1100_GPIO1_INT
50#define DB1XXX_PCMCIA_CARD0 AU1100_GPIO2_INT
51#define DB1XXX_PCMCIA_CD1 AU1100_GPIO3_INT
52#define DB1XXX_PCMCIA_STSCHG1 AU1100_GPIO4_INT
53#define DB1XXX_PCMCIA_CARD1 AU1100_GPIO5_INT
54#define BOARD_FLASH_SIZE 0x02000000 /* 32MB */
55#define BOARD_FLASH_WIDTH 4 /* 32-bits */
56#elif defined(CONFIG_MIPS_DB1500)
57#define DB1XXX_PCMCIA_CD0 AU1500_GPIO0_INT
58#define DB1XXX_PCMCIA_STSCHG0 AU1500_GPIO1_INT
59#define DB1XXX_PCMCIA_CARD0 AU1500_GPIO2_INT
60#define DB1XXX_PCMCIA_CD1 AU1500_GPIO3_INT
61#define DB1XXX_PCMCIA_STSCHG1 AU1500_GPIO4_INT
62#define DB1XXX_PCMCIA_CARD1 AU1500_GPIO5_INT
63#define BOARD_FLASH_SIZE 0x02000000 /* 32MB */
64#define BOARD_FLASH_WIDTH 4 /* 32-bits */
65#elif defined(CONFIG_MIPS_DB1550)
66#define DB1XXX_PCMCIA_CD0 AU1550_GPIO0_INT
67#define DB1XXX_PCMCIA_STSCHG0 AU1550_GPIO21_INT
68#define DB1XXX_PCMCIA_CARD0 AU1550_GPIO3_INT
69#define DB1XXX_PCMCIA_CD1 AU1550_GPIO1_INT
70#define DB1XXX_PCMCIA_STSCHG1 AU1550_GPIO22_INT
71#define DB1XXX_PCMCIA_CARD1 AU1550_GPIO5_INT
72#define BOARD_FLASH_SIZE 0x08000000 /* 128MB */
73#define BOARD_FLASH_WIDTH 4 /* 32-bits */
74#else
75/* other board: no PCMCIA */
76#undef DB1XXX_HAS_PCMCIA
77#undef F_SWAPPED
78#define F_SWAPPED 0
79#if defined(CONFIG_MIPS_BOSPORUS)
80#define BOARD_FLASH_SIZE 0x01000000 /* 16MB */
81#define BOARD_FLASH_WIDTH 2 /* 16-bits */
82#elif defined(CONFIG_MIPS_MIRAGE)
83#define BOARD_FLASH_SIZE 0x04000000 /* 64MB */
84#define BOARD_FLASH_WIDTH 4 /* 32-bits */
85#endif
86#endif
87
88static int __init db1xxx_dev_init(void)
89{
90#ifdef DB1XXX_HAS_PCMCIA
91 db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR,
92 PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
93 PCMCIA_MEM_PHYS_ADDR,
94 PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
95 PCMCIA_IO_PHYS_ADDR,
96 PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
97 DB1XXX_PCMCIA_CARD0,
98 DB1XXX_PCMCIA_CD0,
99 /*DB1XXX_PCMCIA_STSCHG0*/0,
100 0,
101 0);
102
103 db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR + 0x004000000,
104 PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1,
105 PCMCIA_MEM_PHYS_ADDR + 0x004000000,
106 PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1,
107 PCMCIA_IO_PHYS_ADDR + 0x004000000,
108 PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1,
109 DB1XXX_PCMCIA_CARD1,
110 DB1XXX_PCMCIA_CD1,
111 /*DB1XXX_PCMCIA_STSCHG1*/0,
112 0,
113 1);
114#endif
115 db1x_register_norflash(BOARD_FLASH_SIZE, BOARD_FLASH_WIDTH, F_SWAPPED);
116 return 0;
117}
118device_initcall(db1xxx_dev_init);
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-31 19:28:07 -0500