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-rw-r--r--arch/mips/alchemy/devboards/db1200/setup.c50
1 files changed, 7 insertions, 43 deletions
diff --git a/arch/mips/alchemy/devboards/db1200/setup.c b/arch/mips/alchemy/devboards/db1200/setup.c
index 379536e3abd1..887619547553 100644
--- a/arch/mips/alchemy/devboards/db1200/setup.c
+++ b/arch/mips/alchemy/devboards/db1200/setup.c
@@ -60,58 +60,22 @@ void __init board_setup(void)
60 wmb(); 60 wmb();
61} 61}
62 62
63/* use the hexleds to count the number of times the cpu has entered
64 * wait, the dots to indicate whether the CPU is currently idle or
65 * active (dots off = sleeping, dots on = working) for cases where
66 * the number doesn't change for a long(er) period of time.
67 */
68static void db1200_wait(void)
69{
70 __asm__(" .set push \n"
71 " .set mips3 \n"
72 " .set noreorder \n"
73 " cache 0x14, 0(%0) \n"
74 " cache 0x14, 32(%0) \n"
75 " cache 0x14, 64(%0) \n"
76 /* dots off: we're about to call wait */
77 " lui $26, 0xb980 \n"
78 " ori $27, $0, 3 \n"
79 " sb $27, 0x18($26) \n"
80 " sync \n"
81 " nop \n"
82 " wait \n"
83 " nop \n"
84 " nop \n"
85 " nop \n"
86 " nop \n"
87 " nop \n"
88 /* dots on: there's work to do, increment cntr */
89 " lui $26, 0xb980 \n"
90 " sb $0, 0x18($26) \n"
91 " lui $26, 0xb9c0 \n"
92 " lb $27, 0($26) \n"
93 " addiu $27, $27, 1 \n"
94 " sb $27, 0($26) \n"
95 " sync \n"
96 " .set pop \n"
97 : : "r" (db1200_wait));
98}
99
100static int __init db1200_arch_init(void) 63static int __init db1200_arch_init(void)
101{ 64{
102 /* GPIO7 is low-level triggered CPLD cascade */ 65 /* GPIO7 is low-level triggered CPLD cascade */
103 set_irq_type(AU1200_GPIO7_INT, IRQF_TRIGGER_LOW); 66 set_irq_type(AU1200_GPIO7_INT, IRQF_TRIGGER_LOW);
104 bcsr_init_irq(DB1200_INT_BEGIN, DB1200_INT_END, AU1200_GPIO7_INT); 67 bcsr_init_irq(DB1200_INT_BEGIN, DB1200_INT_END, AU1200_GPIO7_INT);
105 68
106 /* do not autoenable these: CPLD has broken edge int handling, 69 /* insert/eject pairs: one of both is always screaming. To avoid
107 * and the CD handler setup requires manual enabling to work 70 * issues they must not be automatically enabled when initially
108 * around that. 71 * requested.
109 */ 72 */
110 irq_to_desc(DB1200_SD0_INSERT_INT)->status |= IRQ_NOAUTOEN; 73 irq_to_desc(DB1200_SD0_INSERT_INT)->status |= IRQ_NOAUTOEN;
111 irq_to_desc(DB1200_SD0_EJECT_INT)->status |= IRQ_NOAUTOEN; 74 irq_to_desc(DB1200_SD0_EJECT_INT)->status |= IRQ_NOAUTOEN;
112 75 irq_to_desc(DB1200_PC0_INSERT_INT)->status |= IRQ_NOAUTOEN;
113 if (cpu_wait) 76 irq_to_desc(DB1200_PC0_EJECT_INT)->status |= IRQ_NOAUTOEN;
114 cpu_wait = db1200_wait; 77 irq_to_desc(DB1200_PC1_INSERT_INT)->status |= IRQ_NOAUTOEN;
78 irq_to_desc(DB1200_PC1_EJECT_INT)->status |= IRQ_NOAUTOEN;
115 79
116 return 0; 80 return 0;
117} 81}