1 files changed, 68 insertions, 50 deletions

diff --git a/arch/mips/alchemy/common/sleeper.S b/arch/mips/alchemy/common/sleeper.S
index 3006e270c8bc..4f4b16741d12 100644
--- a/arch/mips/alchemy/common/sleeper.S
+++ b/arch/mips/alchemy/common/sleeper.S
@@ -15,16 +15,17 @@
 #include <asm/regdef.h>
 #include <asm/stackframe.h>
 
+        .extern __flush_cache_all
+
         .text
-        .set    macro
-        .set    noat
+        .set noreorder
+        .set noat
         .align  5
 
 /* Save all of the processor general registers and go to sleep.
  * A wakeup condition will get us back here to restore the registers.
  */
-LEAF(save_and_sleep)
-
+LEAF(au1xxx_save_and_sleep)
         subu    sp, PT_SIZE
         sw      $1, PT_R1(sp)
         sw      $2, PT_R2(sp)
@@ -33,14 +34,6 @@ LEAF(save_and_sleep)
         sw      $5, PT_R5(sp)
         sw      $6, PT_R6(sp)
         sw      $7, PT_R7(sp)
-        sw      $8, PT_R8(sp)
-        sw      $9, PT_R9(sp)
-        sw      $10, PT_R10(sp)
-        sw      $11, PT_R11(sp)
-        sw      $12, PT_R12(sp)
-        sw      $13, PT_R13(sp)
-        sw      $14, PT_R14(sp)
-        sw      $15, PT_R15(sp)
         sw      $16, PT_R16(sp)
         sw      $17, PT_R17(sp)
         sw      $18, PT_R18(sp)
@@ -49,12 +42,9 @@ LEAF(save_and_sleep)
         sw      $21, PT_R21(sp)
         sw      $22, PT_R22(sp)
         sw      $23, PT_R23(sp)
-        sw      $24, PT_R24(sp)
-        sw      $25, PT_R25(sp)
         sw      $26, PT_R26(sp)
         sw      $27, PT_R27(sp)
         sw      $28, PT_R28(sp)
-        sw      $29, PT_R29(sp)
         sw      $30, PT_R30(sp)
         sw      $31, PT_R31(sp)
         mfc0    k0, CP0_STATUS
@@ -66,20 +56,26 @@ LEAF(save_and_sleep)
         mfc0    k0, CP0_CONFIG
         sw      k0, 0x14(sp)
 
+        /* flush caches to make sure context is in memory */
+        la      t1, __flush_cache_all
+        lw      t0, 0(t1)
+        jalr    t0
+         nop
+
         /* Now set up the scratch registers so the boot rom will
          * return to this point upon wakeup.
+         * sys_scratch0 : SP
+         * sys_scratch1 : RA
          */
-        la      k0, 1f
-        lui     k1, 0xb190
-        ori     k1, 0x18
-        sw      sp, 0(k1)
-        ori     k1, 0x1c
-        sw      k0, 0(k1)
+        lui     t3, 0xb190              /* sys_xxx */
+        sw      sp, 0x0018(t3)
+        la      k0, 3f                  /* resume path */
+        sw      k0, 0x001c(t3)
 
-/* Put SDRAM into self refresh.  Preload instructions into cache,
- * issue a precharge, then auto refresh, then sleep commands to it.
- */
-        la      t0, sdsleep
+        /* Put SDRAM into self refresh:  Preload instructions into cache,
+         * issue a precharge, auto/self refresh, then sleep commands to it.
+         */
+        la      t0, 1f
         .set    mips3
         cache   0x14, 0(t0)
         cache   0x14, 32(t0)
@@ -87,24 +83,57 @@ LEAF(save_and_sleep)
         cache   0x14, 96(t0)
         .set    mips0
 
-sdsleep:
-        lui     k0, 0xb400
-        sw      zero, 0x001c(k0)        /* Precharge */
-        sw      zero, 0x0020(k0)        /* Auto refresh */
-        sw      zero, 0x0030(k0)        /* SDRAM sleep */
+1:      lui     a0, 0xb400              /* mem_xxx */
+#if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1100) || \
+    defined(CONFIG_SOC_AU1500)
+        sw      zero, 0x001c(a0)        /* Precharge */
+        sync
+        sw      zero, 0x0020(a0)        /* Auto Refresh */
+        sync
+        sw      zero, 0x0030(a0)        /* Sleep */
+        sync
+#endif
+
+#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
+        sw      zero, 0x08c0(a0)        /* Precharge */
         sync
+        sw      zero, 0x08d0(a0)        /* Self Refresh */
+        sync
+
+        /* wait for sdram to enter self-refresh mode */
+        lui     t0, 0x0100
+2:      lw      t1, 0x0850(a0)          /* mem_sdstat */
+        and     t2, t1, t0
+        beq     t2, zero, 2b
+         nop
 
-        lui     k1, 0xb190
-        sw      zero, 0x0078(k1)        /* get ready  to sleep */
+        /* disable SDRAM clocks */
+        lui     t0, 0xcfff
+        ori     t0, t0, 0xffff
+        lw      t1, 0x0840(a0)          /* mem_sdconfiga */
+        and     t1, t0, t1              /* clear CE[1:0] */
+        sw      t1, 0x0840(a0)          /* mem_sdconfiga */
         sync
-        sw      zero, 0x007c(k1)        /* Put processor to sleep */
+#endif
+
+        /* put power supply and processor to sleep */
+        sw      zero, 0x0078(t3)        /* sys_slppwr */
+        sync
+        sw      zero, 0x007c(t3)        /* sys_sleep */
         sync
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
 
         /* This is where we return upon wakeup.
          * Reload all of the registers and return.
          */
-1:      nop
-        lw      k0, 0x20(sp)
+3:      lw      k0, 0x20(sp)
         mtc0    k0, CP0_STATUS
         lw      k0, 0x1c(sp)
         mtc0    k0, CP0_CONTEXT
@@ -113,10 +142,11 @@ sdsleep:
         lw      k0, 0x14(sp)
         mtc0    k0, CP0_CONFIG
 
-        /* We need to catch the ealry Alchemy SOCs with
+        /* We need to catch the early Alchemy SOCs with
          * the write-only Config[OD] bit and set it back to one...
          */
         jal     au1x00_fixup_config_od
+         nop
         lw      $1, PT_R1(sp)
         lw      $2, PT_R2(sp)
         lw      $3, PT_R3(sp)
@@ -124,14 +154,6 @@ sdsleep:
         lw      $5, PT_R5(sp)
         lw      $6, PT_R6(sp)
         lw      $7, PT_R7(sp)
-        lw      $8, PT_R8(sp)
-        lw      $9, PT_R9(sp)
-        lw      $10, PT_R10(sp)
-        lw      $11, PT_R11(sp)
-        lw      $12, PT_R12(sp)
-        lw      $13, PT_R13(sp)
-        lw      $14, PT_R14(sp)
-        lw      $15, PT_R15(sp)
         lw      $16, PT_R16(sp)
         lw      $17, PT_R17(sp)
         lw      $18, PT_R18(sp)
@@ -140,15 +162,11 @@ sdsleep:
         lw      $21, PT_R21(sp)
         lw      $22, PT_R22(sp)
         lw      $23, PT_R23(sp)
-        lw      $24, PT_R24(sp)
-        lw      $25, PT_R25(sp)
         lw      $26, PT_R26(sp)
         lw      $27, PT_R27(sp)
         lw      $28, PT_R28(sp)
-        lw      $29, PT_R29(sp)
         lw      $30, PT_R30(sp)
         lw      $31, PT_R31(sp)
-        addiu   sp, PT_SIZE
-
         jr      ra
-END(save_and_sleep)
+         addiu  sp, PT_SIZE
+END(au1xxx_save_and_sleep)