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-rw-r--r--arch/mips/alchemy/common/irq.c11
1 files changed, 0 insertions, 11 deletions
diff --git a/arch/mips/alchemy/common/irq.c b/arch/mips/alchemy/common/irq.c
index 8b60ba0675e2..2a94a64b7333 100644
--- a/arch/mips/alchemy/common/irq.c
+++ b/arch/mips/alchemy/common/irq.c
@@ -35,9 +35,6 @@
35#include <asm/irq_cpu.h> 35#include <asm/irq_cpu.h>
36#include <asm/mipsregs.h> 36#include <asm/mipsregs.h>
37#include <asm/mach-au1x00/au1000.h> 37#include <asm/mach-au1x00/au1000.h>
38#ifdef CONFIG_MIPS_PB1000
39#include <asm/mach-pb1x00/pb1000.h>
40#endif
41 38
42/* Interrupt Controller register offsets */ 39/* Interrupt Controller register offsets */
43#define IC_CFG0RD 0x40 40#define IC_CFG0RD 0x40
@@ -265,14 +262,6 @@ static void au1x_ic1_unmask(struct irq_data *d)
265 262
266 __raw_writel(1 << bit, base + IC_MASKSET); 263 __raw_writel(1 << bit, base + IC_MASKSET);
267 __raw_writel(1 << bit, base + IC_WAKESET); 264 __raw_writel(1 << bit, base + IC_WAKESET);
268
269/* very hacky. does the pb1000 cpld auto-disable this int?
270 * nowhere in the current kernel sources is it disabled. --mlau
271 */
272#if defined(CONFIG_MIPS_PB1000)
273 if (d->irq == AU1000_GPIO15_INT)
274 __raw_writel(0x4000, (void __iomem *)PB1000_MDR); /* enable int */
275#endif
276 wmb(); 265 wmb();
277} 266}
278 267