diff options
Diffstat (limited to 'arch/mips/Kconfig')
-rw-r--r-- | arch/mips/Kconfig | 71 |
1 files changed, 69 insertions, 2 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index a5255e7c79e0..52c80c2a57f2 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig | |||
@@ -595,6 +595,44 @@ config WR_PPMC | |||
595 | This enables support for the Wind River MIPS32 4KC PPMC evaluation | 595 | This enables support for the Wind River MIPS32 4KC PPMC evaluation |
596 | board, which is based on GT64120 bridge chip. | 596 | board, which is based on GT64120 bridge chip. |
597 | 597 | ||
598 | config CAVIUM_OCTEON_SIMULATOR | ||
599 | bool "Support for the Cavium Networks Octeon Simulator" | ||
600 | select CEVT_R4K | ||
601 | select 64BIT_PHYS_ADDR | ||
602 | select DMA_COHERENT | ||
603 | select SYS_SUPPORTS_64BIT_KERNEL | ||
604 | select SYS_SUPPORTS_BIG_ENDIAN | ||
605 | select SYS_SUPPORTS_HIGHMEM | ||
606 | select CPU_CAVIUM_OCTEON | ||
607 | help | ||
608 | The Octeon simulator is software performance model of the Cavium | ||
609 | Octeon Processor. It supports simulating Octeon processors on x86 | ||
610 | hardware. | ||
611 | |||
612 | config CAVIUM_OCTEON_REFERENCE_BOARD | ||
613 | bool "Support for the Cavium Networks Octeon reference board" | ||
614 | select CEVT_R4K | ||
615 | select 64BIT_PHYS_ADDR | ||
616 | select DMA_COHERENT | ||
617 | select SYS_SUPPORTS_64BIT_KERNEL | ||
618 | select SYS_SUPPORTS_BIG_ENDIAN | ||
619 | select SYS_SUPPORTS_HIGHMEM | ||
620 | select SYS_HAS_EARLY_PRINTK | ||
621 | select CPU_CAVIUM_OCTEON | ||
622 | select SWAP_IO_SPACE | ||
623 | help | ||
624 | This option supports all of the Octeon reference boards from Cavium | ||
625 | Networks. It builds a kernel that dynamically determines the Octeon | ||
626 | CPU type and supports all known board reference implementations. | ||
627 | Some of the supported boards are: | ||
628 | EBT3000 | ||
629 | EBH3000 | ||
630 | EBH3100 | ||
631 | Thunder | ||
632 | Kodama | ||
633 | Hikari | ||
634 | Say Y here for most Octeon reference boards. | ||
635 | |||
598 | endchoice | 636 | endchoice |
599 | 637 | ||
600 | source "arch/mips/alchemy/Kconfig" | 638 | source "arch/mips/alchemy/Kconfig" |
@@ -607,6 +645,7 @@ source "arch/mips/sgi-ip27/Kconfig" | |||
607 | source "arch/mips/sibyte/Kconfig" | 645 | source "arch/mips/sibyte/Kconfig" |
608 | source "arch/mips/txx9/Kconfig" | 646 | source "arch/mips/txx9/Kconfig" |
609 | source "arch/mips/vr41xx/Kconfig" | 647 | source "arch/mips/vr41xx/Kconfig" |
648 | source "arch/mips/cavium-octeon/Kconfig" | ||
610 | 649 | ||
611 | endmenu | 650 | endmenu |
612 | 651 | ||
@@ -682,7 +721,11 @@ config CEVT_DS1287 | |||
682 | config CEVT_GT641XX | 721 | config CEVT_GT641XX |
683 | bool | 722 | bool |
684 | 723 | ||
724 | config CEVT_R4K_LIB | ||
725 | bool | ||
726 | |||
685 | config CEVT_R4K | 727 | config CEVT_R4K |
728 | select CEVT_R4K_LIB | ||
686 | bool | 729 | bool |
687 | 730 | ||
688 | config CEVT_SB1250 | 731 | config CEVT_SB1250 |
@@ -697,7 +740,11 @@ config CSRC_BCM1480 | |||
697 | config CSRC_IOASIC | 740 | config CSRC_IOASIC |
698 | bool | 741 | bool |
699 | 742 | ||
743 | config CSRC_R4K_LIB | ||
744 | bool | ||
745 | |||
700 | config CSRC_R4K | 746 | config CSRC_R4K |
747 | select CSRC_R4K_LIB | ||
701 | bool | 748 | bool |
702 | 749 | ||
703 | config CSRC_SB1250 | 750 | config CSRC_SB1250 |
@@ -835,6 +882,9 @@ config IRQ_GT641XX | |||
835 | config IRQ_GIC | 882 | config IRQ_GIC |
836 | bool | 883 | bool |
837 | 884 | ||
885 | config IRQ_CPU_OCTEON | ||
886 | bool | ||
887 | |||
838 | config MIPS_BOARDS_GEN | 888 | config MIPS_BOARDS_GEN |
839 | bool | 889 | bool |
840 | 890 | ||
@@ -924,7 +974,7 @@ config BOOT_ELF32 | |||
924 | config MIPS_L1_CACHE_SHIFT | 974 | config MIPS_L1_CACHE_SHIFT |
925 | int | 975 | int |
926 | default "4" if MACH_DECSTATION || MIKROTIK_RB532 | 976 | default "4" if MACH_DECSTATION || MIKROTIK_RB532 |
927 | default "7" if SGI_IP22 || SGI_IP27 || SGI_IP28 || SNI_RM | 977 | default "7" if SGI_IP22 || SGI_IP27 || SGI_IP28 || SNI_RM || CPU_CAVIUM_OCTEON |
928 | default "4" if PMC_MSP4200_EVAL | 978 | default "4" if PMC_MSP4200_EVAL |
929 | default "5" | 979 | default "5" |
930 | 980 | ||
@@ -1185,6 +1235,23 @@ config CPU_SB1 | |||
1185 | select CPU_SUPPORTS_HIGHMEM | 1235 | select CPU_SUPPORTS_HIGHMEM |
1186 | select WEAK_ORDERING | 1236 | select WEAK_ORDERING |
1187 | 1237 | ||
1238 | config CPU_CAVIUM_OCTEON | ||
1239 | bool "Cavium Octeon processor" | ||
1240 | select IRQ_CPU | ||
1241 | select IRQ_CPU_OCTEON | ||
1242 | select CPU_HAS_PREFETCH | ||
1243 | select CPU_SUPPORTS_64BIT_KERNEL | ||
1244 | select SYS_SUPPORTS_SMP | ||
1245 | select NR_CPUS_DEFAULT_16 | ||
1246 | select WEAK_ORDERING | ||
1247 | select WEAK_REORDERING_BEYOND_LLSC | ||
1248 | select CPU_SUPPORTS_HIGHMEM | ||
1249 | help | ||
1250 | The Cavium Octeon processor is a highly integrated chip containing | ||
1251 | many ethernet hardware widgets for networking tasks. The processor | ||
1252 | can have up to 16 Mips64v2 cores and 8 integrated gigabit ethernets. | ||
1253 | Full details can be found at http://www.caviumnetworks.com. | ||
1254 | |||
1188 | endchoice | 1255 | endchoice |
1189 | 1256 | ||
1190 | config SYS_HAS_CPU_LOONGSON2 | 1257 | config SYS_HAS_CPU_LOONGSON2 |
@@ -1285,7 +1352,7 @@ config CPU_MIPSR1 | |||
1285 | 1352 | ||
1286 | config CPU_MIPSR2 | 1353 | config CPU_MIPSR2 |
1287 | bool | 1354 | bool |
1288 | default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 | 1355 | default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON |
1289 | 1356 | ||
1290 | config SYS_SUPPORTS_32BIT_KERNEL | 1357 | config SYS_SUPPORTS_32BIT_KERNEL |
1291 | bool | 1358 | bool |