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+config MIPS
+        bool
+        default y
+        # Horrible source of confusion.  Die, die, die ...
+        select EMBEDDED
+config MIPS64
+        bool "64-bit kernel"
+        help
+          Select this option if you want to build a 64-bit kernel.  You should
+          only select this option if you have hardware that actually has a
+          64-bit processor and if your application will actually benefit from
+          64-bit processing, otherwise say N.  You must say Y for kernels for
+          SGI IP27 (Origin 200 and 2000) and SGI IP32 (O2).  If in doubt say N.
+config 64BIT
+        def_bool MIPS64
+config MIPS32
+        bool
+        depends on MIPS64 = 'n'
+        default y
+mainmenu "Linux/MIPS Kernel Configuration"
+source "init/Kconfig"
+menu "Machine selection"
+config MACH_JAZZ
+        bool "Support for the Jazz family of machines"
+        select ARC
+        select ARC32
+        select GENERIC_ISA_DMA
+        select I8259
+        select ISA
+        help
+         This a family of machines based on the MIPS R4030 chipset which was
+         used by several vendors to build RISC/os and Windows NT workstations.
+         Members include the Acer PICA, MIPS Magnum 4000, MIPS Millenium and
+         Olivetti M700-10 workstations.
+config ACER_PICA_61
+        bool "Support for Acer PICA 1 chipset (EXPERIMENTAL)"
+        depends on MACH_JAZZ && EXPERIMENTAL
+        select DMA_NONCOHERENT
+        help
+          This is a machine with a R4400 133/150 MHz CPU. To compile a Linux
+          kernel that runs on these, say Y here. For details about Linux on
+          the MIPS architecture, check out the Linux/MIPS FAQ on the WWW at
+          <http://www.linux-mips.org/>.
+config MIPS_MAGNUM_4000
+        bool "Support for MIPS Magnum 4000"
+        depends on MACH_JAZZ
+        select DMA_NONCOHERENT
+        help
+          This is a machine with a R4000 100 MHz CPU. To compile a Linux
+          kernel that runs on these, say Y here. For details about Linux on
+          the MIPS architecture, check out the Linux/MIPS FAQ on the WWW at
+          <http://www.linux-mips.org/>.
+config OLIVETTI_M700
+        bool "Support for Olivetti M700-10"
+        depends on MACH_JAZZ
+        select DMA_NONCOHERENT
+        help
+          This is a machine with a R4000 100 MHz CPU. To compile a Linux
+          kernel that runs on these, say Y here. For details about Linux on
+          the MIPS architecture, check out the Linux/MIPS FAQ on the WWW at
+          <http://www.linux-mips.org/>.
+config MACH_VR41XX
+        bool "Support for NEC VR41XX-based machines"
+config NEC_CMBVR4133
+        bool "Support for NEC CMB-VR4133"
+        depends on MACH_VR41XX
+        select CPU_VR41XX
+        select DMA_NONCOHERENT
+        select IRQ_CPU
+        select HW_HAS_PCI
+        select PCI_VR41XX
+config ROCKHOPPER
+        bool "Support for Rockhopper baseboard"
+        depends on NEC_CMBVR4133
+        select I8259
+        select HAVE_STD_PC_SERIAL_PORT
+config CASIO_E55
+        bool "Support for CASIO CASSIOPEIA E-10/15/55/65"
+        depends on MACH_VR41XX
+        select DMA_NONCOHERENT
+        select IRQ_CPU
+        select ISA
+config IBM_WORKPAD
+        bool "Support for IBM WorkPad z50"
+        depends on MACH_VR41XX
+        select DMA_NONCOHERENT
+        select IRQ_CPU
+        select ISA
+config TANBAC_TB0226
+        bool "Support for TANBAC TB0226 (Mbase)"
+        depends on MACH_VR41XX
+        select DMA_NONCOHERENT
+        select HW_HAS_PCI
+        select IRQ_CPU
+        help
+          The TANBAC TB0226 (Mbase) is a MIPS-based platform manufactured by TANBAC.
+          Please refer to <http://www.tanbac.co.jp/> about Mbase.
+config TANBAC_TB0229
+        bool "Support for TANBAC TB0229 (VR4131DIMM)"
+        depends on MACH_VR41XX
+        select DMA_NONCOHERENT
+        select HW_HAS_PCI
+        select IRQ_CPU
+        help
+          The TANBAC TB0229 (VR4131DIMM) is a MIPS-based platform manufactured by TANBAC.
+          Please refer to <http://www.tanbac.co.jp/> about VR4131DIMM.
+config VICTOR_MPC30X
+        bool "Support for Victor MP-C303/304"
+        select DMA_NONCOHERENT
+        select HW_HAS_PCI
+        select IRQ_CPU
+        depends on MACH_VR41XX
+config ZAO_CAPCELLA
+        bool "Support for ZAO Networks Capcella"
+        depends on MACH_VR41XX
+        select DMA_NONCOHERENT
+        select HW_HAS_PCI
+        select IRQ_CPU
+config PCI_VR41XX
+        bool "Add PCI control unit support of NEC VR4100 series"
+        depends on MACH_VR41XX && PCI
+config VRC4171
+        tristate "Add NEC VRC4171 companion chip support"
+        depends on MACH_VR41XX && ISA
+        ---help---
+          The NEC VRC4171/4171A is a companion chip for NEC VR4111/VR4121.
+config VRC4173
+        tristate "Add NEC VRC4173 companion chip support"
+        depends on MACH_VR41XX && PCI_VR41XX
+        ---help---
+          The NEC VRC4173 is a companion chip for NEC VR4122/VR4131.
+config TOSHIBA_JMR3927
+        bool "Support for Toshiba JMR-TX3927 board"
+        depends on MIPS32
+        select DMA_NONCOHERENT
+        select HW_HAS_PCI
+        select SWAP_IO_SPACE
+config MIPS_COBALT
+        bool "Support for Cobalt Server (EXPERIMENTAL)"
+        depends on EXPERIMENTAL
+        select DMA_NONCOHERENT
+        select HW_HAS_PCI
+        select I8259
+        select IRQ_CPU
+config MACH_DECSTATION
+        bool "Support for DECstations"
+        select BOOT_ELF32
+        select DMA_NONCOHERENT
+        select IRQ_CPU
+        depends on MIPS32 || EXPERIMENTAL
+        ---help---
+          This enables support for DEC's MIPS based workstations.  For details
+          see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
+          DECstation porting pages on <http://decstation.unix-ag.org/>.
+          If you have one of the following DECstation Models you definitely
+          want to choose R4xx0 for the CPU Type:
+                DECstation 5000/50
+                DECstation 5000/150
+                DECstation 5000/260
+                DECsystem 5900/260
+          otherwise choose R3000.
+config MIPS_EV64120
+        bool "Support for Galileo EV64120 Evaluation board (EXPERIMENTAL)"
+        depends on EXPERIMENTAL
+        select DMA_NONCOHERENT
+        select HW_HAS_PCI
+        select MIPS_GT64120
+        help
+          This is an evaluation board based on the Galileo GT-64120
+          single-chip system controller that contains a MIPS R5000 compatible
+          core running at 75/100MHz.  Their website is located at
+          <http://www.marvell.com/>.  Say Y here if you wish to build a
+          kernel for this platform.
+config EVB_PCI1
+        bool "Enable Second PCI (PCI1)"
+        depends on MIPS_EV64120
+config MIPS_EV96100
+        bool "Support for Galileo EV96100 Evaluation board (EXPERIMENTAL)"
+        depends on EXPERIMENTAL
+        select DMA_NONCOHERENT
+        select HW_HAS_PCI
+        select IRQ_CPU
+        select MIPS_GT96100
+        select RM7000_CPU_SCACHE
+        select SWAP_IO_SPACE
+        help
+          This is an evaluation board based on the Galileo GT-96100 LAN/WAN
+          communications controllers containing a MIPS R5000 compatible core
+          running at 83MHz. Their website is <http://www.marvell.com/>. Say Y
+          here if you wish to build a kernel for this platform.
+config MIPS_IVR
+        bool "Support for Globespan IVR board"
+        select DMA_NONCOHERENT
+        select HW_HAS_PCI
+        help
+          This is an evaluation board built by Globespan to showcase thir
+          iVR (Internet Video Recorder) design. It utilizes a QED RM5231
+          R5000 MIPS core. More information can be found out their website
+          located at <http://www.globespan.net/>. Say Y here if you wish to
+          build a kernel for this platform.
+config LASAT
+        bool "Support for LASAT Networks platforms"
+        select DMA_NONCOHERENT
+        select HW_HAS_PCI
+        select MIPS_GT64120
+        select R5000_CPU_SCACHE
+config PICVUE
+        tristate "PICVUE LCD display driver"
+        depends on LASAT
+config PICVUE_PROC
+        tristate "PICVUE LCD display driver /proc interface"
+        depends on PICVUE
+config DS1603
+        bool "DS1603 RTC driver"
+        depends on LASAT
+config LASAT_SYSCTL
+        bool "LASAT sysctl interface"
+        depends on LASAT
+config MIPS_ITE8172
+        bool "Support for ITE 8172G board"
+        select DMA_NONCOHERENT
+        select HW_HAS_PCI
+        help
+          Ths is an evaluation board made by ITE <http://www.ite.com.tw/>
+          with ATX form factor that utilizes a MIPS R5000 to work with its
+          ITE8172G companion internet appliance chip. The MIPS core can be
+          either a NEC Vr5432 or QED RM5231. Say Y here if you wish to build
+          a kernel for this platform.
+config IT8172_REVC
+        bool "Support for older IT8172 (Rev C)"
+        depends on MIPS_ITE8172
+        help
+          Say Y here to support the older, Revision C version of the Integrated
+          Technology Express, Inc. ITE8172 SBC.  Vendor page at
+          <http://www.ite.com.tw/ia/brief_it8172bsp.htm>; picture of the
+          board at <http://www.mvista.com/partners/semiconductor/ite.html>.
+config MIPS_ATLAS
+        bool "Support for MIPS Atlas board"
+        select BOOT_ELF32
+        select DMA_NONCOHERENT
+        select HW_HAS_PCI
+        select MIPS_GT64120
+        select SWAP_IO_SPACE
+        help
+          This enables support for the QED R5231-based MIPS Atlas evaluation
+          board.
+config MIPS_MALTA
+        bool "Support for MIPS Malta board"
+        select BOOT_ELF32
+        select HAVE_STD_PC_SERIAL_PORT
+        select DMA_NONCOHERENT
+        select GENERIC_ISA_DMA
+        select HW_HAS_PCI
+        select I8259
+        select MIPS_GT64120
+        select SWAP_IO_SPACE
+        help
+          This enables support for the VR5000-based MIPS Malta evaluation
+          board.
+config MIPS_SEAD
+        bool "Support for MIPS SEAD board (EXPERIMENTAL)"
+        depends on EXPERIMENTAL
+        select IRQ_CPU
+        select DMA_NONCOHERENT
+config MOMENCO_OCELOT
+        bool "Support for Momentum Ocelot board"
+        select DMA_NONCOHERENT
+        select HW_HAS_PCI
+        select IRQ_CPU
+        select IRQ_CPU_RM7K
+        select MIPS_GT64120
+        select RM7000_CPU_SCACHE
+        select SWAP_IO_SPACE
+        help
+          The Ocelot is a MIPS-based Single Board Computer (SBC) made by
+          Momentum Computer <http://www.momenco.com/>.
+config MOMENCO_OCELOT_G
+        bool "Support for Momentum Ocelot-G board"
+        select DMA_NONCOHERENT
+        select HW_HAS_PCI
+        select IRQ_CPU
+        select IRQ_CPU_RM7K
+        select PCI_MARVELL
+        select RM7000_CPU_SCACHE
+        select SWAP_IO_SPACE
+        help
+          The Ocelot is a MIPS-based Single Board Computer (SBC) made by
+          Momentum Computer <http://www.momenco.com/>.
+config MOMENCO_OCELOT_C
+        bool "Support for Momentum Ocelot-C board"
+        select DMA_NONCOHERENT
+        select HW_HAS_PCI
+        select IRQ_CPU
+        select IRQ_MV64340
+        select PCI_MARVELL
+        select RM7000_CPU_SCACHE
+        select SWAP_IO_SPACE
+        help
+          The Ocelot is a MIPS-based Single Board Computer (SBC) made by
+          Momentum Computer <http://www.momenco.com/>.
+config MOMENCO_OCELOT_3
+        bool "Support for Momentum Ocelot-3 board"
+        select BOOT_ELF32
+        select DMA_NONCOHERENT
+        select HW_HAS_PCI
+        select IRQ_CPU
+        select IRQ_CPU_RM7K
+        select IRQ_MV64340
+        select PCI_MARVELL
+        select RM7000_CPU_SCACHE
+        select SWAP_IO_SPACE
+        help
+          The Ocelot-3 is based off Discovery III System Controller and
+          PMC-Sierra Rm79000 core.
+config MOMENCO_JAGUAR_ATX
+        bool "Support for Momentum Jaguar board"
+        select BOOT_ELF32
+        select DMA_NONCOHERENT
+        select HW_HAS_PCI
+        select IRQ_CPU
+        select IRQ_CPU_RM7K
+        select IRQ_MV64340
+        select LIMITED_DMA
+        select PCI_MARVELL
+        select RM7000_CPU_SCACHE
+        select SWAP_IO_SPACE
+        help
+          The Jaguar ATX is a MIPS-based Single Board Computer (SBC) made by
+          Momentum Computer <http://www.momenco.com/>.
+config JAGUAR_DMALOW
+        bool "Low DMA Mode"
+        depends on MOMENCO_JAGUAR_ATX
+        help
+          Select to Y if jump JP5 is set on your board, N otherwise.  Normally
+          the jumper is set, so if you feel unsafe, just say Y.
+config PMC_YOSEMITE
+        bool "Support for PMC-Sierra Yosemite eval board"
+        select DMA_COHERENT
+        select HW_HAS_PCI
+        select IRQ_CPU
+        select IRQ_CPU_RM7K
+        select IRQ_CPU_RM9K
+        select SWAP_IO_SPACE
+        help
+          Yosemite is an evaluation board for the RM9000x2 processor
+          manufactured by PMC-Sierra
+config HYPERTRANSPORT
+        bool "Hypertransport Support for PMC-Sierra Yosemite"
+        depends on PMC_YOSEMITE
+config DDB5074
+        bool "Support for NEC DDB Vrc-5074 (EXPERIMENTAL)"
+        depends on EXPERIMENTAL
+        select DMA_NONCOHERENT
+        select HAVE_STD_PC_SERIAL_PORT
+        select HW_HAS_PCI
+        select IRQ_CPU
+        select I8259
+        select ISA
+        help
+          This enables support for the VR5000-based NEC DDB Vrc-5074
+          evaluation board.
+config DDB5476
+        bool "Support for NEC DDB Vrc-5476"
+        select DMA_NONCOHERENT
+        select HAVE_STD_PC_SERIAL_PORT
+        select HW_HAS_PCI
+        select IRQ_CPU
+        select I8259
+        select ISA
+        help
+          This enables support for the R5432-based NEC DDB Vrc-5476
+          evaluation board.
+          Features : kernel debugging, serial terminal, NFS root fs, on-board
+          ether port USB, AC97, PCI, PCI VGA card & framebuffer console,
+          IDE controller, PS2 keyboard, PS2 mouse, etc.
+config DDB5477
+        bool "Support for NEC DDB Vrc-5477"
+        select DMA_NONCOHERENT
+        select HW_HAS_PCI
+        select I8259
+        select IRQ_CPU
+        help
+          This enables support for the R5432-based NEC DDB Vrc-5477,
+          or Rockhopper/SolutionGear boards with R5432/R5500 CPUs.
+          Features : kernel debugging, serial terminal, NFS root fs, on-board
+          ether port USB, AC97, PCI, etc.
+config DDB5477_BUS_FREQUENCY
+        int "bus frequency (in kHZ, 0 for auto-detect)"
+        depends on DDB5477
+        default 0
+config NEC_OSPREY
+        bool "Support for NEC Osprey board"
+        select DMA_NONCOHERENT
+        select IRQ_CPU
+config SGI_IP22
+        bool "Support for SGI IP22 (Indy/Indigo2)"
+        select ARC
+        select ARC32
+        select BOOT_ELF32
+        select DMA_NONCOHERENT
+        select IP22_CPU_SCACHE
+        select IRQ_CPU
+        select SWAP_IO_SPACE
+        help
+          This are the SGI Indy, Challenge S and Indigo2, as well as certain
+          OEM variants like the Tandem CMN B006S. To compile a Linux kernel
+          that runs on these, say Y here.
+config SGI_IP27
+        bool "Support for SGI IP27 (Origin200/2000)"
+        depends on MIPS64
+        select ARC
+        select ARC64
+        select DMA_IP27
+        select HW_HAS_PCI
+        select PCI_DOMAINS
+        help
+          This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
+          workstations.  To compile a Linux kernel that runs on these, say Y
+          here.
+#config SGI_SN0_XXL
+#       bool "IP27 XXL"
+#       depends on SGI_IP27
+#         This options adds support for userspace processes upto 16TB size.
+#         Normally the limit is just .5TB.
+config SGI_SN0_N_MODE
+        bool "IP27 N-Mode"
+        depends on SGI_IP27
+        help
+          The nodes of Origin 200, Origin 2000 and Onyx 2 systems can be
+          configured in either N-Modes which allows for more nodes or M-Mode
+          which allows for more memory.  Your system is most probably
+          running in M-Mode, so you should say N here.
+config DISCONTIGMEM
+        bool
+        default y if SGI_IP27
+        help
+          Say Y to upport efficient handling of discontiguous physical memory,
+          for architectures which are either NUMA (Non-Uniform Memory Access)
+          or have huge holes in the physical address space for other reasons.
+          See <file:Documentation/vm/numa> for more.
+config NUMA
+        bool "NUMA Support"
+        depends on SGI_IP27
+        help
+          Say Y to compile the kernel to support NUMA (Non-Uniform Memory
+          Access).  This option is for configuring high-end multiprocessor
+          server machines.  If in doubt, say N.
+config MAPPED_KERNEL
+        bool "Mapped kernel support"
+        depends on SGI_IP27
+        help
+          Change the way a Linux kernel is loaded into memory on a MIPS64
+          machine.  This is required in order to support text replication and
+          NUMA.  If you need to understand it, read the source code.
+config REPLICATE_KTEXT
+        bool "Kernel text replication support"
+        depends on SGI_IP27
+        help
+          Say Y here to enable replicating the kernel text across multiple
+          nodes in a NUMA cluster.  This trades memory for speed.
+config REPLICATE_EXHANDLERS
+        bool "Exception handler replication support"
+        depends on SGI_IP27
+        help
+          Say Y here to enable replicating the kernel exception handlers
+          across multiple nodes in a NUMA cluster. This trades memory for
+          speed.
+config SGI_IP32
+        bool "Support for SGI IP32 (O2) (EXPERIMENTAL)"
+        depends on MIPS64 && EXPERIMENTAL
+        select ARC
+        select ARC32
+        select BOOT_ELF32
+        select OWN_DMA
+        select DMA_IP32
+        select DMA_NONCOHERENT
+        select HW_HAS_PCI
+        select R5000_CPU_SCACHE
+        select RM7000_CPU_SCACHE
+        help
+          If you want this kernel to run on SGI O2 workstation, say Y here.
+config SOC_AU1X00
+        depends on MIPS32
+        bool "Support for AMD/Alchemy Au1X00 SOCs"
+choice
+        prompt "Au1X00 SOC Type"
+        depends on SOC_AU1X00
+        help
+          Say Y here to enable support for one of three AMD/Alchemy
+          SOCs. For additional documentation see www.amd.com.
+config SOC_AU1000
+        bool "SOC_AU1000"
+config SOC_AU1100
+        bool "SOC_AU1100"
+config SOC_AU1500
+        bool "SOC_AU1500"
+config SOC_AU1550
+        bool "SOC_AU1550"
+endchoice
+choice
+        prompt "AMD/Alchemy Au1x00 board support"
+        depends on SOC_AU1X00
+        help
+          These are evaluation boards built by AMD/Alchemy to
+          showcase their Au1X00 Internet Edge Processors. The SOC design
+          is based on the MIPS32 architecture running at 266/400/500MHz
+          with many integrated peripherals. Further information can be
+          found at their website, <http://www.amd.com/>. Say Y here if you
+          wish to build a kernel for this platform.
+config MIPS_PB1000
+        bool "PB1000 board"
+        depends on SOC_AU1000
+        select DMA_NONCOHERENT
+        select HW_HAS_PCI
+        select SWAP_IO_SPACE
+config MIPS_PB1100
+        bool "PB1100 board"
+        depends on SOC_AU1100
+        select DMA_NONCOHERENT
+        select HW_HAS_PCI
+        select SWAP_IO_SPACE
+config MIPS_PB1500
+        bool "PB1500 board"
+        depends on SOC_AU1500
+        select DMA_COHERENT
+        select HW_HAS_PCI
+config MIPS_PB1550
+        bool "PB1550 board"
+        depends on SOC_AU1550
+        select DMA_COHERENT
+        select HW_HAS_PCI
+        select MIPS_DISABLE_OBSOLETE_IDE
+config MIPS_DB1000
+        bool "DB1000 board"
+        depends on SOC_AU1000
+        select DMA_NONCOHERENT
+        select HW_HAS_PCI
+config MIPS_DB1100
+        bool "DB1100 board"
+        depends on SOC_AU1100
+        select DMA_NONCOHERENT
+config MIPS_DB1500
+        bool "DB1500 board"
+        depends on SOC_AU1500
+        select DMA_COHERENT
+        select HW_HAS_PCI
+        select MIPS_DISABLE_OBSOLETE_IDE
+config MIPS_DB1550
+        bool "DB1550 board"
+        depends on SOC_AU1550
+        select HW_HAS_PCI
+        select DMA_COHERENT
+        select MIPS_DISABLE_OBSOLETE_IDE
+config MIPS_BOSPORUS
+        bool "Bosporus board"
+        depends on SOC_AU1500
+        select DMA_NONCOHERENT
+config MIPS_MIRAGE
+        bool "Mirage board"
+        depends on SOC_AU1500
+        select DMA_NONCOHERENT
+config MIPS_XXS1500
+        bool "MyCable XXS1500 board"
+        depends on SOC_AU1500
+        select DMA_NONCOHERENT
+config MIPS_MTX1
+        bool "4G Systems MTX-1 board"
+        depends on SOC_AU1500
+        select HW_HAS_PCI
+        select DMA_NONCOHERENT
+endchoice
+config SIBYTE_SB1xxx_SOC
+        bool "Support for Broadcom BCM1xxx SOCs (EXPERIMENTAL)"
+        depends on EXPERIMENTAL
+        select BOOT_ELF32
+        select DMA_COHERENT
+        select SWAP_IO_SPACE
+choice
+        prompt "BCM1xxx SOC-based board"
+        depends on SIBYTE_SB1xxx_SOC
+        default SIBYTE_SWARM
+        help
+          Enable support for boards based on the SiByte line of SOCs
+          from Broadcom.  There are configurations for the known
+          evaluation boards, or you can choose "Other" and add your
+          own board support code.
+config SIBYTE_SWARM
+        bool "BCM91250A-SWARM"
+        select SIBYTE_SB1250
+config SIBYTE_SENTOSA
+        bool "BCM91250E-Sentosa"
+        select SIBYTE_SB1250
+config SIBYTE_RHONE
+        bool "BCM91125E-Rhone"
+        select SIBYTE_BCM1125H
+config SIBYTE_CARMEL
+        bool "BCM91120x-Carmel"
+        select SIBYTE_BCM1120
+config SIBYTE_PTSWARM
+        bool "BCM91250PT-PTSWARM"
+        select SIBYTE_SB1250
+config SIBYTE_LITTLESUR
+        bool "BCM91250C2-LittleSur"
+        select SIBYTE_SB1250
+config SIBYTE_CRHINE
+        bool "BCM91120C-CRhine"
+        select SIBYTE_BCM1120
+config SIBYTE_CRHONE
+        bool "BCM91125C-CRhone"
+        select SIBYTE_BCM1125
+config SIBYTE_UNKNOWN
+        bool "Other"
+endchoice
+config SIBYTE_BOARD
+        bool
+        depends on SIBYTE_SB1xxx_SOC && !SIBYTE_UNKNOWN
+        default y
+choice
+        prompt "BCM1xxx SOC Type"
+        depends on SIBYTE_UNKNOWN
+        default SIBYTE_UNK_BCM1250
+        help
+          Since you haven't chosen a known evaluation board from
+          Broadcom, you must explicitly pick the SOC this kernel is
+          targetted for.
+config SIBYTE_UNK_BCM1250
+        bool "BCM1250"
+        select SIBYTE_SB1250
+config SIBYTE_UNK_BCM1120
+        bool "BCM1120"
+        select SIBYTE_BCM1120
+config SIBYTE_UNK_BCM1125
+        bool "BCM1125"
+        select SIBYTE_BCM1125
+config SIBYTE_UNK_BCM1125H
+        bool "BCM1125H"
+        select SIBYTE_BCM1125H
+endchoice
+config SIBYTE_SB1250
+        bool
+        select HW_HAS_PCI
+config SIBYTE_BCM1120
+        bool
+        select SIBYTE_BCM112X
+config SIBYTE_BCM1125
+        bool
+        select HW_HAS_PCI
+        select SIBYTE_BCM112X
+config SIBYTE_BCM1125H
+        bool
+        select HW_HAS_PCI
+        select SIBYTE_BCM112X
+config SIBYTE_BCM112X
+        bool
+choice
+        prompt "SiByte SOC Stepping"
+        depends on SIBYTE_SB1xxx_SOC
+config CPU_SB1_PASS_1
+        bool "1250 Pass1"
+        depends on SIBYTE_SB1250
+        select CPU_HAS_PREFETCH
+config CPU_SB1_PASS_2_1250
+        bool "1250 An"
+        depends on SIBYTE_SB1250
+        select CPU_SB1_PASS_2
+        help
+          Also called BCM1250 Pass 2
+config CPU_SB1_PASS_2_2
+        bool "1250 Bn"
+        depends on SIBYTE_SB1250
+        select CPU_HAS_PREFETCH
+        help
+          Also called BCM1250 Pass 2.2
+config CPU_SB1_PASS_4
+        bool "1250 Cn"
+        depends on SIBYTE_SB1250
+        select CPU_HAS_PREFETCH
+        help
+          Also called BCM1250 Pass 3
+config CPU_SB1_PASS_2_112x
+        bool "112x Hybrid"
+        depends on SIBYTE_BCM112X
+        select CPU_SB1_PASS_2
+config CPU_SB1_PASS_3
+        bool "112x An"
+        depends on SIBYTE_BCM112X
+        select CPU_HAS_PREFETCH
+endchoice
+config CPU_SB1_PASS_2
+        bool
+config SIBYTE_HAS_LDT
+        bool
+        depends on PCI && (SIBYTE_SB1250 || SIBYTE_BCM1125H)
+        default y
+config SIMULATION
+        bool "Running under simulation"
+        depends on SIBYTE_SB1xxx_SOC
+        help
+          Build a kernel suitable for running under the GDB simulator.
+          Primarily adjusts the kernel's notion of time.
+config SIBYTE_CFE
+        bool "Booting from CFE"
+        depends on SIBYTE_SB1xxx_SOC
+        help
+          Make use of the CFE API for enumerating available memory,
+          controlling secondary CPUs, and possibly console output.
+config SIBYTE_CFE_CONSOLE
+        bool "Use firmware console"
+        depends on SIBYTE_CFE
+        help
+          Use the CFE API's console write routines during boot.  Other console
+          options (VT console, sb1250 duart console, etc.) should not be
+          configured.
+config SIBYTE_STANDALONE
+        bool
+        depends on SIBYTE_SB1xxx_SOC && !SIBYTE_CFE
+        default y
+config SIBYTE_STANDALONE_RAM_SIZE
+        int "Memory size (in megabytes)"
+        depends on SIBYTE_STANDALONE
+        default "32"
+config SIBYTE_BUS_WATCHER
+        bool "Support for Bus Watcher statistics"
+        depends on SIBYTE_SB1xxx_SOC
+        help
+          Handle and keep statistics on the bus error interrupts (COR_ECC,
+          BAD_ECC, IO_BUS).
+config SIBYTE_BW_TRACE
+        bool "Capture bus trace before bus error"
+        depends on SIBYTE_BUS_WATCHER
+        help
+          Run a continuous bus trace, dumping the raw data as soon as
+          a ZBbus error is detected.  Cannot work if ZBbus profiling
+          is turned on, and also will interfere with JTAG-based trace
+          buffer activity.  Raw buffer data is dumped to console, and
+          must be processed off-line.
+config SIBYTE_SB1250_PROF
+        bool "Support for SB1/SOC profiling - SB1/SCD perf counters"
+        depends on SIBYTE_SB1xxx_SOC
+config SIBYTE_TBPROF
+        bool "Support for ZBbus profiling"
+        depends on SIBYTE_SB1xxx_SOC
+config SNI_RM200_PCI
+        bool "Support for SNI RM200 PCI"
+        select ARC
+        select ARC32
+        select BOOT_ELF32
+        select DMA_NONCOHERENT
+        select GENERIC_ISA_DMA
+        select HAVE_STD_PC_SERIAL_PORT
+        select HW_HAS_PCI
+        select I8259
+        select ISA
+        help
+          The SNI RM200 PCI was a MIPS-based platform manufactured by Siemens
+          Nixdorf Informationssysteme (SNI), parent company of Pyramid
+          Technology and now in turn merged with Fujitsu.  Say Y here to
+          support this machine type.
+config TOSHIBA_RBTX4927
+        bool "Support for Toshiba TBTX49[23]7 board"
+        depends on MIPS32
+        select DMA_NONCOHERENT
+        select HAS_TXX9_SERIAL
+        select HW_HAS_PCI
+        select I8259
+        select ISA
+        select SWAP_IO_SPACE
+        help
+          This Toshiba board is based on the TX4927 processor. Say Y here to
+          support this machine type
+config TOSHIBA_FPCIB0
+        bool "FPCIB0 Backplane Support"
+        depends on TOSHIBA_RBTX4927
+config RWSEM_GENERIC_SPINLOCK
+        bool
+        default y
+config RWSEM_XCHGADD_ALGORITHM
+        bool
+config GENERIC_CALIBRATE_DELAY
+        bool
+        default y
+config HAVE_DEC_LOCK
+        bool
+        default y
+#
+# Select some configuration options automatically based on user selections.
+#
+config ARC
+        bool
+        depends on SNI_RM200_PCI || SGI_IP32 || SGI_IP27 || SGI_IP22 || MIPS_MAGNUM_4000 || OLIVETTI_M700 || ACER_PICA_61
+        default y
+config  DMA_COHERENT
+        bool
+config  DMA_IP27
+        bool
+config  DMA_NONCOHERENT
+        bool
+config EARLY_PRINTK
+        bool
+        depends on MACH_DECSTATION
+        default y
+config GENERIC_ISA_DMA
+        bool
+        depends on SNI_RM200_PCI || MIPS_MAGNUM_4000 || OLIVETTI_M700 || ACER_PICA_61 || MIPS_MALTA
+        default y
+config I8259
+        bool
+        depends on SNI_RM200_PCI || DDB5477 || DDB5476 || DDB5074 || MACH_JAZZ || MIPS_MALTA || MIPS_COBALT
+        default y
+config LIMITED_DMA
+        bool
+        select HIGHMEM
+config MIPS_BONITO64
+        bool
+        depends on MIPS_ATLAS || MIPS_MALTA
+        default y
+config MIPS_MSC
+        bool
+        depends on MIPS_ATLAS || MIPS_MALTA
+        default y
+config MIPS_NILE4
+        bool
+        depends on LASAT
+        default y
+config MIPS_DISABLE_OBSOLETE_IDE
+        bool
+config CPU_LITTLE_ENDIAN
+        bool "Generate little endian code"
+        default y if ACER_PICA_61 || CASIO_E55 || DDB5074 || DDB5476 || DDB5477 || MACH_DECSTATION || IBM_WORKPAD || LASAT || MIPS_COBALT || MIPS_ITE8172 || MIPS_IVR || SOC_AU1X00 || NEC_OSPREY || OLIVETTI_M700 || SNI_RM200_PCI || VICTOR_MPC30X || ZAO_CAPCELLA
+        default n if MIPS_EV64120 || MIPS_EV96100 || MOMENCO_OCELOT || MOMENCO_OCELOT_G || SGI_IP22 || SGI_IP27 || SGI_IP32 || TOSHIBA_JMR3927
+        help
+          Some MIPS machines can be configured for either little or big endian
+          byte order. These modes require different kernels. Say Y if your
+          machine is little endian, N if it's a big endian machine.
+config IRQ_CPU
+        bool
+config IRQ_CPU_RM7K
+        bool
+config IRQ_MV64340
+        bool
+config DDB5XXX_COMMON
+        bool
+        depends on DDB5074 || DDB5476 || DDB5477
+        default y
+config MIPS_BOARDS_GEN
+        bool
+        depends on MIPS_ATLAS || MIPS_MALTA || MIPS_SEAD
+        default y
+config MIPS_GT64111
+        bool
+        depends on MIPS_COBALT
+        default y
+config MIPS_GT64120
+        bool
+        depends on MIPS_EV64120 || MIPS_EV96100 || LASAT || MIPS_ATLAS || MIPS_MALTA || MOMENCO_OCELOT
+        default y
+config MIPS_TX3927
+        bool
+        depends on TOSHIBA_JMR3927
+        select HAS_TXX9_SERIAL
+        default y
+config PCI_MARVELL
+        bool
+config ITE_BOARD_GEN
+        bool
+        depends on MIPS_IVR || MIPS_ITE8172
+        default y
+config SWAP_IO_SPACE
+        bool
+#
+# Unfortunately not all GT64120 systems run the chip at the same clock.
+# As the user for the clock rate and try to minimize the available options.
+#
+choice
+        prompt "Galileo Chip Clock"
+        #default SYSCLK_83 if MIPS_EV64120
+        depends on MIPS_EV64120 || MOMENCO_OCELOT || MOMENCO_OCELOT_G
+        default SYSCLK_83 if MIPS_EV64120
+        default SYSCLK_100 if MOMENCO_OCELOT || MOMENCO_OCELOT_G
+config SYSCLK_75
+        bool "75" if MIPS_EV64120
+config SYSCLK_83
+        bool "83.3" if MIPS_EV64120
+config SYSCLK_100
+        bool "100" if MIPS_EV64120 || MOMENCO_OCELOT || MOMENCO_OCELOT_G
+endchoice
+config AU1X00_USB_DEVICE
+        bool
+        depends on MIPS_PB1500 || MIPS_PB1100 || MIPS_PB1000
+        default n
+config MIPS_GT96100
+        bool
+        depends on MIPS_EV96100
+        default y
+        help
+          Say Y here to support the Galileo Technology GT96100 communications
+          controller card.  There is a web page at <http://www.galileot.com/>.
+config IT8172_CIR
+        bool
+        depends on MIPS_ITE8172 || MIPS_IVR
+        default y
+config IT8712
+        bool
+        depends on MIPS_ITE8172
+        default y
+config BOOT_ELF32
+        bool
+        depends on MACH_DECSTATION || MIPS_ATLAS || MIPS_MALTA || MOMENCO_JAGUAR_ATX || MOMENCO_OCELOT_3 || SIBYTE_SB1xxx_SOC || SGI_IP32 || SGI_IP22 || SNI_RM200_PCI
+        default y
+config MIPS_L1_CACHE_SHIFT
+        int
+        default "4" if MACH_DECSTATION
+        default "7" if SGI_IP27
+        default "5"
+config ARC32
+        bool
+        depends on MACH_JAZZ || SNI_RM200_PCI || SGI_IP22 || SGI_IP32
+        default y
+config FB
+        bool
+        depends on MIPS_MAGNUM_4000 || OLIVETTI_M700
+        default y
+        ---help---
+          The frame buffer device provides an abstraction for the graphics
+          hardware. It represents the frame buffer of some video hardware and
+          allows application software to access the graphics hardware through
+          a well-defined interface, so the software doesn't need to know
+          anything about the low-level (hardware register) stuff.
+          Frame buffer devices work identically across the different
+          architectures supported by Linux and make the implementation of
+          application programs easier and more portable; at this point, an X
+          server exists which uses the frame buffer device exclusively.
+          On several non-X86 architectures, the frame buffer device is the
+          only way to use the graphics hardware.
+          The device is accessed through special device nodes, usually located
+          in the /dev directory, i.e. /dev/fb*.
+          You need an utility program called fbset to make full use of frame
+          buffer devices. Please read <file:Documentation/fb/framebuffer.txt>
+          and the Framebuffer-HOWTO at <http://www.tldp.org/docs.html#howto>
+          for more information.
+          Say Y here and to the driver for your graphics board below if you
+          are compiling a kernel for a non-x86 architecture.
+          If you are compiling for the x86 architecture, you can say Y if you
+          want to play with it, but it is not essential. Please note that
+          running graphical applications that directly touch the hardware
+          (e.g. an accelerated X server) and that are not frame buffer
+          device-aware may cause unexpected results. If unsure, say N.
+config HAVE_STD_PC_SERIAL_PORT
+        bool
+config VR4181
+        bool
+        depends on NEC_OSPREY
+        default y
+config ARC_CONSOLE
+        bool "ARC console support"
+        depends on SGI_IP22 || SNI_RM200_PCI
+config ARC_MEMORY
+        bool
+        depends on MACH_JAZZ || SNI_RM200_PCI || SGI_IP32
+        default y
+config ARC_PROMLIB
+        bool
+        depends on MACH_JAZZ || SNI_RM200_PCI || SGI_IP22 || SGI_IP32
+        default y
+config ARC64
+        bool
+        depends on SGI_IP27
+        default y
+config BOOT_ELF64
+        bool
+        depends on SGI_IP27
+        default y
+#config MAPPED_PCI_IO y
+#       bool
+#       depends on SGI_IP27
+#       default y
+config QL_ISP_A64
+        bool
+        depends on SGI_IP27
+        default y
+config TOSHIBA_BOARDS
+        bool
+        depends on TOSHIBA_JMR3927 || TOSHIBA_RBTX4927
+        default y
+endmenu
+menu "CPU selection"
+choice
+        prompt "CPU type"
+        default CPU_R4X00
+config CPU_MIPS32
+        bool "MIPS32"
+config CPU_MIPS64
+        bool "MIPS64"
+config CPU_R3000
+        bool "R3000"
+        depends on MIPS32
+        help
+          Please make sure to pick the right CPU type. Linux/MIPS is not
+          designed to be generic, i.e. Kernels compiled for R3000 CPUs will
+          *not* work on R4000 machines and vice versa.  However, since most
+          of the supported machines have an R4000 (or similar) CPU, R4x00
+          might be a safe bet.  If the resulting kernel does not work,
+          try to recompile with R3000.
+config CPU_TX39XX
+        bool "R39XX"
+        depends on MIPS32
+config CPU_VR41XX
+        bool "R41xx"
+        help
+          The options selects support for the NEC VR41xx series of processors.
+          Only choose this option if you have one of these processors as a
+          kernel built with this option will not run on any other type of
+          processor or vice versa.
+config CPU_R4300
+        bool "R4300"
+        help
+          MIPS Technologies R4300-series processors.
+config CPU_R4X00
+        bool "R4x00"
+        help
+          MIPS Technologies R4000-series processors other than 4300, including
+          the R4000, R4400, R4600, and 4700.
+config CPU_TX49XX
+        bool "R49XX"
+config CPU_R5000
+        bool "R5000"
+        help
+          MIPS Technologies R5000-series processors other than the Nevada.
+config CPU_R5432
+        bool "R5432"
+config CPU_R6000
+        bool "R6000"
+        depends on MIPS32 && EXPERIMENTAL
+        help
+          MIPS Technologies R6000 and R6000A series processors.  Note these
+          processors are extremly rare and the support for them is incomplete.
+config CPU_NEVADA
+        bool "RM52xx"
+        help
+          QED / PMC-Sierra RM52xx-series ("Nevada") processors.
+config CPU_R8000
+        bool "R8000"
+        depends on MIPS64 && EXPERIMENTAL
+        help
+          MIPS Technologies R8000 processors.  Note these processors are
+          uncommon and the support for them is incomplete.
+config CPU_R10000
+        bool "R10000"
+        help
+          MIPS Technologies R10000-series processors.
+config CPU_RM7000
+        bool "RM7000"
+config CPU_RM9000
+        bool "RM9000"
+config CPU_SB1
+        bool "SB1"
+endchoice
+choice
+        prompt "Kernel page size"
+        default PAGE_SIZE_4KB
+config PAGE_SIZE_4KB
+        bool "4kB"
+        help
+         This option select the standard 4kB Linux page size.  On some
+         R3000-family processors this is the only available page size.  Using
+         4kB page size will minimize memory consumption and is therefore
+         recommended for low memory systems.
+config PAGE_SIZE_8KB
+        bool "8kB"
+        depends on EXPERIMENTAL && CPU_R8000
+        help
+          Using 8kB page size will result in higher performance kernel at
+          the price of higher memory consumption.  This option is available
+          only on the R8000 processor.  Not that at the time of this writing
+          this option is still high experimental; there are also issues with
+          compatibility of user applications.
+config PAGE_SIZE_16KB
+        bool "16kB"
+        depends on EXPERIMENTAL && !CPU_R3000 && !CPU_TX39XX
+        help
+          Using 16kB page size will result in higher performance kernel at
+          the price of higher memory consumption.  This option is available on
+          all non-R3000 family processor.  Not that at the time of this
+          writing this option is still high experimental; there are also
+          issues with compatibility of user applications.
+config PAGE_SIZE_64KB
+        bool "64kB"
+        depends on EXPERIMENTAL && !CPU_R3000 && !CPU_TX39XX
+        help
+          Using 64kB page size will result in higher performance kernel at
+          the price of higher memory consumption.  This option is available on
+          all non-R3000 family processor.  Not that at the time of this
+          writing this option is still high experimental; there are also
+          issues with compatibility of user applications.
+endchoice
+config BOARD_SCACHE
+        bool
+config IP22_CPU_SCACHE
+        bool
+        select BOARD_SCACHE
+config R5000_CPU_SCACHE
+        bool
+        select BOARD_SCACHE
+config RM7000_CPU_SCACHE
+        bool
+        select BOARD_SCACHE
+config SIBYTE_DMA_PAGEOPS
+        bool "Use DMA to clear/copy pages"
+        depends on CPU_SB1
+        help
+          Instead of using the CPU to zero and copy pages, use a Data Mover
+          channel.  These DMA channels are otherwise unused by the standard
+          SiByte Linux port.  Seems to give a small performance benefit.
+config CPU_HAS_PREFETCH
+        bool "Enable prefetches" if CPU_SB1 && !CPU_SB1_PASS_2
+        default y if CPU_MIPS32 || CPU_MIPS64 || CPU_RM7000 || CPU_RM9000 || CPU_R10000
+config VTAG_ICACHE
+        bool "Support for Virtual Tagged I-cache" if CPU_MIPS64 || CPU_MIPS32
+        default y if CPU_SB1
+config SB1_PASS_1_WORKAROUNDS
+        bool
+        depends on CPU_SB1_PASS_1
+        default y
+config SB1_PASS_2_WORKAROUNDS
+        bool
+        depends on CPU_SB1 && (CPU_SB1_PASS_2_2 || CPU_SB1_PASS_2)
+        default y
+config SB1_PASS_2_1_WORKAROUNDS
+        bool
+        depends on CPU_SB1 && CPU_SB1_PASS_2
+        default y
+config 64BIT_PHYS_ADDR
+        bool "Support for 64-bit physical address space"
+        depends on (CPU_R4X00 || CPU_R5000 || CPU_RM7000 || CPU_RM9000 || CPU_R10000 || CPU_SB1 || CPU_MIPS32 || CPU_MIPS64) && MIPS32
+config CPU_ADVANCED
+        bool "Override CPU Options"
+        depends on MIPS32
+        help
+          Saying yes here allows you to select support for various features
+          your CPU may or may not have.  Most people should say N here.
+config CPU_HAS_LLSC
+        bool "ll/sc Instructions available" if CPU_ADVANCED
+        default y if !CPU_ADVANCED && !CPU_R3000 && !CPU_VR41XX && !CPU_TX39XX
+        help
+          MIPS R4000 series and later provide the Load Linked (ll)
+          and Store Conditional (sc) instructions. More information is
+          available at <http://www.go-ecs.com/mips/miptek1.htm>.
+          Say Y here if your CPU has the ll and sc instructions.  Say Y here
+          for better performance, N if you don't know.  You must say Y here
+          for multiprocessor machines.
+config CPU_HAS_LLDSCD
+        bool "lld/scd Instructions available" if CPU_ADVANCED
+        default y if !CPU_ADVANCED && !CPU_R3000 && !CPU_VR41XX && !CPU_TX39XX && !CPU_MIPS32
+        help
+          Say Y here if your CPU has the lld and scd instructions, the 64-bit
+          equivalents of ll and sc.  Say Y here for better performance, N if
+          you don't know.  You must say Y here for multiprocessor machines.
+config CPU_HAS_WB
+        bool "Writeback Buffer available" if CPU_ADVANCED
+        default y if !CPU_ADVANCED && CPU_R3000 && MACH_DECSTATION
+        help
+          Say N here for slightly better performance.  You must say Y here for
+          machines which require flushing of write buffers in software.  Saying
+          Y is the safe option; N may result in kernel malfunction and crashes.
+config CPU_HAS_SYNC
+        bool
+        depends on !CPU_R3000
+        default y
+#
+# - Highmem only makes sense for the 32-bit kernel.
+# - The current highmem code will only work properly on physically indexed
+#   caches such as R3000, SB1, R7000 or those that look like they're virtually
+#   indexed such as R4000/R4400 SC and MC versions or R10000.  So for the
+#   moment we protect the user and offer the highmem option only on machines
+#   where it's known to be safe.  This will not offer highmem on a few systems
+#   such as MIPS32 and MIPS64 CPUs which may have virtual and physically
+#   indexed CPUs but we're playing safe.
+# - We should not offer highmem for system of which we already know that they
+#   don't have memory configurations that could gain from highmem support in
+#   the kernel because they don't support configurations with RAM at physical
+#   addresses > 0x20000000.
+#
+config HIGHMEM
+        bool "High Memory Support"
+        depends on MIPS32 && (CPU_R3000 || CPU_SB1 || CPU_R7000 || CPU_RM9000 || CPU_R10000) && !(MACH_DECSTATION || MOMENCO_JAGUAR_ATX)
+config SMP
+        bool "Multi-Processing support"
+        depends on CPU_RM9000 || (SIBYTE_SB1250 && !SIBYTE_STANDALONE) || SGI_IP27
+        ---help---
+          This enables support for systems with more than one CPU. If you have
+          a system with only one CPU, like most personal computers, say N. If
+          you have a system with more than one CPU, say Y.
+          If you say N here, the kernel will run on single and multiprocessor
+          machines, but will use only one CPU of a multiprocessor machine. If
+          you say Y here, the kernel will run on many, but not all,
+          singleprocessor machines. On a singleprocessor machine, the kernel
+          will run faster if you say N here.
+          People using multiprocessor machines who say Y here should also say
+          Y to "Enhanced Real Time Clock Support", below.
+          See also the <file:Documentation/smp.txt> and the SMP-HOWTO
+          available at <http://www.tldp.org/docs.html#howto>.
+          If you don't know what to do here, say N.
+config NR_CPUS
+        int "Maximum number of CPUs (2-64)"
+        range 2 64
+        depends on SMP
+        default "64" if SGI_IP27
+        default "2"
+        help
+          This allows you to specify the maximum number of CPUs which this
+          kernel will support.  The maximum supported value is 32 for 32-bit
+          kernel and 64 for 64-bit kernels; the minimum value which makes
+          sense is 2.
+          This is purely to save memory - each supported CPU adds
+          approximately eight kilobytes to the kernel image.
+config PREEMPT
+        bool "Preemptible Kernel"
+        help
+          This option reduces the latency of the kernel when reacting to
+          real-time or interactive events by allowing a low priority process to
+          be preempted even if it is in kernel mode executing a system call.
+          This allows applications to run more reliably even when the system is
+          under load.
+config RTC_DS1742
+        bool "DS1742 BRAM/RTC support"
+        depends on TOSHIBA_JMR3927 || TOSHIBA_RBTX4927
+config MIPS_INSANE_LARGE
+        bool "Support for large 64-bit configurations"
+        depends on CPU_R10000 && MIPS64
+        help
+          MIPS R10000 does support a 44 bit / 16TB address space as opposed to
+          previous 64-bit processors which only supported 40 bit / 1TB. If you
+          need processes of more than 1TB virtual address space, say Y here.
+          This will result in additional memory usage, so it is not
+          recommended for normal users.
+config RWSEM_GENERIC_SPINLOCK
+        bool
+        default y
+endmenu
+menu "Bus options (PCI, PCMCIA, EISA, ISA, TC)"
+config HW_HAS_PCI
+        bool
+config PCI
+        bool "Support for PCI controller"
+        depends on HW_HAS_PCI
+        help
+          Find out whether you have a PCI motherboard. PCI is the name of a
+          bus system, i.e. the way the CPU talks to the other stuff inside
+          your box. Other bus systems are ISA, EISA, or VESA. If you have PCI,
+          say Y, otherwise N.
+          The PCI-HOWTO, available from
+          <http://www.tldp.org/docs.html#howto>, contains valuable
+          information about which PCI hardware does work under Linux and which
+          doesn't.
+config PCI_DOMAINS
+        bool
+        depends on PCI
+source "drivers/pci/Kconfig"
+#
+# ISA support is now enabled via select.  Too many systems still have the one
+# or other ISA chip on the board that users don't know about so don't expect
+# users to choose the right thing ...
+#
+config ISA
+        bool
+config EISA
+        bool "EISA support"
+        depends on SGI_IP22 || SNI_RM200_PCI
+        select ISA
+        ---help---
+          The Extended Industry Standard Architecture (EISA) bus was
+          developed as an open alternative to the IBM MicroChannel bus.
+          The EISA bus provided some of the features of the IBM MicroChannel
+          bus while maintaining backward compatibility with cards made for
+          the older ISA bus.  The EISA bus saw limited use between 1988 and
+          1995 when it was made obsolete by the PCI bus.
+          Say Y here if you are building a kernel for an EISA-based machine.
+          Otherwise, say N.
+source "drivers/eisa/Kconfig"
+config TC
+        bool "TURBOchannel support"
+        depends on MACH_DECSTATION
+        help
+          TurboChannel is a DEC (now Compaq (now HP)) bus for Alpha and MIPS
+          processors.  Documentation on writing device drivers for TurboChannel
+          is available at:
+          <http://www.cs.arizona.edu/computer.help/policy/DIGITAL_unix/AA-PS3HD-TET1_html/TITLE.html>.
+#config ACCESSBUS
+#       bool "Access.Bus support"
+#       depends on TC
+config MMU
+        bool
+        default y
+config MCA
+        bool
+config SBUS
+        bool
+source "drivers/pcmcia/Kconfig"
+source "drivers/pci/hotplug/Kconfig"
+endmenu
+menu "Executable file formats"
+source "fs/Kconfig.binfmt"
+config TRAD_SIGNALS
+        bool
+        default y if MIPS32
+config BUILD_ELF64
+        bool "Use 64-bit ELF format for building"
+        depends on MIPS64
+        help
+          A 64-bit kernel is usually built using the 64-bit ELF binary object
+          format as it's one that allows arbitrary 64-bit constructs.  For
+          kernels that are loaded within the KSEG compatibility segments the
+          32-bit ELF format can optionally be used resulting in a somewhat
+          smaller binary, but this option is not explicitly supported by the
+          toolchain and since binutils 2.14 it does not even work at all.
+          Say Y to use the 64-bit format or N to use the 32-bit one.
+          If unsure say Y.
+config BINFMT_IRIX
+        bool "Include IRIX binary compatibility"
+        depends on !CPU_LITTLE_ENDIAN && MIPS32 && BROKEN
+config MIPS32_COMPAT
+        bool "Kernel support for Linux/MIPS 32-bit binary compatibility"
+        depends on MIPS64
+        help
+          Select this option if you want Linux/MIPS 32-bit binary
+          compatibility. Since all software available for Linux/MIPS is
+          currently 32-bit you should say Y here.
+config COMPAT
+        bool
+        depends on MIPS32_COMPAT
+        default y
+config MIPS32_O32
+        bool "Kernel support for o32 binaries"
+        depends on MIPS32_COMPAT
+        help
+          Select this option if you want to run o32 binaries.  These are pure
+          32-bit binaries as used by the 32-bit Linux/MIPS port.  Most of
+          existing binaries are in this format.
+          If unsure, say Y.
+config MIPS32_N32
+        bool "Kernel support for n32 binaries"
+        depends on MIPS32_COMPAT
+        help
+          Select this option if you want to run n32 binaries.  These are
+          64-bit binaries using 32-bit quantities for addressing and certain
+          data that would normally be 64-bit.  They are used in special
+          cases.
+          If unsure, say N.
+config BINFMT_ELF32
+        bool
+        default y if MIPS32_O32 || MIPS32_N32
+config PM
+        bool "Power Management support (EXPERIMENTAL)"
+        depends on EXPERIMENTAL && MACH_AU1X00
+endmenu
+source "drivers/Kconfig"
+source "fs/Kconfig"
+source "arch/mips/Kconfig.debug"
+source "security/Kconfig"
+source "crypto/Kconfig"
+source "lib/Kconfig"
+#
+# Use the generic interrupt handling code in kernel/irq/:
+#
+config GENERIC_HARDIRQS
+        bool
+        default y
+config GENERIC_IRQ_PROBE
+        bool
+        default y