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-rw-r--r--arch/microblaze/Kconfig27
-rw-r--r--arch/microblaze/Kconfig.debug4
-rw-r--r--arch/microblaze/Makefile2
-rw-r--r--arch/microblaze/boot/Makefile12
-rw-r--r--arch/microblaze/configs/mmu_defconfig3
-rw-r--r--arch/microblaze/configs/nommu_defconfig2
-rw-r--r--arch/microblaze/include/asm/cacheflush.h13
-rw-r--r--arch/microblaze/include/asm/cpuinfo.h4
-rw-r--r--arch/microblaze/include/asm/entry.h36
-rw-r--r--arch/microblaze/include/asm/exceptions.h3
-rw-r--r--arch/microblaze/include/asm/futex.h31
-rw-r--r--arch/microblaze/include/asm/irq.h2
-rw-r--r--arch/microblaze/include/asm/irqflags.h2
-rw-r--r--arch/microblaze/include/asm/pci-bridge.h12
-rw-r--r--arch/microblaze/include/asm/pgtable.h35
-rw-r--r--arch/microblaze/include/asm/processor.h2
-rw-r--r--arch/microblaze/include/asm/prom.h18
-rw-r--r--arch/microblaze/include/asm/ptrace.h14
-rw-r--r--arch/microblaze/include/asm/pvr.h185
-rw-r--r--arch/microblaze/include/asm/syscall.h3
-rw-r--r--arch/microblaze/include/asm/syscalls.h8
-rw-r--r--arch/microblaze/include/asm/tlb.h1
-rw-r--r--arch/microblaze/include/asm/uaccess.h8
-rw-r--r--arch/microblaze/include/asm/unaligned.h11
-rw-r--r--arch/microblaze/kernel/cpu/cache.c16
-rw-r--r--arch/microblaze/kernel/cpu/cpuinfo.c2
-rw-r--r--arch/microblaze/kernel/cpu/pvr.c4
-rw-r--r--arch/microblaze/kernel/dma.c1
-rw-r--r--arch/microblaze/kernel/entry-nommu.S4
-rw-r--r--arch/microblaze/kernel/entry.S359
-rw-r--r--arch/microblaze/kernel/exceptions.c5
-rw-r--r--arch/microblaze/kernel/head.S45
-rw-r--r--arch/microblaze/kernel/hw_exception_handler.S61
-rw-r--r--arch/microblaze/kernel/intc.c51
-rw-r--r--arch/microblaze/kernel/irq.c12
-rw-r--r--arch/microblaze/kernel/microblaze_ksyms.c12
-rw-r--r--arch/microblaze/kernel/process.c2
-rw-r--r--arch/microblaze/kernel/prom.c10
-rw-r--r--arch/microblaze/kernel/prom_parse.c115
-rw-r--r--arch/microblaze/kernel/ptrace.c3
-rw-r--r--arch/microblaze/kernel/setup.c16
-rw-r--r--arch/microblaze/kernel/signal.c8
-rw-r--r--arch/microblaze/kernel/sys_microblaze.c3
-rw-r--r--arch/microblaze/kernel/timer.c6
-rw-r--r--arch/microblaze/kernel/unwind.c2
-rw-r--r--arch/microblaze/kernel/vmlinux.lds.S21
-rw-r--r--arch/microblaze/lib/fastcopy.S4
-rw-r--r--arch/microblaze/lib/memmove.c2
-rw-r--r--arch/microblaze/lib/muldi3.S121
-rw-r--r--arch/microblaze/lib/muldi3.c61
-rw-r--r--arch/microblaze/mm/consistent.c2
-rw-r--r--arch/microblaze/mm/fault.c2
-rw-r--r--arch/microblaze/pci/pci-common.c1
-rw-r--r--arch/microblaze/pci/pci_32.c1
54 files changed, 638 insertions, 752 deletions
diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig
index 387d5ffdfd3a..922c4194c7bb 100644
--- a/arch/microblaze/Kconfig
+++ b/arch/microblaze/Kconfig
@@ -14,7 +14,10 @@ config MICROBLAZE
14 select HAVE_DMA_API_DEBUG 14 select HAVE_DMA_API_DEBUG
15 select TRACING_SUPPORT 15 select TRACING_SUPPORT
16 select OF 16 select OF
17 select OF_FLATTREE 17 select OF_EARLY_FLATTREE
18 select HAVE_GENERIC_HARDIRQS
19 select GENERIC_IRQ_PROBE
20 select GENERIC_HARDIRQS_NO_DEPRECATED
18 21
19config SWAP 22config SWAP
20 def_bool n 23 def_bool n
@@ -37,12 +40,6 @@ config GENERIC_FIND_NEXT_BIT
37config GENERIC_HWEIGHT 40config GENERIC_HWEIGHT
38 def_bool y 41 def_bool y
39 42
40config GENERIC_HARDIRQS
41 def_bool y
42
43config GENERIC_IRQ_PROBE
44 def_bool y
45
46config GENERIC_CALIBRATE_DELAY 43config GENERIC_CALIBRATE_DELAY
47 def_bool y 44 def_bool y
48 45
@@ -52,9 +49,6 @@ config GENERIC_TIME_VSYSCALL
52config GENERIC_CLOCKEVENTS 49config GENERIC_CLOCKEVENTS
53 def_bool y 50 def_bool y
54 51
55config GENERIC_HARDIRQS_NO__DO_IRQ
56 def_bool y
57
58config GENERIC_GPIO 52config GENERIC_GPIO
59 def_bool y 53 def_bool y
60 54
@@ -190,6 +184,17 @@ config LOWMEM_SIZE
190 hex "Maximum low memory size (in bytes)" if LOWMEM_SIZE_BOOL 184 hex "Maximum low memory size (in bytes)" if LOWMEM_SIZE_BOOL
191 default "0x30000000" 185 default "0x30000000"
192 186
187config MANUAL_RESET_VECTOR
188 hex "Microblaze reset vector address setup"
189 default "0x0"
190 help
191 Set this option to have the kernel override the CPU Reset vector.
192 If zero, no change will be made to the MicroBlaze reset vector at
193 address 0x0.
194 If non-zero, a jump instruction to this address, will be written
195 to the reset vector at address 0x0.
196 If you are unsure, set it to default value 0x0.
197
193config KERNEL_START_BOOL 198config KERNEL_START_BOOL
194 bool "Set custom kernel base address" 199 bool "Set custom kernel base address"
195 depends on ADVANCED_OPTIONS 200 depends on ADVANCED_OPTIONS
@@ -254,7 +259,7 @@ endmenu
254 259
255source "mm/Kconfig" 260source "mm/Kconfig"
256 261
257menu "Exectuable file formats" 262menu "Executable file formats"
258 263
259source "fs/Kconfig.binfmt" 264source "fs/Kconfig.binfmt"
260 265
diff --git a/arch/microblaze/Kconfig.debug b/arch/microblaze/Kconfig.debug
index e66e25c4b0b2..012e377330cd 100644
--- a/arch/microblaze/Kconfig.debug
+++ b/arch/microblaze/Kconfig.debug
@@ -23,8 +23,4 @@ config HEART_BEAT
23 This option turns on/off heart beat kernel functionality. 23 This option turns on/off heart beat kernel functionality.
24 First GPIO node is taken. 24 First GPIO node is taken.
25 25
26config DEBUG_BOOTMEM
27 depends on DEBUG_KERNEL
28 bool "Debug BOOTMEM initialization"
29
30endmenu 26endmenu
diff --git a/arch/microblaze/Makefile b/arch/microblaze/Makefile
index 15f1f1d1840d..6f432e6df9af 100644
--- a/arch/microblaze/Makefile
+++ b/arch/microblaze/Makefile
@@ -17,7 +17,7 @@ export CPU_VER CPU_MAJOR CPU_MINOR CPU_REV
17# The various CONFIG_XILINX cpu features options are integers 0/1/2... 17# The various CONFIG_XILINX cpu features options are integers 0/1/2...
18# rather than bools y/n 18# rather than bools y/n
19 19
20# Work out HW multipler support. This is icky. 20# Work out HW multipler support. This is tricky.
21# 1. Spartan2 has no HW multiplers. 21# 1. Spartan2 has no HW multiplers.
22# 2. MicroBlaze v3.x always uses them, except in Spartan 2 22# 2. MicroBlaze v3.x always uses them, except in Spartan 2
23# 3. All other FPGa/CPU ver combos, we can trust the CONFIG_ settings 23# 3. All other FPGa/CPU ver combos, we can trust the CONFIG_ settings
diff --git a/arch/microblaze/boot/Makefile b/arch/microblaze/boot/Makefile
index be01d78750d9..4c4e58ef0cb6 100644
--- a/arch/microblaze/boot/Makefile
+++ b/arch/microblaze/boot/Makefile
@@ -10,9 +10,6 @@ targets := linux.bin linux.bin.gz simpleImage.%
10 10
11OBJCOPYFLAGS := -O binary 11OBJCOPYFLAGS := -O binary
12 12
13# Where the DTS files live
14dtstree := $(srctree)/$(src)/dts
15
16# Ensure system.dtb exists 13# Ensure system.dtb exists
17$(obj)/linked_dtb.o: $(obj)/system.dtb 14$(obj)/linked_dtb.o: $(obj)/system.dtb
18 15
@@ -51,14 +48,11 @@ $(obj)/simpleImage.%: vmlinux FORCE
51 $(call if_changed,strip) 48 $(call if_changed,strip)
52 @echo 'Kernel: $@ is ready' ' (#'`cat .version`')' 49 @echo 'Kernel: $@ is ready' ' (#'`cat .version`')'
53 50
54# Rule to build device tree blobs
55DTC = $(objtree)/scripts/dtc/dtc
56 51
57# Rule to build device tree blobs 52# Rule to build device tree blobs
58quiet_cmd_dtc = DTC $@ 53DTC_FLAGS := -p 1024
59 cmd_dtc = $(DTC) -O dtb -o $(obj)/$*.dtb -b 0 -p 1024 $(dtstree)/$*.dts
60 54
61$(obj)/%.dtb: $(dtstree)/%.dts FORCE 55$(obj)/%.dtb: $(src)/dts/%.dts FORCE
62 $(call if_changed,dtc) 56 $(call cmd,dtc)
63 57
64clean-files += *.dtb simpleImage.*.unstrip linux.bin.ub 58clean-files += *.dtb simpleImage.*.unstrip linux.bin.ub
diff --git a/arch/microblaze/configs/mmu_defconfig b/arch/microblaze/configs/mmu_defconfig
index 8b422b12ef78..b3f5eecff2a7 100644
--- a/arch/microblaze/configs/mmu_defconfig
+++ b/arch/microblaze/configs/mmu_defconfig
@@ -7,7 +7,7 @@ CONFIG_BLK_DEV_INITRD=y
7CONFIG_INITRAMFS_SOURCE="rootfs.cpio" 7CONFIG_INITRAMFS_SOURCE="rootfs.cpio"
8CONFIG_INITRAMFS_COMPRESSION_GZIP=y 8CONFIG_INITRAMFS_COMPRESSION_GZIP=y
9# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 9# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
10CONFIG_EMBEDDED=y 10CONFIG_EXPERT=y
11CONFIG_KALLSYMS_ALL=y 11CONFIG_KALLSYMS_ALL=y
12CONFIG_KALLSYMS_EXTRA_PASS=y 12CONFIG_KALLSYMS_EXTRA_PASS=y
13# CONFIG_HOTPLUG is not set 13# CONFIG_HOTPLUG is not set
@@ -66,5 +66,4 @@ CONFIG_DEBUG_SPINLOCK=y
66CONFIG_DEBUG_INFO=y 66CONFIG_DEBUG_INFO=y
67# CONFIG_RCU_CPU_STALL_DETECTOR is not set 67# CONFIG_RCU_CPU_STALL_DETECTOR is not set
68CONFIG_EARLY_PRINTK=y 68CONFIG_EARLY_PRINTK=y
69CONFIG_DEBUG_BOOTMEM=y
70# CONFIG_CRYPTO_ANSI_CPRNG is not set 69# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/microblaze/configs/nommu_defconfig b/arch/microblaze/configs/nommu_defconfig
index ebc143c5368e..0249e4b7e1d3 100644
--- a/arch/microblaze/configs/nommu_defconfig
+++ b/arch/microblaze/configs/nommu_defconfig
@@ -6,7 +6,7 @@ CONFIG_BSD_PROCESS_ACCT_V3=y
6CONFIG_IKCONFIG=y 6CONFIG_IKCONFIG=y
7CONFIG_IKCONFIG_PROC=y 7CONFIG_IKCONFIG_PROC=y
8CONFIG_SYSFS_DEPRECATED_V2=y 8CONFIG_SYSFS_DEPRECATED_V2=y
9CONFIG_EMBEDDED=y 9CONFIG_EXPERT=y
10CONFIG_KALLSYMS_ALL=y 10CONFIG_KALLSYMS_ALL=y
11CONFIG_KALLSYMS_EXTRA_PASS=y 11CONFIG_KALLSYMS_EXTRA_PASS=y
12# CONFIG_HOTPLUG is not set 12# CONFIG_HOTPLUG is not set
diff --git a/arch/microblaze/include/asm/cacheflush.h b/arch/microblaze/include/asm/cacheflush.h
index 7ebd955460d9..0f553bc009a0 100644
--- a/arch/microblaze/include/asm/cacheflush.h
+++ b/arch/microblaze/include/asm/cacheflush.h
@@ -84,12 +84,13 @@ do { \
84#define flush_dcache_mmap_lock(mapping) do { } while (0) 84#define flush_dcache_mmap_lock(mapping) do { } while (0)
85#define flush_dcache_mmap_unlock(mapping) do { } while (0) 85#define flush_dcache_mmap_unlock(mapping) do { } while (0)
86 86
87
88#define flush_cache_dup_mm(mm) do { } while (0) 87#define flush_cache_dup_mm(mm) do { } while (0)
89#define flush_cache_vmap(start, end) do { } while (0) 88#define flush_cache_vmap(start, end) do { } while (0)
90#define flush_cache_vunmap(start, end) do { } while (0) 89#define flush_cache_vunmap(start, end) do { } while (0)
91#define flush_cache_mm(mm) do { } while (0) 90#define flush_cache_mm(mm) do { } while (0)
92#define flush_cache_page(vma, vmaddr, pfn) do { } while (0) 91
92#define flush_cache_page(vma, vmaddr, pfn) \
93 flush_dcache_range(pfn << PAGE_SHIFT, (pfn << PAGE_SHIFT) + PAGE_SIZE);
93 94
94/* MS: kgdb code use this macro, wrong len with FLASH */ 95/* MS: kgdb code use this macro, wrong len with FLASH */
95#if 0 96#if 0
@@ -104,9 +105,13 @@ do { \
104#define copy_to_user_page(vma, page, vaddr, dst, src, len) \ 105#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
105do { \ 106do { \
106 u32 addr = virt_to_phys(dst); \ 107 u32 addr = virt_to_phys(dst); \
107 invalidate_icache_range((unsigned) (addr), (unsigned) (addr) + (len));\
108 memcpy((dst), (src), (len)); \ 108 memcpy((dst), (src), (len)); \
109 flush_dcache_range((unsigned) (addr), (unsigned) (addr) + (len));\ 109 if (vma->vm_flags & VM_EXEC) { \
110 invalidate_icache_range((unsigned) (addr), \
111 (unsigned) (addr) + PAGE_SIZE); \
112 flush_dcache_range((unsigned) (addr), \
113 (unsigned) (addr) + PAGE_SIZE); \
114 } \
110} while (0) 115} while (0)
111 116
112#define copy_from_user_page(vma, page, vaddr, dst, src, len) \ 117#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
diff --git a/arch/microblaze/include/asm/cpuinfo.h b/arch/microblaze/include/asm/cpuinfo.h
index cd257537ae54..d8f013347a9e 100644
--- a/arch/microblaze/include/asm/cpuinfo.h
+++ b/arch/microblaze/include/asm/cpuinfo.h
@@ -96,8 +96,8 @@ void set_cpuinfo_pvr_full(struct cpuinfo *ci, struct device_node *cpu);
96 96
97static inline unsigned int fcpu(struct device_node *cpu, char *n) 97static inline unsigned int fcpu(struct device_node *cpu, char *n)
98{ 98{
99 int *val; 99 const __be32 *val;
100 return (val = (int *) of_get_property(cpu, n, NULL)) ? 100 return (val = of_get_property(cpu, n, NULL)) ?
101 be32_to_cpup(val) : 0; 101 be32_to_cpup(val) : 0;
102} 102}
103 103
diff --git a/arch/microblaze/include/asm/entry.h b/arch/microblaze/include/asm/entry.h
index ec89f2ad0fe1..af0144b91b79 100644
--- a/arch/microblaze/include/asm/entry.h
+++ b/arch/microblaze/include/asm/entry.h
@@ -31,40 +31,4 @@ DECLARE_PER_CPU(unsigned int, R11_SAVE); /* Temp variable for entry */
31DECLARE_PER_CPU(unsigned int, CURRENT_SAVE); /* Saved current pointer */ 31DECLARE_PER_CPU(unsigned int, CURRENT_SAVE); /* Saved current pointer */
32# endif /* __ASSEMBLY__ */ 32# endif /* __ASSEMBLY__ */
33 33
34#ifndef CONFIG_MMU
35
36/* noMMU hasn't any space for args */
37# define STATE_SAVE_ARG_SPACE (0)
38
39#else /* CONFIG_MMU */
40
41/* If true, system calls save and restore all registers (except result
42 * registers, of course). If false, then `call clobbered' registers
43 * will not be preserved, on the theory that system calls are basically
44 * function calls anyway, and the caller should be able to deal with it.
45 * This is a security risk, of course, as `internal' values may leak out
46 * after a system call, but that certainly doesn't matter very much for
47 * a processor with no MMU protection! For a protected-mode kernel, it
48 * would be faster to just zero those registers before returning.
49 *
50 * I can not rely on the glibc implementation. If you turn it off make
51 * sure that r11/r12 is saved in user-space. --KAA
52 *
53 * These are special variables using by the kernel trap/interrupt code
54 * to save registers in, at a time when there are no spare registers we
55 * can use to do so, and we can't depend on the value of the stack
56 * pointer. This means that they must be within a signed 16-bit
57 * displacement of 0x00000000.
58 */
59
60/* A `state save frame' is a struct pt_regs preceded by some extra space
61 * suitable for a function call stack frame. */
62
63/* Amount of room on the stack reserved for arguments and to satisfy the
64 * C calling conventions, in addition to the space used by the struct
65 * pt_regs that actually holds saved values. */
66#define STATE_SAVE_ARG_SPACE (6*4) /* Up to six arguments */
67
68#endif /* CONFIG_MMU */
69
70#endif /* _ASM_MICROBLAZE_ENTRY_H */ 34#endif /* _ASM_MICROBLAZE_ENTRY_H */
diff --git a/arch/microblaze/include/asm/exceptions.h b/arch/microblaze/include/asm/exceptions.h
index 6479097b802b..e6a8ddea1dca 100644
--- a/arch/microblaze/include/asm/exceptions.h
+++ b/arch/microblaze/include/asm/exceptions.h
@@ -66,6 +66,9 @@
66asmlinkage void full_exception(struct pt_regs *regs, unsigned int type, 66asmlinkage void full_exception(struct pt_regs *regs, unsigned int type,
67 int fsr, int addr); 67 int fsr, int addr);
68 68
69asmlinkage void sw_exception(struct pt_regs *regs);
70void bad_page_fault(struct pt_regs *regs, unsigned long address, int sig);
71
69void die(const char *str, struct pt_regs *fp, long err); 72void die(const char *str, struct pt_regs *fp, long err);
70void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr); 73void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr);
71 74
diff --git a/arch/microblaze/include/asm/futex.h b/arch/microblaze/include/asm/futex.h
index ad3fd61b2fe7..b0526d2716fa 100644
--- a/arch/microblaze/include/asm/futex.h
+++ b/arch/microblaze/include/asm/futex.h
@@ -29,7 +29,7 @@
29}) 29})
30 30
31static inline int 31static inline int
32futex_atomic_op_inuser(int encoded_op, int __user *uaddr) 32futex_atomic_op_inuser(int encoded_op, u32 __user *uaddr)
33{ 33{
34 int op = (encoded_op >> 28) & 7; 34 int op = (encoded_op >> 28) & 7;
35 int cmp = (encoded_op >> 24) & 15; 35 int cmp = (encoded_op >> 24) & 15;
@@ -39,7 +39,7 @@ futex_atomic_op_inuser(int encoded_op, int __user *uaddr)
39 if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28)) 39 if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
40 oparg = 1 << oparg; 40 oparg = 1 << oparg;
41 41
42 if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int))) 42 if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32)))
43 return -EFAULT; 43 return -EFAULT;
44 44
45 pagefault_disable(); 45 pagefault_disable();
@@ -94,31 +94,34 @@ futex_atomic_op_inuser(int encoded_op, int __user *uaddr)
94} 94}
95 95
96static inline int 96static inline int
97futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval) 97futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
98 u32 oldval, u32 newval)
98{ 99{
99 int prev, cmp; 100 int ret = 0, cmp;
101 u32 prev;
100 102
101 if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int))) 103 if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32)))
102 return -EFAULT; 104 return -EFAULT;
103 105
104 __asm__ __volatile__ ("1: lwx %0, %2, r0; \ 106 __asm__ __volatile__ ("1: lwx %1, %3, r0; \
105 cmp %1, %0, %3; \ 107 cmp %2, %1, %4; \
106 beqi %1, 3f; \ 108 beqi %2, 3f; \
107 2: swx %4, %2, r0; \ 109 2: swx %5, %3, r0; \
108 addic %1, r0, 0; \ 110 addic %2, r0, 0; \
109 bnei %1, 1b; \ 111 bnei %2, 1b; \
110 3: \ 112 3: \
111 .section .fixup,\"ax\"; \ 113 .section .fixup,\"ax\"; \
112 4: brid 3b; \ 114 4: brid 3b; \
113 addik %0, r0, %5; \ 115 addik %0, r0, %6; \
114 .previous; \ 116 .previous; \
115 .section __ex_table,\"a\"; \ 117 .section __ex_table,\"a\"; \
116 .word 1b,4b,2b,4b; \ 118 .word 1b,4b,2b,4b; \
117 .previous;" \ 119 .previous;" \
118 : "=&r" (prev), "=&r"(cmp) \ 120 : "+r" (ret), "=&r" (prev), "=&r"(cmp) \
119 : "r" (uaddr), "r" (oldval), "r" (newval), "i" (-EFAULT)); 121 : "r" (uaddr), "r" (oldval), "r" (newval), "i" (-EFAULT));
120 122
121 return prev; 123 *uval = prev;
124 return ret;
122} 125}
123 126
124#endif /* __KERNEL__ */ 127#endif /* __KERNEL__ */
diff --git a/arch/microblaze/include/asm/irq.h b/arch/microblaze/include/asm/irq.h
index ec5583d6111c..cc54187f3d38 100644
--- a/arch/microblaze/include/asm/irq.h
+++ b/arch/microblaze/include/asm/irq.h
@@ -12,8 +12,6 @@
12#define NR_IRQS 32 12#define NR_IRQS 32
13#include <asm-generic/irq.h> 13#include <asm-generic/irq.h>
14 14
15#include <linux/interrupt.h>
16
17/* This type is the placeholder for a hardware interrupt number. It has to 15/* This type is the placeholder for a hardware interrupt number. It has to
18 * be big enough to enclose whatever representation is used by a given 16 * be big enough to enclose whatever representation is used by a given
19 * platform. 17 * platform.
diff --git a/arch/microblaze/include/asm/irqflags.h b/arch/microblaze/include/asm/irqflags.h
index 5fd31905775d..c4532f032b3b 100644
--- a/arch/microblaze/include/asm/irqflags.h
+++ b/arch/microblaze/include/asm/irqflags.h
@@ -12,7 +12,7 @@
12#include <linux/types.h> 12#include <linux/types.h>
13#include <asm/registers.h> 13#include <asm/registers.h>
14 14
15#ifdef CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR 15#if CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR
16 16
17static inline unsigned long arch_local_irq_save(void) 17static inline unsigned long arch_local_irq_save(void)
18{ 18{
diff --git a/arch/microblaze/include/asm/pci-bridge.h b/arch/microblaze/include/asm/pci-bridge.h
index 0c68764ab547..10717669e0c2 100644
--- a/arch/microblaze/include/asm/pci-bridge.h
+++ b/arch/microblaze/include/asm/pci-bridge.h
@@ -104,11 +104,22 @@ struct pci_controller {
104 int global_number; /* PCI domain number */ 104 int global_number; /* PCI domain number */
105}; 105};
106 106
107#ifdef CONFIG_PCI
107static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus) 108static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus)
108{ 109{
109 return bus->sysdata; 110 return bus->sysdata;
110} 111}
111 112
113static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
114{
115 struct pci_controller *host;
116
117 if (bus->self)
118 return pci_device_to_OF_node(bus->self);
119 host = pci_bus_to_host(bus);
120 return host ? host->dn : NULL;
121}
122
112static inline int isa_vaddr_is_ioport(void __iomem *address) 123static inline int isa_vaddr_is_ioport(void __iomem *address)
113{ 124{
114 /* No specific ISA handling on ppc32 at this stage, it 125 /* No specific ISA handling on ppc32 at this stage, it
@@ -116,6 +127,7 @@ static inline int isa_vaddr_is_ioport(void __iomem *address)
116 */ 127 */
117 return 0; 128 return 0;
118} 129}
130#endif /* CONFIG_PCI */
119 131
120/* These are used for config access before all the PCI probing 132/* These are used for config access before all the PCI probing
121 has been done. */ 133 has been done. */
diff --git a/arch/microblaze/include/asm/pgtable.h b/arch/microblaze/include/asm/pgtable.h
index cae268c22ba2..b2af42311a12 100644
--- a/arch/microblaze/include/asm/pgtable.h
+++ b/arch/microblaze/include/asm/pgtable.h
@@ -411,20 +411,19 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
411static inline unsigned long pte_update(pte_t *p, unsigned long clr, 411static inline unsigned long pte_update(pte_t *p, unsigned long clr,
412 unsigned long set) 412 unsigned long set)
413{ 413{
414 unsigned long old, tmp, msr; 414 unsigned long flags, old, tmp;
415 415
416 __asm__ __volatile__("\ 416 raw_local_irq_save(flags);
417 msrclr %2, 0x2\n\ 417
418 nop\n\ 418 __asm__ __volatile__( "lw %0, %2, r0 \n"
419 lw %0, %4, r0\n\ 419 "andn %1, %0, %3 \n"
420 andn %1, %0, %5\n\ 420 "or %1, %1, %4 \n"
421 or %1, %1, %6\n\ 421 "sw %1, %2, r0 \n"
422 sw %1, %4, r0\n\ 422 : "=&r" (old), "=&r" (tmp)
423 mts rmsr, %2\n\ 423 : "r" ((unsigned long)(p + 1) - 4), "r" (clr), "r" (set)
424 nop" 424 : "cc");
425 : "=&r" (old), "=&r" (tmp), "=&r" (msr), "=m" (*p) 425
426 : "r" ((unsigned long)(p + 1) - 4), "r" (clr), "r" (set), "m" (*p) 426 raw_local_irq_restore(flags);
427 : "cc");
428 427
429 return old; 428 return old;
430} 429}
@@ -444,8 +443,9 @@ static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
444 *ptep = pte; 443 *ptep = pte;
445} 444}
446 445
447static inline int ptep_test_and_clear_young(struct mm_struct *mm, 446#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
448 unsigned long addr, pte_t *ptep) 447static inline int ptep_test_and_clear_young(struct vm_area_struct *vma,
448 unsigned long address, pte_t *ptep)
449{ 449{
450 return (pte_update(ptep, _PAGE_ACCESSED, 0) & _PAGE_ACCESSED) != 0; 450 return (pte_update(ptep, _PAGE_ACCESSED, 0) & _PAGE_ACCESSED) != 0;
451} 451}
@@ -457,6 +457,7 @@ static inline int ptep_test_and_clear_dirty(struct mm_struct *mm,
457 (_PAGE_DIRTY | _PAGE_HWWRITE), 0) & _PAGE_DIRTY) != 0; 457 (_PAGE_DIRTY | _PAGE_HWWRITE), 0) & _PAGE_DIRTY) != 0;
458} 458}
459 459
460#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
460static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 461static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
461 unsigned long addr, pte_t *ptep) 462 unsigned long addr, pte_t *ptep)
462{ 463{
@@ -571,7 +572,7 @@ void __init *early_get_page(void);
571 572
572extern unsigned long ioremap_bot, ioremap_base; 573extern unsigned long ioremap_bot, ioremap_base;
573 574
574void *consistent_alloc(int gfp, size_t size, dma_addr_t *dma_handle); 575void *consistent_alloc(gfp_t gfp, size_t size, dma_addr_t *dma_handle);
575void consistent_free(size_t size, void *vaddr); 576void consistent_free(size_t size, void *vaddr);
576void consistent_sync(void *vaddr, size_t size, int direction); 577void consistent_sync(void *vaddr, size_t size, int direction);
577void consistent_sync_page(struct page *page, unsigned long offset, 578void consistent_sync_page(struct page *page, unsigned long offset,
diff --git a/arch/microblaze/include/asm/processor.h b/arch/microblaze/include/asm/processor.h
index 8eeb09211ece..aed2a6be8e27 100644
--- a/arch/microblaze/include/asm/processor.h
+++ b/arch/microblaze/include/asm/processor.h
@@ -155,7 +155,7 @@ unsigned long get_wchan(struct task_struct *p);
155# define task_regs(task) ((struct pt_regs *)task_tos(task) - 1) 155# define task_regs(task) ((struct pt_regs *)task_tos(task) - 1)
156 156
157# define task_pt_regs_plus_args(tsk) \ 157# define task_pt_regs_plus_args(tsk) \
158 (((void *)task_pt_regs(tsk)) - STATE_SAVE_ARG_SPACE) 158 ((void *)task_pt_regs(tsk))
159 159
160# define task_sp(task) (task_regs(task)->r1) 160# define task_sp(task) (task_regs(task)->r1)
161# define task_pc(task) (task_regs(task)->pc) 161# define task_pc(task) (task_regs(task)->pc)
diff --git a/arch/microblaze/include/asm/prom.h b/arch/microblaze/include/asm/prom.h
index bdc38312ae4a..d0890d36ef61 100644
--- a/arch/microblaze/include/asm/prom.h
+++ b/arch/microblaze/include/asm/prom.h
@@ -64,24 +64,6 @@ extern void kdump_move_device_tree(void);
64/* CPU OF node matching */ 64/* CPU OF node matching */
65struct device_node *of_get_cpu_node(int cpu, unsigned int *thread); 65struct device_node *of_get_cpu_node(int cpu, unsigned int *thread);
66 66
67/* Get the MAC address */
68extern const void *of_get_mac_address(struct device_node *np);
69
70/**
71 * of_irq_map_pci - Resolve the interrupt for a PCI device
72 * @pdev: the device whose interrupt is to be resolved
73 * @out_irq: structure of_irq filled by this function
74 *
75 * This function resolves the PCI interrupt for a given PCI device. If a
76 * device-node exists for a given pci_dev, it will use normal OF tree
77 * walking. If not, it will implement standard swizzling and walk up the
78 * PCI tree until an device-node is found, at which point it will finish
79 * resolving using the OF tree walking.
80 */
81struct pci_dev;
82struct of_irq;
83extern int of_irq_map_pci(struct pci_dev *pdev, struct of_irq *out_irq);
84
85#endif /* __ASSEMBLY__ */ 67#endif /* __ASSEMBLY__ */
86#endif /* __KERNEL__ */ 68#endif /* __KERNEL__ */
87 69
diff --git a/arch/microblaze/include/asm/ptrace.h b/arch/microblaze/include/asm/ptrace.h
index d74dbfb92c04..d9b66304d5dd 100644
--- a/arch/microblaze/include/asm/ptrace.h
+++ b/arch/microblaze/include/asm/ptrace.h
@@ -66,13 +66,13 @@ void show_regs(struct pt_regs *);
66#else /* __KERNEL__ */ 66#else /* __KERNEL__ */
67 67
68/* pt_regs offsets used by gdbserver etc in ptrace syscalls */ 68/* pt_regs offsets used by gdbserver etc in ptrace syscalls */
69#define PT_GPR(n) ((n) * sizeof(microblaze_reg_t)) 69#define PT_GPR(n) ((n) * sizeof(microblaze_reg_t))
70#define PT_PC (32 * sizeof(microblaze_reg_t)) 70#define PT_PC (32 * sizeof(microblaze_reg_t))
71#define PT_MSR (33 * sizeof(microblaze_reg_t)) 71#define PT_MSR (33 * sizeof(microblaze_reg_t))
72#define PT_EAR (34 * sizeof(microblaze_reg_t)) 72#define PT_EAR (34 * sizeof(microblaze_reg_t))
73#define PT_ESR (35 * sizeof(microblaze_reg_t)) 73#define PT_ESR (35 * sizeof(microblaze_reg_t))
74#define PT_FSR (36 * sizeof(microblaze_reg_t)) 74#define PT_FSR (36 * sizeof(microblaze_reg_t))
75#define PT_KERNEL_MODE (37 * sizeof(microblaze_reg_t)) 75#define PT_KERNEL_MODE (37 * sizeof(microblaze_reg_t))
76 76
77#endif /* __KERNEL */ 77#endif /* __KERNEL */
78 78
diff --git a/arch/microblaze/include/asm/pvr.h b/arch/microblaze/include/asm/pvr.h
index 37db96a15b45..a10bec62e857 100644
--- a/arch/microblaze/include/asm/pvr.h
+++ b/arch/microblaze/include/asm/pvr.h
@@ -1,9 +1,9 @@
1/* 1/*
2 * Support for the MicroBlaze PVR (Processor Version Register) 2 * Support for the MicroBlaze PVR (Processor Version Register)
3 * 3 *
4 * Copyright (C) 2009 Michal Simek <monstr@monstr.eu> 4 * Copyright (C) 2009 - 2011 Michal Simek <monstr@monstr.eu>
5 * Copyright (C) 2007 John Williams <john.williams@petalogix.com> 5 * Copyright (C) 2007 John Williams <john.williams@petalogix.com>
6 * Copyright (C) 2007 - 2009 PetaLogix 6 * Copyright (C) 2007 - 2011 PetaLogix
7 * 7 *
8 * This file is subject to the terms and conditions of the GNU General 8 * This file is subject to the terms and conditions of the GNU General
9 * Public License. See the file COPYING in the main directory of this 9 * Public License. See the file COPYING in the main directory of this
@@ -46,11 +46,11 @@ struct pvr_s {
46#define PVR2_I_LMB_MASK 0x10000000 46#define PVR2_I_LMB_MASK 0x10000000
47#define PVR2_INTERRUPT_IS_EDGE_MASK 0x08000000 47#define PVR2_INTERRUPT_IS_EDGE_MASK 0x08000000
48#define PVR2_EDGE_IS_POSITIVE_MASK 0x04000000 48#define PVR2_EDGE_IS_POSITIVE_MASK 0x04000000
49#define PVR2_D_PLB_MASK 0x02000000 /* new */ 49#define PVR2_D_PLB_MASK 0x02000000 /* new */
50#define PVR2_I_PLB_MASK 0x01000000 /* new */ 50#define PVR2_I_PLB_MASK 0x01000000 /* new */
51#define PVR2_INTERCONNECT 0x00800000 /* new */ 51#define PVR2_INTERCONNECT 0x00800000 /* new */
52#define PVR2_USE_EXTEND_FSL 0x00080000 /* new */ 52#define PVR2_USE_EXTEND_FSL 0x00080000 /* new */
53#define PVR2_USE_FSL_EXC 0x00040000 /* new */ 53#define PVR2_USE_FSL_EXC 0x00040000 /* new */
54#define PVR2_USE_MSR_INSTR 0x00020000 54#define PVR2_USE_MSR_INSTR 0x00020000
55#define PVR2_USE_PCMP_INSTR 0x00010000 55#define PVR2_USE_PCMP_INSTR 0x00010000
56#define PVR2_AREA_OPTIMISED 0x00008000 56#define PVR2_AREA_OPTIMISED 0x00008000
@@ -59,7 +59,7 @@ struct pvr_s {
59#define PVR2_USE_HW_MUL_MASK 0x00001000 59#define PVR2_USE_HW_MUL_MASK 0x00001000
60#define PVR2_USE_FPU_MASK 0x00000800 60#define PVR2_USE_FPU_MASK 0x00000800
61#define PVR2_USE_MUL64_MASK 0x00000400 61#define PVR2_USE_MUL64_MASK 0x00000400
62#define PVR2_USE_FPU2_MASK 0x00000200 /* new */ 62#define PVR2_USE_FPU2_MASK 0x00000200 /* new */
63#define PVR2_USE_IPLBEXC 0x00000100 63#define PVR2_USE_IPLBEXC 0x00000100
64#define PVR2_USE_DPLBEXC 0x00000080 64#define PVR2_USE_DPLBEXC 0x00000080
65#define PVR2_OPCODE_0x0_ILL_MASK 0x00000040 65#define PVR2_OPCODE_0x0_ILL_MASK 0x00000040
@@ -122,96 +122,103 @@ struct pvr_s {
122 122
123 123
124/* PVR access macros */ 124/* PVR access macros */
125#define PVR_IS_FULL(pvr) (pvr.pvr[0] & PVR0_PVR_FULL_MASK) 125#define PVR_IS_FULL(_pvr) (_pvr.pvr[0] & PVR0_PVR_FULL_MASK)
126#define PVR_USE_BARREL(pvr) (pvr.pvr[0] & PVR0_USE_BARREL_MASK) 126#define PVR_USE_BARREL(_pvr) (_pvr.pvr[0] & PVR0_USE_BARREL_MASK)
127#define PVR_USE_DIV(pvr) (pvr.pvr[0] & PVR0_USE_DIV_MASK) 127#define PVR_USE_DIV(_pvr) (_pvr.pvr[0] & PVR0_USE_DIV_MASK)
128#define PVR_USE_HW_MUL(pvr) (pvr.pvr[0] & PVR0_USE_HW_MUL_MASK) 128#define PVR_USE_HW_MUL(_pvr) (_pvr.pvr[0] & PVR0_USE_HW_MUL_MASK)
129#define PVR_USE_FPU(pvr) (pvr.pvr[0] & PVR0_USE_FPU_MASK) 129#define PVR_USE_FPU(_pvr) (_pvr.pvr[0] & PVR0_USE_FPU_MASK)
130#define PVR_USE_FPU2(pvr) (pvr.pvr[2] & PVR2_USE_FPU2_MASK) 130#define PVR_USE_FPU2(_pvr) (_pvr.pvr[2] & PVR2_USE_FPU2_MASK)
131#define PVR_USE_ICACHE(pvr) (pvr.pvr[0] & PVR0_USE_ICACHE_MASK) 131#define PVR_USE_ICACHE(_pvr) (_pvr.pvr[0] & PVR0_USE_ICACHE_MASK)
132#define PVR_USE_DCACHE(pvr) (pvr.pvr[0] & PVR0_USE_DCACHE_MASK) 132#define PVR_USE_DCACHE(_pvr) (_pvr.pvr[0] & PVR0_USE_DCACHE_MASK)
133#define PVR_VERSION(pvr) ((pvr.pvr[0] & PVR0_VERSION_MASK) >> 8) 133#define PVR_VERSION(_pvr) ((_pvr.pvr[0] & PVR0_VERSION_MASK) >> 8)
134#define PVR_USER1(pvr) (pvr.pvr[0] & PVR0_USER1_MASK) 134#define PVR_USER1(_pvr) (_pvr.pvr[0] & PVR0_USER1_MASK)
135#define PVR_USER2(pvr) (pvr.pvr[1] & PVR1_USER2_MASK) 135#define PVR_USER2(_pvr) (_pvr.pvr[1] & PVR1_USER2_MASK)
136 136
137#define PVR_D_OPB(pvr) (pvr.pvr[2] & PVR2_D_OPB_MASK) 137#define PVR_D_OPB(_pvr) (_pvr.pvr[2] & PVR2_D_OPB_MASK)
138#define PVR_D_LMB(pvr) (pvr.pvr[2] & PVR2_D_LMB_MASK) 138#define PVR_D_LMB(_pvr) (_pvr.pvr[2] & PVR2_D_LMB_MASK)
139#define PVR_I_OPB(pvr) (pvr.pvr[2] & PVR2_I_OPB_MASK) 139#define PVR_I_OPB(_pvr) (_pvr.pvr[2] & PVR2_I_OPB_MASK)
140#define PVR_I_LMB(pvr) (pvr.pvr[2] & PVR2_I_LMB_MASK) 140#define PVR_I_LMB(_pvr) (_pvr.pvr[2] & PVR2_I_LMB_MASK)
141#define PVR_INTERRUPT_IS_EDGE(pvr) \ 141#define PVR_INTERRUPT_IS_EDGE(_pvr) \
142 (pvr.pvr[2] & PVR2_INTERRUPT_IS_EDGE_MASK) 142 (_pvr.pvr[2] & PVR2_INTERRUPT_IS_EDGE_MASK)
143#define PVR_EDGE_IS_POSITIVE(pvr) \ 143#define PVR_EDGE_IS_POSITIVE(_pvr) \
144 (pvr.pvr[2] & PVR2_EDGE_IS_POSITIVE_MASK) 144 (_pvr.pvr[2] & PVR2_EDGE_IS_POSITIVE_MASK)
145#define PVR_USE_MSR_INSTR(pvr) (pvr.pvr[2] & PVR2_USE_MSR_INSTR) 145#define PVR_USE_MSR_INSTR(_pvr) (_pvr.pvr[2] & PVR2_USE_MSR_INSTR)
146#define PVR_USE_PCMP_INSTR(pvr) (pvr.pvr[2] & PVR2_USE_PCMP_INSTR) 146#define PVR_USE_PCMP_INSTR(_pvr) (_pvr.pvr[2] & PVR2_USE_PCMP_INSTR)
147#define PVR_AREA_OPTIMISED(pvr) (pvr.pvr[2] & PVR2_AREA_OPTIMISED) 147#define PVR_AREA_OPTIMISED(_pvr) (_pvr.pvr[2] & PVR2_AREA_OPTIMISED)
148#define PVR_USE_MUL64(pvr) (pvr.pvr[2] & PVR2_USE_MUL64_MASK) 148#define PVR_USE_MUL64(_pvr) (_pvr.pvr[2] & PVR2_USE_MUL64_MASK)
149#define PVR_OPCODE_0x0_ILLEGAL(pvr) \ 149#define PVR_OPCODE_0x0_ILLEGAL(_pvr) \
150 (pvr.pvr[2] & PVR2_OPCODE_0x0_ILL_MASK) 150 (_pvr.pvr[2] & PVR2_OPCODE_0x0_ILL_MASK)
151#define PVR_UNALIGNED_EXCEPTION(pvr) \ 151#define PVR_UNALIGNED_EXCEPTION(_pvr) \
152 (pvr.pvr[2] & PVR2_UNALIGNED_EXC_MASK) 152 (_pvr.pvr[2] & PVR2_UNALIGNED_EXC_MASK)
153#define PVR_ILL_OPCODE_EXCEPTION(pvr) \ 153#define PVR_ILL_OPCODE_EXCEPTION(_pvr) \
154 (pvr.pvr[2] & PVR2_ILL_OPCODE_EXC_MASK) 154 (_pvr.pvr[2] & PVR2_ILL_OPCODE_EXC_MASK)
155#define PVR_IOPB_BUS_EXCEPTION(pvr) \ 155#define PVR_IOPB_BUS_EXCEPTION(_pvr) \
156 (pvr.pvr[2] & PVR2_IOPB_BUS_EXC_MASK) 156 (_pvr.pvr[2] & PVR2_IOPB_BUS_EXC_MASK)
157#define PVR_DOPB_BUS_EXCEPTION(pvr) \ 157#define PVR_DOPB_BUS_EXCEPTION(_pvr) \
158 (pvr.pvr[2] & PVR2_DOPB_BUS_EXC_MASK) 158 (_pvr.pvr[2] & PVR2_DOPB_BUS_EXC_MASK)
159#define PVR_DIV_ZERO_EXCEPTION(pvr) \ 159#define PVR_DIV_ZERO_EXCEPTION(_pvr) \
160 (pvr.pvr[2] & PVR2_DIV_ZERO_EXC_MASK) 160 (_pvr.pvr[2] & PVR2_DIV_ZERO_EXC_MASK)
161#define PVR_FPU_EXCEPTION(pvr) (pvr.pvr[2] & PVR2_FPU_EXC_MASK) 161#define PVR_FPU_EXCEPTION(_pvr) (_pvr.pvr[2] & PVR2_FPU_EXC_MASK)
162#define PVR_FSL_EXCEPTION(pvr) (pvr.pvr[2] & PVR2_USE_EXTEND_FSL) 162#define PVR_FSL_EXCEPTION(_pvr) (_pvr.pvr[2] & PVR2_USE_EXTEND_FSL)
163 163
164#define PVR_DEBUG_ENABLED(pvr) (pvr.pvr[3] & PVR3_DEBUG_ENABLED_MASK) 164#define PVR_DEBUG_ENABLED(_pvr) (_pvr.pvr[3] & PVR3_DEBUG_ENABLED_MASK)
165#define PVR_NUMBER_OF_PC_BRK(pvr) \ 165#define PVR_NUMBER_OF_PC_BRK(_pvr) \
166 ((pvr.pvr[3] & PVR3_NUMBER_OF_PC_BRK_MASK) >> 25) 166 ((_pvr.pvr[3] & PVR3_NUMBER_OF_PC_BRK_MASK) >> 25)
167#define PVR_NUMBER_OF_RD_ADDR_BRK(pvr) \ 167#define PVR_NUMBER_OF_RD_ADDR_BRK(_pvr) \
168 ((pvr.pvr[3] & PVR3_NUMBER_OF_RD_ADDR_BRK_MASK) >> 19) 168 ((_pvr.pvr[3] & PVR3_NUMBER_OF_RD_ADDR_BRK_MASK) >> 19)
169#define PVR_NUMBER_OF_WR_ADDR_BRK(pvr) \ 169#define PVR_NUMBER_OF_WR_ADDR_BRK(_pvr) \
170 ((pvr.pvr[3] & PVR3_NUMBER_OF_WR_ADDR_BRK_MASK) >> 13) 170 ((_pvr.pvr[3] & PVR3_NUMBER_OF_WR_ADDR_BRK_MASK) >> 13)
171#define PVR_FSL_LINKS(pvr) ((pvr.pvr[3] & PVR3_FSL_LINKS_MASK) >> 7) 171#define PVR_FSL_LINKS(_pvr) ((_pvr.pvr[3] & PVR3_FSL_LINKS_MASK) >> 7)
172 172
173#define PVR_ICACHE_ADDR_TAG_BITS(pvr) \ 173#define PVR_ICACHE_ADDR_TAG_BITS(_pvr) \
174 ((pvr.pvr[4] & PVR4_ICACHE_ADDR_TAG_BITS_MASK) >> 26) 174 ((_pvr.pvr[4] & PVR4_ICACHE_ADDR_TAG_BITS_MASK) >> 26)
175#define PVR_ICACHE_USE_FSL(pvr) (pvr.pvr[4] & PVR4_ICACHE_USE_FSL_MASK) 175#define PVR_ICACHE_USE_FSL(_pvr) \
176#define PVR_ICACHE_ALLOW_WR(pvr) (pvr.pvr[4] & PVR4_ICACHE_ALLOW_WR_MASK) 176 (_pvr.pvr[4] & PVR4_ICACHE_USE_FSL_MASK)
177#define PVR_ICACHE_LINE_LEN(pvr) \ 177#define PVR_ICACHE_ALLOW_WR(_pvr) \
178 (1 << ((pvr.pvr[4] & PVR4_ICACHE_LINE_LEN_MASK) >> 21)) 178 (_pvr.pvr[4] & PVR4_ICACHE_ALLOW_WR_MASK)
179#define PVR_ICACHE_BYTE_SIZE(pvr) \ 179#define PVR_ICACHE_LINE_LEN(_pvr) \
180 (1 << ((pvr.pvr[4] & PVR4_ICACHE_BYTE_SIZE_MASK) >> 16)) 180 (1 << ((_pvr.pvr[4] & PVR4_ICACHE_LINE_LEN_MASK) >> 21))
181 181#define PVR_ICACHE_BYTE_SIZE(_pvr) \
182#define PVR_DCACHE_ADDR_TAG_BITS(pvr) \ 182 (1 << ((_pvr.pvr[4] & PVR4_ICACHE_BYTE_SIZE_MASK) >> 16))
183 ((pvr.pvr[5] & PVR5_DCACHE_ADDR_TAG_BITS_MASK) >> 26) 183
184#define PVR_DCACHE_USE_FSL(pvr) (pvr.pvr[5] & PVR5_DCACHE_USE_FSL_MASK) 184#define PVR_DCACHE_ADDR_TAG_BITS(_pvr) \
185#define PVR_DCACHE_ALLOW_WR(pvr) (pvr.pvr[5] & PVR5_DCACHE_ALLOW_WR_MASK) 185 ((_pvr.pvr[5] & PVR5_DCACHE_ADDR_TAG_BITS_MASK) >> 26)
186#define PVR_DCACHE_USE_FSL(_pvr) (_pvr.pvr[5] & PVR5_DCACHE_USE_FSL_MASK)
187#define PVR_DCACHE_ALLOW_WR(_pvr) \
188 (_pvr.pvr[5] & PVR5_DCACHE_ALLOW_WR_MASK)
186/* FIXME two shifts on one line needs any comment */ 189/* FIXME two shifts on one line needs any comment */
187#define PVR_DCACHE_LINE_LEN(pvr) \ 190#define PVR_DCACHE_LINE_LEN(_pvr) \
188 (1 << ((pvr.pvr[5] & PVR5_DCACHE_LINE_LEN_MASK) >> 21)) 191 (1 << ((_pvr.pvr[5] & PVR5_DCACHE_LINE_LEN_MASK) >> 21))
189#define PVR_DCACHE_BYTE_SIZE(pvr) \ 192#define PVR_DCACHE_BYTE_SIZE(_pvr) \
190 (1 << ((pvr.pvr[5] & PVR5_DCACHE_BYTE_SIZE_MASK) >> 16)) 193 (1 << ((_pvr.pvr[5] & PVR5_DCACHE_BYTE_SIZE_MASK) >> 16))
191 194
192#define PVR_DCACHE_USE_WRITEBACK(pvr) \ 195#define PVR_DCACHE_USE_WRITEBACK(_pvr) \
193 ((pvr.pvr[5] & PVR5_DCACHE_USE_WRITEBACK) >> 14) 196 ((_pvr.pvr[5] & PVR5_DCACHE_USE_WRITEBACK) >> 14)
194 197
195#define PVR_ICACHE_BASEADDR(pvr) (pvr.pvr[6] & PVR6_ICACHE_BASEADDR_MASK) 198#define PVR_ICACHE_BASEADDR(_pvr) \
196#define PVR_ICACHE_HIGHADDR(pvr) (pvr.pvr[7] & PVR7_ICACHE_HIGHADDR_MASK) 199 (_pvr.pvr[6] & PVR6_ICACHE_BASEADDR_MASK)
200#define PVR_ICACHE_HIGHADDR(_pvr) \
201 (_pvr.pvr[7] & PVR7_ICACHE_HIGHADDR_MASK)
202#define PVR_DCACHE_BASEADDR(_pvr) \
203 (_pvr.pvr[8] & PVR8_DCACHE_BASEADDR_MASK)
204#define PVR_DCACHE_HIGHADDR(_pvr) \
205 (_pvr.pvr[9] & PVR9_DCACHE_HIGHADDR_MASK)
197 206
198#define PVR_DCACHE_BASEADDR(pvr) (pvr.pvr[8] & PVR8_DCACHE_BASEADDR_MASK) 207#define PVR_TARGET_FAMILY(_pvr) \
199#define PVR_DCACHE_HIGHADDR(pvr) (pvr.pvr[9] & PVR9_DCACHE_HIGHADDR_MASK) 208 ((_pvr.pvr[10] & PVR10_TARGET_FAMILY_MASK) >> 24)
200 209
201#define PVR_TARGET_FAMILY(pvr) ((pvr.pvr[10] & PVR10_TARGET_FAMILY_MASK) >> 24) 210#define PVR_MSR_RESET_VALUE(_pvr) \
202 211 (_pvr.pvr[11] & PVR11_MSR_RESET_VALUE_MASK)
203#define PVR_MSR_RESET_VALUE(pvr) \
204 (pvr.pvr[11] & PVR11_MSR_RESET_VALUE_MASK)
205 212
206/* mmu */ 213/* mmu */
207#define PVR_USE_MMU(pvr) ((pvr.pvr[11] & PVR11_USE_MMU) >> 30) 214#define PVR_USE_MMU(_pvr) ((_pvr.pvr[11] & PVR11_USE_MMU) >> 30)
208#define PVR_MMU_ITLB_SIZE(pvr) (pvr.pvr[11] & PVR11_MMU_ITLB_SIZE) 215#define PVR_MMU_ITLB_SIZE(_pvr) (_pvr.pvr[11] & PVR11_MMU_ITLB_SIZE)
209#define PVR_MMU_DTLB_SIZE(pvr) (pvr.pvr[11] & PVR11_MMU_DTLB_SIZE) 216#define PVR_MMU_DTLB_SIZE(_pvr) (_pvr.pvr[11] & PVR11_MMU_DTLB_SIZE)
210#define PVR_MMU_TLB_ACCESS(pvr) (pvr.pvr[11] & PVR11_MMU_TLB_ACCESS) 217#define PVR_MMU_TLB_ACCESS(_pvr) (_pvr.pvr[11] & PVR11_MMU_TLB_ACCESS)
211#define PVR_MMU_ZONES(pvr) (pvr.pvr[11] & PVR11_MMU_ZONES) 218#define PVR_MMU_ZONES(_pvr) (_pvr.pvr[11] & PVR11_MMU_ZONES)
212 219
213/* endian */ 220/* endian */
214#define PVR_ENDIAN(pvr) (pvr.pvr[0] & PVR0_ENDI) 221#define PVR_ENDIAN(_pvr) (_pvr.pvr[0] & PVR0_ENDI)
215 222
216int cpu_has_pvr(void); 223int cpu_has_pvr(void);
217void get_pvr(struct pvr_s *pvr); 224void get_pvr(struct pvr_s *pvr);
diff --git a/arch/microblaze/include/asm/syscall.h b/arch/microblaze/include/asm/syscall.h
index 048dfcd8d89d..9bc431783105 100644
--- a/arch/microblaze/include/asm/syscall.h
+++ b/arch/microblaze/include/asm/syscall.h
@@ -96,4 +96,7 @@ static inline void syscall_set_arguments(struct task_struct *task,
96 microblaze_set_syscall_arg(regs, i++, *args++); 96 microblaze_set_syscall_arg(regs, i++, *args++);
97} 97}
98 98
99asmlinkage long do_syscall_trace_enter(struct pt_regs *regs);
100asmlinkage void do_syscall_trace_leave(struct pt_regs *regs);
101
99#endif /* __ASM_MICROBLAZE_SYSCALL_H */ 102#endif /* __ASM_MICROBLAZE_SYSCALL_H */
diff --git a/arch/microblaze/include/asm/syscalls.h b/arch/microblaze/include/asm/syscalls.h
index 720761cc741f..27f2f4c0f39f 100644
--- a/arch/microblaze/include/asm/syscalls.h
+++ b/arch/microblaze/include/asm/syscalls.h
@@ -1,5 +1,13 @@
1#ifndef __ASM_MICROBLAZE_SYSCALLS_H 1#ifndef __ASM_MICROBLAZE_SYSCALLS_H
2 2
3asmlinkage long microblaze_vfork(struct pt_regs *regs);
4asmlinkage long microblaze_clone(int flags, unsigned long stack,
5 struct pt_regs *regs);
6asmlinkage long microblaze_execve(const char __user *filenamei,
7 const char __user *const __user *argv,
8 const char __user *const __user *envp,
9 struct pt_regs *regs);
10
3asmlinkage long sys_clone(int flags, unsigned long stack, struct pt_regs *regs); 11asmlinkage long sys_clone(int flags, unsigned long stack, struct pt_regs *regs);
4#define sys_clone sys_clone 12#define sys_clone sys_clone
5 13
diff --git a/arch/microblaze/include/asm/tlb.h b/arch/microblaze/include/asm/tlb.h
index e8abd4a0349c..8aa97817cc8c 100644
--- a/arch/microblaze/include/asm/tlb.h
+++ b/arch/microblaze/include/asm/tlb.h
@@ -13,6 +13,7 @@
13 13
14#define tlb_flush(tlb) flush_tlb_mm((tlb)->mm) 14#define tlb_flush(tlb) flush_tlb_mm((tlb)->mm)
15 15
16#include <linux/pagemap.h>
16#include <asm-generic/tlb.h> 17#include <asm-generic/tlb.h>
17 18
18#ifdef CONFIG_MMU 19#ifdef CONFIG_MMU
diff --git a/arch/microblaze/include/asm/uaccess.h b/arch/microblaze/include/asm/uaccess.h
index d840f4a2d3c9..5bb95a11880d 100644
--- a/arch/microblaze/include/asm/uaccess.h
+++ b/arch/microblaze/include/asm/uaccess.h
@@ -120,16 +120,16 @@ static inline unsigned long __must_check __clear_user(void __user *to,
120{ 120{
121 /* normal memset with two words to __ex_table */ 121 /* normal memset with two words to __ex_table */
122 __asm__ __volatile__ ( \ 122 __asm__ __volatile__ ( \
123 "1: sb r0, %2, r0;" \ 123 "1: sb r0, %1, r0;" \
124 " addik %0, %0, -1;" \ 124 " addik %0, %0, -1;" \
125 " bneid %0, 1b;" \ 125 " bneid %0, 1b;" \
126 " addik %2, %2, 1;" \ 126 " addik %1, %1, 1;" \
127 "2: " \ 127 "2: " \
128 __EX_TABLE_SECTION \ 128 __EX_TABLE_SECTION \
129 ".word 1b,2b;" \ 129 ".word 1b,2b;" \
130 ".previous;" \ 130 ".previous;" \
131 : "=r"(n) \ 131 : "=r"(n), "=r"(to) \
132 : "0"(n), "r"(to) 132 : "0"(n), "1"(to)
133 ); 133 );
134 return n; 134 return n;
135} 135}
diff --git a/arch/microblaze/include/asm/unaligned.h b/arch/microblaze/include/asm/unaligned.h
index 2b97cbe500e9..b162ed880495 100644
--- a/arch/microblaze/include/asm/unaligned.h
+++ b/arch/microblaze/include/asm/unaligned.h
@@ -12,18 +12,19 @@
12 12
13# ifdef __KERNEL__ 13# ifdef __KERNEL__
14 14
15# include <linux/unaligned/be_byteshift.h>
16# include <linux/unaligned/le_byteshift.h>
17# include <linux/unaligned/generic.h>
18
19
20# ifdef __MICROBLAZEEL__ 15# ifdef __MICROBLAZEEL__
16# include <linux/unaligned/le_struct.h>
17# include <linux/unaligned/be_byteshift.h>
21# define get_unaligned __get_unaligned_le 18# define get_unaligned __get_unaligned_le
22# define put_unaligned __put_unaligned_le 19# define put_unaligned __put_unaligned_le
23# else 20# else
21# include <linux/unaligned/be_struct.h>
22# include <linux/unaligned/le_byteshift.h>
24# define get_unaligned __get_unaligned_be 23# define get_unaligned __get_unaligned_be
25# define put_unaligned __put_unaligned_be 24# define put_unaligned __put_unaligned_be
26# endif 25# endif
27 26
27# include <linux/unaligned/generic.h>
28
28# endif /* __KERNEL__ */ 29# endif /* __KERNEL__ */
29#endif /* _ASM_MICROBLAZE_UNALIGNED_H */ 30#endif /* _ASM_MICROBLAZE_UNALIGNED_H */
diff --git a/arch/microblaze/kernel/cpu/cache.c b/arch/microblaze/kernel/cpu/cache.c
index 109876e8d643..cf0afd90a2c0 100644
--- a/arch/microblaze/kernel/cpu/cache.c
+++ b/arch/microblaze/kernel/cpu/cache.c
@@ -519,7 +519,7 @@ static void __flush_dcache_range_wb(unsigned long start, unsigned long end)
519struct scache *mbc; 519struct scache *mbc;
520 520
521/* new wb cache model */ 521/* new wb cache model */
522const struct scache wb_msr = { 522static const struct scache wb_msr = {
523 .ie = __enable_icache_msr, 523 .ie = __enable_icache_msr,
524 .id = __disable_icache_msr, 524 .id = __disable_icache_msr,
525 .ifl = __flush_icache_all_noirq, 525 .ifl = __flush_icache_all_noirq,
@@ -535,7 +535,7 @@ const struct scache wb_msr = {
535}; 535};
536 536
537/* There is only difference in ie, id, de, dd functions */ 537/* There is only difference in ie, id, de, dd functions */
538const struct scache wb_nomsr = { 538static const struct scache wb_nomsr = {
539 .ie = __enable_icache_nomsr, 539 .ie = __enable_icache_nomsr,
540 .id = __disable_icache_nomsr, 540 .id = __disable_icache_nomsr,
541 .ifl = __flush_icache_all_noirq, 541 .ifl = __flush_icache_all_noirq,
@@ -551,7 +551,7 @@ const struct scache wb_nomsr = {
551}; 551};
552 552
553/* Old wt cache model with disabling irq and turn off cache */ 553/* Old wt cache model with disabling irq and turn off cache */
554const struct scache wt_msr = { 554static const struct scache wt_msr = {
555 .ie = __enable_icache_msr, 555 .ie = __enable_icache_msr,
556 .id = __disable_icache_msr, 556 .id = __disable_icache_msr,
557 .ifl = __flush_icache_all_msr_irq, 557 .ifl = __flush_icache_all_msr_irq,
@@ -566,7 +566,7 @@ const struct scache wt_msr = {
566 .dinr = __invalidate_dcache_range_msr_irq_wt, 566 .dinr = __invalidate_dcache_range_msr_irq_wt,
567}; 567};
568 568
569const struct scache wt_nomsr = { 569static const struct scache wt_nomsr = {
570 .ie = __enable_icache_nomsr, 570 .ie = __enable_icache_nomsr,
571 .id = __disable_icache_nomsr, 571 .id = __disable_icache_nomsr,
572 .ifl = __flush_icache_all_nomsr_irq, 572 .ifl = __flush_icache_all_nomsr_irq,
@@ -582,7 +582,7 @@ const struct scache wt_nomsr = {
582}; 582};
583 583
584/* New wt cache model for newer Microblaze versions */ 584/* New wt cache model for newer Microblaze versions */
585const struct scache wt_msr_noirq = { 585static const struct scache wt_msr_noirq = {
586 .ie = __enable_icache_msr, 586 .ie = __enable_icache_msr,
587 .id = __disable_icache_msr, 587 .id = __disable_icache_msr,
588 .ifl = __flush_icache_all_noirq, 588 .ifl = __flush_icache_all_noirq,
@@ -597,7 +597,7 @@ const struct scache wt_msr_noirq = {
597 .dinr = __invalidate_dcache_range_nomsr_wt, 597 .dinr = __invalidate_dcache_range_nomsr_wt,
598}; 598};
599 599
600const struct scache wt_nomsr_noirq = { 600static const struct scache wt_nomsr_noirq = {
601 .ie = __enable_icache_nomsr, 601 .ie = __enable_icache_nomsr,
602 .id = __disable_icache_nomsr, 602 .id = __disable_icache_nomsr,
603 .ifl = __flush_icache_all_noirq, 603 .ifl = __flush_icache_all_noirq,
@@ -624,7 +624,7 @@ void microblaze_cache_init(void)
624 if (cpuinfo.dcache_wb) { 624 if (cpuinfo.dcache_wb) {
625 INFO("wb_msr"); 625 INFO("wb_msr");
626 mbc = (struct scache *)&wb_msr; 626 mbc = (struct scache *)&wb_msr;
627 if (cpuinfo.ver_code < CPUVER_7_20_D) { 627 if (cpuinfo.ver_code <= CPUVER_7_20_D) {
628 /* MS: problem with signal handling - hw bug */ 628 /* MS: problem with signal handling - hw bug */
629 INFO("WB won't work properly"); 629 INFO("WB won't work properly");
630 } 630 }
@@ -641,7 +641,7 @@ void microblaze_cache_init(void)
641 if (cpuinfo.dcache_wb) { 641 if (cpuinfo.dcache_wb) {
642 INFO("wb_nomsr"); 642 INFO("wb_nomsr");
643 mbc = (struct scache *)&wb_nomsr; 643 mbc = (struct scache *)&wb_nomsr;
644 if (cpuinfo.ver_code < CPUVER_7_20_D) { 644 if (cpuinfo.ver_code <= CPUVER_7_20_D) {
645 /* MS: problem with signal handling - hw bug */ 645 /* MS: problem with signal handling - hw bug */
646 INFO("WB won't work properly"); 646 INFO("WB won't work properly");
647 } 647 }
diff --git a/arch/microblaze/kernel/cpu/cpuinfo.c b/arch/microblaze/kernel/cpu/cpuinfo.c
index 87c79fa275c3..c1640c52711f 100644
--- a/arch/microblaze/kernel/cpu/cpuinfo.c
+++ b/arch/microblaze/kernel/cpu/cpuinfo.c
@@ -32,6 +32,8 @@ const struct cpu_ver_key cpu_ver_lookup[] = {
32 {"7.30.a", 0x10}, 32 {"7.30.a", 0x10},
33 {"7.30.b", 0x11}, 33 {"7.30.b", 0x11},
34 {"8.00.a", 0x12}, 34 {"8.00.a", 0x12},
35 {"8.00.b", 0x13},
36 {"8.10.a", 0x14},
35 {NULL, 0}, 37 {NULL, 0},
36}; 38};
37 39
diff --git a/arch/microblaze/kernel/cpu/pvr.c b/arch/microblaze/kernel/cpu/pvr.c
index e01afa68273e..488c1ed24e38 100644
--- a/arch/microblaze/kernel/cpu/pvr.c
+++ b/arch/microblaze/kernel/cpu/pvr.c
@@ -27,7 +27,7 @@
27 register unsigned tmp __asm__("r3"); \ 27 register unsigned tmp __asm__("r3"); \
28 tmp = 0x0; /* Prevent warning about unused */ \ 28 tmp = 0x0; /* Prevent warning about unused */ \
29 __asm__ __volatile__ ( \ 29 __asm__ __volatile__ ( \
30 "mfs %0, rpvr" #pvrid ";" \ 30 "mfs %0, rpvr" #pvrid ";" \
31 : "=r" (tmp) : : "memory"); \ 31 : "=r" (tmp) : : "memory"); \
32 val = tmp; \ 32 val = tmp; \
33} 33}
@@ -54,7 +54,7 @@ int cpu_has_pvr(void)
54 if (!(flags & PVR_MSR_BIT)) 54 if (!(flags & PVR_MSR_BIT))
55 return 0; 55 return 0;
56 56
57 get_single_pvr(0x00, pvr0); 57 get_single_pvr(0, pvr0);
58 pr_debug("%s: pvr0 is 0x%08x\n", __func__, pvr0); 58 pr_debug("%s: pvr0 is 0x%08x\n", __func__, pvr0);
59 59
60 if (pvr0 & PVR0_PVR_FULL_MASK) 60 if (pvr0 & PVR0_PVR_FULL_MASK)
diff --git a/arch/microblaze/kernel/dma.c b/arch/microblaze/kernel/dma.c
index 79c74659f204..393e6b2db688 100644
--- a/arch/microblaze/kernel/dma.c
+++ b/arch/microblaze/kernel/dma.c
@@ -26,6 +26,7 @@ static inline void __dma_sync_page(unsigned long paddr, unsigned long offset,
26{ 26{
27 switch (direction) { 27 switch (direction) {
28 case DMA_TO_DEVICE: 28 case DMA_TO_DEVICE:
29 case DMA_BIDIRECTIONAL:
29 flush_dcache_range(paddr + offset, paddr + offset + size); 30 flush_dcache_range(paddr + offset, paddr + offset + size);
30 break; 31 break;
31 case DMA_FROM_DEVICE: 32 case DMA_FROM_DEVICE:
diff --git a/arch/microblaze/kernel/entry-nommu.S b/arch/microblaze/kernel/entry-nommu.S
index ca84368570b6..34b526f59b43 100644
--- a/arch/microblaze/kernel/entry-nommu.S
+++ b/arch/microblaze/kernel/entry-nommu.S
@@ -115,7 +115,7 @@ ENTRY(_interrupt)
115 /* restore r31 */ 115 /* restore r31 */
116 lwi r31, r0, PER_CPU(CURRENT_SAVE) 116 lwi r31, r0, PER_CPU(CURRENT_SAVE)
117 /* prepare the link register, the argument and jump */ 117 /* prepare the link register, the argument and jump */
118 la r15, r0, ret_from_intr - 8 118 addik r15, r0, ret_from_intr - 8
119 addk r6, r0, r15 119 addk r6, r0, r15
120 braid do_IRQ 120 braid do_IRQ
121 add r5, r0, r1 121 add r5, r0, r1
@@ -283,7 +283,7 @@ ENTRY(_user_exception)
283 add r12, r12, r12 /* convert num -> ptr */ 283 add r12, r12, r12 /* convert num -> ptr */
284 add r12, r12, r12 284 add r12, r12, r12
285 lwi r12, r12, sys_call_table /* Get function pointer */ 285 lwi r12, r12, sys_call_table /* Get function pointer */
286 la r15, r0, ret_to_user-8 /* set return address */ 286 addik r15, r0, ret_to_user-8 /* set return address */
287 bra r12 /* Make the system call. */ 287 bra r12 /* Make the system call. */
288 bri 0 /* won't reach here */ 288 bri 0 /* won't reach here */
2891: 2891:
diff --git a/arch/microblaze/kernel/entry.S b/arch/microblaze/kernel/entry.S
index 819238b8a429..ca15bc5c7449 100644
--- a/arch/microblaze/kernel/entry.S
+++ b/arch/microblaze/kernel/entry.S
@@ -33,11 +33,14 @@
33 33
34#undef DEBUG 34#undef DEBUG
35 35
36/* The size of a state save frame. */ 36#ifdef DEBUG
37#define STATE_SAVE_SIZE (PT_SIZE + STATE_SAVE_ARG_SPACE) 37/* Create space for syscalls counting. */
38 38.section .data
39/* The offset of the struct pt_regs in a `state save frame' on the stack. */ 39.global syscall_debug_table
40#define PTO STATE_SAVE_ARG_SPACE /* 24 the space for args */ 40.align 4
41syscall_debug_table:
42 .space (__NR_syscalls * 4)
43#endif /* DEBUG */
41 44
42#define C_ENTRY(name) .globl name; .align 4; name 45#define C_ENTRY(name) .globl name; .align 4; name
43 46
@@ -172,72 +175,72 @@
1721: 1751:
173 176
174#define SAVE_REGS \ 177#define SAVE_REGS \
175 swi r2, r1, PTO+PT_R2; /* Save SDA */ \ 178 swi r2, r1, PT_R2; /* Save SDA */ \
176 swi r3, r1, PTO+PT_R3; \ 179 swi r3, r1, PT_R3; \
177 swi r4, r1, PTO+PT_R4; \ 180 swi r4, r1, PT_R4; \
178 swi r5, r1, PTO+PT_R5; \ 181 swi r5, r1, PT_R5; \
179 swi r6, r1, PTO+PT_R6; \ 182 swi r6, r1, PT_R6; \
180 swi r7, r1, PTO+PT_R7; \ 183 swi r7, r1, PT_R7; \
181 swi r8, r1, PTO+PT_R8; \ 184 swi r8, r1, PT_R8; \
182 swi r9, r1, PTO+PT_R9; \ 185 swi r9, r1, PT_R9; \
183 swi r10, r1, PTO+PT_R10; \ 186 swi r10, r1, PT_R10; \
184 swi r11, r1, PTO+PT_R11; /* save clobbered regs after rval */\ 187 swi r11, r1, PT_R11; /* save clobbered regs after rval */\
185 swi r12, r1, PTO+PT_R12; \ 188 swi r12, r1, PT_R12; \
186 swi r13, r1, PTO+PT_R13; /* Save SDA2 */ \ 189 swi r13, r1, PT_R13; /* Save SDA2 */ \
187 swi r14, r1, PTO+PT_PC; /* PC, before IRQ/trap */ \ 190 swi r14, r1, PT_PC; /* PC, before IRQ/trap */ \
188 swi r15, r1, PTO+PT_R15; /* Save LP */ \ 191 swi r15, r1, PT_R15; /* Save LP */ \
189 swi r16, r1, PTO+PT_R16; \ 192 swi r16, r1, PT_R16; \
190 swi r17, r1, PTO+PT_R17; \ 193 swi r17, r1, PT_R17; \
191 swi r18, r1, PTO+PT_R18; /* Save asm scratch reg */ \ 194 swi r18, r1, PT_R18; /* Save asm scratch reg */ \
192 swi r19, r1, PTO+PT_R19; \ 195 swi r19, r1, PT_R19; \
193 swi r20, r1, PTO+PT_R20; \ 196 swi r20, r1, PT_R20; \
194 swi r21, r1, PTO+PT_R21; \ 197 swi r21, r1, PT_R21; \
195 swi r22, r1, PTO+PT_R22; \ 198 swi r22, r1, PT_R22; \
196 swi r23, r1, PTO+PT_R23; \ 199 swi r23, r1, PT_R23; \
197 swi r24, r1, PTO+PT_R24; \ 200 swi r24, r1, PT_R24; \
198 swi r25, r1, PTO+PT_R25; \ 201 swi r25, r1, PT_R25; \
199 swi r26, r1, PTO+PT_R26; \ 202 swi r26, r1, PT_R26; \
200 swi r27, r1, PTO+PT_R27; \ 203 swi r27, r1, PT_R27; \
201 swi r28, r1, PTO+PT_R28; \ 204 swi r28, r1, PT_R28; \
202 swi r29, r1, PTO+PT_R29; \ 205 swi r29, r1, PT_R29; \
203 swi r30, r1, PTO+PT_R30; \ 206 swi r30, r1, PT_R30; \
204 swi r31, r1, PTO+PT_R31; /* Save current task reg */ \ 207 swi r31, r1, PT_R31; /* Save current task reg */ \
205 mfs r11, rmsr; /* save MSR */ \ 208 mfs r11, rmsr; /* save MSR */ \
206 swi r11, r1, PTO+PT_MSR; 209 swi r11, r1, PT_MSR;
207 210
208#define RESTORE_REGS \ 211#define RESTORE_REGS \
209 lwi r11, r1, PTO+PT_MSR; \ 212 lwi r11, r1, PT_MSR; \
210 mts rmsr , r11; \ 213 mts rmsr , r11; \
211 lwi r2, r1, PTO+PT_R2; /* restore SDA */ \ 214 lwi r2, r1, PT_R2; /* restore SDA */ \
212 lwi r3, r1, PTO+PT_R3; \ 215 lwi r3, r1, PT_R3; \
213 lwi r4, r1, PTO+PT_R4; \ 216 lwi r4, r1, PT_R4; \
214 lwi r5, r1, PTO+PT_R5; \ 217 lwi r5, r1, PT_R5; \
215 lwi r6, r1, PTO+PT_R6; \ 218 lwi r6, r1, PT_R6; \
216 lwi r7, r1, PTO+PT_R7; \ 219 lwi r7, r1, PT_R7; \
217 lwi r8, r1, PTO+PT_R8; \ 220 lwi r8, r1, PT_R8; \
218 lwi r9, r1, PTO+PT_R9; \ 221 lwi r9, r1, PT_R9; \
219 lwi r10, r1, PTO+PT_R10; \ 222 lwi r10, r1, PT_R10; \
220 lwi r11, r1, PTO+PT_R11; /* restore clobbered regs after rval */\ 223 lwi r11, r1, PT_R11; /* restore clobbered regs after rval */\
221 lwi r12, r1, PTO+PT_R12; \ 224 lwi r12, r1, PT_R12; \
222 lwi r13, r1, PTO+PT_R13; /* restore SDA2 */ \ 225 lwi r13, r1, PT_R13; /* restore SDA2 */ \
223 lwi r14, r1, PTO+PT_PC; /* RESTORE_LINK PC, before IRQ/trap */\ 226 lwi r14, r1, PT_PC; /* RESTORE_LINK PC, before IRQ/trap */\
224 lwi r15, r1, PTO+PT_R15; /* restore LP */ \ 227 lwi r15, r1, PT_R15; /* restore LP */ \
225 lwi r16, r1, PTO+PT_R16; \ 228 lwi r16, r1, PT_R16; \
226 lwi r17, r1, PTO+PT_R17; \ 229 lwi r17, r1, PT_R17; \
227 lwi r18, r1, PTO+PT_R18; /* restore asm scratch reg */ \ 230 lwi r18, r1, PT_R18; /* restore asm scratch reg */ \
228 lwi r19, r1, PTO+PT_R19; \ 231 lwi r19, r1, PT_R19; \
229 lwi r20, r1, PTO+PT_R20; \ 232 lwi r20, r1, PT_R20; \
230 lwi r21, r1, PTO+PT_R21; \ 233 lwi r21, r1, PT_R21; \
231 lwi r22, r1, PTO+PT_R22; \ 234 lwi r22, r1, PT_R22; \
232 lwi r23, r1, PTO+PT_R23; \ 235 lwi r23, r1, PT_R23; \
233 lwi r24, r1, PTO+PT_R24; \ 236 lwi r24, r1, PT_R24; \
234 lwi r25, r1, PTO+PT_R25; \ 237 lwi r25, r1, PT_R25; \
235 lwi r26, r1, PTO+PT_R26; \ 238 lwi r26, r1, PT_R26; \
236 lwi r27, r1, PTO+PT_R27; \ 239 lwi r27, r1, PT_R27; \
237 lwi r28, r1, PTO+PT_R28; \ 240 lwi r28, r1, PT_R28; \
238 lwi r29, r1, PTO+PT_R29; \ 241 lwi r29, r1, PT_R29; \
239 lwi r30, r1, PTO+PT_R30; \ 242 lwi r30, r1, PT_R30; \
240 lwi r31, r1, PTO+PT_R31; /* Restore cur task reg */ 243 lwi r31, r1, PT_R31; /* Restore cur task reg */
241 244
242#define SAVE_STATE \ 245#define SAVE_STATE \
243 swi r1, r0, TOPHYS(PER_CPU(ENTRY_SP)); /* save stack */ \ 246 swi r1, r0, TOPHYS(PER_CPU(ENTRY_SP)); /* save stack */ \
@@ -250,11 +253,11 @@
250 lwi r1, r0, TOPHYS(PER_CPU(ENTRY_SP)); \ 253 lwi r1, r0, TOPHYS(PER_CPU(ENTRY_SP)); \
251 /* FIXME: I can add these two lines to one */ \ 254 /* FIXME: I can add these two lines to one */ \
252 /* tophys(r1,r1); */ \ 255 /* tophys(r1,r1); */ \
253 /* addik r1, r1, -STATE_SAVE_SIZE; */ \ 256 /* addik r1, r1, -PT_SIZE; */ \
254 addik r1, r1, CONFIG_KERNEL_BASE_ADDR - CONFIG_KERNEL_START - STATE_SAVE_SIZE; \ 257 addik r1, r1, CONFIG_KERNEL_BASE_ADDR - CONFIG_KERNEL_START - PT_SIZE; \
255 SAVE_REGS \ 258 SAVE_REGS \
256 brid 2f; \ 259 brid 2f; \
257 swi r1, r1, PTO+PT_MODE; \ 260 swi r1, r1, PT_MODE; \
2581: /* User-mode state save. */ \ 2611: /* User-mode state save. */ \
259 lwi r1, r0, TOPHYS(PER_CPU(CURRENT_SAVE)); /* get saved current */\ 262 lwi r1, r0, TOPHYS(PER_CPU(CURRENT_SAVE)); /* get saved current */\
260 tophys(r1,r1); \ 263 tophys(r1,r1); \
@@ -262,12 +265,12 @@
262 /* MS these three instructions can be added to one */ \ 265 /* MS these three instructions can be added to one */ \
263 /* addik r1, r1, THREAD_SIZE; */ \ 266 /* addik r1, r1, THREAD_SIZE; */ \
264 /* tophys(r1,r1); */ \ 267 /* tophys(r1,r1); */ \
265 /* addik r1, r1, -STATE_SAVE_SIZE; */ \ 268 /* addik r1, r1, -PT_SIZE; */ \
266 addik r1, r1, THREAD_SIZE + CONFIG_KERNEL_BASE_ADDR - CONFIG_KERNEL_START - STATE_SAVE_SIZE; \ 269 addik r1, r1, THREAD_SIZE + CONFIG_KERNEL_BASE_ADDR - CONFIG_KERNEL_START - PT_SIZE; \
267 SAVE_REGS \ 270 SAVE_REGS \
268 lwi r11, r0, TOPHYS(PER_CPU(ENTRY_SP)); \ 271 lwi r11, r0, TOPHYS(PER_CPU(ENTRY_SP)); \
269 swi r11, r1, PTO+PT_R1; /* Store user SP. */ \ 272 swi r11, r1, PT_R1; /* Store user SP. */ \
270 swi r0, r1, PTO + PT_MODE; /* Was in user-mode. */ \ 273 swi r0, r1, PT_MODE; /* Was in user-mode. */ \
271 /* MS: I am clearing UMS even in case when I come from kernel space */ \ 274 /* MS: I am clearing UMS even in case when I come from kernel space */ \
272 clear_ums; \ 275 clear_ums; \
2732: lwi CURRENT_TASK, r0, TOPHYS(PER_CPU(CURRENT_SAVE)); 2762: lwi CURRENT_TASK, r0, TOPHYS(PER_CPU(CURRENT_SAVE));
@@ -287,27 +290,46 @@
287 * are masked. This is nice, means we don't have to CLI before state save 290 * are masked. This is nice, means we don't have to CLI before state save
288 */ 291 */
289C_ENTRY(_user_exception): 292C_ENTRY(_user_exception):
290 addi r14, r14, 4 /* return address is 4 byte after call */
291 swi r1, r0, TOPHYS(PER_CPU(ENTRY_SP)) /* save stack */ 293 swi r1, r0, TOPHYS(PER_CPU(ENTRY_SP)) /* save stack */
294 addi r14, r14, 4 /* return address is 4 byte after call */
295
296 mfs r1, rmsr
297 nop
298 andi r1, r1, MSR_UMS
299 bnei r1, 1f
292 300
301/* Kernel-mode state save - kernel execve */
302 lwi r1, r0, TOPHYS(PER_CPU(ENTRY_SP)); /* Reload kernel stack-ptr*/
303 tophys(r1,r1);
304
305 addik r1, r1, -PT_SIZE; /* Make room on the stack. */
306 SAVE_REGS
307
308 swi r1, r1, PT_MODE; /* pt_regs -> kernel mode */
309 brid 2f;
310 nop; /* Fill delay slot */
311
312/* User-mode state save. */
3131:
293 lwi r1, r0, TOPHYS(PER_CPU(CURRENT_SAVE)); /* get saved current */ 314 lwi r1, r0, TOPHYS(PER_CPU(CURRENT_SAVE)); /* get saved current */
294 tophys(r1,r1); 315 tophys(r1,r1);
295 lwi r1, r1, TS_THREAD_INFO; /* get stack from task_struct */ 316 lwi r1, r1, TS_THREAD_INFO; /* get stack from task_struct */
296 /* MS these three instructions can be added to one */ 317/* calculate kernel stack pointer from task struct 8k */
297 /* addik r1, r1, THREAD_SIZE; */ 318 addik r1, r1, THREAD_SIZE;
298 /* tophys(r1,r1); */ 319 tophys(r1,r1);
299 /* addik r1, r1, -STATE_SAVE_SIZE; */ 320
300 addik r1, r1, THREAD_SIZE + CONFIG_KERNEL_BASE_ADDR - CONFIG_KERNEL_START - STATE_SAVE_SIZE; 321 addik r1, r1, -PT_SIZE; /* Make room on the stack. */
301 SAVE_REGS 322 SAVE_REGS
302 swi r0, r1, PTO + PT_R3 323 swi r0, r1, PT_R3
303 swi r0, r1, PTO + PT_R4 324 swi r0, r1, PT_R4
304 325
326 swi r0, r1, PT_MODE; /* Was in user-mode. */
305 lwi r11, r0, TOPHYS(PER_CPU(ENTRY_SP)); 327 lwi r11, r0, TOPHYS(PER_CPU(ENTRY_SP));
306 swi r11, r1, PTO+PT_R1; /* Store user SP. */ 328 swi r11, r1, PT_R1; /* Store user SP. */
307 clear_ums; 329 clear_ums;
308 lwi CURRENT_TASK, r0, TOPHYS(PER_CPU(CURRENT_SAVE)); 3302: lwi CURRENT_TASK, r0, TOPHYS(PER_CPU(CURRENT_SAVE));
309 /* Save away the syscall number. */ 331 /* Save away the syscall number. */
310 swi r12, r1, PTO+PT_R0; 332 swi r12, r1, PT_R0;
311 tovirt(r1,r1) 333 tovirt(r1,r1)
312 334
313/* where the trap should return need -8 to adjust for rtsd r15, 8*/ 335/* where the trap should return need -8 to adjust for rtsd r15, 8*/
@@ -326,18 +348,18 @@ C_ENTRY(_user_exception):
326 beqi r11, 4f 348 beqi r11, 4f
327 349
328 addik r3, r0, -ENOSYS 350 addik r3, r0, -ENOSYS
329 swi r3, r1, PTO + PT_R3 351 swi r3, r1, PT_R3
330 brlid r15, do_syscall_trace_enter 352 brlid r15, do_syscall_trace_enter
331 addik r5, r1, PTO + PT_R0 353 addik r5, r1, PT_R0
332 354
333 # do_syscall_trace_enter returns the new syscall nr. 355 # do_syscall_trace_enter returns the new syscall nr.
334 addk r12, r0, r3 356 addk r12, r0, r3
335 lwi r5, r1, PTO+PT_R5; 357 lwi r5, r1, PT_R5;
336 lwi r6, r1, PTO+PT_R6; 358 lwi r6, r1, PT_R6;
337 lwi r7, r1, PTO+PT_R7; 359 lwi r7, r1, PT_R7;
338 lwi r8, r1, PTO+PT_R8; 360 lwi r8, r1, PT_R8;
339 lwi r9, r1, PTO+PT_R9; 361 lwi r9, r1, PT_R9;
340 lwi r10, r1, PTO+PT_R10; 362 lwi r10, r1, PT_R10;
3414: 3634:
342/* Jump to the appropriate function for the system call number in r12 364/* Jump to the appropriate function for the system call number in r12
343 * (r12 is not preserved), or return an error if r12 is not valid. 365 * (r12 is not preserved), or return an error if r12 is not valid.
@@ -352,10 +374,14 @@ C_ENTRY(_user_exception):
352 add r12, r12, r12; 374 add r12, r12, r12;
353 375
354#ifdef DEBUG 376#ifdef DEBUG
355 /* Trac syscalls and stored them to r0_ram */ 377 /* Trac syscalls and stored them to syscall_debug_table */
356 lwi r3, r12, 0x400 + r0_ram 378 /* The first syscall location stores total syscall number */
379 lwi r3, r0, syscall_debug_table
357 addi r3, r3, 1 380 addi r3, r3, 1
358 swi r3, r12, 0x400 + r0_ram 381 swi r3, r0, syscall_debug_table
382 lwi r3, r12, syscall_debug_table
383 addi r3, r3, 1
384 swi r3, r12, syscall_debug_table
359#endif 385#endif
360 386
361 # Find and jump into the syscall handler. 387 # Find and jump into the syscall handler.
@@ -372,9 +398,12 @@ C_ENTRY(_user_exception):
372/* Entry point used to return from a syscall/trap */ 398/* Entry point used to return from a syscall/trap */
373/* We re-enable BIP bit before state restore */ 399/* We re-enable BIP bit before state restore */
374C_ENTRY(ret_from_trap): 400C_ENTRY(ret_from_trap):
375 swi r3, r1, PTO + PT_R3 401 swi r3, r1, PT_R3
376 swi r4, r1, PTO + PT_R4 402 swi r4, r1, PT_R4
377 403
404 lwi r11, r1, PT_MODE;
405/* See if returning to kernel mode, if so, skip resched &c. */
406 bnei r11, 2f;
378 /* We're returning to user mode, so check for various conditions that 407 /* We're returning to user mode, so check for various conditions that
379 * trigger rescheduling. */ 408 * trigger rescheduling. */
380 /* FIXME: Restructure all these flag checks. */ 409 /* FIXME: Restructure all these flag checks. */
@@ -384,7 +413,7 @@ C_ENTRY(ret_from_trap):
384 beqi r11, 1f 413 beqi r11, 1f
385 414
386 brlid r15, do_syscall_trace_leave 415 brlid r15, do_syscall_trace_leave
387 addik r5, r1, PTO + PT_R0 416 addik r5, r1, PT_R0
3881: 4171:
389 /* We're returning to user mode, so check for various conditions that 418 /* We're returning to user mode, so check for various conditions that
390 * trigger rescheduling. */ 419 * trigger rescheduling. */
@@ -404,7 +433,7 @@ C_ENTRY(ret_from_trap):
404 andi r11, r11, _TIF_SIGPENDING; 433 andi r11, r11, _TIF_SIGPENDING;
405 beqi r11, 1f; /* Signals to handle, handle them */ 434 beqi r11, 1f; /* Signals to handle, handle them */
406 435
407 addik r5, r1, PTO; /* Arg 1: struct pt_regs *regs */ 436 addik r5, r1, 0; /* Arg 1: struct pt_regs *regs */
408 addi r7, r0, 1; /* Arg 3: int in_syscall */ 437 addi r7, r0, 1; /* Arg 3: int in_syscall */
409 bralid r15, do_signal; /* Handle any signals */ 438 bralid r15, do_signal; /* Handle any signals */
410 add r6, r0, r0; /* Arg 2: sigset_t *oldset */ 439 add r6, r0, r0; /* Arg 2: sigset_t *oldset */
@@ -415,8 +444,18 @@ C_ENTRY(ret_from_trap):
415 VM_OFF; 444 VM_OFF;
416 tophys(r1,r1); 445 tophys(r1,r1);
417 RESTORE_REGS; 446 RESTORE_REGS;
418 addik r1, r1, STATE_SAVE_SIZE /* Clean up stack space. */ 447 addik r1, r1, PT_SIZE /* Clean up stack space. */
419 lwi r1, r1, PT_R1 - PT_SIZE;/* Restore user stack pointer. */ 448 lwi r1, r1, PT_R1 - PT_SIZE;/* Restore user stack pointer. */
449 bri 6f;
450
451/* Return to kernel state. */
4522: set_bip; /* Ints masked for state restore */
453 VM_OFF;
454 tophys(r1,r1);
455 RESTORE_REGS;
456 addik r1, r1, PT_SIZE /* Clean up stack space. */
457 tovirt(r1,r1);
4586:
420TRAP_return: /* Make global symbol for debugging */ 459TRAP_return: /* Make global symbol for debugging */
421 rtbd r14, 0; /* Instructions to return from an IRQ */ 460 rtbd r14, 0; /* Instructions to return from an IRQ */
422 nop; 461 nop;
@@ -427,8 +466,8 @@ TRAP_return: /* Make global symbol for debugging */
427 466
428C_ENTRY(sys_fork_wrapper): 467C_ENTRY(sys_fork_wrapper):
429 addi r5, r0, SIGCHLD /* Arg 0: flags */ 468 addi r5, r0, SIGCHLD /* Arg 0: flags */
430 lwi r6, r1, PTO+PT_R1 /* Arg 1: child SP (use parent's) */ 469 lwi r6, r1, PT_R1 /* Arg 1: child SP (use parent's) */
431 addik r7, r1, PTO /* Arg 2: parent context */ 470 addik r7, r1, 0 /* Arg 2: parent context */
432 add r8. r0, r0 /* Arg 3: (unused) */ 471 add r8. r0, r0 /* Arg 3: (unused) */
433 add r9, r0, r0; /* Arg 4: (unused) */ 472 add r9, r0, r0; /* Arg 4: (unused) */
434 brid do_fork /* Do real work (tail-call) */ 473 brid do_fork /* Do real work (tail-call) */
@@ -448,12 +487,12 @@ C_ENTRY(ret_from_fork):
448 487
449C_ENTRY(sys_vfork): 488C_ENTRY(sys_vfork):
450 brid microblaze_vfork /* Do real work (tail-call) */ 489 brid microblaze_vfork /* Do real work (tail-call) */
451 addik r5, r1, PTO 490 addik r5, r1, 0
452 491
453C_ENTRY(sys_clone): 492C_ENTRY(sys_clone):
454 bnei r6, 1f; /* See if child SP arg (arg 1) is 0. */ 493 bnei r6, 1f; /* See if child SP arg (arg 1) is 0. */
455 lwi r6, r1, PTO + PT_R1; /* If so, use paret's stack ptr */ 494 lwi r6, r1, PT_R1; /* If so, use paret's stack ptr */
4561: addik r7, r1, PTO; /* Arg 2: parent context */ 4951: addik r7, r1, 0; /* Arg 2: parent context */
457 add r8, r0, r0; /* Arg 3: (unused) */ 496 add r8, r0, r0; /* Arg 3: (unused) */
458 add r9, r0, r0; /* Arg 4: (unused) */ 497 add r9, r0, r0; /* Arg 4: (unused) */
459 brid do_fork /* Do real work (tail-call) */ 498 brid do_fork /* Do real work (tail-call) */
@@ -461,11 +500,11 @@ C_ENTRY(sys_clone):
461 500
462C_ENTRY(sys_execve): 501C_ENTRY(sys_execve):
463 brid microblaze_execve; /* Do real work (tail-call).*/ 502 brid microblaze_execve; /* Do real work (tail-call).*/
464 addik r8, r1, PTO; /* add user context as 4th arg */ 503 addik r8, r1, 0; /* add user context as 4th arg */
465 504
466C_ENTRY(sys_rt_sigreturn_wrapper): 505C_ENTRY(sys_rt_sigreturn_wrapper):
467 brid sys_rt_sigreturn /* Do real work */ 506 brid sys_rt_sigreturn /* Do real work */
468 addik r5, r1, PTO; /* add user context as 1st arg */ 507 addik r5, r1, 0; /* add user context as 1st arg */
469 508
470/* 509/*
471 * HW EXCEPTION rutine start 510 * HW EXCEPTION rutine start
@@ -476,7 +515,7 @@ C_ENTRY(full_exception_trap):
476 addik r17, r17, -4 515 addik r17, r17, -4
477 SAVE_STATE /* Save registers */ 516 SAVE_STATE /* Save registers */
478 /* PC, before IRQ/trap - this is one instruction above */ 517 /* PC, before IRQ/trap - this is one instruction above */
479 swi r17, r1, PTO+PT_PC; 518 swi r17, r1, PT_PC;
480 tovirt(r1,r1) 519 tovirt(r1,r1)
481 /* FIXME this can be store directly in PT_ESR reg. 520 /* FIXME this can be store directly in PT_ESR reg.
482 * I tested it but there is a fault */ 521 * I tested it but there is a fault */
@@ -486,7 +525,7 @@ C_ENTRY(full_exception_trap):
486 mfs r7, rfsr; /* save FSR */ 525 mfs r7, rfsr; /* save FSR */
487 mts rfsr, r0; /* Clear sticky fsr */ 526 mts rfsr, r0; /* Clear sticky fsr */
488 rted r0, full_exception 527 rted r0, full_exception
489 addik r5, r1, PTO /* parameter struct pt_regs * regs */ 528 addik r5, r1, 0 /* parameter struct pt_regs * regs */
490 529
491/* 530/*
492 * Unaligned data trap. 531 * Unaligned data trap.
@@ -512,14 +551,14 @@ C_ENTRY(unaligned_data_trap):
512 lwi r11, r0, TOPHYS(PER_CPU(ENTRY_SP)); 551 lwi r11, r0, TOPHYS(PER_CPU(ENTRY_SP));
513 SAVE_STATE /* Save registers.*/ 552 SAVE_STATE /* Save registers.*/
514 /* PC, before IRQ/trap - this is one instruction above */ 553 /* PC, before IRQ/trap - this is one instruction above */
515 swi r17, r1, PTO+PT_PC; 554 swi r17, r1, PT_PC;
516 tovirt(r1,r1) 555 tovirt(r1,r1)
517 /* where the trap should return need -8 to adjust for rtsd r15, 8 */ 556 /* where the trap should return need -8 to adjust for rtsd r15, 8 */
518 addik r15, r0, ret_from_exc-8 557 addik r15, r0, ret_from_exc-8
519 mfs r3, resr /* ESR */ 558 mfs r3, resr /* ESR */
520 mfs r4, rear /* EAR */ 559 mfs r4, rear /* EAR */
521 rtbd r0, _unaligned_data_exception 560 rtbd r0, _unaligned_data_exception
522 addik r7, r1, PTO /* parameter struct pt_regs * regs */ 561 addik r7, r1, 0 /* parameter struct pt_regs * regs */
523 562
524/* 563/*
525 * Page fault traps. 564 * Page fault traps.
@@ -542,30 +581,30 @@ C_ENTRY(unaligned_data_trap):
542C_ENTRY(page_fault_data_trap): 581C_ENTRY(page_fault_data_trap):
543 SAVE_STATE /* Save registers.*/ 582 SAVE_STATE /* Save registers.*/
544 /* PC, before IRQ/trap - this is one instruction above */ 583 /* PC, before IRQ/trap - this is one instruction above */
545 swi r17, r1, PTO+PT_PC; 584 swi r17, r1, PT_PC;
546 tovirt(r1,r1) 585 tovirt(r1,r1)
547 /* where the trap should return need -8 to adjust for rtsd r15, 8 */ 586 /* where the trap should return need -8 to adjust for rtsd r15, 8 */
548 addik r15, r0, ret_from_exc-8 587 addik r15, r0, ret_from_exc-8
549 mfs r6, rear /* parameter unsigned long address */ 588 mfs r6, rear /* parameter unsigned long address */
550 mfs r7, resr /* parameter unsigned long error_code */ 589 mfs r7, resr /* parameter unsigned long error_code */
551 rted r0, do_page_fault 590 rted r0, do_page_fault
552 addik r5, r1, PTO /* parameter struct pt_regs * regs */ 591 addik r5, r1, 0 /* parameter struct pt_regs * regs */
553 592
554C_ENTRY(page_fault_instr_trap): 593C_ENTRY(page_fault_instr_trap):
555 SAVE_STATE /* Save registers.*/ 594 SAVE_STATE /* Save registers.*/
556 /* PC, before IRQ/trap - this is one instruction above */ 595 /* PC, before IRQ/trap - this is one instruction above */
557 swi r17, r1, PTO+PT_PC; 596 swi r17, r1, PT_PC;
558 tovirt(r1,r1) 597 tovirt(r1,r1)
559 /* where the trap should return need -8 to adjust for rtsd r15, 8 */ 598 /* where the trap should return need -8 to adjust for rtsd r15, 8 */
560 addik r15, r0, ret_from_exc-8 599 addik r15, r0, ret_from_exc-8
561 mfs r6, rear /* parameter unsigned long address */ 600 mfs r6, rear /* parameter unsigned long address */
562 ori r7, r0, 0 /* parameter unsigned long error_code */ 601 ori r7, r0, 0 /* parameter unsigned long error_code */
563 rted r0, do_page_fault 602 rted r0, do_page_fault
564 addik r5, r1, PTO /* parameter struct pt_regs * regs */ 603 addik r5, r1, 0 /* parameter struct pt_regs * regs */
565 604
566/* Entry point used to return from an exception. */ 605/* Entry point used to return from an exception. */
567C_ENTRY(ret_from_exc): 606C_ENTRY(ret_from_exc):
568 lwi r11, r1, PTO + PT_MODE; 607 lwi r11, r1, PT_MODE;
569 bnei r11, 2f; /* See if returning to kernel mode, */ 608 bnei r11, 2f; /* See if returning to kernel mode, */
570 /* ... if so, skip resched &c. */ 609 /* ... if so, skip resched &c. */
571 610
@@ -597,7 +636,7 @@ C_ENTRY(ret_from_exc):
597 * complete register state. Here we save anything not saved by 636 * complete register state. Here we save anything not saved by
598 * the normal entry sequence, so that it may be safely restored 637 * the normal entry sequence, so that it may be safely restored
599 * (in a possibly modified form) after do_signal returns. */ 638 * (in a possibly modified form) after do_signal returns. */
600 addik r5, r1, PTO; /* Arg 1: struct pt_regs *regs */ 639 addik r5, r1, 0; /* Arg 1: struct pt_regs *regs */
601 addi r7, r0, 0; /* Arg 3: int in_syscall */ 640 addi r7, r0, 0; /* Arg 3: int in_syscall */
602 bralid r15, do_signal; /* Handle any signals */ 641 bralid r15, do_signal; /* Handle any signals */
603 add r6, r0, r0; /* Arg 2: sigset_t *oldset */ 642 add r6, r0, r0; /* Arg 2: sigset_t *oldset */
@@ -609,7 +648,7 @@ C_ENTRY(ret_from_exc):
609 tophys(r1,r1); 648 tophys(r1,r1);
610 649
611 RESTORE_REGS; 650 RESTORE_REGS;
612 addik r1, r1, STATE_SAVE_SIZE /* Clean up stack space. */ 651 addik r1, r1, PT_SIZE /* Clean up stack space. */
613 652
614 lwi r1, r1, PT_R1 - PT_SIZE; /* Restore user stack pointer. */ 653 lwi r1, r1, PT_R1 - PT_SIZE; /* Restore user stack pointer. */
615 bri 6f; 654 bri 6f;
@@ -618,7 +657,7 @@ C_ENTRY(ret_from_exc):
618 VM_OFF; 657 VM_OFF;
619 tophys(r1,r1); 658 tophys(r1,r1);
620 RESTORE_REGS; 659 RESTORE_REGS;
621 addik r1, r1, STATE_SAVE_SIZE /* Clean up stack space. */ 660 addik r1, r1, PT_SIZE /* Clean up stack space. */
622 661
623 tovirt(r1,r1); 662 tovirt(r1,r1);
6246: 6636:
@@ -651,10 +690,10 @@ C_ENTRY(_interrupt):
651 tophys(r1,r1); /* MS: I have in r1 physical address where stack is */ 690 tophys(r1,r1); /* MS: I have in r1 physical address where stack is */
652 /* save registers */ 691 /* save registers */
653/* MS: Make room on the stack -> activation record */ 692/* MS: Make room on the stack -> activation record */
654 addik r1, r1, -STATE_SAVE_SIZE; 693 addik r1, r1, -PT_SIZE;
655 SAVE_REGS 694 SAVE_REGS
656 brid 2f; 695 brid 2f;
657 swi r1, r1, PTO + PT_MODE; /* 0 - user mode, 1 - kernel mode */ 696 swi r1, r1, PT_MODE; /* 0 - user mode, 1 - kernel mode */
6581: 6971:
659/* User-mode state save. */ 698/* User-mode state save. */
660 /* MS: get the saved current */ 699 /* MS: get the saved current */
@@ -664,23 +703,23 @@ C_ENTRY(_interrupt):
664 addik r1, r1, THREAD_SIZE; 703 addik r1, r1, THREAD_SIZE;
665 tophys(r1,r1); 704 tophys(r1,r1);
666 /* save registers */ 705 /* save registers */
667 addik r1, r1, -STATE_SAVE_SIZE; 706 addik r1, r1, -PT_SIZE;
668 SAVE_REGS 707 SAVE_REGS
669 /* calculate mode */ 708 /* calculate mode */
670 swi r0, r1, PTO + PT_MODE; 709 swi r0, r1, PT_MODE;
671 lwi r11, r0, TOPHYS(PER_CPU(ENTRY_SP)); 710 lwi r11, r0, TOPHYS(PER_CPU(ENTRY_SP));
672 swi r11, r1, PTO+PT_R1; 711 swi r11, r1, PT_R1;
673 clear_ums; 712 clear_ums;
6742: 7132:
675 lwi CURRENT_TASK, r0, TOPHYS(PER_CPU(CURRENT_SAVE)); 714 lwi CURRENT_TASK, r0, TOPHYS(PER_CPU(CURRENT_SAVE));
676 tovirt(r1,r1) 715 tovirt(r1,r1)
677 addik r15, r0, irq_call; 716 addik r15, r0, irq_call;
678irq_call:rtbd r0, do_IRQ; 717irq_call:rtbd r0, do_IRQ;
679 addik r5, r1, PTO; 718 addik r5, r1, 0;
680 719
681/* MS: we are in virtual mode */ 720/* MS: we are in virtual mode */
682ret_from_irq: 721ret_from_irq:
683 lwi r11, r1, PTO + PT_MODE; 722 lwi r11, r1, PT_MODE;
684 bnei r11, 2f; 723 bnei r11, 2f;
685 724
686 lwi r11, CURRENT_TASK, TS_THREAD_INFO; 725 lwi r11, CURRENT_TASK, TS_THREAD_INFO;
@@ -697,7 +736,7 @@ ret_from_irq:
697 beqid r11, no_intr_resched 736 beqid r11, no_intr_resched
698/* Handle a signal return; Pending signals should be in r18. */ 737/* Handle a signal return; Pending signals should be in r18. */
699 addi r7, r0, 0; /* Arg 3: int in_syscall */ 738 addi r7, r0, 0; /* Arg 3: int in_syscall */
700 addik r5, r1, PTO; /* Arg 1: struct pt_regs *regs */ 739 addik r5, r1, 0; /* Arg 1: struct pt_regs *regs */
701 bralid r15, do_signal; /* Handle any signals */ 740 bralid r15, do_signal; /* Handle any signals */
702 add r6, r0, r0; /* Arg 2: sigset_t *oldset */ 741 add r6, r0, r0; /* Arg 2: sigset_t *oldset */
703 742
@@ -709,7 +748,7 @@ no_intr_resched:
709 VM_OFF; 748 VM_OFF;
710 tophys(r1,r1); 749 tophys(r1,r1);
711 RESTORE_REGS 750 RESTORE_REGS
712 addik r1, r1, STATE_SAVE_SIZE /* MS: Clean up stack space. */ 751 addik r1, r1, PT_SIZE /* MS: Clean up stack space. */
713 lwi r1, r1, PT_R1 - PT_SIZE; 752 lwi r1, r1, PT_R1 - PT_SIZE;
714 bri 6f; 753 bri 6f;
715/* MS: Return to kernel state. */ 754/* MS: Return to kernel state. */
@@ -737,7 +776,7 @@ restore:
737 VM_OFF /* MS: turn off MMU */ 776 VM_OFF /* MS: turn off MMU */
738 tophys(r1,r1) 777 tophys(r1,r1)
739 RESTORE_REGS 778 RESTORE_REGS
740 addik r1, r1, STATE_SAVE_SIZE /* MS: Clean up stack space. */ 779 addik r1, r1, PT_SIZE /* MS: Clean up stack space. */
741 tovirt(r1,r1); 780 tovirt(r1,r1);
7426: 7816:
743IRQ_return: /* MS: Make global symbol for debugging */ 782IRQ_return: /* MS: Make global symbol for debugging */
@@ -760,29 +799,29 @@ C_ENTRY(_debug_exception):
760 lwi r1, r0, TOPHYS(PER_CPU(ENTRY_SP)); /* Reload kernel stack-ptr*/ 799 lwi r1, r0, TOPHYS(PER_CPU(ENTRY_SP)); /* Reload kernel stack-ptr*/
761 800
762 /* BIP bit is set on entry, no interrupts can occur */ 801 /* BIP bit is set on entry, no interrupts can occur */
763 addik r1, r1, CONFIG_KERNEL_BASE_ADDR - CONFIG_KERNEL_START - STATE_SAVE_SIZE; 802 addik r1, r1, CONFIG_KERNEL_BASE_ADDR - CONFIG_KERNEL_START - PT_SIZE;
764 SAVE_REGS; 803 SAVE_REGS;
765 /* save all regs to pt_reg structure */ 804 /* save all regs to pt_reg structure */
766 swi r0, r1, PTO+PT_R0; /* R0 must be saved too */ 805 swi r0, r1, PT_R0; /* R0 must be saved too */
767 swi r14, r1, PTO+PT_R14 /* rewrite saved R14 value */ 806 swi r14, r1, PT_R14 /* rewrite saved R14 value */
768 swi r16, r1, PTO+PT_PC; /* PC and r16 are the same */ 807 swi r16, r1, PT_PC; /* PC and r16 are the same */
769 /* save special purpose registers to pt_regs */ 808 /* save special purpose registers to pt_regs */
770 mfs r11, rear; 809 mfs r11, rear;
771 swi r11, r1, PTO+PT_EAR; 810 swi r11, r1, PT_EAR;
772 mfs r11, resr; 811 mfs r11, resr;
773 swi r11, r1, PTO+PT_ESR; 812 swi r11, r1, PT_ESR;
774 mfs r11, rfsr; 813 mfs r11, rfsr;
775 swi r11, r1, PTO+PT_FSR; 814 swi r11, r1, PT_FSR;
776 815
777 /* stack pointer is in physical address at it is decrease 816 /* stack pointer is in physical address at it is decrease
778 * by STATE_SAVE_SIZE but we need to get correct R1 value */ 817 * by PT_SIZE but we need to get correct R1 value */
779 addik r11, r1, CONFIG_KERNEL_START - CONFIG_KERNEL_BASE_ADDR + STATE_SAVE_SIZE; 818 addik r11, r1, CONFIG_KERNEL_START - CONFIG_KERNEL_BASE_ADDR + PT_SIZE;
780 swi r11, r1, PTO+PT_R1 819 swi r11, r1, PT_R1
781 /* MS: r31 - current pointer isn't changed */ 820 /* MS: r31 - current pointer isn't changed */
782 tovirt(r1,r1) 821 tovirt(r1,r1)
783#ifdef CONFIG_KGDB 822#ifdef CONFIG_KGDB
784 addi r5, r1, PTO /* pass pt_reg address as the first arg */ 823 addi r5, r1, 0 /* pass pt_reg address as the first arg */
785 la r15, r0, dbtrap_call; /* return address */ 824 addik r15, r0, dbtrap_call; /* return address */
786 rtbd r0, microblaze_kgdb_break 825 rtbd r0, microblaze_kgdb_break
787 nop; 826 nop;
788#endif 827#endif
@@ -797,16 +836,16 @@ C_ENTRY(_debug_exception):
797 addik r1, r1, THREAD_SIZE; /* calculate kernel stack pointer */ 836 addik r1, r1, THREAD_SIZE; /* calculate kernel stack pointer */
798 tophys(r1,r1); 837 tophys(r1,r1);
799 838
800 addik r1, r1, -STATE_SAVE_SIZE; /* Make room on the stack. */ 839 addik r1, r1, -PT_SIZE; /* Make room on the stack. */
801 SAVE_REGS; 840 SAVE_REGS;
802 swi r16, r1, PTO+PT_PC; /* Save LP */ 841 swi r16, r1, PT_PC; /* Save LP */
803 swi r0, r1, PTO + PT_MODE; /* Was in user-mode. */ 842 swi r0, r1, PT_MODE; /* Was in user-mode. */
804 lwi r11, r0, TOPHYS(PER_CPU(ENTRY_SP)); 843 lwi r11, r0, TOPHYS(PER_CPU(ENTRY_SP));
805 swi r11, r1, PTO+PT_R1; /* Store user SP. */ 844 swi r11, r1, PT_R1; /* Store user SP. */
806 lwi CURRENT_TASK, r0, TOPHYS(PER_CPU(CURRENT_SAVE)); 845 lwi CURRENT_TASK, r0, TOPHYS(PER_CPU(CURRENT_SAVE));
807 tovirt(r1,r1) 846 tovirt(r1,r1)
808 set_vms; 847 set_vms;
809 addik r5, r1, PTO; 848 addik r5, r1, 0;
810 addik r15, r0, dbtrap_call; 849 addik r15, r0, dbtrap_call;
811dbtrap_call: /* Return point for kernel/user entry + 8 because of rtsd r15, 8 */ 850dbtrap_call: /* Return point for kernel/user entry + 8 because of rtsd r15, 8 */
812 rtbd r0, sw_exception 851 rtbd r0, sw_exception
@@ -814,7 +853,7 @@ dbtrap_call: /* Return point for kernel/user entry + 8 because of rtsd r15, 8 */
814 853
815 /* MS: The first instruction for the second part of the gdb/kgdb */ 854 /* MS: The first instruction for the second part of the gdb/kgdb */
816 set_bip; /* Ints masked for state restore */ 855 set_bip; /* Ints masked for state restore */
817 lwi r11, r1, PTO + PT_MODE; 856 lwi r11, r1, PT_MODE;
818 bnei r11, 2f; 857 bnei r11, 2f;
819/* MS: Return to user space - gdb */ 858/* MS: Return to user space - gdb */
820 /* Get current task ptr into r11 */ 859 /* Get current task ptr into r11 */
@@ -833,7 +872,7 @@ dbtrap_call: /* Return point for kernel/user entry + 8 because of rtsd r15, 8 */
833 andi r11, r11, _TIF_SIGPENDING; 872 andi r11, r11, _TIF_SIGPENDING;
834 beqi r11, 1f; /* Signals to handle, handle them */ 873 beqi r11, 1f; /* Signals to handle, handle them */
835 874
836 addik r5, r1, PTO; /* Arg 1: struct pt_regs *regs */ 875 addik r5, r1, 0; /* Arg 1: struct pt_regs *regs */
837 addi r7, r0, 0; /* Arg 3: int in_syscall */ 876 addi r7, r0, 0; /* Arg 3: int in_syscall */
838 bralid r15, do_signal; /* Handle any signals */ 877 bralid r15, do_signal; /* Handle any signals */
839 add r6, r0, r0; /* Arg 2: sigset_t *oldset */ 878 add r6, r0, r0; /* Arg 2: sigset_t *oldset */
@@ -844,7 +883,7 @@ dbtrap_call: /* Return point for kernel/user entry + 8 because of rtsd r15, 8 */
844 tophys(r1,r1); 883 tophys(r1,r1);
845 /* MS: Restore all regs */ 884 /* MS: Restore all regs */
846 RESTORE_REGS 885 RESTORE_REGS
847 addik r1, r1, STATE_SAVE_SIZE /* Clean up stack space */ 886 addik r1, r1, PT_SIZE /* Clean up stack space */
848 lwi r1, r1, PT_R1 - PT_SIZE; /* Restore user stack pointer */ 887 lwi r1, r1, PT_R1 - PT_SIZE; /* Restore user stack pointer */
849DBTRAP_return_user: /* MS: Make global symbol for debugging */ 888DBTRAP_return_user: /* MS: Make global symbol for debugging */
850 rtbd r16, 0; /* MS: Instructions to return from a debug trap */ 889 rtbd r16, 0; /* MS: Instructions to return from a debug trap */
@@ -855,9 +894,9 @@ DBTRAP_return_user: /* MS: Make global symbol for debugging */
855 tophys(r1,r1); 894 tophys(r1,r1);
856 /* MS: Restore all regs */ 895 /* MS: Restore all regs */
857 RESTORE_REGS 896 RESTORE_REGS
858 lwi r14, r1, PTO+PT_R14; 897 lwi r14, r1, PT_R14;
859 lwi r16, r1, PTO+PT_PC; 898 lwi r16, r1, PT_PC;
860 addik r1, r1, STATE_SAVE_SIZE; /* MS: Clean up stack space */ 899 addik r1, r1, PT_SIZE; /* MS: Clean up stack space */
861 tovirt(r1,r1); 900 tovirt(r1,r1);
862DBTRAP_return_kernel: /* MS: Make global symbol for debugging */ 901DBTRAP_return_kernel: /* MS: Make global symbol for debugging */
863 rtbd r16, 0; /* MS: Instructions to return from a debug trap */ 902 rtbd r16, 0; /* MS: Instructions to return from a debug trap */
@@ -949,20 +988,22 @@ ENTRY(_switch_to)
949 nop 988 nop
950 989
951ENTRY(_reset) 990ENTRY(_reset)
952 brai 0x70; /* Jump back to FS-boot */ 991 brai 0; /* Jump to reset vector */
953 992
954 /* These are compiled and loaded into high memory, then 993 /* These are compiled and loaded into high memory, then
955 * copied into place in mach_early_setup */ 994 * copied into place in mach_early_setup */
956 .section .init.ivt, "ax" 995 .section .init.ivt, "ax"
996#if CONFIG_MANUAL_RESET_VECTOR
957 .org 0x0 997 .org 0x0
958 /* this is very important - here is the reset vector */ 998 brai CONFIG_MANUAL_RESET_VECTOR
959 /* in current MMU branch you don't care what is here - it is 999#endif
960 * used from bootloader site - but this is correct for FS-BOOT */ 1000 .org 0x8
961 brai 0x70
962 nop
963 brai TOPHYS(_user_exception); /* syscall handler */ 1001 brai TOPHYS(_user_exception); /* syscall handler */
1002 .org 0x10
964 brai TOPHYS(_interrupt); /* Interrupt handler */ 1003 brai TOPHYS(_interrupt); /* Interrupt handler */
1004 .org 0x18
965 brai TOPHYS(_debug_exception); /* debug trap handler */ 1005 brai TOPHYS(_debug_exception); /* debug trap handler */
1006 .org 0x20
966 brai TOPHYS(_hw_exception_handler); /* HW exception handler */ 1007 brai TOPHYS(_hw_exception_handler); /* HW exception handler */
967 1008
968.section .rodata,"a" 1009.section .rodata,"a"
diff --git a/arch/microblaze/kernel/exceptions.c b/arch/microblaze/kernel/exceptions.c
index 478f2943ede7..66fad2301221 100644
--- a/arch/microblaze/kernel/exceptions.c
+++ b/arch/microblaze/kernel/exceptions.c
@@ -25,6 +25,7 @@
25#include <linux/errno.h> 25#include <linux/errno.h>
26#include <linux/ptrace.h> 26#include <linux/ptrace.h>
27#include <asm/current.h> 27#include <asm/current.h>
28#include <asm/cacheflush.h>
28 29
29#define MICROBLAZE_ILL_OPCODE_EXCEPTION 0x02 30#define MICROBLAZE_ILL_OPCODE_EXCEPTION 0x02
30#define MICROBLAZE_IBUS_EXCEPTION 0x03 31#define MICROBLAZE_IBUS_EXCEPTION 0x03
@@ -49,9 +50,11 @@ void die(const char *str, struct pt_regs *fp, long err)
49} 50}
50 51
51/* for user application debugging */ 52/* for user application debugging */
52void sw_exception(struct pt_regs *regs) 53asmlinkage void sw_exception(struct pt_regs *regs)
53{ 54{
54 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->r16); 55 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->r16);
56 flush_dcache_range(regs->r16, regs->r16 + 0x4);
57 flush_icache_range(regs->r16, regs->r16 + 0x4);
55} 58}
56 59
57void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr) 60void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr)
diff --git a/arch/microblaze/kernel/head.S b/arch/microblaze/kernel/head.S
index 42434008209e..77320b8fc16a 100644
--- a/arch/microblaze/kernel/head.S
+++ b/arch/microblaze/kernel/head.S
@@ -39,7 +39,7 @@
39#include <asm/mmu.h> 39#include <asm/mmu.h>
40#include <asm/processor.h> 40#include <asm/processor.h>
41 41
42.data 42.section .data
43.global empty_zero_page 43.global empty_zero_page
44.align 12 44.align 12
45empty_zero_page: 45empty_zero_page:
@@ -50,6 +50,11 @@ swapper_pg_dir:
50 50
51#endif /* CONFIG_MMU */ 51#endif /* CONFIG_MMU */
52 52
53.section .rodata
54.align 4
55endian_check:
56 .word 1
57
53 __HEAD 58 __HEAD
54ENTRY(_start) 59ENTRY(_start)
55#if CONFIG_KERNEL_BASE_ADDR == 0 60#if CONFIG_KERNEL_BASE_ADDR == 0
@@ -62,23 +67,29 @@ real_start:
62 andi r1, r1, ~2 67 andi r1, r1, ~2
63 mts rmsr, r1 68 mts rmsr, r1
64/* 69/*
65 * Here is checking mechanism which check if Microblaze has msr instructions 70 * According to Xilinx, msrclr instruction behaves like 'mfs rX,rpc'
66 * We load msr and compare it with previous r1 value - if is the same, 71 * if the msrclr instruction is not enabled. We use this to detect
67 * msr instructions works if not - cpu don't have them. 72 * if the opcode is available, by issuing msrclr and then testing the result.
73 * r8 == 0 - msr instructions are implemented
74 * r8 != 0 - msr instructions are not implemented
68 */ 75 */
69 /* r8=0 - I have msr instr, 1 - I don't have them */ 76 msrclr r8, 0 /* clear nothing - just read msr for test */
70 rsubi r0, r0, 1 /* set the carry bit */ 77 cmpu r8, r8, r1 /* r1 must contain msr reg content */
71 msrclr r0, 0x4 /* try to clear it */
72 /* read the carry bit, r8 will be '0' if msrclr exists */
73 addik r8, r0, 0
74 78
75/* r7 may point to an FDT, or there may be one linked in. 79/* r7 may point to an FDT, or there may be one linked in.
76 if it's in r7, we've got to save it away ASAP. 80 if it's in r7, we've got to save it away ASAP.
77 We ensure r7 points to a valid FDT, just in case the bootloader 81 We ensure r7 points to a valid FDT, just in case the bootloader
78 is broken or non-existent */ 82 is broken or non-existent */
79 beqi r7, no_fdt_arg /* NULL pointer? don't copy */ 83 beqi r7, no_fdt_arg /* NULL pointer? don't copy */
80 lw r11, r0, r7 /* Does r7 point to a */ 84/* Does r7 point to a valid FDT? Load HEADER magic number */
81 rsubi r11, r11, OF_DT_HEADER /* valid FDT? */ 85 /* Run time Big/Little endian platform */
86 /* Save 1 as word and load byte - 0 - BIG, 1 - LITTLE */
87 lbui r11, r0, TOPHYS(endian_check)
88 beqid r11, big_endian /* DO NOT break delay stop dependency */
89 lw r11, r0, r7 /* Big endian load in delay slot */
90 lwr r11, r0, r7 /* Little endian load */
91big_endian:
92 rsubi r11, r11, OF_DT_HEADER /* Check FDT header */
82 beqi r11, _prepare_copy_fdt 93 beqi r11, _prepare_copy_fdt
83 or r7, r0, r0 /* clear R7 when not valid DTB */ 94 or r7, r0, r0 /* clear R7 when not valid DTB */
84 bnei r11, no_fdt_arg /* No - get out of here */ 95 bnei r11, no_fdt_arg /* No - get out of here */
@@ -213,26 +224,26 @@ start_here:
213#endif /* CONFIG_MMU */ 224#endif /* CONFIG_MMU */
214 225
215 /* Initialize small data anchors */ 226 /* Initialize small data anchors */
216 la r13, r0, _KERNEL_SDA_BASE_ 227 addik r13, r0, _KERNEL_SDA_BASE_
217 la r2, r0, _KERNEL_SDA2_BASE_ 228 addik r2, r0, _KERNEL_SDA2_BASE_
218 229
219 /* Initialize stack pointer */ 230 /* Initialize stack pointer */
220 la r1, r0, init_thread_union + THREAD_SIZE - 4 231 addik r1, r0, init_thread_union + THREAD_SIZE - 4
221 232
222 /* Initialize r31 with current task address */ 233 /* Initialize r31 with current task address */
223 la r31, r0, init_task 234 addik r31, r0, init_task
224 235
225 /* 236 /*
226 * Call platform dependent initialize function. 237 * Call platform dependent initialize function.
227 * Please see $(ARCH)/mach-$(SUBARCH)/setup.c for 238 * Please see $(ARCH)/mach-$(SUBARCH)/setup.c for
228 * the function. 239 * the function.
229 */ 240 */
230 la r9, r0, machine_early_init 241 addik r9, r0, machine_early_init
231 brald r15, r9 242 brald r15, r9
232 nop 243 nop
233 244
234#ifndef CONFIG_MMU 245#ifndef CONFIG_MMU
235 la r15, r0, machine_halt 246 addik r15, r0, machine_halt
236 braid start_kernel 247 braid start_kernel
237 nop 248 nop
238#else 249#else
diff --git a/arch/microblaze/kernel/hw_exception_handler.S b/arch/microblaze/kernel/hw_exception_handler.S
index 781195438ee6..56572e923a83 100644
--- a/arch/microblaze/kernel/hw_exception_handler.S
+++ b/arch/microblaze/kernel/hw_exception_handler.S
@@ -77,6 +77,8 @@
77#include <asm/signal.h> 77#include <asm/signal.h>
78#include <asm/asm-offsets.h> 78#include <asm/asm-offsets.h>
79 79
80#undef DEBUG
81
80/* Helpful Macros */ 82/* Helpful Macros */
81#define NUM_TO_REG(num) r ## num 83#define NUM_TO_REG(num) r ## num
82 84
@@ -91,7 +93,7 @@
91 lwi r6, r1, PT_R6; \ 93 lwi r6, r1, PT_R6; \
92 lwi r11, r1, PT_R11; \ 94 lwi r11, r1, PT_R11; \
93 lwi r31, r1, PT_R31; \ 95 lwi r31, r1, PT_R31; \
94 lwi r1, r0, TOPHYS(r0_ram + 0); 96 lwi r1, r1, PT_R1;
95#endif /* CONFIG_MMU */ 97#endif /* CONFIG_MMU */
96 98
97#define LWREG_NOP \ 99#define LWREG_NOP \
@@ -147,10 +149,6 @@
147 #if CONFIG_XILINX_MICROBLAZE0_USE_BARREL > 0 149 #if CONFIG_XILINX_MICROBLAZE0_USE_BARREL > 0
148 #define BSRLI(rD, rA, imm) \ 150 #define BSRLI(rD, rA, imm) \
149 bsrli rD, rA, imm 151 bsrli rD, rA, imm
150 #elif CONFIG_XILINX_MICROBLAZE0_USE_DIV > 0
151 #define BSRLI(rD, rA, imm) \
152 ori rD, r0, (1 << imm); \
153 idivu rD, rD, rA
154 #else 152 #else
155 #define BSRLI(rD, rA, imm) BSRLI ## imm (rD, rA) 153 #define BSRLI(rD, rA, imm) BSRLI ## imm (rD, rA)
156 /* Only the used shift constants defined here - add more if needed */ 154 /* Only the used shift constants defined here - add more if needed */
@@ -210,8 +208,8 @@
210 * | . | 208 * | . |
211 * | . | 209 * | . |
212 * 210 *
213 * NO_MMU kernel use the same r0_ram pointed space - look to vmlinux.lds.S 211 * MMU kernel uses the same 'pt_pool_space' pointed space
214 * which is used for storing register values - old style was, that value were 212 * which is used for storing register values - noMMu style was, that values were
215 * stored in stack but in case of failure you lost information about register. 213 * stored in stack but in case of failure you lost information about register.
216 * Currently you can see register value in memory in specific place. 214 * Currently you can see register value in memory in specific place.
217 * In compare to with previous solution the speed should be the same. 215 * In compare to with previous solution the speed should be the same.
@@ -230,8 +228,22 @@
230 */ 228 */
231 229
232/* wrappers to restore state before coming to entry.S */ 230/* wrappers to restore state before coming to entry.S */
233
234#ifdef CONFIG_MMU 231#ifdef CONFIG_MMU
232.section .data
233.align 4
234pt_pool_space:
235 .space PT_SIZE
236
237#ifdef DEBUG
238/* Create space for exception counting. */
239.section .data
240.global exception_debug_table
241.align 4
242exception_debug_table:
243 /* Look at exception vector table. There is 32 exceptions * word size */
244 .space (32 * 4)
245#endif /* DEBUG */
246
235.section .rodata 247.section .rodata
236.align 4 248.align 4
237_MB_HW_ExceptionVectorTable: 249_MB_HW_ExceptionVectorTable:
@@ -291,10 +303,10 @@ _hw_exception_handler:
291#ifndef CONFIG_MMU 303#ifndef CONFIG_MMU
292 addik r1, r1, -(EX_HANDLER_STACK_SIZ); /* Create stack frame */ 304 addik r1, r1, -(EX_HANDLER_STACK_SIZ); /* Create stack frame */
293#else 305#else
294 swi r1, r0, TOPHYS(r0_ram + 0); /* GET_SP */ 306 swi r1, r0, TOPHYS(pt_pool_space + PT_R1); /* GET_SP */
295 /* Save date to kernel memory. Here is the problem 307 /* Save date to kernel memory. Here is the problem
296 * when you came from user space */ 308 * when you came from user space */
297 ori r1, r0, TOPHYS(r0_ram + 28); 309 ori r1, r0, TOPHYS(pt_pool_space);
298#endif 310#endif
299 swi r3, r1, PT_R3 311 swi r3, r1, PT_R3
300 swi r4, r1, PT_R4 312 swi r4, r1, PT_R4
@@ -333,12 +345,12 @@ not_in_delay_slot:
333 345
334#ifdef DEBUG 346#ifdef DEBUG
335/* counting which exception happen */ 347/* counting which exception happen */
336 lwi r5, r0, 0x200 + TOPHYS(r0_ram) 348 lwi r5, r0, TOPHYS(exception_debug_table)
337 addi r5, r5, 1 349 addi r5, r5, 1
338 swi r5, r0, 0x200 + TOPHYS(r0_ram) 350 swi r5, r0, TOPHYS(exception_debug_table)
339 lwi r5, r6, 0x200 + TOPHYS(r0_ram) 351 lwi r5, r6, TOPHYS(exception_debug_table)
340 addi r5, r5, 1 352 addi r5, r5, 1
341 swi r5, r6, 0x200 + TOPHYS(r0_ram) 353 swi r5, r6, TOPHYS(exception_debug_table)
342#endif 354#endif
343/* end */ 355/* end */
344 /* Load the HW Exception vector */ 356 /* Load the HW Exception vector */
@@ -478,7 +490,7 @@ ex_lw_tail:
478 /* Get the destination register number into r5 */ 490 /* Get the destination register number into r5 */
479 lbui r5, r0, TOPHYS(ex_reg_op); 491 lbui r5, r0, TOPHYS(ex_reg_op);
480 /* Form load_word jump table offset (lw_table + (8 * regnum)) */ 492 /* Form load_word jump table offset (lw_table + (8 * regnum)) */
481 la r6, r0, TOPHYS(lw_table); 493 addik r6, r0, TOPHYS(lw_table);
482 addk r5, r5, r5; 494 addk r5, r5, r5;
483 addk r5, r5, r5; 495 addk r5, r5, r5;
484 addk r5, r5, r5; 496 addk r5, r5, r5;
@@ -489,7 +501,7 @@ ex_sw:
489 /* Get the destination register number into r5 */ 501 /* Get the destination register number into r5 */
490 lbui r5, r0, TOPHYS(ex_reg_op); 502 lbui r5, r0, TOPHYS(ex_reg_op);
491 /* Form store_word jump table offset (sw_table + (8 * regnum)) */ 503 /* Form store_word jump table offset (sw_table + (8 * regnum)) */
492 la r6, r0, TOPHYS(sw_table); 504 addik r6, r0, TOPHYS(sw_table);
493 add r5, r5, r5; 505 add r5, r5, r5;
494 add r5, r5, r5; 506 add r5, r5, r5;
495 add r5, r5, r5; 507 add r5, r5, r5;
@@ -900,7 +912,7 @@ ex_lw_vm:
900 beqid r6, ex_lhw_vm; 912 beqid r6, ex_lhw_vm;
901load1: lbui r5, r4, 0; /* Exception address in r4 - delay slot */ 913load1: lbui r5, r4, 0; /* Exception address in r4 - delay slot */
902/* Load a word, byte-by-byte from destination address and save it in tmp space*/ 914/* Load a word, byte-by-byte from destination address and save it in tmp space*/
903 la r6, r0, ex_tmp_data_loc_0; 915 addik r6, r0, ex_tmp_data_loc_0;
904 sbi r5, r6, 0; 916 sbi r5, r6, 0;
905load2: lbui r5, r4, 1; 917load2: lbui r5, r4, 1;
906 sbi r5, r6, 1; 918 sbi r5, r6, 1;
@@ -914,7 +926,7 @@ load4: lbui r5, r4, 3;
914ex_lhw_vm: 926ex_lhw_vm:
915 /* Load a half-word, byte-by-byte from destination address and 927 /* Load a half-word, byte-by-byte from destination address and
916 * save it in tmp space */ 928 * save it in tmp space */
917 la r6, r0, ex_tmp_data_loc_0; 929 addik r6, r0, ex_tmp_data_loc_0;
918 sbi r5, r6, 0; 930 sbi r5, r6, 0;
919load5: lbui r5, r4, 1; 931load5: lbui r5, r4, 1;
920 sbi r5, r6, 1; 932 sbi r5, r6, 1;
@@ -930,7 +942,7 @@ ex_sw_vm:
930 addik r5, r8, sw_table_vm; 942 addik r5, r8, sw_table_vm;
931 bra r5; 943 bra r5;
932ex_sw_tail_vm: 944ex_sw_tail_vm:
933 la r5, r0, ex_tmp_data_loc_0; 945 addik r5, r0, ex_tmp_data_loc_0;
934 beqid r6, ex_shw_vm; 946 beqid r6, ex_shw_vm;
935 swi r3, r5, 0; /* Get the word - delay slot */ 947 swi r3, r5, 0; /* Get the word - delay slot */
936 /* Store the word, byte-by-byte into destination address */ 948 /* Store the word, byte-by-byte into destination address */
@@ -945,11 +957,20 @@ store3: sbi r3, r4, 2;
945store4: sbi r3, r4, 3; /* Delay slot */ 957store4: sbi r3, r4, 3; /* Delay slot */
946ex_shw_vm: 958ex_shw_vm:
947 /* Store the lower half-word, byte-by-byte into destination address */ 959 /* Store the lower half-word, byte-by-byte into destination address */
960#ifdef __MICROBLAZEEL__
961 lbui r3, r5, 0;
962store5: sbi r3, r4, 0;
963 lbui r3, r5, 1;
964 brid ret_from_exc;
965store6: sbi r3, r4, 1; /* Delay slot */
966#else
948 lbui r3, r5, 2; 967 lbui r3, r5, 2;
949store5: sbi r3, r4, 0; 968store5: sbi r3, r4, 0;
950 lbui r3, r5, 3; 969 lbui r3, r5, 3;
951 brid ret_from_exc; 970 brid ret_from_exc;
952store6: sbi r3, r4, 1; /* Delay slot */ 971store6: sbi r3, r4, 1; /* Delay slot */
972#endif
973
953ex_sw_end_vm: /* Exception handling of store word, ends. */ 974ex_sw_end_vm: /* Exception handling of store word, ends. */
954 975
955/* We have to prevent cases that get/put_user macros get unaligned pointer 976/* We have to prevent cases that get/put_user macros get unaligned pointer
@@ -964,7 +985,7 @@ ex_unaligned_fixup:
964 addik r7, r0, SIGSEGV 985 addik r7, r0, SIGSEGV
965 /* call bad_page_fault for finding aligned fixup, fixup address is saved 986 /* call bad_page_fault for finding aligned fixup, fixup address is saved
966 * in PT_PC which is used as return address from exception */ 987 * in PT_PC which is used as return address from exception */
967 la r15, r0, ret_from_exc-8 /* setup return address */ 988 addik r15, r0, ret_from_exc-8 /* setup return address */
968 brid bad_page_fault 989 brid bad_page_fault
969 nop 990 nop
970 991
diff --git a/arch/microblaze/kernel/intc.c b/arch/microblaze/kernel/intc.c
index d61ea33aff7c..e4661285118e 100644
--- a/arch/microblaze/kernel/intc.c
+++ b/arch/microblaze/kernel/intc.c
@@ -40,59 +40,46 @@ unsigned int nr_irq;
40#define MER_ME (1<<0) 40#define MER_ME (1<<0)
41#define MER_HIE (1<<1) 41#define MER_HIE (1<<1)
42 42
43static void intc_enable_or_unmask(unsigned int irq) 43static void intc_enable_or_unmask(struct irq_data *d)
44{ 44{
45 unsigned long mask = 1 << irq; 45 unsigned long mask = 1 << d->irq;
46 pr_debug("enable_or_unmask: %d\n", irq); 46 pr_debug("enable_or_unmask: %d\n", d->irq);
47 out_be32(INTC_BASE + SIE, mask); 47 out_be32(INTC_BASE + SIE, mask);
48 48
49 /* ack level irqs because they can't be acked during 49 /* ack level irqs because they can't be acked during
50 * ack function since the handle_level_irq function 50 * ack function since the handle_level_irq function
51 * acks the irq before calling the interrupt handler 51 * acks the irq before calling the interrupt handler
52 */ 52 */
53 if (irq_desc[irq].status & IRQ_LEVEL) 53 if (irq_to_desc(d->irq)->status & IRQ_LEVEL)
54 out_be32(INTC_BASE + IAR, mask); 54 out_be32(INTC_BASE + IAR, mask);
55} 55}
56 56
57static void intc_disable_or_mask(unsigned int irq) 57static void intc_disable_or_mask(struct irq_data *d)
58{ 58{
59 pr_debug("disable: %d\n", irq); 59 pr_debug("disable: %d\n", d->irq);
60 out_be32(INTC_BASE + CIE, 1 << irq); 60 out_be32(INTC_BASE + CIE, 1 << d->irq);
61} 61}
62 62
63static void intc_ack(unsigned int irq) 63static void intc_ack(struct irq_data *d)
64{ 64{
65 pr_debug("ack: %d\n", irq); 65 pr_debug("ack: %d\n", d->irq);
66 out_be32(INTC_BASE + IAR, 1 << irq); 66 out_be32(INTC_BASE + IAR, 1 << d->irq);
67} 67}
68 68
69static void intc_mask_ack(unsigned int irq) 69static void intc_mask_ack(struct irq_data *d)
70{ 70{
71 unsigned long mask = 1 << irq; 71 unsigned long mask = 1 << d->irq;
72 pr_debug("disable_and_ack: %d\n", irq); 72 pr_debug("disable_and_ack: %d\n", d->irq);
73 out_be32(INTC_BASE + CIE, mask); 73 out_be32(INTC_BASE + CIE, mask);
74 out_be32(INTC_BASE + IAR, mask); 74 out_be32(INTC_BASE + IAR, mask);
75} 75}
76 76
77static void intc_end(unsigned int irq)
78{
79 unsigned long mask = 1 << irq;
80 pr_debug("end: %d\n", irq);
81 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
82 out_be32(INTC_BASE + SIE, mask);
83 /* ack level sensitive intr */
84 if (irq_desc[irq].status & IRQ_LEVEL)
85 out_be32(INTC_BASE + IAR, mask);
86 }
87}
88
89static struct irq_chip intc_dev = { 77static struct irq_chip intc_dev = {
90 .name = "Xilinx INTC", 78 .name = "Xilinx INTC",
91 .unmask = intc_enable_or_unmask, 79 .irq_unmask = intc_enable_or_unmask,
92 .mask = intc_disable_or_mask, 80 .irq_mask = intc_disable_or_mask,
93 .ack = intc_ack, 81 .irq_ack = intc_ack,
94 .mask_ack = intc_mask_ack, 82 .irq_mask_ack = intc_mask_ack,
95 .end = intc_end,
96}; 83};
97 84
98unsigned int get_irq(struct pt_regs *regs) 85unsigned int get_irq(struct pt_regs *regs)
@@ -172,11 +159,11 @@ void __init init_IRQ(void)
172 if (intr_type & (0x00000001 << i)) { 159 if (intr_type & (0x00000001 << i)) {
173 set_irq_chip_and_handler_name(i, &intc_dev, 160 set_irq_chip_and_handler_name(i, &intc_dev,
174 handle_edge_irq, intc_dev.name); 161 handle_edge_irq, intc_dev.name);
175 irq_desc[i].status &= ~IRQ_LEVEL; 162 irq_clear_status_flags(i, IRQ_LEVEL);
176 } else { 163 } else {
177 set_irq_chip_and_handler_name(i, &intc_dev, 164 set_irq_chip_and_handler_name(i, &intc_dev,
178 handle_level_irq, intc_dev.name); 165 handle_level_irq, intc_dev.name);
179 irq_desc[i].status |= IRQ_LEVEL; 166 irq_set_status_flags(i, IRQ_LEVEL);
180 } 167 }
181 } 168 }
182} 169}
diff --git a/arch/microblaze/kernel/irq.c b/arch/microblaze/kernel/irq.c
index a9345fb4906a..098822413729 100644
--- a/arch/microblaze/kernel/irq.c
+++ b/arch/microblaze/kernel/irq.c
@@ -50,6 +50,7 @@ next_irq:
50int show_interrupts(struct seq_file *p, void *v) 50int show_interrupts(struct seq_file *p, void *v)
51{ 51{
52 int i = *(loff_t *) v, j; 52 int i = *(loff_t *) v, j;
53 struct irq_desc *desc;
53 struct irqaction *action; 54 struct irqaction *action;
54 unsigned long flags; 55 unsigned long flags;
55 56
@@ -61,8 +62,9 @@ int show_interrupts(struct seq_file *p, void *v)
61 } 62 }
62 63
63 if (i < nr_irq) { 64 if (i < nr_irq) {
64 raw_spin_lock_irqsave(&irq_desc[i].lock, flags); 65 desc = irq_to_desc(i);
65 action = irq_desc[i].action; 66 raw_spin_lock_irqsave(&desc->lock, flags);
67 action = desc->action;
66 if (!action) 68 if (!action)
67 goto skip; 69 goto skip;
68 seq_printf(p, "%3d: ", i); 70 seq_printf(p, "%3d: ", i);
@@ -72,9 +74,9 @@ int show_interrupts(struct seq_file *p, void *v)
72 for_each_online_cpu(j) 74 for_each_online_cpu(j)
73 seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]); 75 seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]);
74#endif 76#endif
75 seq_printf(p, " %8s", irq_desc[i].status & 77 seq_printf(p, " %8s", desc->status &
76 IRQ_LEVEL ? "level" : "edge"); 78 IRQ_LEVEL ? "level" : "edge");
77 seq_printf(p, " %8s", irq_desc[i].chip->name); 79 seq_printf(p, " %8s", desc->irq_data.chip->name);
78 seq_printf(p, " %s", action->name); 80 seq_printf(p, " %s", action->name);
79 81
80 for (action = action->next; action; action = action->next) 82 for (action = action->next; action; action = action->next)
@@ -82,7 +84,7 @@ int show_interrupts(struct seq_file *p, void *v)
82 84
83 seq_putc(p, '\n'); 85 seq_putc(p, '\n');
84skip: 86skip:
85 raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags); 87 raw_spin_unlock_irqrestore(&desc->lock, flags);
86 } 88 }
87 return 0; 89 return 0;
88} 90}
diff --git a/arch/microblaze/kernel/microblaze_ksyms.c b/arch/microblaze/kernel/microblaze_ksyms.c
index 5cb034174005..49faeb429599 100644
--- a/arch/microblaze/kernel/microblaze_ksyms.c
+++ b/arch/microblaze/kernel/microblaze_ksyms.c
@@ -24,6 +24,7 @@
24 24
25extern char *_ebss; 25extern char *_ebss;
26EXPORT_SYMBOL_GPL(_ebss); 26EXPORT_SYMBOL_GPL(_ebss);
27
27#ifdef CONFIG_FUNCTION_TRACER 28#ifdef CONFIG_FUNCTION_TRACER
28extern void _mcount(void); 29extern void _mcount(void);
29EXPORT_SYMBOL(_mcount); 30EXPORT_SYMBOL(_mcount);
@@ -45,3 +46,14 @@ EXPORT_SYMBOL(empty_zero_page);
45#endif 46#endif
46 47
47EXPORT_SYMBOL(mbc); 48EXPORT_SYMBOL(mbc);
49
50extern void __divsi3(void);
51EXPORT_SYMBOL(__divsi3);
52extern void __modsi3(void);
53EXPORT_SYMBOL(__modsi3);
54extern void __mulsi3(void);
55EXPORT_SYMBOL(__mulsi3);
56extern void __udivsi3(void);
57EXPORT_SYMBOL(__udivsi3);
58extern void __umodsi3(void);
59EXPORT_SYMBOL(__umodsi3);
diff --git a/arch/microblaze/kernel/process.c b/arch/microblaze/kernel/process.c
index ba7c4b16ed35..968648a81c1e 100644
--- a/arch/microblaze/kernel/process.c
+++ b/arch/microblaze/kernel/process.c
@@ -159,7 +159,7 @@ int copy_thread(unsigned long clone_flags, unsigned long usp,
159 } 159 }
160 160
161 /* FIXME STATE_SAVE_PT_OFFSET; */ 161 /* FIXME STATE_SAVE_PT_OFFSET; */
162 ti->cpu_context.r1 = (unsigned long)childregs - STATE_SAVE_ARG_SPACE; 162 ti->cpu_context.r1 = (unsigned long)childregs;
163 /* we should consider the fact that childregs is a copy of the parent 163 /* we should consider the fact that childregs is a copy of the parent
164 * regs which were saved immediately after entering the kernel state 164 * regs which were saved immediately after entering the kernel state
165 * before enabling VM. This MSR will be restored in switch_to and 165 * before enabling VM. This MSR will be restored in switch_to and
diff --git a/arch/microblaze/kernel/prom.c b/arch/microblaze/kernel/prom.c
index a105301e2b7f..00ee90f08343 100644
--- a/arch/microblaze/kernel/prom.c
+++ b/arch/microblaze/kernel/prom.c
@@ -47,9 +47,9 @@ void __init early_init_dt_add_memory_arch(u64 base, u64 size)
47 memblock_add(base, size); 47 memblock_add(base, size);
48} 48}
49 49
50u64 __init early_init_dt_alloc_memory_arch(u64 size, u64 align) 50void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align)
51{ 51{
52 return memblock_alloc(size, align); 52 return __va(memblock_alloc(size, align));
53} 53}
54 54
55#ifdef CONFIG_EARLY_PRINTK 55#ifdef CONFIG_EARLY_PRINTK
@@ -59,16 +59,14 @@ static int __init early_init_dt_scan_serial(unsigned long node,
59{ 59{
60 unsigned long l; 60 unsigned long l;
61 char *p; 61 char *p;
62 int *addr; 62 const __be32 *addr;
63 63
64 pr_debug("search \"chosen\", depth: %d, uname: %s\n", depth, uname); 64 pr_debug("search \"serial\", depth: %d, uname: %s\n", depth, uname);
65 65
66/* find all serial nodes */ 66/* find all serial nodes */
67 if (strncmp(uname, "serial", 6) != 0) 67 if (strncmp(uname, "serial", 6) != 0)
68 return 0; 68 return 0;
69 69
70 early_init_dt_check_for_initrd(node);
71
72/* find compatible node with uartlite */ 70/* find compatible node with uartlite */
73 p = of_get_flat_dt_prop(node, "compatible", &l); 71 p = of_get_flat_dt_prop(node, "compatible", &l);
74 if ((strncmp(p, "xlnx,xps-uartlite", 17) != 0) && 72 if ((strncmp(p, "xlnx,xps-uartlite", 17) != 0) &&
diff --git a/arch/microblaze/kernel/prom_parse.c b/arch/microblaze/kernel/prom_parse.c
index 99d9b61cccb5..47187cc2cf00 100644
--- a/arch/microblaze/kernel/prom_parse.c
+++ b/arch/microblaze/kernel/prom_parse.c
@@ -2,88 +2,11 @@
2 2
3#include <linux/kernel.h> 3#include <linux/kernel.h>
4#include <linux/string.h> 4#include <linux/string.h>
5#include <linux/pci_regs.h>
6#include <linux/module.h> 5#include <linux/module.h>
7#include <linux/ioport.h> 6#include <linux/ioport.h>
8#include <linux/etherdevice.h> 7#include <linux/etherdevice.h>
9#include <linux/of_address.h> 8#include <linux/of_address.h>
10#include <asm/prom.h> 9#include <asm/prom.h>
11#include <asm/pci-bridge.h>
12
13#ifdef CONFIG_PCI
14int of_irq_map_pci(struct pci_dev *pdev, struct of_irq *out_irq)
15{
16 struct device_node *dn, *ppnode;
17 struct pci_dev *ppdev;
18 u32 lspec;
19 u32 laddr[3];
20 u8 pin;
21 int rc;
22
23 /* Check if we have a device node, if yes, fallback to standard OF
24 * parsing
25 */
26 dn = pci_device_to_OF_node(pdev);
27 if (dn)
28 return of_irq_map_one(dn, 0, out_irq);
29
30 /* Ok, we don't, time to have fun. Let's start by building up an
31 * interrupt spec. we assume #interrupt-cells is 1, which is standard
32 * for PCI. If you do different, then don't use that routine.
33 */
34 rc = pci_read_config_byte(pdev, PCI_INTERRUPT_PIN, &pin);
35 if (rc != 0)
36 return rc;
37 /* No pin, exit */
38 if (pin == 0)
39 return -ENODEV;
40
41 /* Now we walk up the PCI tree */
42 lspec = pin;
43 for (;;) {
44 /* Get the pci_dev of our parent */
45 ppdev = pdev->bus->self;
46
47 /* Ouch, it's a host bridge... */
48 if (ppdev == NULL) {
49 struct pci_controller *host;
50 host = pci_bus_to_host(pdev->bus);
51 ppnode = host ? host->dn : NULL;
52 /* No node for host bridge ? give up */
53 if (ppnode == NULL)
54 return -EINVAL;
55 } else
56 /* We found a P2P bridge, check if it has a node */
57 ppnode = pci_device_to_OF_node(ppdev);
58
59 /* Ok, we have found a parent with a device-node, hand over to
60 * the OF parsing code.
61 * We build a unit address from the linux device to be used for
62 * resolution. Note that we use the linux bus number which may
63 * not match your firmware bus numbering.
64 * Fortunately, in most cases, interrupt-map-mask doesn't
65 * include the bus number as part of the matching.
66 * You should still be careful about that though if you intend
67 * to rely on this function (you ship a firmware that doesn't
68 * create device nodes for all PCI devices).
69 */
70 if (ppnode)
71 break;
72
73 /* We can only get here if we hit a P2P bridge with no node,
74 * let's do standard swizzling and try again
75 */
76 lspec = pci_swizzle_interrupt_pin(pdev, lspec);
77 pdev = ppdev;
78 }
79
80 laddr[0] = (pdev->bus->number << 16)
81 | (pdev->devfn << 8);
82 laddr[1] = laddr[2] = 0;
83 return of_irq_map_raw(ppnode, &lspec, 1, laddr, out_irq);
84}
85EXPORT_SYMBOL_GPL(of_irq_map_pci);
86#endif /* CONFIG_PCI */
87 10
88void of_parse_dma_window(struct device_node *dn, const void *dma_window_prop, 11void of_parse_dma_window(struct device_node *dn, const void *dma_window_prop,
89 unsigned long *busno, unsigned long *phys, unsigned long *size) 12 unsigned long *busno, unsigned long *phys, unsigned long *size)
@@ -110,41 +33,3 @@ void of_parse_dma_window(struct device_node *dn, const void *dma_window_prop,
110 cells = prop ? *(u32 *)prop : of_n_size_cells(dn); 33 cells = prop ? *(u32 *)prop : of_n_size_cells(dn);
111 *size = of_read_number(dma_window, cells); 34 *size = of_read_number(dma_window, cells);
112} 35}
113
114/**
115 * Search the device tree for the best MAC address to use. 'mac-address' is
116 * checked first, because that is supposed to contain to "most recent" MAC
117 * address. If that isn't set, then 'local-mac-address' is checked next,
118 * because that is the default address. If that isn't set, then the obsolete
119 * 'address' is checked, just in case we're using an old device tree.
120 *
121 * Note that the 'address' property is supposed to contain a virtual address of
122 * the register set, but some DTS files have redefined that property to be the
123 * MAC address.
124 *
125 * All-zero MAC addresses are rejected, because those could be properties that
126 * exist in the device tree, but were not set by U-Boot. For example, the
127 * DTS could define 'mac-address' and 'local-mac-address', with zero MAC
128 * addresses. Some older U-Boots only initialized 'local-mac-address'. In
129 * this case, the real MAC is in 'local-mac-address', and 'mac-address' exists
130 * but is all zeros.
131*/
132const void *of_get_mac_address(struct device_node *np)
133{
134 struct property *pp;
135
136 pp = of_find_property(np, "mac-address", NULL);
137 if (pp && (pp->length == 6) && is_valid_ether_addr(pp->value))
138 return pp->value;
139
140 pp = of_find_property(np, "local-mac-address", NULL);
141 if (pp && (pp->length == 6) && is_valid_ether_addr(pp->value))
142 return pp->value;
143
144 pp = of_find_property(np, "address", NULL);
145 if (pp && (pp->length == 6) && is_valid_ether_addr(pp->value))
146 return pp->value;
147
148 return NULL;
149}
150EXPORT_SYMBOL(of_get_mac_address);
diff --git a/arch/microblaze/kernel/ptrace.c b/arch/microblaze/kernel/ptrace.c
index 05ac8cc975d5..6a8e0cc5c57d 100644
--- a/arch/microblaze/kernel/ptrace.c
+++ b/arch/microblaze/kernel/ptrace.c
@@ -39,6 +39,7 @@
39#include <linux/uaccess.h> 39#include <linux/uaccess.h>
40#include <asm/asm-offsets.h> 40#include <asm/asm-offsets.h>
41#include <asm/cacheflush.h> 41#include <asm/cacheflush.h>
42#include <asm/syscall.h>
42#include <asm/io.h> 43#include <asm/io.h>
43 44
44/* Returns the address where the register at REG_OFFS in P is stashed away. */ 45/* Returns the address where the register at REG_OFFS in P is stashed away. */
@@ -123,7 +124,7 @@ long arch_ptrace(struct task_struct *child, long request,
123 rval = -EIO; 124 rval = -EIO;
124 125
125 if (rval == 0 && request == PTRACE_PEEKUSR) 126 if (rval == 0 && request == PTRACE_PEEKUSR)
126 rval = put_user(val, (unsigned long *)data); 127 rval = put_user(val, (unsigned long __user *)data);
127 break; 128 break;
128 default: 129 default:
129 rval = ptrace_request(child, request, addr, data); 130 rval = ptrace_request(child, request, addr, data);
diff --git a/arch/microblaze/kernel/setup.c b/arch/microblaze/kernel/setup.c
index bb1558e4b283..8e2c09b7ff26 100644
--- a/arch/microblaze/kernel/setup.c
+++ b/arch/microblaze/kernel/setup.c
@@ -95,7 +95,8 @@ inline unsigned get_romfs_len(unsigned *addr)
95void __init machine_early_init(const char *cmdline, unsigned int ram, 95void __init machine_early_init(const char *cmdline, unsigned int ram,
96 unsigned int fdt, unsigned int msr) 96 unsigned int fdt, unsigned int msr)
97{ 97{
98 unsigned long *src, *dst = (unsigned long *)0x0; 98 unsigned long *src, *dst;
99 unsigned int offset = 0;
99 100
100 /* If CONFIG_MTD_UCLINUX is defined, assume ROMFS is at the 101 /* If CONFIG_MTD_UCLINUX is defined, assume ROMFS is at the
101 * end of kernel. There are two position which we want to check. 102 * end of kernel. There are two position which we want to check.
@@ -161,14 +162,21 @@ void __init machine_early_init(const char *cmdline, unsigned int ram,
161#if CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR 162#if CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR
162 if (msr) 163 if (msr)
163 eprintk("!!!Your kernel has setup MSR instruction but " 164 eprintk("!!!Your kernel has setup MSR instruction but "
164 "CPU don't have it %d\n", msr); 165 "CPU don't have it %x\n", msr);
165#else 166#else
166 if (!msr) 167 if (!msr)
167 eprintk("!!!Your kernel not setup MSR instruction but " 168 eprintk("!!!Your kernel not setup MSR instruction but "
168 "CPU have it %d\n", msr); 169 "CPU have it %x\n", msr);
169#endif 170#endif
170 171
171 for (src = __ivt_start; src < __ivt_end; src++, dst++) 172 /* Do not copy reset vectors. offset = 0x2 means skip the first
173 * two instructions. dst is pointer to MB vectors which are placed
174 * in block ram. If you want to copy reset vector setup offset to 0x0 */
175#if !CONFIG_MANUAL_RESET_VECTOR
176 offset = 0x2;
177#endif
178 dst = (unsigned long *) (offset * sizeof(u32));
179 for (src = __ivt_start + offset; src < __ivt_end; src++, dst++)
172 *dst = *src; 180 *dst = *src;
173 181
174 /* Initialize global data */ 182 /* Initialize global data */
diff --git a/arch/microblaze/kernel/signal.c b/arch/microblaze/kernel/signal.c
index d8d3bb396cd6..599671168980 100644
--- a/arch/microblaze/kernel/signal.c
+++ b/arch/microblaze/kernel/signal.c
@@ -93,7 +93,7 @@ static int restore_sigcontext(struct pt_regs *regs,
93asmlinkage long sys_rt_sigreturn(struct pt_regs *regs) 93asmlinkage long sys_rt_sigreturn(struct pt_regs *regs)
94{ 94{
95 struct rt_sigframe __user *frame = 95 struct rt_sigframe __user *frame =
96 (struct rt_sigframe __user *)(regs->r1 + STATE_SAVE_ARG_SPACE); 96 (struct rt_sigframe __user *)(regs->r1);
97 97
98 sigset_t set; 98 sigset_t set;
99 int rval; 99 int rval;
@@ -197,8 +197,8 @@ static void setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
197 197
198 /* Create the ucontext. */ 198 /* Create the ucontext. */
199 err |= __put_user(0, &frame->uc.uc_flags); 199 err |= __put_user(0, &frame->uc.uc_flags);
200 err |= __put_user(0, &frame->uc.uc_link); 200 err |= __put_user(NULL, &frame->uc.uc_link);
201 err |= __put_user((void *)current->sas_ss_sp, 201 err |= __put_user((void __user *)current->sas_ss_sp,
202 &frame->uc.uc_stack.ss_sp); 202 &frame->uc.uc_stack.ss_sp);
203 err |= __put_user(sas_ss_flags(regs->r1), 203 err |= __put_user(sas_ss_flags(regs->r1),
204 &frame->uc.uc_stack.ss_flags); 204 &frame->uc.uc_stack.ss_flags);
@@ -247,7 +247,7 @@ static void setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
247 goto give_sigsegv; 247 goto give_sigsegv;
248 248
249 /* Set up registers for signal handler */ 249 /* Set up registers for signal handler */
250 regs->r1 = (unsigned long) frame - STATE_SAVE_ARG_SPACE; 250 regs->r1 = (unsigned long) frame;
251 251
252 /* Signal handler args: */ 252 /* Signal handler args: */
253 regs->r5 = signal; /* arg 0: signum */ 253 regs->r5 = signal; /* arg 0: signum */
diff --git a/arch/microblaze/kernel/sys_microblaze.c b/arch/microblaze/kernel/sys_microblaze.c
index 2250fe9d269b..e5b154f24f85 100644
--- a/arch/microblaze/kernel/sys_microblaze.c
+++ b/arch/microblaze/kernel/sys_microblaze.c
@@ -40,7 +40,8 @@ asmlinkage long microblaze_vfork(struct pt_regs *regs)
40 regs, 0, NULL, NULL); 40 regs, 0, NULL, NULL);
41} 41}
42 42
43asmlinkage long microblaze_clone(int flags, unsigned long stack, struct pt_regs *regs) 43asmlinkage long microblaze_clone(int flags, unsigned long stack,
44 struct pt_regs *regs)
44{ 45{
45 if (!stack) 46 if (!stack)
46 stack = regs->r1; 47 stack = regs->r1;
diff --git a/arch/microblaze/kernel/timer.c b/arch/microblaze/kernel/timer.c
index a5aa33db1df3..d8a214f11ac2 100644
--- a/arch/microblaze/kernel/timer.c
+++ b/arch/microblaze/kernel/timer.c
@@ -38,8 +38,8 @@ static unsigned int timer_baseaddr;
38#define TIMER_BASE timer_baseaddr 38#define TIMER_BASE timer_baseaddr
39#endif 39#endif
40 40
41unsigned int freq_div_hz; 41static unsigned int freq_div_hz;
42unsigned int timer_clock_freq; 42static unsigned int timer_clock_freq;
43 43
44#define TCSR0 (0x00) 44#define TCSR0 (0x00)
45#define TLR0 (0x04) 45#define TLR0 (0x04)
@@ -202,7 +202,7 @@ static struct cyclecounter microblaze_cc = {
202 .shift = 8, 202 .shift = 8,
203}; 203};
204 204
205int __init init_microblaze_timecounter(void) 205static int __init init_microblaze_timecounter(void)
206{ 206{
207 microblaze_cc.mult = div_sc(timer_clock_freq, NSEC_PER_SEC, 207 microblaze_cc.mult = div_sc(timer_clock_freq, NSEC_PER_SEC,
208 microblaze_cc.shift); 208 microblaze_cc.shift);
diff --git a/arch/microblaze/kernel/unwind.c b/arch/microblaze/kernel/unwind.c
index fefac5c33586..9781a528cfc9 100644
--- a/arch/microblaze/kernel/unwind.c
+++ b/arch/microblaze/kernel/unwind.c
@@ -183,7 +183,7 @@ static inline void unwind_trap(struct task_struct *task, unsigned long pc,
183 * @trace : Where to store stack backtrace (PC values). 183 * @trace : Where to store stack backtrace (PC values).
184 * NULL == print backtrace to kernel log 184 * NULL == print backtrace to kernel log
185 */ 185 */
186void microblaze_unwind_inner(struct task_struct *task, 186static void microblaze_unwind_inner(struct task_struct *task,
187 unsigned long pc, unsigned long fp, 187 unsigned long pc, unsigned long fp,
188 unsigned long leaf_return, 188 unsigned long leaf_return,
189 struct stack_trace *trace) 189 struct stack_trace *trace)
diff --git a/arch/microblaze/kernel/vmlinux.lds.S b/arch/microblaze/kernel/vmlinux.lds.S
index 96a88c31fe48..ac0e1a5d4782 100644
--- a/arch/microblaze/kernel/vmlinux.lds.S
+++ b/arch/microblaze/kernel/vmlinux.lds.S
@@ -70,11 +70,6 @@ SECTIONS {
70 RW_DATA_SECTION(32, PAGE_SIZE, THREAD_SIZE) 70 RW_DATA_SECTION(32, PAGE_SIZE, THREAD_SIZE)
71 _edata = . ; 71 _edata = . ;
72 72
73 /* Reserve some low RAM for r0 based memory references */
74 . = ALIGN(0x4) ;
75 r0_ram = . ;
76 . = . + PAGE_SIZE; /* a page should be enough */
77
78 /* Under the microblaze ABI, .sdata and .sbss must be contiguous */ 73 /* Under the microblaze ABI, .sdata and .sbss must be contiguous */
79 . = ALIGN(8); 74 . = ALIGN(8);
80 .sdata : AT(ADDR(.sdata) - LOAD_OFFSET) { 75 .sdata : AT(ADDR(.sdata) - LOAD_OFFSET) {
@@ -123,20 +118,10 @@ SECTIONS {
123 118
124 __init_end_before_initramfs = .; 119 __init_end_before_initramfs = .;
125 120
126 .init.ramfs ALIGN(PAGE_SIZE) : AT(ADDR(.init.ramfs) - LOAD_OFFSET) { 121 .init.ramfs : AT(ADDR(.init.ramfs) - LOAD_OFFSET) {
127 __initramfs_start = .; 122 INIT_RAM_FS
128 *(.init.ramfs)
129 __initramfs_end = .;
130 . = ALIGN(4);
131 LONG(0);
132/*
133 * FIXME this can break initramfs for MMU.
134 * Pad init.ramfs up to page boundary,
135 * so that __init_end == __bss_start. This will make image.elf
136 * consistent with the image.bin
137 */
138 /* . = ALIGN(PAGE_SIZE); */
139 } 123 }
124
140 __init_end = .; 125 __init_end = .;
141 126
142 .bss ALIGN (PAGE_SIZE) : AT(ADDR(.bss) - LOAD_OFFSET) { 127 .bss ALIGN (PAGE_SIZE) : AT(ADDR(.bss) - LOAD_OFFSET) {
diff --git a/arch/microblaze/lib/fastcopy.S b/arch/microblaze/lib/fastcopy.S
index fdc48bb065d8..62021d7e249e 100644
--- a/arch/microblaze/lib/fastcopy.S
+++ b/arch/microblaze/lib/fastcopy.S
@@ -29,6 +29,10 @@
29 * between mem locations with size of xfer spec'd in bytes 29 * between mem locations with size of xfer spec'd in bytes
30 */ 30 */
31 31
32#ifdef __MICROBLAZEEL__
33#error Microblaze LE not support ASM optimized lib func. Disable OPT_LIB_ASM.
34#endif
35
32#include <linux/linkage.h> 36#include <linux/linkage.h>
33 .text 37 .text
34 .globl memcpy 38 .globl memcpy
diff --git a/arch/microblaze/lib/memmove.c b/arch/microblaze/lib/memmove.c
index 123e3616f2dd..810fd68775e3 100644
--- a/arch/microblaze/lib/memmove.c
+++ b/arch/microblaze/lib/memmove.c
@@ -182,7 +182,7 @@ void *memmove(void *v_dst, const void *v_src, __kernel_size_t c)
182 for (; c >= 4; c -= 4) { 182 for (; c >= 4; c -= 4) {
183 value = *--i_src; 183 value = *--i_src;
184 *--i_dst = buf_hold | ((value & 0xFF000000)>> 24); 184 *--i_dst = buf_hold | ((value & 0xFF000000)>> 24);
185 buf_hold = (value & 0xFFFFFF) << 8;; 185 buf_hold = (value & 0xFFFFFF) << 8;
186 } 186 }
187#endif 187#endif
188 /* Realign the source */ 188 /* Realign the source */
diff --git a/arch/microblaze/lib/muldi3.S b/arch/microblaze/lib/muldi3.S
deleted file mode 100644
index ceeaa8c407f2..000000000000
--- a/arch/microblaze/lib/muldi3.S
+++ /dev/null
@@ -1,121 +0,0 @@
1#include <linux/linkage.h>
2
3/*
4 * Multiply operation for 64 bit integers, for devices with hard multiply
5 * Input : Operand1[H] in Reg r5
6 * Operand1[L] in Reg r6
7 * Operand2[H] in Reg r7
8 * Operand2[L] in Reg r8
9 * Output: Result[H] in Reg r3
10 * Result[L] in Reg r4
11 *
12 * Explaination:
13 *
14 * Both the input numbers are divided into 16 bit number as follows
15 * op1 = A B C D
16 * op2 = E F G H
17 * result = D * H
18 * + (C * H + D * G) << 16
19 * + (B * H + C * G + D * F) << 32
20 * + (A * H + B * G + C * F + D * E) << 48
21 *
22 * Only 64 bits of the output are considered
23 */
24
25 .text
26 .globl __muldi3
27 .type __muldi3, @function
28 .ent __muldi3
29
30__muldi3:
31 addi r1, r1, -40
32
33/* Save the input operands on the caller's stack */
34 swi r5, r1, 44
35 swi r6, r1, 48
36 swi r7, r1, 52
37 swi r8, r1, 56
38
39/* Store all the callee saved registers */
40 sw r20, r1, r0
41 swi r21, r1, 4
42 swi r22, r1, 8
43 swi r23, r1, 12
44 swi r24, r1, 16
45 swi r25, r1, 20
46 swi r26, r1, 24
47 swi r27, r1, 28
48
49/* Load all the 16 bit values for A thru H */
50 lhui r20, r1, 44 /* A */
51 lhui r21, r1, 46 /* B */
52 lhui r22, r1, 48 /* C */
53 lhui r23, r1, 50 /* D */
54 lhui r24, r1, 52 /* E */
55 lhui r25, r1, 54 /* F */
56 lhui r26, r1, 56 /* G */
57 lhui r27, r1, 58 /* H */
58
59/* D * H ==> LSB of the result on stack ==> Store1 */
60 mul r9, r23, r27
61 swi r9, r1, 36 /* Pos2 and Pos3 */
62
63/* Hi (Store1) + C * H + D * G ==> Store2 ==> Pos1 and Pos2 */
64/* Store the carry generated in position 2 for Pos 3 */
65 lhui r11, r1, 36 /* Pos2 */
66 mul r9, r22, r27 /* C * H */
67 mul r10, r23, r26 /* D * G */
68 add r9, r9, r10
69 addc r12, r0, r0
70 add r9, r9, r11
71 addc r12, r12, r0 /* Store the Carry */
72 shi r9, r1, 36 /* Store Pos2 */
73 swi r9, r1, 32
74 lhui r11, r1, 32
75 shi r11, r1, 34 /* Store Pos1 */
76
77/* Hi (Store2) + B * H + C * G + D * F ==> Store3 ==> Pos0 and Pos1 */
78 mul r9, r21, r27 /* B * H */
79 mul r10, r22, r26 /* C * G */
80 mul r7, r23, r25 /* D * F */
81 add r9, r9, r11
82 add r9, r9, r10
83 add r9, r9, r7
84 swi r9, r1, 32 /* Pos0 and Pos1 */
85
86/* Hi (Store3) + A * H + B * G + C * F + D * E ==> Store3 ==> Pos0 */
87 lhui r11, r1, 32 /* Pos0 */
88 mul r9, r20, r27 /* A * H */
89 mul r10, r21, r26 /* B * G */
90 mul r7, r22, r25 /* C * F */
91 mul r8, r23, r24 /* D * E */
92 add r9, r9, r11
93 add r9, r9, r10
94 add r9, r9, r7
95 add r9, r9, r8
96 sext16 r9, r9 /* Sign extend the MSB */
97 shi r9, r1, 32
98
99/* Move results to r3 and r4 */
100 lhui r3, r1, 32
101 add r3, r3, r12
102 shi r3, r1, 32
103 lwi r3, r1, 32 /* Hi Part */
104 lwi r4, r1, 36 /* Lo Part */
105
106/* Restore Callee saved registers */
107 lw r20, r1, r0
108 lwi r21, r1, 4
109 lwi r22, r1, 8
110 lwi r23, r1, 12
111 lwi r24, r1, 16
112 lwi r25, r1, 20
113 lwi r26, r1, 24
114 lwi r27, r1, 28
115
116/* Restore Frame and return */
117 rtsd r15, 8
118 addi r1, r1, 40
119
120.size __muldi3, . - __muldi3
121.end __muldi3
diff --git a/arch/microblaze/lib/muldi3.c b/arch/microblaze/lib/muldi3.c
new file mode 100644
index 000000000000..0585bccb7fad
--- /dev/null
+++ b/arch/microblaze/lib/muldi3.c
@@ -0,0 +1,61 @@
1#include <linux/module.h>
2
3#include "libgcc.h"
4
5#define DWtype long long
6#define UWtype unsigned long
7#define UHWtype unsigned short
8
9#define W_TYPE_SIZE 32
10
11#define __ll_B ((UWtype) 1 << (W_TYPE_SIZE / 2))
12#define __ll_lowpart(t) ((UWtype) (t) & (__ll_B - 1))
13#define __ll_highpart(t) ((UWtype) (t) >> (W_TYPE_SIZE / 2))
14
15/* If we still don't have umul_ppmm, define it using plain C. */
16#if !defined(umul_ppmm)
17#define umul_ppmm(w1, w0, u, v) \
18 do { \
19 UWtype __x0, __x1, __x2, __x3; \
20 UHWtype __ul, __vl, __uh, __vh; \
21 \
22 __ul = __ll_lowpart(u); \
23 __uh = __ll_highpart(u); \
24 __vl = __ll_lowpart(v); \
25 __vh = __ll_highpart(v); \
26 \
27 __x0 = (UWtype) __ul * __vl; \
28 __x1 = (UWtype) __ul * __vh; \
29 __x2 = (UWtype) __uh * __vl; \
30 __x3 = (UWtype) __uh * __vh; \
31 \
32 __x1 += __ll_highpart(__x0); /* this can't give carry */\
33 __x1 += __x2; /* but this indeed can */ \
34 if (__x1 < __x2) /* did we get it? */ \
35 __x3 += __ll_B; /* yes, add it in the proper pos */ \
36 \
37 (w1) = __x3 + __ll_highpart(__x1); \
38 (w0) = __ll_lowpart(__x1) * __ll_B + __ll_lowpart(__x0);\
39 } while (0)
40#endif
41
42#if !defined(__umulsidi3)
43#define __umulsidi3(u, v) ({ \
44 DWunion __w; \
45 umul_ppmm(__w.s.high, __w.s.low, u, v); \
46 __w.ll; \
47 })
48#endif
49
50DWtype __muldi3(DWtype u, DWtype v)
51{
52 const DWunion uu = {.ll = u};
53 const DWunion vv = {.ll = v};
54 DWunion w = {.ll = __umulsidi3(uu.s.low, vv.s.low)};
55
56 w.s.high += ((UWtype) uu.s.low * (UWtype) vv.s.high
57 + (UWtype) uu.s.high * (UWtype) vv.s.low);
58
59 return w.ll;
60}
61EXPORT_SYMBOL(__muldi3);
diff --git a/arch/microblaze/mm/consistent.c b/arch/microblaze/mm/consistent.c
index 5a59dad62bd2..a1e2e18e0961 100644
--- a/arch/microblaze/mm/consistent.c
+++ b/arch/microblaze/mm/consistent.c
@@ -59,7 +59,7 @@
59 * uncached region. This will no doubt cause big problems if memory allocated 59 * uncached region. This will no doubt cause big problems if memory allocated
60 * here is not also freed properly. -- JW 60 * here is not also freed properly. -- JW
61 */ 61 */
62void *consistent_alloc(int gfp, size_t size, dma_addr_t *dma_handle) 62void *consistent_alloc(gfp_t gfp, size_t size, dma_addr_t *dma_handle)
63{ 63{
64 unsigned long order, vaddr; 64 unsigned long order, vaddr;
65 void *ret; 65 void *ret;
diff --git a/arch/microblaze/mm/fault.c b/arch/microblaze/mm/fault.c
index 57bd2a09610c..ae97d2ccdc22 100644
--- a/arch/microblaze/mm/fault.c
+++ b/arch/microblaze/mm/fault.c
@@ -48,7 +48,7 @@ static int store_updates_sp(struct pt_regs *regs)
48{ 48{
49 unsigned int inst; 49 unsigned int inst;
50 50
51 if (get_user(inst, (unsigned int *)regs->pc)) 51 if (get_user(inst, (unsigned int __user *)regs->pc))
52 return 0; 52 return 0;
53 /* check for 1 in the rD field */ 53 /* check for 1 in the rD field */
54 if (((inst >> 21) & 0x1f) != 1) 54 if (((inst >> 21) & 0x1f) != 1)
diff --git a/arch/microblaze/pci/pci-common.c b/arch/microblaze/pci/pci-common.c
index e363615d6798..1e01a1253631 100644
--- a/arch/microblaze/pci/pci-common.c
+++ b/arch/microblaze/pci/pci-common.c
@@ -29,6 +29,7 @@
29#include <linux/slab.h> 29#include <linux/slab.h>
30#include <linux/of.h> 30#include <linux/of.h>
31#include <linux/of_address.h> 31#include <linux/of_address.h>
32#include <linux/of_pci.h>
32 33
33#include <asm/processor.h> 34#include <asm/processor.h>
34#include <asm/io.h> 35#include <asm/io.h>
diff --git a/arch/microblaze/pci/pci_32.c b/arch/microblaze/pci/pci_32.c
index 3c3d808d7ce0..92728a6cfd80 100644
--- a/arch/microblaze/pci/pci_32.c
+++ b/arch/microblaze/pci/pci_32.c
@@ -332,6 +332,7 @@ static void __devinit pcibios_scan_phb(struct pci_controller *hose)
332 hose->global_number); 332 hose->global_number);
333 return; 333 return;
334 } 334 }
335 bus.dev->of_node = of_node_get(node);
335 bus->secondary = hose->first_busno; 336 bus->secondary = hose->first_busno;
336 hose->bus = bus; 337 hose->bus = bus;
337 338
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-29 22:35:00 -0500