1 files changed, 9 insertions, 34 deletions

diff --git a/arch/microblaze/kernel/misc.S b/arch/microblaze/kernel/misc.S
index df16c6287a8e..0fb5fc6c1fc2 100644
--- a/arch/microblaze/kernel/misc.S
+++ b/arch/microblaze/kernel/misc.S
@@ -26,9 +26,10 @@
  * We avoid flushing the pinned 0, 1 and possibly 2 entries.
  */
 .globl _tlbia;
+.type  _tlbia, @function
 .align 4;
 _tlbia:
-        addik   r12, r0, 63 /* flush all entries (63 - 3) */
+        addik   r12, r0, MICROBLAZE_TLB_SIZE - 1 /* flush all entries (63 - 3) */
         /* isync */
 _tlbia_1:
         mts     rtlbx, r12
@@ -41,11 +42,13 @@ _tlbia_1:
         /* sync */
         rtsd    r15, 8
         nop
+        .size  _tlbia, . - _tlbia
 
 /*
  * Flush MMU TLB for a particular address (in r5)
  */
 .globl _tlbie;
+.type  _tlbie, @function
 .align 4;
 _tlbie:
         mts     rtlbsx, r5 /* look up the address in TLB */
@@ -59,17 +62,20 @@ _tlbie_1:
         rtsd    r15, 8
         nop
 
+        .size  _tlbie, . - _tlbie
+
 /*
  * Allocate TLB entry for early console
  */
 .globl early_console_reg_tlb_alloc;
+.type  early_console_reg_tlb_alloc, @function
 .align 4;
 early_console_reg_tlb_alloc:
         /*
          * Load a TLB entry for the UART, so that microblaze_progress() can use
          * the UARTs nice and early.  We use a 4k real==virtual mapping.
          */
-        ori     r4, r0, 63
+        ori     r4, r0, MICROBLAZE_TLB_SIZE - 1
         mts     rtlbx, r4 /* TLB slot 2 */
 
         or      r4,r5,r0
@@ -86,35 +92,4 @@ early_console_reg_tlb_alloc:
         rtsd    r15, 8
         nop
 
-/*
- * Copy a whole page (4096 bytes).
- */
-#define COPY_16_BYTES           \
-        lwi     r7, r6, 0;      \
-        lwi     r8, r6, 4;      \
-        lwi     r9, r6, 8;      \
-        lwi     r10, r6, 12;    \
-        swi     r7, r5, 0;      \
-        swi     r8, r5, 4;      \
-        swi     r9, r5, 8;      \
-        swi     r10, r5, 12
-
-
-/* FIXME DCACHE_LINE_BYTES (CONFIG_XILINX_MICROBLAZE0_DCACHE_LINE_LEN * 4)*/
-#define DCACHE_LINE_BYTES (4 * 4)
-
-.globl copy_page;
-.align 4;
-copy_page:
-        ori     r11, r0, (PAGE_SIZE/DCACHE_LINE_BYTES) - 1
-_copy_page_loop:
-        COPY_16_BYTES
-#if DCACHE_LINE_BYTES >= 32
-        COPY_16_BYTES
-#endif
-        addik   r6, r6, DCACHE_LINE_BYTES
-        addik   r5, r5, DCACHE_LINE_BYTES
-        bneid   r11, _copy_page_loop
-        addik   r11, r11, -1
-        rtsd    r15, 8
-        nop
+        .size  early_console_reg_tlb_alloc, . - early_console_reg_tlb_alloc