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Diffstat (limited to 'arch/microblaze/kernel/cpu/cpuinfo-static.c')
-rw-r--r--arch/microblaze/kernel/cpu/cpuinfo-static.c17
1 files changed, 9 insertions, 8 deletions
diff --git a/arch/microblaze/kernel/cpu/cpuinfo-static.c b/arch/microblaze/kernel/cpu/cpuinfo-static.c
index adb448f93d5f..6095aa6b5c88 100644
--- a/arch/microblaze/kernel/cpu/cpuinfo-static.c
+++ b/arch/microblaze/kernel/cpu/cpuinfo-static.c
@@ -72,12 +72,12 @@ void __init set_cpuinfo_static(struct cpuinfo *ci, struct device_node *cpu)
72 ci->use_icache = fcpu(cpu, "xlnx,use-icache"); 72 ci->use_icache = fcpu(cpu, "xlnx,use-icache");
73 ci->icache_tagbits = fcpu(cpu, "xlnx,addr-tag-bits"); 73 ci->icache_tagbits = fcpu(cpu, "xlnx,addr-tag-bits");
74 ci->icache_write = fcpu(cpu, "xlnx,allow-icache-wr"); 74 ci->icache_write = fcpu(cpu, "xlnx,allow-icache-wr");
75 ci->icache_line = fcpu(cpu, "xlnx,icache-line-len") << 2; 75 ci->icache_line_length = fcpu(cpu, "xlnx,icache-line-len") << 2;
76 if (!ci->icache_line) { 76 if (!ci->icache_line_length) {
77 if (fcpu(cpu, "xlnx,icache-use-fsl")) 77 if (fcpu(cpu, "xlnx,icache-use-fsl"))
78 ci->icache_line = 4 << 2; 78 ci->icache_line_length = 4 << 2;
79 else 79 else
80 ci->icache_line = 1 << 2; 80 ci->icache_line_length = 1 << 2;
81 } 81 }
82 ci->icache_size = fcpu(cpu, "i-cache-size"); 82 ci->icache_size = fcpu(cpu, "i-cache-size");
83 ci->icache_base = fcpu(cpu, "i-cache-baseaddr"); 83 ci->icache_base = fcpu(cpu, "i-cache-baseaddr");
@@ -86,16 +86,17 @@ void __init set_cpuinfo_static(struct cpuinfo *ci, struct device_node *cpu)
86 ci->use_dcache = fcpu(cpu, "xlnx,use-dcache"); 86 ci->use_dcache = fcpu(cpu, "xlnx,use-dcache");
87 ci->dcache_tagbits = fcpu(cpu, "xlnx,dcache-addr-tag"); 87 ci->dcache_tagbits = fcpu(cpu, "xlnx,dcache-addr-tag");
88 ci->dcache_write = fcpu(cpu, "xlnx,allow-dcache-wr"); 88 ci->dcache_write = fcpu(cpu, "xlnx,allow-dcache-wr");
89 ci->dcache_line = fcpu(cpu, "xlnx,dcache-line-len") << 2; 89 ci->dcache_line_length = fcpu(cpu, "xlnx,dcache-line-len") << 2;
90 if (!ci->dcache_line) { 90 if (!ci->dcache_line_length) {
91 if (fcpu(cpu, "xlnx,dcache-use-fsl")) 91 if (fcpu(cpu, "xlnx,dcache-use-fsl"))
92 ci->dcache_line = 4 << 2; 92 ci->dcache_line_length = 4 << 2;
93 else 93 else
94 ci->dcache_line = 1 << 2; 94 ci->dcache_line_length = 1 << 2;
95 } 95 }
96 ci->dcache_size = fcpu(cpu, "d-cache-size"); 96 ci->dcache_size = fcpu(cpu, "d-cache-size");
97 ci->dcache_base = fcpu(cpu, "d-cache-baseaddr"); 97 ci->dcache_base = fcpu(cpu, "d-cache-baseaddr");
98 ci->dcache_high = fcpu(cpu, "d-cache-highaddr"); 98 ci->dcache_high = fcpu(cpu, "d-cache-highaddr");
99 ci->dcache_wb = fcpu(cpu, "xlnx,dcache-use-writeback");
99 100
100 ci->use_dopb = fcpu(cpu, "xlnx,d-opb"); 101 ci->use_dopb = fcpu(cpu, "xlnx,d-opb");
101 ci->use_iopb = fcpu(cpu, "xlnx,i-opb"); 102 ci->use_iopb = fcpu(cpu, "xlnx,i-opb");