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-rw-r--r--arch/m68knommu/platform/520x/config.c36
-rw-r--r--arch/m68knommu/platform/coldfire/head.S4
2 files changed, 20 insertions, 20 deletions
diff --git a/arch/m68knommu/platform/520x/config.c b/arch/m68knommu/platform/520x/config.c
index 71d2ba474c63..621238f1a219 100644
--- a/arch/m68knommu/platform/520x/config.c
+++ b/arch/m68knommu/platform/520x/config.c
@@ -27,15 +27,15 @@
27 27
28static struct mcf_platform_uart m520x_uart_platform[] = { 28static struct mcf_platform_uart m520x_uart_platform[] = {
29 { 29 {
30 .mapbase = MCF_MBAR + MCFUART_BASE1, 30 .mapbase = MCFUART_BASE1,
31 .irq = MCFINT_VECBASE + MCFINT_UART0, 31 .irq = MCFINT_VECBASE + MCFINT_UART0,
32 }, 32 },
33 { 33 {
34 .mapbase = MCF_MBAR + MCFUART_BASE2, 34 .mapbase = MCFUART_BASE2,
35 .irq = MCFINT_VECBASE + MCFINT_UART1, 35 .irq = MCFINT_VECBASE + MCFINT_UART1,
36 }, 36 },
37 { 37 {
38 .mapbase = MCF_MBAR + MCFUART_BASE3, 38 .mapbase = MCFUART_BASE3,
39 .irq = MCFINT_VECBASE + MCFINT_UART2, 39 .irq = MCFINT_VECBASE + MCFINT_UART2,
40 }, 40 },
41 { }, 41 { },
@@ -49,8 +49,8 @@ static struct platform_device m520x_uart = {
49 49
50static struct resource m520x_fec_resources[] = { 50static struct resource m520x_fec_resources[] = {
51 { 51 {
52 .start = MCF_MBAR + 0x30000, 52 .start = MCFFEC_BASE,
53 .end = MCF_MBAR + 0x30000 + 0x7ff, 53 .end = MCFFEC_BASE + MCFFEC_SIZE - 1,
54 .flags = IORESOURCE_MEM, 54 .flags = IORESOURCE_MEM,
55 }, 55 },
56 { 56 {
@@ -208,11 +208,11 @@ static void __init m520x_qspi_init(void)
208{ 208{
209 u16 par; 209 u16 par;
210 /* setup Port QS for QSPI with gpio CS control */ 210 /* setup Port QS for QSPI with gpio CS control */
211 writeb(0x3f, MCF_IPSBAR + MCF_GPIO_PAR_QSPI); 211 writeb(0x3f, MCF_GPIO_PAR_QSPI);
212 /* make U1CTS and U2RTS gpio for cs_control */ 212 /* make U1CTS and U2RTS gpio for cs_control */
213 par = readw(MCF_IPSBAR + MCF_GPIO_PAR_UART); 213 par = readw(MCF_GPIO_PAR_UART);
214 par &= 0x00ff; 214 par &= 0x00ff;
215 writew(par, MCF_IPSBAR + MCF_GPIO_PAR_UART); 215 writew(par, MCF_GPIO_PAR_UART);
216} 216}
217#endif /* defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) */ 217#endif /* defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) */
218 218
@@ -234,23 +234,23 @@ static void __init m520x_uart_init_line(int line, int irq)
234 234
235 switch (line) { 235 switch (line) {
236 case 0: 236 case 0:
237 par = readw(MCF_IPSBAR + MCF_GPIO_PAR_UART); 237 par = readw(MCF_GPIO_PAR_UART);
238 par |= MCF_GPIO_PAR_UART_PAR_UTXD0 | 238 par |= MCF_GPIO_PAR_UART_PAR_UTXD0 |
239 MCF_GPIO_PAR_UART_PAR_URXD0; 239 MCF_GPIO_PAR_UART_PAR_URXD0;
240 writew(par, MCF_IPSBAR + MCF_GPIO_PAR_UART); 240 writew(par, MCF_GPIO_PAR_UART);
241 break; 241 break;
242 case 1: 242 case 1:
243 par = readw(MCF_IPSBAR + MCF_GPIO_PAR_UART); 243 par = readw(MCF_GPIO_PAR_UART);
244 par |= MCF_GPIO_PAR_UART_PAR_UTXD1 | 244 par |= MCF_GPIO_PAR_UART_PAR_UTXD1 |
245 MCF_GPIO_PAR_UART_PAR_URXD1; 245 MCF_GPIO_PAR_UART_PAR_URXD1;
246 writew(par, MCF_IPSBAR + MCF_GPIO_PAR_UART); 246 writew(par, MCF_GPIO_PAR_UART);
247 break; 247 break;
248 case 2: 248 case 2:
249 par2 = readb(MCF_IPSBAR + MCF_GPIO_PAR_FECI2C); 249 par2 = readb(MCF_GPIO_PAR_FECI2C);
250 par2 &= ~0x0F; 250 par2 &= ~0x0F;
251 par2 |= MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 | 251 par2 |= MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 |
252 MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2; 252 MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2;
253 writeb(par2, MCF_IPSBAR + MCF_GPIO_PAR_FECI2C); 253 writeb(par2, MCF_GPIO_PAR_FECI2C);
254 break; 254 break;
255 } 255 }
256} 256}
@@ -271,11 +271,11 @@ static void __init m520x_fec_init(void)
271 u8 v; 271 u8 v;
272 272
273 /* Set multi-function pins to ethernet mode */ 273 /* Set multi-function pins to ethernet mode */
274 v = readb(MCF_IPSBAR + MCF_GPIO_PAR_FEC); 274 v = readb(MCF_GPIO_PAR_FEC);
275 writeb(v | 0xf0, MCF_IPSBAR + MCF_GPIO_PAR_FEC); 275 writeb(v | 0xf0, MCF_GPIO_PAR_FEC);
276 276
277 v = readb(MCF_IPSBAR + MCF_GPIO_PAR_FECI2C); 277 v = readb(MCF_GPIO_PAR_FECI2C);
278 writeb(v | 0x0f, MCF_IPSBAR + MCF_GPIO_PAR_FECI2C); 278 writeb(v | 0x0f, MCF_GPIO_PAR_FECI2C);
279} 279}
280 280
281/***************************************************************************/ 281/***************************************************************************/
diff --git a/arch/m68knommu/platform/coldfire/head.S b/arch/m68knommu/platform/coldfire/head.S
index d5977909ae5f..7967e8ab9fae 100644
--- a/arch/m68knommu/platform/coldfire/head.S
+++ b/arch/m68knommu/platform/coldfire/head.S
@@ -68,14 +68,14 @@
68#elif defined(CONFIG_M520x) 68#elif defined(CONFIG_M520x)
69.macro GET_MEM_SIZE 69.macro GET_MEM_SIZE
70 clrl %d0 70 clrl %d0
71 movel MCF_MBAR+MCFSIM_SDCS0, %d2 /* Get SDRAM chip select 0 config */ 71 movel MCFSIM_SDCS0, %d2 /* Get SDRAM chip select 0 config */
72 andl #0x1f, %d2 /* Get only the chip select size */ 72 andl #0x1f, %d2 /* Get only the chip select size */
73 beq 3f /* Check if it is enabled */ 73 beq 3f /* Check if it is enabled */
74 addql #1, %d2 /* Form exponent */ 74 addql #1, %d2 /* Form exponent */
75 moveql #1, %d0 75 moveql #1, %d0
76 lsll %d2, %d0 /* 2 ^ exponent */ 76 lsll %d2, %d0 /* 2 ^ exponent */
773: 773:
78 movel MCF_MBAR+MCFSIM_SDCS1, %d2 /* Get SDRAM chip select 1 config */ 78 movel MCFSIM_SDCS1, %d2 /* Get SDRAM chip select 1 config */
79 andl #0x1f, %d2 /* Get only the chip select size */ 79 andl #0x1f, %d2 /* Get only the chip select size */
80 beq 4f /* Check if it is enabled */ 80 beq 4f /* Check if it is enabled */
81 addql #1, %d2 /* Form exponent */ 81 addql #1, %d2 /* Form exponent */