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-rw-r--r--arch/m68knommu/platform/coldfire/timers.c68
1 files changed, 44 insertions, 24 deletions
diff --git a/arch/m68knommu/platform/coldfire/timers.c b/arch/m68knommu/platform/coldfire/timers.c
index 489dec85c859..a60213e877ef 100644
--- a/arch/m68knommu/platform/coldfire/timers.c
+++ b/arch/m68knommu/platform/coldfire/timers.c
@@ -3,7 +3,7 @@
3/* 3/*
4 * timers.c -- generic ColdFire hardware timer support. 4 * timers.c -- generic ColdFire hardware timer support.
5 * 5 *
6 * Copyright (C) 1999-2007, Greg Ungerer (gerg@snapgear.com) 6 * Copyright (C) 1999-2008, Greg Ungerer <gerg@snapgear.com>
7 */ 7 */
8 8
9/***************************************************************************/ 9/***************************************************************************/
@@ -13,6 +13,8 @@
13#include <linux/sched.h> 13#include <linux/sched.h>
14#include <linux/interrupt.h> 14#include <linux/interrupt.h>
15#include <linux/irq.h> 15#include <linux/irq.h>
16#include <linux/profile.h>
17#include <linux/clocksource.h>
16#include <asm/io.h> 18#include <asm/io.h>
17#include <asm/traps.h> 19#include <asm/traps.h>
18#include <asm/machdep.h> 20#include <asm/machdep.h>
@@ -25,6 +27,7 @@
25/* 27/*
26 * By default use timer1 as the system clock timer. 28 * By default use timer1 as the system clock timer.
27 */ 29 */
30#define FREQ (MCF_BUSCLK / 16)
28#define TA(a) (MCF_MBAR + MCFTIMER_BASE1 + (a)) 31#define TA(a) (MCF_MBAR + MCFTIMER_BASE1 + (a))
29 32
30/* 33/*
@@ -41,7 +44,7 @@ unsigned int mcf_timerlevel = 5;
41 * Unfortunately it is a little different on each ColdFire. 44 * Unfortunately it is a little different on each ColdFire.
42 */ 45 */
43extern void mcf_settimericr(int timer, int level); 46extern void mcf_settimericr(int timer, int level);
44extern int mcf_timerirqpending(int timer); 47void coldfire_profile_init(void);
45 48
46#if defined(CONFIG_M532x) 49#if defined(CONFIG_M532x)
47#define __raw_readtrr __raw_readl 50#define __raw_readtrr __raw_readl
@@ -51,38 +54,70 @@ extern int mcf_timerirqpending(int timer);
51#define __raw_writetrr __raw_writew 54#define __raw_writetrr __raw_writew
52#endif 55#endif
53 56
57static u32 mcftmr_cycles_per_jiffy;
58static u32 mcftmr_cnt;
59
54/***************************************************************************/ 60/***************************************************************************/
55 61
56static irqreturn_t hw_tick(int irq, void *dummy) 62static irqreturn_t mcftmr_tick(int irq, void *dummy)
57{ 63{
58 /* Reset the ColdFire timer */ 64 /* Reset the ColdFire timer */
59 __raw_writeb(MCFTIMER_TER_CAP | MCFTIMER_TER_REF, TA(MCFTIMER_TER)); 65 __raw_writeb(MCFTIMER_TER_CAP | MCFTIMER_TER_REF, TA(MCFTIMER_TER));
60 66
67 mcftmr_cnt += mcftmr_cycles_per_jiffy;
61 return arch_timer_interrupt(irq, dummy); 68 return arch_timer_interrupt(irq, dummy);
62} 69}
63 70
64/***************************************************************************/ 71/***************************************************************************/
65 72
66static struct irqaction coldfire_timer_irq = { 73static struct irqaction mcftmr_timer_irq = {
67 .name = "timer", 74 .name = "timer",
68 .flags = IRQF_DISABLED | IRQF_TIMER, 75 .flags = IRQF_DISABLED | IRQF_TIMER,
69 .handler = hw_tick, 76 .handler = mcftmr_tick,
70}; 77};
71 78
72/***************************************************************************/ 79/***************************************************************************/
73 80
74static int ticks_per_intr; 81static cycle_t mcftmr_read_clk(void)
82{
83 unsigned long flags;
84 u32 cycles;
85 u16 tcn;
86
87 local_irq_save(flags);
88 tcn = __raw_readw(TA(MCFTIMER_TCN));
89 cycles = mcftmr_cnt;
90 local_irq_restore(flags);
91
92 return cycles + tcn;
93}
94
95/***************************************************************************/
96
97static struct clocksource mcftmr_clk = {
98 .name = "tmr",
99 .rating = 250,
100 .read = mcftmr_read_clk,
101 .shift = 20,
102 .mask = CLOCKSOURCE_MASK(32),
103 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
104};
105
106/***************************************************************************/
75 107
76void hw_timer_init(void) 108void hw_timer_init(void)
77{ 109{
78 setup_irq(mcf_timervector, &coldfire_timer_irq); 110 setup_irq(mcf_timervector, &mcftmr_timer_irq);
79 111
80 __raw_writew(MCFTIMER_TMR_DISABLE, TA(MCFTIMER_TMR)); 112 __raw_writew(MCFTIMER_TMR_DISABLE, TA(MCFTIMER_TMR));
81 ticks_per_intr = (MCF_BUSCLK / 16) / HZ; 113 mcftmr_cycles_per_jiffy = FREQ / HZ;
82 __raw_writetrr(ticks_per_intr - 1, TA(MCFTIMER_TRR)); 114 __raw_writetrr(mcftmr_cycles_per_jiffy, TA(MCFTIMER_TRR));
83 __raw_writew(MCFTIMER_TMR_ENORI | MCFTIMER_TMR_CLK16 | 115 __raw_writew(MCFTIMER_TMR_ENORI | MCFTIMER_TMR_CLK16 |
84 MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENABLE, TA(MCFTIMER_TMR)); 116 MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENABLE, TA(MCFTIMER_TMR));
85 117
118 mcftmr_clk.mult = clocksource_hz2mult(FREQ, mcftmr_clk.shift);
119 clocksource_register(&mcftmr_clk);
120
86 mcf_settimericr(1, mcf_timerlevel); 121 mcf_settimericr(1, mcf_timerlevel);
87 122
88#ifdef CONFIG_HIGHPROFILE 123#ifdef CONFIG_HIGHPROFILE
@@ -91,21 +126,6 @@ void hw_timer_init(void)
91} 126}
92 127
93/***************************************************************************/ 128/***************************************************************************/
94
95unsigned long hw_timer_offset(void)
96{
97 unsigned long tcn, offset;
98
99 tcn = __raw_readw(TA(MCFTIMER_TCN));
100 offset = ((tcn + 1) * (1000000 / HZ)) / ticks_per_intr;
101
102 /* Check if we just wrapped the counters and maybe missed a tick */
103 if ((offset < (1000000 / HZ / 2)) && mcf_timerirqpending(1))
104 offset += 1000000 / HZ;
105 return offset;
106}
107
108/***************************************************************************/
109#ifdef CONFIG_HIGHPROFILE 129#ifdef CONFIG_HIGHPROFILE
110/***************************************************************************/ 130/***************************************************************************/
111 131