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-rw-r--r--arch/m68knommu/platform/68360/head-ram.S408
1 files changed, 408 insertions, 0 deletions
diff --git a/arch/m68knommu/platform/68360/head-ram.S b/arch/m68knommu/platform/68360/head-ram.S
new file mode 100644
index 000000000000..a5c639a51eef
--- /dev/null
+++ b/arch/m68knommu/platform/68360/head-ram.S
@@ -0,0 +1,408 @@
1/* arch/m68knommu/platform/68360/head-ram.S
2 *
3 * Startup code for Motorola 68360
4 *
5 * Copyright 2001 (C) SED Systems, a Division of Calian Ltd.
6 * Based on: arch/m68knommu/platform/68328/pilot/crt0_rom.S
7 * Based on: arch/m68knommu/platform/68360/uCquicc/crt0_rom.S, 2.0.38.1.pre7
8 * uClinux Kernel
9 * Copyright (C) Michael Leslie <mleslie@lineo.com>
10 * Based on: arch/m68knommu/platform/68EZ328/ucsimm/crt0_rom.S
11 * Copyright (C) 1998 D. Jeff Dionne <jeff@uclinux.org>,
12 *
13 */
14#define ASSEMBLY
15#include <linux/config.h>
16
17.global _stext
18.global _start
19
20.global _rambase
21.global __ramvec
22.global _ramvec
23.global _ramstart
24.global _ramend
25
26.global _quicc_base
27.global _periph_base
28
29#define REGB 0x1000
30#define PEPAR (_dprbase + REGB + 0x0016)
31#define GMR (_dprbase + REGB + 0x0040)
32#define OR0 (_dprbase + REGB + 0x0054)
33#define BR0 (_dprbase + REGB + 0x0050)
34#define OR1 (_dprbase + REGB + 0x0064)
35#define BR1 (_dprbase + REGB + 0x0060)
36#define OR4 (_dprbase + REGB + 0x0094)
37#define BR4 (_dprbase + REGB + 0x0090)
38#define OR6 (_dprbase + REGB + 0x00b4)
39#define BR6 (_dprbase + REGB + 0x00b0)
40#define OR7 (_dprbase + REGB + 0x00c4)
41#define BR7 (_dprbase + REGB + 0x00c0)
42
43#define MCR (_dprbase + REGB + 0x0000)
44#define AVR (_dprbase + REGB + 0x0008)
45
46#define SYPCR (_dprbase + REGB + 0x0022)
47
48#define PLLCR (_dprbase + REGB + 0x0010)
49#define CLKOCR (_dprbase + REGB + 0x000C)
50#define CDVCR (_dprbase + REGB + 0x0014)
51
52#define BKAR (_dprbase + REGB + 0x0030)
53#define BKCR (_dprbase + REGB + 0x0034)
54#define SWIV (_dprbase + REGB + 0x0023)
55#define PICR (_dprbase + REGB + 0x0026)
56#define PITR (_dprbase + REGB + 0x002A)
57
58/* Define for all memory configuration */
59#define MCU_SIM_GMR 0x00000000
60#define SIM_OR_MASK 0x0fffffff
61
62/* Defines for chip select zero - the flash */
63#define SIM_OR0_MASK 0x20000002
64#define SIM_BR0_MASK 0x00000001
65
66
67/* Defines for chip select one - the RAM */
68#define SIM_OR1_MASK 0x10000000
69#define SIM_BR1_MASK 0x00000001
70
71#define MCU_SIM_MBAR_ADRS 0x0003ff00
72#define MCU_SIM_MBAR_BA_MASK 0xfffff000
73#define MCU_SIM_MBAR_AS_MASK 0x00000001
74
75#define MCU_SIM_PEPAR 0x00B4
76
77#define MCU_DISABLE_INTRPTS 0x2700
78#define MCU_SIM_AVR 0x00
79
80#define MCU_SIM_MCR 0x00005cff
81
82#define MCU_SIM_CLKOCR 0x00
83#define MCU_SIM_PLLCR 0x8000
84#define MCU_SIM_CDVCR 0x0000
85
86#define MCU_SIM_SYPCR 0x0000
87#define MCU_SIM_SWIV 0x00
88#define MCU_SIM_PICR 0x0000
89#define MCU_SIM_PITR 0x0000
90
91
92#include <asm/m68360_regs.h>
93
94
95/*
96 * By the time this RAM specific code begins to execute, DPRAM
97 * and DRAM should already be mapped and accessible.
98 */
99
100 .text
101_start:
102_stext:
103 nop
104 ori.w #MCU_DISABLE_INTRPTS, %sr /* disable interrupts: */
105 /* We should not need to setup the boot stack the reset should do it. */
106 movea.l #__ramend, %sp /*set up stack at the end of DRAM:*/
107
108set_mbar_register:
109 moveq.l #0x07, %d1 /* Setup MBAR */
110 movec %d1, %dfc
111
112 lea.l MCU_SIM_MBAR_ADRS, %a0
113 move.l #_dprbase, %d0
114 andi.l #MCU_SIM_MBAR_BA_MASK, %d0
115 ori.l #MCU_SIM_MBAR_AS_MASK, %d0
116 moves.l %d0, %a0@
117
118 moveq.l #0x05, %d1
119 movec.l %d1, %dfc
120
121 /* Now we can begin to access registers in DPRAM */
122
123set_sim_mcr:
124 /* Set Module Configuration Register */
125 move.l #MCU_SIM_MCR, MCR
126
127 /* to do: Determine cause of reset */
128
129 /*
130 * configure system clock MC68360 p. 6-40
131 * (value +1)*osc/128 = system clock
132 */
133set_sim_clock:
134 move.w #MCU_SIM_PLLCR, PLLCR
135 move.b #MCU_SIM_CLKOCR, CLKOCR
136 move.w #MCU_SIM_CDVCR, CDVCR
137
138 /* Wait for the PLL to settle */
139 move.w #16384, %d0
140pll_settle_wait:
141 subi.w #1, %d0
142 bne pll_settle_wait
143
144 /* Setup the system protection register, and watchdog timer register */
145 move.b #MCU_SIM_SWIV, SWIV
146 move.w #MCU_SIM_PICR, PICR
147 move.w #MCU_SIM_PITR, PITR
148 move.w #MCU_SIM_SYPCR, SYPCR
149
150 /* Clear DPRAM - system + parameter */
151 movea.l #_dprbase, %a0
152 movea.l #_dprbase+0x2000, %a1
153
154 /* Copy 0 to %a0 until %a0 == %a1 */
155clear_dpram:
156 movel #0, %a0@+
157 cmpal %a0, %a1
158 bhi clear_dpram
159
160configure_memory_controller:
161 /* Set up Global Memory Register (GMR) */
162 move.l #MCU_SIM_GMR, %d0
163 move.l %d0, GMR
164
165configure_chip_select_0:
166 move.l #__ramend, %d0
167 subi.l #__ramstart, %d0
168 subq.l #0x01, %d0
169 eori.l #SIM_OR_MASK, %d0
170 ori.l #SIM_OR0_MASK, %d0
171 move.l %d0, OR0
172
173 move.l #__ramstart, %d0
174 ori.l #SIM_BR0_MASK, %d0
175 move.l %d0, BR0
176
177configure_chip_select_1:
178 move.l #__rom_end, %d0
179 subi.l #__rom_start, %d0
180 subq.l #0x01, %d0
181 eori.l #SIM_OR_MASK, %d0
182 ori.l #SIM_OR1_MASK, %d0
183 move.l %d0, OR1
184
185 move.l #__rom_start, %d0
186 ori.l #SIM_BR1_MASK, %d0
187 move.l %d0, BR1
188
189 move.w #MCU_SIM_PEPAR, PEPAR
190
191 /* point to vector table: */
192 move.l #_romvec, %a0
193 move.l #_ramvec, %a1
194copy_vectors:
195 move.l %a0@, %d0
196 move.l %d0, %a1@
197 move.l %a0@, %a1@
198 addq.l #0x04, %a0
199 addq.l #0x04, %a1
200 cmp.l #_start, %a0
201 blt copy_vectors
202
203 move.l #_ramvec, %a1
204 movec %a1, %vbr
205
206
207 /* Copy data segment from ROM to RAM */
208 moveal #_stext, %a0
209 moveal #_sdata, %a1
210 moveal #_edata, %a2
211
212 /* Copy %a0 to %a1 until %a1 == %a2 */
213LD1:
214 move.l %a0@, %d0
215 addq.l #0x04, %a0
216 move.l %d0, %a1@
217 addq.l #0x04, %a1
218 cmp.l #_edata, %a1
219 blt LD1
220
221 moveal #_sbss, %a0
222 moveal #_ebss, %a1
223
224 /* Copy 0 to %a0 until %a0 == %a1 */
225L1:
226 movel #0, %a0@+
227 cmpal %a0, %a1
228 bhi L1
229
230load_quicc:
231 move.l #_dprbase, _quicc_base
232
233store_ram_size:
234 /* Set ram size information */
235 move.l #_sdata, _rambase
236 move.l #_ebss, _ramstart
237 move.l #__ramend, %d0
238 sub.l #0x1000, %d0 /* Reserve 4K for stack space.*/
239 move.l %d0, _ramend /* Different from __ramend.*/
240
241store_flash_size:
242 /* Set rom size information */
243 move.l #__rom_end, %d0
244 sub.l #__rom_start, %d0
245 move.l %d0, rom_length
246
247 pea 0
248 pea env
249 pea %sp@(4)
250 pea 0
251
252 lea init_thread_union, %a2
253 lea 0x2000(%a2), %sp
254
255lp:
256 jsr start_kernel
257
258_exit:
259 jmp _exit
260
261
262 .data
263 .align 4
264env:
265 .long 0
266_quicc_base:
267 .long 0
268_periph_base:
269 .long 0
270_ramvec:
271 .long 0
272_rambase:
273 .long 0
274_ramstart:
275 .long 0
276_ramend:
277 .long 0
278_dprbase:
279 .long 0xffffe000
280
281 .text
282
283 /*
284 * These are the exception vectors at boot up, they are copied into RAM
285 * and then overwritten as needed.
286 */
287
288.section ".data.initvect","awx"
289 .long __ramend /* Reset: Initial Stack Pointer - 0. */
290 .long _start /* Reset: Initial Program Counter - 1. */
291 .long buserr /* Bus Error - 2. */
292 .long trap /* Address Error - 3. */
293 .long trap /* Illegal Instruction - 4. */
294 .long trap /* Divide by zero - 5. */
295 .long trap /* CHK, CHK2 Instructions - 6. */
296 .long trap /* TRAPcc, TRAPV Instructions - 7. */
297 .long trap /* Privilege Violation - 8. */
298 .long trap /* Trace - 9. */
299 .long trap /* Line 1010 Emulator - 10. */
300 .long trap /* Line 1111 Emualtor - 11. */
301 .long trap /* Harware Breakpoint - 12. */
302 .long trap /* (Reserved for Coprocessor Protocol Violation)- 13. */
303 .long trap /* Format Error - 14. */
304 .long trap /* Uninitialized Interrupt - 15. */
305 .long trap /* (Unassigned, Reserver) - 16. */
306 .long trap /* (Unassigned, Reserver) - 17. */
307 .long trap /* (Unassigned, Reserver) - 18. */
308 .long trap /* (Unassigned, Reserver) - 19. */
309 .long trap /* (Unassigned, Reserver) - 20. */
310 .long trap /* (Unassigned, Reserver) - 21. */
311 .long trap /* (Unassigned, Reserver) - 22. */
312 .long trap /* (Unassigned, Reserver) - 23. */
313 .long trap /* Spurious Interrupt - 24. */
314 .long trap /* Level 1 Interrupt Autovector - 25. */
315 .long trap /* Level 2 Interrupt Autovector - 26. */
316 .long trap /* Level 3 Interrupt Autovector - 27. */
317 .long trap /* Level 4 Interrupt Autovector - 28. */
318 .long trap /* Level 5 Interrupt Autovector - 29. */
319 .long trap /* Level 6 Interrupt Autovector - 30. */
320 .long trap /* Level 7 Interrupt Autovector - 31. */
321 .long system_call /* Trap Instruction Vectors 0 - 32. */
322 .long trap /* Trap Instruction Vectors 1 - 33. */
323 .long trap /* Trap Instruction Vectors 2 - 34. */
324 .long trap /* Trap Instruction Vectors 3 - 35. */
325 .long trap /* Trap Instruction Vectors 4 - 36. */
326 .long trap /* Trap Instruction Vectors 5 - 37. */
327 .long trap /* Trap Instruction Vectors 6 - 38. */
328 .long trap /* Trap Instruction Vectors 7 - 39. */
329 .long trap /* Trap Instruction Vectors 8 - 40. */
330 .long trap /* Trap Instruction Vectors 9 - 41. */
331 .long trap /* Trap Instruction Vectors 10 - 42. */
332 .long trap /* Trap Instruction Vectors 11 - 43. */
333 .long trap /* Trap Instruction Vectors 12 - 44. */
334 .long trap /* Trap Instruction Vectors 13 - 45. */
335 .long trap /* Trap Instruction Vectors 14 - 46. */
336 .long trap /* Trap Instruction Vectors 15 - 47. */
337 .long 0 /* (Reserved for Coprocessor) - 48. */
338 .long 0 /* (Reserved for Coprocessor) - 49. */
339 .long 0 /* (Reserved for Coprocessor) - 50. */
340 .long 0 /* (Reserved for Coprocessor) - 51. */
341 .long 0 /* (Reserved for Coprocessor) - 52. */
342 .long 0 /* (Reserved for Coprocessor) - 53. */
343 .long 0 /* (Reserved for Coprocessor) - 54. */
344 .long 0 /* (Reserved for Coprocessor) - 55. */
345 .long 0 /* (Reserved for Coprocessor) - 56. */
346 .long 0 /* (Reserved for Coprocessor) - 57. */
347 .long 0 /* (Reserved for Coprocessor) - 58. */
348 .long 0 /* (Unassigned, Reserved) - 59. */
349 .long 0 /* (Unassigned, Reserved) - 60. */
350 .long 0 /* (Unassigned, Reserved) - 61. */
351 .long 0 /* (Unassigned, Reserved) - 62. */
352 .long 0 /* (Unassigned, Reserved) - 63. */
353 /* The assignment of these vectors to the CPM is */
354 /* dependent on the configuration of the CPM vba */
355 /* fields. */
356 .long 0 /* (User-Defined Vectors 1) CPM Error - 64. */
357 .long 0 /* (User-Defined Vectors 2) CPM Parallel IO PC11- 65. */
358 .long 0 /* (User-Defined Vectors 3) CPM Parallel IO PC10- 66. */
359 .long 0 /* (User-Defined Vectors 4) CPM SMC2 / PIP - 67. */
360 .long 0 /* (User-Defined Vectors 5) CPM SMC1 - 68. */
361 .long 0 /* (User-Defined Vectors 6) CPM SPI - 69. */
362 .long 0 /* (User-Defined Vectors 7) CPM Parallel IO PC9 - 70. */
363 .long 0 /* (User-Defined Vectors 8) CPM Timer 4 - 71. */
364 .long 0 /* (User-Defined Vectors 9) CPM Reserved - 72. */
365 .long 0 /* (User-Defined Vectors 10) CPM Parallel IO PC8- 73. */
366 .long 0 /* (User-Defined Vectors 11) CPM Parallel IO PC7- 74. */
367 .long 0 /* (User-Defined Vectors 12) CPM Parallel IO PC6- 75. */
368 .long 0 /* (User-Defined Vectors 13) CPM Timer 3 - 76. */
369 .long 0 /* (User-Defined Vectors 14) CPM Reserved - 77. */
370 .long 0 /* (User-Defined Vectors 15) CPM Parallel IO PC5- 78. */
371 .long 0 /* (User-Defined Vectors 16) CPM Parallel IO PC4- 79. */
372 .long 0 /* (User-Defined Vectors 17) CPM Reserved - 80. */
373 .long 0 /* (User-Defined Vectors 18) CPM RISC Timer Tbl - 81. */
374 .long 0 /* (User-Defined Vectors 19) CPM Timer 2 - 82. */
375 .long 0 /* (User-Defined Vectors 21) CPM Reserved - 83. */
376 .long 0 /* (User-Defined Vectors 22) CPM IDMA2 - 84. */
377 .long 0 /* (User-Defined Vectors 23) CPM IDMA1 - 85. */
378 .long 0 /* (User-Defined Vectors 24) CPM SDMA Bus Err - 86. */
379 .long 0 /* (User-Defined Vectors 25) CPM Parallel IO PC3- 87. */
380 .long 0 /* (User-Defined Vectors 26) CPM Parallel IO PC2- 88. */
381 .long 0 /* (User-Defined Vectors 27) CPM Timer 1 - 89. */
382 .long 0 /* (User-Defined Vectors 28) CPM Parallel IO PC1- 90. */
383 .long 0 /* (User-Defined Vectors 29) CPM SCC 4 - 91. */
384 .long 0 /* (User-Defined Vectors 30) CPM SCC 3 - 92. */
385 .long 0 /* (User-Defined Vectors 31) CPM SCC 2 - 93. */
386 .long 0 /* (User-Defined Vectors 32) CPM SCC 1 - 94. */
387 .long 0 /* (User-Defined Vectors 33) CPM Parallel IO PC0- 95. */
388 /* I don't think anything uses the vectors after here. */
389 .long 0 /* (User-Defined Vectors 34) - 96. */
390 .long 0,0,0,0,0 /* (User-Defined Vectors 35 - 39). */
391 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 40 - 49). */
392 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 50 - 59). */
393 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 60 - 69). */
394 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 70 - 79). */
395 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 80 - 89). */
396 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 90 - 99). */
397 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 100 - 109). */
398 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 110 - 119). */
399 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 120 - 129). */
400 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 130 - 139). */
401 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 140 - 149). */
402 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 150 - 159). */
403 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 160 - 169). */
404 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 170 - 179). */
405 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 180 - 189). */
406 .long 0,0,0 /* (User-Defined Vectors 190 - 192). */
407.text
408ignore: rte
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