6 files changed, 288 insertions, 1 deletions

diff --git a/arch/m68knommu/Kconfig b/arch/m68knommu/Kconfig
index fd28178b5877..9287150e5fb0 100644
--- a/arch/m68knommu/Kconfig
+++ b/arch/m68knommu/Kconfig
@@ -175,6 +175,11 @@ config M5407
         help
           Motorola ColdFire 5407 processor support.
 
+config M548x
+        bool "MCF548x"
+        help
+          Freescale ColdFire 5480/5481/5482/5483/5484/5485 processor support.
+
 endchoice
 
 config M527x
@@ -185,7 +190,7 @@ config M527x
 
 config COLDFIRE
         bool
-        depends on (M5206 || M5206e || M520x || M523x || M5249 || M527x || M5272 || M528x || M5307 || M532x || M5407)
+        depends on (M5206 || M5206e || M520x || M523x || M5249 || M527x || M5272 || M528x || M5307 || M532x || M5407 || M548x)
         select GENERIC_GPIO
         select ARCH_REQUIRE_GPIOLIB
         default y
diff --git a/arch/m68knommu/Makefile b/arch/m68knommu/Makefile
index 14042574ac21..026ef16fa68e 100644
--- a/arch/m68knommu/Makefile
+++ b/arch/m68knommu/Makefile
@@ -25,6 +25,7 @@ platform-$(CONFIG_M528x)	:= 528x
 platform-$(CONFIG_M5307)        := 5307
 platform-$(CONFIG_M532x)        := 532x
 platform-$(CONFIG_M5407)        := 5407
+platform-$(CONFIG_M548x)        := 548x
 PLATFORM := $(platform-y)
 
 board-$(CONFIG_PILOT)           := pilot
@@ -73,6 +74,7 @@ cpuclass-$(CONFIG_M528x)	:= coldfire
 cpuclass-$(CONFIG_M5307)        := coldfire
 cpuclass-$(CONFIG_M532x)        := coldfire
 cpuclass-$(CONFIG_M5407)        := coldfire
+cpuclass-$(CONFIG_M548x)        := coldfire
 cpuclass-$(CONFIG_M68328)       := 68328
 cpuclass-$(CONFIG_M68EZ328)     := 68328
 cpuclass-$(CONFIG_M68VZ328)     := 68328
@@ -100,6 +102,7 @@ cflags-$(CONFIG_M528x)		:= $(call cc-option,-m528x,-m5307)
 cflags-$(CONFIG_M5307)          := $(call cc-option,-m5307,-m5200)
 cflags-$(CONFIG_M532x)          := $(call cc-option,-mcpu=532x,-m5307)
 cflags-$(CONFIG_M5407)          := $(call cc-option,-m5407,-m5200)
+cflags-$(CONFIG_M548x)          := $(call cc-option,-m5407,-m5200)
 cflags-$(CONFIG_M68328)         := -m68000
 cflags-$(CONFIG_M68EZ328)       := -m68000
 cflags-$(CONFIG_M68VZ328)       := -m68000
diff --git a/arch/m68knommu/platform/548x/Makefile b/arch/m68knommu/platform/548x/Makefile
new file mode 100644
index 000000000000..e6035e7a2d3f
--- /dev/null
+++ b/arch/m68knommu/platform/548x/Makefile
@@ -0,0 +1,18 @@
+#
+# Makefile for the m68knommu linux kernel.
+#
+
+#
+# If you want to play with the HW breakpoints then you will
+# need to add define this,  which will give you a stack backtrace
+# on the console port whenever a DBG interrupt occurs. You have to
+# set up you HW breakpoints to trigger a DBG interrupt:
+#
+# EXTRA_CFLAGS += -DTRAP_DBG_INTERRUPT
+# EXTRA_AFLAGS += -DTRAP_DBG_INTERRUPT
+#
+
+asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
+
+obj-y := config.o
+
diff --git a/arch/m68knommu/platform/548x/config.c b/arch/m68knommu/platform/548x/config.c
new file mode 100644
index 000000000000..9888846bd1cf
--- /dev/null
+++ b/arch/m68knommu/platform/548x/config.c
@@ -0,0 +1,115 @@
+/***************************************************************************/
+
+/*
+ *      linux/arch/m68knommu/platform/548x/config.c
+ *
+ *      Copyright (C) 2010, Philippe De Muyter <phdm@macqel.be>
+ */
+
+/***************************************************************************/
+
+#include <linux/kernel.h>
+#include <linux/param.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <asm/machdep.h>
+#include <asm/coldfire.h>
+#include <asm/m548xsim.h>
+#include <asm/mcfuart.h>
+#include <asm/m548xgpt.h>
+
+/***************************************************************************/
+
+static struct mcf_platform_uart m548x_uart_platform[] = {
+        {
+                .mapbase        = MCF_MBAR + MCFUART_BASE1,
+                .irq            = 64 + 35,
+        },
+        {
+                .mapbase        = MCF_MBAR + MCFUART_BASE2,
+                .irq            = 64 + 34,
+        },
+        {
+                .mapbase        = MCF_MBAR + MCFUART_BASE3,
+                .irq            = 64 + 33,
+        },
+        {
+                .mapbase        = MCF_MBAR + MCFUART_BASE4,
+                .irq            = 64 + 32,
+        },
+};
+
+static struct platform_device m548x_uart = {
+        .name                   = "mcfuart",
+        .id                     = 0,
+        .dev.platform_data      = m548x_uart_platform,
+};
+
+static struct platform_device *m548x_devices[] __initdata = {
+        &m548x_uart,
+};
+
+
+/***************************************************************************/
+
+static void __init m548x_uart_init_line(int line, int irq)
+{
+        int rts_cts;
+
+        /* enable io pins */
+        switch (line) {
+        case 0:
+                rts_cts = 0; break;
+        case 1:
+                rts_cts = MCF_PAR_PSC_RTS_RTS; break;
+        case 2:
+                rts_cts = MCF_PAR_PSC_RTS_RTS | MCF_PAR_PSC_CTS_CTS; break;
+        case 3:
+                rts_cts = 0; break;
+        }
+        __raw_writeb(MCF_PAR_PSC_TXD | rts_cts | MCF_PAR_PSC_RXD,
+                                                MCF_MBAR + MCF_PAR_PSC(line));
+}
+
+static void __init m548x_uarts_init(void)
+{
+        const int nrlines = ARRAY_SIZE(m548x_uart_platform);
+        int line;
+
+        for (line = 0; (line < nrlines); line++)
+                m548x_uart_init_line(line, m548x_uart_platform[line].irq);
+}
+
+/***************************************************************************/
+
+static void mcf548x_reset(void)
+{
+        /* disable interrupts and enable the watchdog */
+        asm("movew #0x2700, %sr\n");
+        __raw_writel(0, MCF_MBAR + MCF_GPT_GMS0);
+        __raw_writel(MCF_GPT_GCIR_CNT(1), MCF_MBAR + MCF_GPT_GCIR0);
+        __raw_writel(MCF_GPT_GMS_WDEN | MCF_GPT_GMS_CE | MCF_GPT_GMS_TMS(4),
+                                                MCF_MBAR + MCF_GPT_GMS0);
+}
+
+/***************************************************************************/
+
+void __init config_BSP(char *commandp, int size)
+{
+        mach_reset = mcf548x_reset;
+        m548x_uarts_init();
+}
+
+/***************************************************************************/
+
+static int __init init_BSP(void)
+{
+
+        platform_add_devices(m548x_devices, ARRAY_SIZE(m548x_devices));
+        return 0;
+}
+
+arch_initcall(init_BSP);
+
+/***************************************************************************/
diff --git a/arch/m68knommu/platform/coldfire/Makefile b/arch/m68knommu/platform/coldfire/Makefile
index f72a0e5d9996..df62171d986c 100644
--- a/arch/m68knommu/platform/coldfire/Makefile
+++ b/arch/m68knommu/platform/coldfire/Makefile
@@ -26,6 +26,7 @@ obj-$(CONFIG_M528x)	+= pit.o intc-2.o
 obj-$(CONFIG_M5307)     += timers.o intc.o
 obj-$(CONFIG_M532x)     += timers.o intc-simr.o
 obj-$(CONFIG_M5407)     += timers.o intc.o
+obj-$(CONFIG_M548x)     += sltimers.o intc-2.o
 
 obj-y                   += pinmux.o gpio.o
 extra-y := head.o
diff --git a/arch/m68knommu/platform/coldfire/sltimers.c b/arch/m68knommu/platform/coldfire/sltimers.c
new file mode 100644
index 000000000000..0a1b937c3e18
--- /dev/null
+++ b/arch/m68knommu/platform/coldfire/sltimers.c
@@ -0,0 +1,145 @@
+/***************************************************************************/
+
+/*
+ *      sltimers.c -- generic ColdFire slice timer support.
+ *
+ *      Copyright (C) 2009-2010, Philippe De Muyter <phdm@macqel.be>
+ *      based on
+ *      timers.c -- generic ColdFire hardware timer support.
+ *      Copyright (C) 1999-2008, Greg Ungerer <gerg@snapgear.com>
+ */
+
+/***************************************************************************/
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/profile.h>
+#include <linux/clocksource.h>
+#include <asm/io.h>
+#include <asm/traps.h>
+#include <asm/machdep.h>
+#include <asm/coldfire.h>
+#include <asm/mcfslt.h>
+#include <asm/mcfsim.h>
+
+/***************************************************************************/
+
+#ifdef CONFIG_HIGHPROFILE
+
+/*
+ *      By default use Slice Timer 1 as the profiler clock timer.
+ */
+#define PA(a)   (MCF_MBAR + MCFSLT_TIMER1 + (a))
+
+/*
+ *      Choose a reasonably fast profile timer. Make it an odd value to
+ *      try and get good coverage of kernel operations.
+ */
+#define PROFILEHZ       1013
+
+irqreturn_t mcfslt_profile_tick(int irq, void *dummy)
+{
+        /* Reset Slice Timer 1 */
+        __raw_writel(MCFSLT_SSR_BE | MCFSLT_SSR_TE, PA(MCFSLT_SSR));
+        if (current->pid)
+                profile_tick(CPU_PROFILING);
+        return IRQ_HANDLED;
+}
+
+static struct irqaction mcfslt_profile_irq = {
+        .name    = "profile timer",
+        .flags   = IRQF_DISABLED | IRQF_TIMER,
+        .handler = mcfslt_profile_tick,
+};
+
+void mcfslt_profile_init(void)
+{
+        printk(KERN_INFO "PROFILE: lodging TIMER 1 @ %dHz as profile timer\n",
+               PROFILEHZ);
+
+        setup_irq(MCF_IRQ_PROFILER, &mcfslt_profile_irq);
+
+        /* Set up TIMER 2 as high speed profile clock */
+        __raw_writel(MCF_BUSCLK / PROFILEHZ - 1, PA(MCFSLT_STCNT));
+        __raw_writel(MCFSLT_SCR_RUN | MCFSLT_SCR_IEN | MCFSLT_SCR_TEN,
+                                                                PA(MCFSLT_SCR));
+
+}
+
+#endif  /* CONFIG_HIGHPROFILE */
+
+/***************************************************************************/
+
+/*
+ *      By default use Slice Timer 0 as the system clock timer.
+ */
+#define TA(a)   (MCF_MBAR + MCFSLT_TIMER0 + (a))
+
+static u32 mcfslt_cycles_per_jiffy;
+static u32 mcfslt_cnt;
+
+static irqreturn_t mcfslt_tick(int irq, void *dummy)
+{
+        /* Reset Slice Timer 0 */
+        __raw_writel(MCFSLT_SSR_BE | MCFSLT_SSR_TE, TA(MCFSLT_SSR));
+        mcfslt_cnt += mcfslt_cycles_per_jiffy;
+        return arch_timer_interrupt(irq, dummy);
+}
+
+static struct irqaction mcfslt_timer_irq = {
+        .name    = "timer",
+        .flags   = IRQF_DISABLED | IRQF_TIMER,
+        .handler = mcfslt_tick,
+};
+
+static cycle_t mcfslt_read_clk(struct clocksource *cs)
+{
+        unsigned long flags;
+        u32 cycles;
+        u16 scnt;
+
+        local_irq_save(flags);
+        scnt = __raw_readl(TA(MCFSLT_SCNT));
+        cycles = mcfslt_cnt;
+        local_irq_restore(flags);
+
+        /* substract because slice timers count down */
+        return cycles - scnt;
+}
+
+static struct clocksource mcfslt_clk = {
+        .name   = "slt",
+        .rating = 250,
+        .read   = mcfslt_read_clk,
+        .shift  = 20,
+        .mask   = CLOCKSOURCE_MASK(32),
+        .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+void hw_timer_init(void)
+{
+        mcfslt_cycles_per_jiffy = MCF_BUSCLK / HZ;
+        /*
+         *      The coldfire slice timer (SLT) runs from STCNT to 0 included,
+         *      then STCNT again and so on.  It counts thus actually
+         *      STCNT + 1 steps for 1 tick, not STCNT.  So if you want
+         *      n cycles, initialize STCNT with n - 1.
+         */
+        __raw_writel(mcfslt_cycles_per_jiffy - 1, TA(MCFSLT_STCNT));
+        __raw_writel(MCFSLT_SCR_RUN | MCFSLT_SCR_IEN | MCFSLT_SCR_TEN,
+                                                                TA(MCFSLT_SCR));
+        /* initialize mcfslt_cnt knowing that slice timers count down */
+        mcfslt_cnt = mcfslt_cycles_per_jiffy;
+
+        setup_irq(MCF_IRQ_TIMER, &mcfslt_timer_irq);
+
+        mcfslt_clk.mult = clocksource_hz2mult(MCF_BUSCLK, mcfslt_clk.shift);
+        clocksource_register(&mcfslt_clk);
+
+#ifdef CONFIG_HIGHPROFILE
+        mcfslt_profile_init();
+#endif
+}