6 files changed, 83 insertions, 34 deletions

diff --git a/arch/m68knommu/platform/5206/config.c b/arch/m68knommu/platform/5206/config.c
index 481617a23d09..0dce2383320d 100644
--- a/arch/m68knommu/platform/5206/config.c
+++ b/arch/m68knommu/platform/5206/config.c
@@ -49,11 +49,11 @@ static void __init m5206_uart_init_line(int line, int irq)
         if (line == 0) {
                 writel(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR);
                 writeb(irq, MCFUART_BASE1 + MCFUART_UIVR);
-                mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_UART1);
+                mcf_clrimr(MCFINTC_UART0);
         } else if (line == 1) {
                 writel(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR);
                 writeb(irq, MCFUART_BASE2 + MCFUART_UIVR);
-                mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_UART2);
+                mcf_clrimr(MCFINTC_UART1);
         }
 }
 
@@ -75,13 +75,13 @@ void mcf_settimericr(unsigned int timer, unsigned int level)
 
         if (timer <= 2) {
                 switch (timer) {
-                case 2:  icr = MCFSIM_TIMER2ICR; imr = MCFSIM_IMR_TIMER2; break;
-                default: icr = MCFSIM_TIMER1ICR; imr = MCFSIM_IMR_TIMER1; break;
+                case 2:  icr = MCFSIM_TIMER2ICR; imr = MCFINTC_TIMER2; break;
+                default: icr = MCFSIM_TIMER1ICR; imr = MCFINTC_TIMER1; break;
                 }
 
                 icrp = (volatile unsigned char *) (MCF_MBAR + icr);
                 *icrp = MCFSIM_ICR_AUTOVEC | (level << 2) | MCFSIM_ICR_PRI3;
-                mcf_setimr(mcf_getimr() & ~imr);
+                mcf_clrimr(imr);
         }
 }
 
@@ -100,7 +100,6 @@ void m5206_cpu_reset(void)
 
 void __init config_BSP(char *commandp, int size)
 {
-        mcf_setimr(MCFSIM_IMR_MASKALL);
         mach_reset = m5206_cpu_reset;
 }
 
diff --git a/arch/m68knommu/platform/5206e/config.c b/arch/m68knommu/platform/5206e/config.c
index 29e565a44431..08ef7e268989 100644
--- a/arch/m68knommu/platform/5206e/config.c
+++ b/arch/m68knommu/platform/5206e/config.c
@@ -50,11 +50,11 @@ static void __init m5206e_uart_init_line(int line, int irq)
         if (line == 0) {
                 writel(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR);
                 writeb(irq, MCFUART_BASE1 + MCFUART_UIVR);
-                mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_UART1);
+                mcf_clrimr(MCFINTC_UART0);
         } else if (line == 1) {
                 writel(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR);
                 writeb(irq, MCFUART_BASE2 + MCFUART_UIVR);
-                mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_UART2);
+                mcf_clrimr(MCFINTC_UART1);
         }
 }
 
@@ -76,13 +76,13 @@ void mcf_settimericr(unsigned int timer, unsigned int level)
 
         if (timer <= 2) {
                 switch (timer) {
-                case 2:  icr = MCFSIM_TIMER2ICR; imr = MCFSIM_IMR_TIMER2; break;
-                default: icr = MCFSIM_TIMER1ICR; imr = MCFSIM_IMR_TIMER1; break;
+                case 2:  icr = MCFSIM_TIMER2ICR; imr = MCFINTC_TIMER2; break;
+                default: icr = MCFSIM_TIMER1ICR; imr = MCFINTC_TIMER1; break;
                 }
 
                 icrp = (volatile unsigned char *) (MCF_MBAR + icr);
                 *icrp = MCFSIM_ICR_AUTOVEC | (level << 2) | MCFSIM_ICR_PRI3;
-                mcf_setimr(mcf_getimr() & ~imr);
+                mcf_clrimr(imr);
         }
 }
 
@@ -101,8 +101,6 @@ void m5206e_cpu_reset(void)
 
 void __init config_BSP(char *commandp, int size)
 {
-        mcf_setimr(MCFSIM_IMR_MASKALL);
-
 #if defined(CONFIG_NETtel)
         /* Copy command line from FLASH to local buffer... */
         memcpy(commandp, (char *) 0xf0004000, size);
diff --git a/arch/m68knommu/platform/5249/config.c b/arch/m68knommu/platform/5249/config.c
index 365fb6c52700..7261a3d28adc 100644
--- a/arch/m68knommu/platform/5249/config.c
+++ b/arch/m68knommu/platform/5249/config.c
@@ -48,11 +48,11 @@ static void __init m5249_uart_init_line(int line, int irq)
         if (line == 0) {
                 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR);
                 writeb(irq, MCF_MBAR + MCFUART_BASE1 + MCFUART_UIVR);
-                mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_UART1);
+                mcf_clrimr(MCFINTC_UART0);
         } else if (line == 1) {
                 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR);
                 writeb(irq, MCF_MBAR + MCFUART_BASE2 + MCFUART_UIVR);
-                mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_UART2);
+                mcf_clrimr(MCFINTC_UART1);
         }
 }
 
@@ -75,13 +75,13 @@ void mcf_settimericr(unsigned int timer, unsigned int level)
 
         if (timer <= 2) {
                 switch (timer) {
-                case 2:  icr = MCFSIM_TIMER2ICR; imr = MCFSIM_IMR_TIMER2; break;
-                default: icr = MCFSIM_TIMER1ICR; imr = MCFSIM_IMR_TIMER1; break;
+                case 2:  icr = MCFSIM_TIMER2ICR; imr = MCFINTC_TIMER2; break;
+                default: icr = MCFSIM_TIMER1ICR; imr = MCFINTC_TIMER1; break;
                 }
 
                 icrp = (volatile unsigned char *) (MCF_MBAR + icr);
                 *icrp = MCFSIM_ICR_AUTOVEC | (level << 2) | MCFSIM_ICR_PRI3;
-                mcf_setimr(mcf_getimr() & ~imr);
+                mcf_clrimr(imr);
         }
 }
 
@@ -100,7 +100,6 @@ void m5249_cpu_reset(void)
 
 void __init config_BSP(char *commandp, int size)
 {
-        mcf_setimr(MCFSIM_IMR_MASKALL);
         mach_reset = m5249_cpu_reset;
 }
 
diff --git a/arch/m68knommu/platform/5307/config.c b/arch/m68knommu/platform/5307/config.c
index 60fe45d51391..3e27d2ec03f0 100644
--- a/arch/m68knommu/platform/5307/config.c
+++ b/arch/m68knommu/platform/5307/config.c
@@ -64,11 +64,11 @@ static void __init m5307_uart_init_line(int line, int irq)
         if (line == 0) {
                 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR);
                 writeb(irq, MCF_MBAR + MCFUART_BASE1 + MCFUART_UIVR);
-                mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_UART1);
+                mcf_clrimr(MCFINTC_UART0);
         } else if (line == 1) {
                 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR);
                 writeb(irq, MCF_MBAR + MCFUART_BASE2 + MCFUART_UIVR);
-                mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_UART2);
+                mcf_clrimr(MCFINTC_UART1);
         }
 }
 
@@ -90,13 +90,13 @@ void mcf_settimericr(unsigned int timer, unsigned int level)
 
         if (timer <= 2) {
                 switch (timer) {
-                case 2:  icr = MCFSIM_TIMER2ICR; imr = MCFSIM_IMR_TIMER2; break;
-                default: icr = MCFSIM_TIMER1ICR; imr = MCFSIM_IMR_TIMER1; break;
+                case 2:  icr = MCFSIM_TIMER2ICR; imr = MCFINTC_TIMER2; break;
+                default: icr = MCFSIM_TIMER1ICR; imr = MCFINTC_TIMER1; break;
                 }
 
                 icrp = (volatile unsigned char *) (MCF_MBAR + icr);
                 *icrp = MCFSIM_ICR_AUTOVEC | (level << 2) | MCFSIM_ICR_PRI3;
-                mcf_setimr(mcf_getimr() & ~imr);
+                mcf_clrimr(imr);
         }
 }
 
@@ -115,8 +115,6 @@ void m5307_cpu_reset(void)
 
 void __init config_BSP(char *commandp, int size)
 {
-        mcf_setimr(MCFSIM_IMR_MASKALL);
-
 #if defined(CONFIG_NETtel) || \
     defined(CONFIG_SECUREEDGEMP3) || defined(CONFIG_CLEOPATRA)
         /* Copy command line from FLASH to local buffer... */
diff --git a/arch/m68knommu/platform/5407/config.c b/arch/m68knommu/platform/5407/config.c
index 1e8ef74ea156..8aa94837bbc3 100644
--- a/arch/m68knommu/platform/5407/config.c
+++ b/arch/m68knommu/platform/5407/config.c
@@ -55,11 +55,11 @@ static void __init m5407_uart_init_line(int line, int irq)
         if (line == 0) {
                 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR);
                 writeb(irq, MCF_MBAR + MCFUART_BASE1 + MCFUART_UIVR);
-                mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_UART1);
+                mcf_clrimr(MCFINTC_UART0);
         } else if (line == 1) {
                 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR);
                 writeb(irq, MCF_MBAR + MCFUART_BASE2 + MCFUART_UIVR);
-                mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_UART2);
+                mcf_clrimr(MCFINTC_UART1);
         }
 }
 
@@ -81,13 +81,13 @@ void mcf_settimericr(unsigned int timer, unsigned int level)
 
         if (timer <= 2) {
                 switch (timer) {
-                case 2:  icr = MCFSIM_TIMER2ICR; imr = MCFSIM_IMR_TIMER2; break;
-                default: icr = MCFSIM_TIMER1ICR; imr = MCFSIM_IMR_TIMER1; break;
+                case 2:  icr = MCFSIM_TIMER2ICR; imr = MCFINTC_TIMER2; break;
+                default: icr = MCFSIM_TIMER1ICR; imr = MCFINTC_TIMER1; break;
                 }
 
                 icrp = (volatile unsigned char *) (MCF_MBAR + icr);
                 *icrp = MCFSIM_ICR_AUTOVEC | (level << 2) | MCFSIM_ICR_PRI3;
-                mcf_setimr(mcf_getimr() & ~imr);
+                mcf_clrimr(imr);
         }
 }
 
@@ -106,8 +106,6 @@ void m5407_cpu_reset(void)
 
 void __init config_BSP(char *commandp, int size)
 {
-        mcf_setimr(MCFSIM_IMR_MASKALL);
-
 #if defined(CONFIG_CLEOPATRA)
         /* Different timer setup - to prevent device clash */
         mcf_timervector = 30;
diff --git a/arch/m68knommu/platform/coldfire/intc.c b/arch/m68knommu/platform/coldfire/intc.c
index f7a61346ee25..88bffac50c67 100644
--- a/arch/m68knommu/platform/coldfire/intc.c
+++ b/arch/m68knommu/platform/coldfire/intc.c
@@ -1,5 +1,5 @@
 /*
- * intc.c
+ * intc.c  -- support for the old ColdFire interrupt controller
  *
  * (C) Copyright 2009, Greg Ungerer <gerg@snapgear.com>
  *
@@ -27,6 +27,62 @@
 #define EIRQ7   31
 
 /*
+ * In the early version 2 core ColdFire parts the IMR register was 16 bits
+ * in size. Version 3 (and later version 2) core parts have a 32 bit
+ * sized IMR register. Provide some size independant methods to access the
+ * IMR register.
+ */
+#ifdef MCFSIM_IMR_IS_16BITS
+
+void mcf_setimr(int index)
+{
+        u16 imr;
+        imr = __raw_readw(MCF_MBAR + MCFSIM_IMR);
+        __raw_writew(imr | (0x1 << index), MCF_MBAR + MCFSIM_IMR);
+}
+
+void mcf_clrimr(int index)
+{
+        u16 imr;
+        imr = __raw_readw(MCF_MBAR + MCFSIM_IMR);
+        __raw_writew(imr & ~(0x1 << index), MCF_MBAR + MCFSIM_IMR);
+}
+
+void mcf_maskimr(unsigned int mask)
+{
+        u16 imr;
+        imr = __raw_readw(MCF_MBAR + MCFSIM_IMR);
+        imr |= mask;
+        __raw_writew(imr, MCF_MBAR + MCFSIM_IMR);
+}
+
+#else
+
+void mcf_setimr(int index)
+{
+        u32 imr;
+        imr = __raw_readl(MCF_MBAR + MCFSIM_IMR);
+        __raw_writel(imr | (0x1 << index), MCF_MBAR + MCFSIM_IMR);
+}
+
+void mcf_clrimr(int index)
+{
+        u32 imr;
+        imr = __raw_readl(MCF_MBAR + MCFSIM_IMR);
+        __raw_writel(imr & ~(0x1 << index), MCF_MBAR + MCFSIM_IMR);
+}
+
+void mcf_maskimr(unsigned int mask)
+{
+        u32 imr;
+        imr = __raw_readl(MCF_MBAR + MCFSIM_IMR);
+        imr |= mask;
+        __raw_writel(imr, MCF_MBAR + MCFSIM_IMR);
+}
+
+#endif
+
+/*
  * Interrupts can be "vectored" on the ColdFire cores that support this old
  * interrupt controller. That is, the device raising the interrupt can also
  * supply the vector number to interrupt through. The AVR register of the
@@ -70,6 +126,7 @@ void __init init_IRQ(void)
         int irq;
 
         init_vectors();
+        mcf_maskimr(0xffffffff);
 
         for (irq = 0; (irq < NR_IRQS); irq++) {
                 irq_desc[irq].status = IRQ_DISABLED;