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-rw-r--r--arch/m68knommu/platform/5206/Makefile4
-rw-r--r--arch/m68knommu/platform/5206e/Makefile4
-rw-r--r--arch/m68knommu/platform/520x/Makefile4
-rw-r--r--arch/m68knommu/platform/523x/Makefile4
-rw-r--r--arch/m68knommu/platform/5249/Makefile4
-rw-r--r--arch/m68knommu/platform/5272/Makefile4
-rw-r--r--arch/m68knommu/platform/5272/config.c16
-rw-r--r--arch/m68knommu/platform/5272/intc.c60
-rw-r--r--arch/m68knommu/platform/527x/Makefile4
-rw-r--r--arch/m68knommu/platform/528x/Makefile4
-rw-r--r--arch/m68knommu/platform/5307/Makefile4
-rw-r--r--arch/m68knommu/platform/532x/Makefile4
-rw-r--r--arch/m68knommu/platform/5407/Makefile4
-rw-r--r--arch/m68knommu/platform/548x/Makefile18
-rw-r--r--arch/m68knommu/platform/548x/config.c115
-rw-r--r--arch/m68knommu/platform/68328/entry.S36
-rw-r--r--arch/m68knommu/platform/68328/head-de2.S6
-rw-r--r--arch/m68knommu/platform/68328/head-ram.S27
-rw-r--r--arch/m68knommu/platform/68328/ints.c6
-rw-r--r--arch/m68knommu/platform/68360/entry.S13
-rw-r--r--arch/m68knommu/platform/68360/ints.c6
-rw-r--r--arch/m68knommu/platform/68VZ328/config.c5
-rw-r--r--arch/m68knommu/platform/coldfire/Makefile5
-rw-r--r--arch/m68knommu/platform/coldfire/entry.S4
-rw-r--r--arch/m68knommu/platform/coldfire/intc-2.c53
-rw-r--r--arch/m68knommu/platform/coldfire/intc-simr.c10
-rw-r--r--arch/m68knommu/platform/coldfire/intc.c8
-rw-r--r--arch/m68knommu/platform/coldfire/sltimers.c145
28 files changed, 455 insertions, 122 deletions
diff --git a/arch/m68knommu/platform/5206/Makefile b/arch/m68knommu/platform/5206/Makefile
index 113c33390064..b5db05625cfa 100644
--- a/arch/m68knommu/platform/5206/Makefile
+++ b/arch/m68knommu/platform/5206/Makefile
@@ -8,8 +8,8 @@
8# on the console port whenever a DBG interrupt occurs. You have to 8# on the console port whenever a DBG interrupt occurs. You have to
9# set up you HW breakpoints to trigger a DBG interrupt: 9# set up you HW breakpoints to trigger a DBG interrupt:
10# 10#
11# EXTRA_CFLAGS += -DTRAP_DBG_INTERRUPT 11# ccflags-y := -DTRAP_DBG_INTERRUPT
12# EXTRA_AFLAGS += -DTRAP_DBG_INTERRUPT 12# asflags-y := -DTRAP_DBG_INTERRUPT
13# 13#
14 14
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
diff --git a/arch/m68knommu/platform/5206e/Makefile b/arch/m68knommu/platform/5206e/Makefile
index 113c33390064..b5db05625cfa 100644
--- a/arch/m68knommu/platform/5206e/Makefile
+++ b/arch/m68knommu/platform/5206e/Makefile
@@ -8,8 +8,8 @@
8# on the console port whenever a DBG interrupt occurs. You have to 8# on the console port whenever a DBG interrupt occurs. You have to
9# set up you HW breakpoints to trigger a DBG interrupt: 9# set up you HW breakpoints to trigger a DBG interrupt:
10# 10#
11# EXTRA_CFLAGS += -DTRAP_DBG_INTERRUPT 11# ccflags-y := -DTRAP_DBG_INTERRUPT
12# EXTRA_AFLAGS += -DTRAP_DBG_INTERRUPT 12# asflags-y := -DTRAP_DBG_INTERRUPT
13# 13#
14 14
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
diff --git a/arch/m68knommu/platform/520x/Makefile b/arch/m68knommu/platform/520x/Makefile
index 435ab3483dc1..ad3f4e5a57ce 100644
--- a/arch/m68knommu/platform/520x/Makefile
+++ b/arch/m68knommu/platform/520x/Makefile
@@ -8,8 +8,8 @@
8# on the console port whenever a DBG interrupt occurs. You have to 8# on the console port whenever a DBG interrupt occurs. You have to
9# set up you HW breakpoints to trigger a DBG interrupt: 9# set up you HW breakpoints to trigger a DBG interrupt:
10# 10#
11# EXTRA_CFLAGS += -DTRAP_DBG_INTERRUPT 11# ccflags-y := -DTRAP_DBG_INTERRUPT
12# EXTRA_AFLAGS += -DTRAP_DBG_INTERRUPT 12# asflags-y := -DTRAP_DBG_INTERRUPT
13# 13#
14 14
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
diff --git a/arch/m68knommu/platform/523x/Makefile b/arch/m68knommu/platform/523x/Makefile
index b8f9b45440c2..c04b8f71c88c 100644
--- a/arch/m68knommu/platform/523x/Makefile
+++ b/arch/m68knommu/platform/523x/Makefile
@@ -8,8 +8,8 @@
8# on the console port whenever a DBG interrupt occurs. You have to 8# on the console port whenever a DBG interrupt occurs. You have to
9# set up you HW breakpoints to trigger a DBG interrupt: 9# set up you HW breakpoints to trigger a DBG interrupt:
10# 10#
11# EXTRA_CFLAGS += -DTRAP_DBG_INTERRUPT 11# ccflags-y := -DTRAP_DBG_INTERRUPT
12# EXTRA_AFLAGS += -DTRAP_DBG_INTERRUPT 12# asflags-y := -DTRAP_DBG_INTERRUPT
13# 13#
14 14
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
diff --git a/arch/m68knommu/platform/5249/Makefile b/arch/m68knommu/platform/5249/Makefile
index f56225d1582f..4bed30fd0073 100644
--- a/arch/m68knommu/platform/5249/Makefile
+++ b/arch/m68knommu/platform/5249/Makefile
@@ -8,8 +8,8 @@
8# on the console port whenever a DBG interrupt occurs. You have to 8# on the console port whenever a DBG interrupt occurs. You have to
9# set up you HW breakpoints to trigger a DBG interrupt: 9# set up you HW breakpoints to trigger a DBG interrupt:
10# 10#
11# EXTRA_CFLAGS += -DTRAP_DBG_INTERRUPT 11# ccflags-y := -DTRAP_DBG_INTERRUPT
12# EXTRA_AFLAGS += -DTRAP_DBG_INTERRUPT 12# asflags-y := -DTRAP_DBG_INTERRUPT
13# 13#
14 14
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
diff --git a/arch/m68knommu/platform/5272/Makefile b/arch/m68knommu/platform/5272/Makefile
index 93673ef8e2c1..34110fc14301 100644
--- a/arch/m68knommu/platform/5272/Makefile
+++ b/arch/m68knommu/platform/5272/Makefile
@@ -8,8 +8,8 @@
8# on the console port whenever a DBG interrupt occurs. You have to 8# on the console port whenever a DBG interrupt occurs. You have to
9# set up you HW breakpoints to trigger a DBG interrupt: 9# set up you HW breakpoints to trigger a DBG interrupt:
10# 10#
11# EXTRA_CFLAGS += -DTRAP_DBG_INTERRUPT 11# ccflags-y := -DTRAP_DBG_INTERRUPT
12# EXTRA_AFLAGS += -DTRAP_DBG_INTERRUPT 12# asflags-y := -DTRAP_DBG_INTERRUPT
13# 13#
14 14
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
diff --git a/arch/m68knommu/platform/5272/config.c b/arch/m68knommu/platform/5272/config.c
index 59278c0887d0..65bb582734e1 100644
--- a/arch/m68knommu/platform/5272/config.c
+++ b/arch/m68knommu/platform/5272/config.c
@@ -13,6 +13,8 @@
13#include <linux/param.h> 13#include <linux/param.h>
14#include <linux/init.h> 14#include <linux/init.h>
15#include <linux/io.h> 15#include <linux/io.h>
16#include <linux/phy.h>
17#include <linux/phy_fixed.h>
16#include <asm/machdep.h> 18#include <asm/machdep.h>
17#include <asm/coldfire.h> 19#include <asm/coldfire.h>
18#include <asm/mcfsim.h> 20#include <asm/mcfsim.h>
@@ -148,9 +150,23 @@ void __init config_BSP(char *commandp, int size)
148 150
149/***************************************************************************/ 151/***************************************************************************/
150 152
153/*
154 * Some 5272 based boards have the FEC ethernet diectly connected to
155 * an ethernet switch. In this case we need to use the fixed phy type,
156 * and we need to declare it early in boot.
157 */
158static struct fixed_phy_status nettel_fixed_phy_status __initdata = {
159 .link = 1,
160 .speed = 100,
161 .duplex = 0,
162};
163
164/***************************************************************************/
165
151static int __init init_BSP(void) 166static int __init init_BSP(void)
152{ 167{
153 m5272_uarts_init(); 168 m5272_uarts_init();
169 fixed_phy_add(PHY_POLL, 0, &nettel_fixed_phy_status);
154 platform_add_devices(m5272_devices, ARRAY_SIZE(m5272_devices)); 170 platform_add_devices(m5272_devices, ARRAY_SIZE(m5272_devices));
155 return 0; 171 return 0;
156} 172}
diff --git a/arch/m68knommu/platform/5272/intc.c b/arch/m68knommu/platform/5272/intc.c
index 7081e0a9720e..3cf681c177aa 100644
--- a/arch/m68knommu/platform/5272/intc.c
+++ b/arch/m68knommu/platform/5272/intc.c
@@ -12,6 +12,7 @@
12#include <linux/init.h> 12#include <linux/init.h>
13#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <linux/interrupt.h> 14#include <linux/interrupt.h>
15#include <linux/kernel_stat.h>
15#include <linux/irq.h> 16#include <linux/irq.h>
16#include <linux/io.h> 17#include <linux/io.h>
17#include <asm/coldfire.h> 18#include <asm/coldfire.h>
@@ -29,6 +30,10 @@
29 * via a set of 4 "Interrupt Controller Registers" (ICR). There is a 30 * via a set of 4 "Interrupt Controller Registers" (ICR). There is a
30 * loose mapping of vector number to register and internal bits, but 31 * loose mapping of vector number to register and internal bits, but
31 * a table is the easiest and quickest way to map them. 32 * a table is the easiest and quickest way to map them.
33 *
34 * Note that the external interrupts are edge triggered (unlike the
35 * internal interrupt sources which are level triggered). Which means
36 * they also need acknowledgeing via acknowledge bits.
32 */ 37 */
33struct irqmap { 38struct irqmap {
34 unsigned char icr; 39 unsigned char icr;
@@ -68,6 +73,11 @@ static struct irqmap intc_irqmap[MCFINT_VECMAX - MCFINT_VECBASE] = {
68 /*MCF_IRQ_SWTO*/ { .icr = MCFSIM_ICR4, .index = 16, .ack = 0, }, 73 /*MCF_IRQ_SWTO*/ { .icr = MCFSIM_ICR4, .index = 16, .ack = 0, },
69}; 74};
70 75
76/*
77 * The act of masking the interrupt also has a side effect of 'ack'ing
78 * an interrupt on this irq (for the external irqs). So this mask function
79 * is also an ack_mask function.
80 */
71static void intc_irq_mask(unsigned int irq) 81static void intc_irq_mask(unsigned int irq)
72{ 82{
73 if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) { 83 if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) {
@@ -95,7 +105,9 @@ static void intc_irq_ack(unsigned int irq)
95 irq -= MCFINT_VECBASE; 105 irq -= MCFINT_VECBASE;
96 if (intc_irqmap[irq].ack) { 106 if (intc_irqmap[irq].ack) {
97 u32 v; 107 u32 v;
98 v = 0xd << intc_irqmap[irq].index; 108 v = readl(MCF_MBAR + intc_irqmap[irq].icr);
109 v &= (0x7 << intc_irqmap[irq].index);
110 v |= (0x8 << intc_irqmap[irq].index);
99 writel(v, MCF_MBAR + intc_irqmap[irq].icr); 111 writel(v, MCF_MBAR + intc_irqmap[irq].icr);
100 } 112 }
101 } 113 }
@@ -103,21 +115,47 @@ static void intc_irq_ack(unsigned int irq)
103 115
104static int intc_irq_set_type(unsigned int irq, unsigned int type) 116static int intc_irq_set_type(unsigned int irq, unsigned int type)
105{ 117{
106 /* We can set the edge type here for external interrupts */ 118 if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) {
119 irq -= MCFINT_VECBASE;
120 if (intc_irqmap[irq].ack) {
121 u32 v;
122 v = readl(MCF_MBAR + MCFSIM_PITR);
123 if (type == IRQ_TYPE_EDGE_FALLING)
124 v &= ~(0x1 << (32 - irq));
125 else
126 v |= (0x1 << (32 - irq));
127 writel(v, MCF_MBAR + MCFSIM_PITR);
128 }
129 }
107 return 0; 130 return 0;
108} 131}
109 132
133/*
134 * Simple flow handler to deal with the external edge triggered interrupts.
135 * We need to be careful with the masking/acking due to the side effects
136 * of masking an interrupt.
137 */
138static void intc_external_irq(unsigned int irq, struct irq_desc *desc)
139{
140 kstat_incr_irqs_this_cpu(irq, desc);
141 desc->status |= IRQ_INPROGRESS;
142 desc->chip->ack(irq);
143 handle_IRQ_event(irq, desc->action);
144 desc->status &= ~IRQ_INPROGRESS;
145}
146
110static struct irq_chip intc_irq_chip = { 147static struct irq_chip intc_irq_chip = {
111 .name = "CF-INTC", 148 .name = "CF-INTC",
112 .mask = intc_irq_mask, 149 .mask = intc_irq_mask,
113 .unmask = intc_irq_unmask, 150 .unmask = intc_irq_unmask,
151 .mask_ack = intc_irq_mask,
114 .ack = intc_irq_ack, 152 .ack = intc_irq_ack,
115 .set_type = intc_irq_set_type, 153 .set_type = intc_irq_set_type,
116}; 154};
117 155
118void __init init_IRQ(void) 156void __init init_IRQ(void)
119{ 157{
120 int irq; 158 int irq, edge;
121 159
122 init_vectors(); 160 init_vectors();
123 161
@@ -128,11 +166,17 @@ void __init init_IRQ(void)
128 writel(0x88888888, MCF_MBAR + MCFSIM_ICR4); 166 writel(0x88888888, MCF_MBAR + MCFSIM_ICR4);
129 167
130 for (irq = 0; (irq < NR_IRQS); irq++) { 168 for (irq = 0; (irq < NR_IRQS); irq++) {
131 irq_desc[irq].status = IRQ_DISABLED; 169 set_irq_chip(irq, &intc_irq_chip);
132 irq_desc[irq].action = NULL; 170 edge = 0;
133 irq_desc[irq].depth = 1; 171 if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX))
134 irq_desc[irq].chip = &intc_irq_chip; 172 edge = intc_irqmap[irq - MCFINT_VECBASE].ack;
135 intc_irq_set_type(irq, 0); 173 if (edge) {
174 set_irq_type(irq, IRQ_TYPE_EDGE_RISING);
175 set_irq_handler(irq, intc_external_irq);
176 } else {
177 set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH);
178 set_irq_handler(irq, handle_level_irq);
179 }
136 } 180 }
137} 181}
138 182
diff --git a/arch/m68knommu/platform/527x/Makefile b/arch/m68knommu/platform/527x/Makefile
index 3d90e6d92459..6ac4b57370ea 100644
--- a/arch/m68knommu/platform/527x/Makefile
+++ b/arch/m68knommu/platform/527x/Makefile
@@ -8,8 +8,8 @@
8# on the console port whenever a DBG interrupt occurs. You have to 8# on the console port whenever a DBG interrupt occurs. You have to
9# set up you HW breakpoints to trigger a DBG interrupt: 9# set up you HW breakpoints to trigger a DBG interrupt:
10# 10#
11# EXTRA_CFLAGS += -DTRAP_DBG_INTERRUPT 11# ccflags-y := -DTRAP_DBG_INTERRUPT
12# EXTRA_AFLAGS += -DTRAP_DBG_INTERRUPT 12# asflags-y := -DTRAP_DBG_INTERRUPT
13# 13#
14 14
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
diff --git a/arch/m68knommu/platform/528x/Makefile b/arch/m68knommu/platform/528x/Makefile
index 3d90e6d92459..6ac4b57370ea 100644
--- a/arch/m68knommu/platform/528x/Makefile
+++ b/arch/m68knommu/platform/528x/Makefile
@@ -8,8 +8,8 @@
8# on the console port whenever a DBG interrupt occurs. You have to 8# on the console port whenever a DBG interrupt occurs. You have to
9# set up you HW breakpoints to trigger a DBG interrupt: 9# set up you HW breakpoints to trigger a DBG interrupt:
10# 10#
11# EXTRA_CFLAGS += -DTRAP_DBG_INTERRUPT 11# ccflags-y := -DTRAP_DBG_INTERRUPT
12# EXTRA_AFLAGS += -DTRAP_DBG_INTERRUPT 12# asflags-y := -DTRAP_DBG_INTERRUPT
13# 13#
14 14
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
diff --git a/arch/m68knommu/platform/5307/Makefile b/arch/m68knommu/platform/5307/Makefile
index 6de526976828..d4293b791f2e 100644
--- a/arch/m68knommu/platform/5307/Makefile
+++ b/arch/m68knommu/platform/5307/Makefile
@@ -8,8 +8,8 @@
8# on the console port whenever a DBG interrupt occurs. You have to 8# on the console port whenever a DBG interrupt occurs. You have to
9# set up you HW breakpoints to trigger a DBG interrupt: 9# set up you HW breakpoints to trigger a DBG interrupt:
10# 10#
11# EXTRA_CFLAGS += -DTRAP_DBG_INTERRUPT 11# ccflags-y := -DTRAP_DBG_INTERRUPT
12# EXTRA_AFLAGS += -DTRAP_DBG_INTERRUPT 12# asflags-y := -DTRAP_DBG_INTERRUPT
13# 13#
14 14
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
diff --git a/arch/m68knommu/platform/532x/Makefile b/arch/m68knommu/platform/532x/Makefile
index 4cc23245bcd1..ce01669399c6 100644
--- a/arch/m68knommu/platform/532x/Makefile
+++ b/arch/m68knommu/platform/532x/Makefile
@@ -8,8 +8,8 @@
8# on the console port whenever a DBG interrupt occurs. You have to 8# on the console port whenever a DBG interrupt occurs. You have to
9# set up you HW breakpoints to trigger a DBG interrupt: 9# set up you HW breakpoints to trigger a DBG interrupt:
10# 10#
11# EXTRA_CFLAGS += -DTRAP_DBG_INTERRUPT 11# ccflags-y := -DTRAP_DBG_INTERRUPT
12# EXTRA_AFLAGS += -DTRAP_DBG_INTERRUPT 12# asflags-y := -DTRAP_DBG_INTERRUPT
13# 13#
14 14
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
diff --git a/arch/m68knommu/platform/5407/Makefile b/arch/m68knommu/platform/5407/Makefile
index dee62c5dbaa6..e83fe148eddc 100644
--- a/arch/m68knommu/platform/5407/Makefile
+++ b/arch/m68knommu/platform/5407/Makefile
@@ -8,8 +8,8 @@
8# on the console port whenever a DBG interrupt occurs. You have to 8# on the console port whenever a DBG interrupt occurs. You have to
9# set up you HW breakpoints to trigger a DBG interrupt: 9# set up you HW breakpoints to trigger a DBG interrupt:
10# 10#
11# EXTRA_CFLAGS += -DTRAP_DBG_INTERRUPT 11# ccflags-y := -DTRAP_DBG_INTERRUPT
12# EXTRA_AFLAGS += -DTRAP_DBG_INTERRUPT 12# asflags-y := -DTRAP_DBG_INTERRUPT
13# 13#
14 14
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
diff --git a/arch/m68knommu/platform/548x/Makefile b/arch/m68knommu/platform/548x/Makefile
new file mode 100644
index 000000000000..e6035e7a2d3f
--- /dev/null
+++ b/arch/m68knommu/platform/548x/Makefile
@@ -0,0 +1,18 @@
1#
2# Makefile for the m68knommu linux kernel.
3#
4
5#
6# If you want to play with the HW breakpoints then you will
7# need to add define this, which will give you a stack backtrace
8# on the console port whenever a DBG interrupt occurs. You have to
9# set up you HW breakpoints to trigger a DBG interrupt:
10#
11# EXTRA_CFLAGS += -DTRAP_DBG_INTERRUPT
12# EXTRA_AFLAGS += -DTRAP_DBG_INTERRUPT
13#
14
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
16
17obj-y := config.o
18
diff --git a/arch/m68knommu/platform/548x/config.c b/arch/m68knommu/platform/548x/config.c
new file mode 100644
index 000000000000..9888846bd1cf
--- /dev/null
+++ b/arch/m68knommu/platform/548x/config.c
@@ -0,0 +1,115 @@
1/***************************************************************************/
2
3/*
4 * linux/arch/m68knommu/platform/548x/config.c
5 *
6 * Copyright (C) 2010, Philippe De Muyter <phdm@macqel.be>
7 */
8
9/***************************************************************************/
10
11#include <linux/kernel.h>
12#include <linux/param.h>
13#include <linux/init.h>
14#include <linux/interrupt.h>
15#include <linux/io.h>
16#include <asm/machdep.h>
17#include <asm/coldfire.h>
18#include <asm/m548xsim.h>
19#include <asm/mcfuart.h>
20#include <asm/m548xgpt.h>
21
22/***************************************************************************/
23
24static struct mcf_platform_uart m548x_uart_platform[] = {
25 {
26 .mapbase = MCF_MBAR + MCFUART_BASE1,
27 .irq = 64 + 35,
28 },
29 {
30 .mapbase = MCF_MBAR + MCFUART_BASE2,
31 .irq = 64 + 34,
32 },
33 {
34 .mapbase = MCF_MBAR + MCFUART_BASE3,
35 .irq = 64 + 33,
36 },
37 {
38 .mapbase = MCF_MBAR + MCFUART_BASE4,
39 .irq = 64 + 32,
40 },
41};
42
43static struct platform_device m548x_uart = {
44 .name = "mcfuart",
45 .id = 0,
46 .dev.platform_data = m548x_uart_platform,
47};
48
49static struct platform_device *m548x_devices[] __initdata = {
50 &m548x_uart,
51};
52
53
54/***************************************************************************/
55
56static void __init m548x_uart_init_line(int line, int irq)
57{
58 int rts_cts;
59
60 /* enable io pins */
61 switch (line) {
62 case 0:
63 rts_cts = 0; break;
64 case 1:
65 rts_cts = MCF_PAR_PSC_RTS_RTS; break;
66 case 2:
67 rts_cts = MCF_PAR_PSC_RTS_RTS | MCF_PAR_PSC_CTS_CTS; break;
68 case 3:
69 rts_cts = 0; break;
70 }
71 __raw_writeb(MCF_PAR_PSC_TXD | rts_cts | MCF_PAR_PSC_RXD,
72 MCF_MBAR + MCF_PAR_PSC(line));
73}
74
75static void __init m548x_uarts_init(void)
76{
77 const int nrlines = ARRAY_SIZE(m548x_uart_platform);
78 int line;
79
80 for (line = 0; (line < nrlines); line++)
81 m548x_uart_init_line(line, m548x_uart_platform[line].irq);
82}
83
84/***************************************************************************/
85
86static void mcf548x_reset(void)
87{
88 /* disable interrupts and enable the watchdog */
89 asm("movew #0x2700, %sr\n");
90 __raw_writel(0, MCF_MBAR + MCF_GPT_GMS0);
91 __raw_writel(MCF_GPT_GCIR_CNT(1), MCF_MBAR + MCF_GPT_GCIR0);
92 __raw_writel(MCF_GPT_GMS_WDEN | MCF_GPT_GMS_CE | MCF_GPT_GMS_TMS(4),
93 MCF_MBAR + MCF_GPT_GMS0);
94}
95
96/***************************************************************************/
97
98void __init config_BSP(char *commandp, int size)
99{
100 mach_reset = mcf548x_reset;
101 m548x_uarts_init();
102}
103
104/***************************************************************************/
105
106static int __init init_BSP(void)
107{
108
109 platform_add_devices(m548x_devices, ARRAY_SIZE(m548x_devices));
110 return 0;
111}
112
113arch_initcall(init_BSP);
114
115/***************************************************************************/
diff --git a/arch/m68knommu/platform/68328/entry.S b/arch/m68knommu/platform/68328/entry.S
index 9d80d2c42866..27241e16a526 100644
--- a/arch/m68knommu/platform/68328/entry.S
+++ b/arch/m68knommu/platform/68328/entry.S
@@ -43,10 +43,10 @@ badsys:
43 jra ret_from_exception 43 jra ret_from_exception
44 44
45do_trace: 45do_trace:
46 movel #-ENOSYS,%sp@(PT_OFF_D0) /* needed for strace*/ 46 movel #-ENOSYS,%sp@(PT_OFF_D0) /* needed for strace*/
47 subql #4,%sp 47 subql #4,%sp
48 SAVE_SWITCH_STACK 48 SAVE_SWITCH_STACK
49 jbsr syscall_trace 49 jbsr syscall_trace_enter
50 RESTORE_SWITCH_STACK 50 RESTORE_SWITCH_STACK
51 addql #4,%sp 51 addql #4,%sp
52 movel %sp@(PT_OFF_ORIG_D0),%d1 52 movel %sp@(PT_OFF_ORIG_D0),%d1
@@ -57,10 +57,10 @@ do_trace:
57 lea sys_call_table, %a0 57 lea sys_call_table, %a0
58 jbsr %a0@(%d1) 58 jbsr %a0@(%d1)
59 59
601: movel %d0,%sp@(PT_OFF_D0) /* save the return value */ 601: movel %d0,%sp@(PT_OFF_D0) /* save the return value */
61 subql #4,%sp /* dummy return address */ 61 subql #4,%sp /* dummy return address */
62 SAVE_SWITCH_STACK 62 SAVE_SWITCH_STACK
63 jbsr syscall_trace 63 jbsr syscall_trace_leave
64 64
65ret_from_signal: 65ret_from_signal:
66 RESTORE_SWITCH_STACK 66 RESTORE_SWITCH_STACK
@@ -71,16 +71,16 @@ ENTRY(system_call)
71 SAVE_ALL 71 SAVE_ALL
72 72
73 /* save top of frame*/ 73 /* save top of frame*/
74 pea %sp@ 74 pea %sp@
75 jbsr set_esp0 75 jbsr set_esp0
76 addql #4,%sp 76 addql #4,%sp
77 77
78 movel %sp@(PT_OFF_ORIG_D0),%d0 78 movel %sp@(PT_OFF_ORIG_D0),%d0
79 79
80 movel %sp,%d1 /* get thread_info pointer */ 80 movel %sp,%d1 /* get thread_info pointer */
81 andl #-THREAD_SIZE,%d1 81 andl #-THREAD_SIZE,%d1
82 movel %d1,%a2 82 movel %d1,%a2
83 btst #TIF_SYSCALL_TRACE,%a2@(TI_FLAGS) 83 btst #(TIF_SYSCALL_TRACE%8),%a2@(TI_FLAGS+(31-TIF_SYSCALL_TRACE)/8)
84 jne do_trace 84 jne do_trace
85 cmpl #NR_syscalls,%d0 85 cmpl #NR_syscalls,%d0
86 jcc badsys 86 jcc badsys
@@ -88,10 +88,10 @@ ENTRY(system_call)
88 lea sys_call_table,%a0 88 lea sys_call_table,%a0
89 movel %a0@(%d0), %a0 89 movel %a0@(%d0), %a0
90 jbsr %a0@ 90 jbsr %a0@
91 movel %d0,%sp@(PT_OFF_D0) /* save the return value*/ 91 movel %d0,%sp@(PT_OFF_D0) /* save the return value*/
92 92
93ret_from_exception: 93ret_from_exception:
94 btst #5,%sp@(PT_OFF_SR) /* check if returning to kernel*/ 94 btst #5,%sp@(PT_OFF_SR) /* check if returning to kernel*/
95 jeq Luser_return /* if so, skip resched, signals*/ 95 jeq Luser_return /* if so, skip resched, signals*/
96 96
97Lkernel_return: 97Lkernel_return:
@@ -133,7 +133,7 @@ Lreturn:
133 */ 133 */
134inthandler1: 134inthandler1:
135 SAVE_ALL 135 SAVE_ALL
136 movew %sp@(PT_OFF_VECTOR), %d0 136 movew %sp@(PT_OFF_FORMATVEC), %d0
137 and #0x3ff, %d0 137 and #0x3ff, %d0
138 138
139 movel %sp,%sp@- 139 movel %sp,%sp@-
@@ -144,7 +144,7 @@ inthandler1:
144 144
145inthandler2: 145inthandler2:
146 SAVE_ALL 146 SAVE_ALL
147 movew %sp@(PT_OFF_VECTOR), %d0 147 movew %sp@(PT_OFF_FORMATVEC), %d0
148 and #0x3ff, %d0 148 and #0x3ff, %d0
149 149
150 movel %sp,%sp@- 150 movel %sp,%sp@-
@@ -155,7 +155,7 @@ inthandler2:
155 155
156inthandler3: 156inthandler3:
157 SAVE_ALL 157 SAVE_ALL
158 movew %sp@(PT_OFF_VECTOR), %d0 158 movew %sp@(PT_OFF_FORMATVEC), %d0
159 and #0x3ff, %d0 159 and #0x3ff, %d0
160 160
161 movel %sp,%sp@- 161 movel %sp,%sp@-
@@ -166,7 +166,7 @@ inthandler3:
166 166
167inthandler4: 167inthandler4:
168 SAVE_ALL 168 SAVE_ALL
169 movew %sp@(PT_OFF_VECTOR), %d0 169 movew %sp@(PT_OFF_FORMATVEC), %d0
170 and #0x3ff, %d0 170 and #0x3ff, %d0
171 171
172 movel %sp,%sp@- 172 movel %sp,%sp@-
@@ -177,7 +177,7 @@ inthandler4:
177 177
178inthandler5: 178inthandler5:
179 SAVE_ALL 179 SAVE_ALL
180 movew %sp@(PT_OFF_VECTOR), %d0 180 movew %sp@(PT_OFF_FORMATVEC), %d0
181 and #0x3ff, %d0 181 and #0x3ff, %d0
182 182
183 movel %sp,%sp@- 183 movel %sp,%sp@-
@@ -188,7 +188,7 @@ inthandler5:
188 188
189inthandler6: 189inthandler6:
190 SAVE_ALL 190 SAVE_ALL
191 movew %sp@(PT_OFF_VECTOR), %d0 191 movew %sp@(PT_OFF_FORMATVEC), %d0
192 and #0x3ff, %d0 192 and #0x3ff, %d0
193 193
194 movel %sp,%sp@- 194 movel %sp,%sp@-
@@ -199,7 +199,7 @@ inthandler6:
199 199
200inthandler7: 200inthandler7:
201 SAVE_ALL 201 SAVE_ALL
202 movew %sp@(PT_OFF_VECTOR), %d0 202 movew %sp@(PT_OFF_FORMATVEC), %d0
203 and #0x3ff, %d0 203 and #0x3ff, %d0
204 204
205 movel %sp,%sp@- 205 movel %sp,%sp@-
@@ -210,7 +210,7 @@ inthandler7:
210 210
211inthandler: 211inthandler:
212 SAVE_ALL 212 SAVE_ALL
213 movew %sp@(PT_OFF_VECTOR), %d0 213 movew %sp@(PT_OFF_FORMATVEC), %d0
214 and #0x3ff, %d0 214 and #0x3ff, %d0
215 215
216 movel %sp,%sp@- 216 movel %sp,%sp@-
diff --git a/arch/m68knommu/platform/68328/head-de2.S b/arch/m68knommu/platform/68328/head-de2.S
index 92d96456d363..f632fdcb93e9 100644
--- a/arch/m68knommu/platform/68328/head-de2.S
+++ b/arch/m68knommu/platform/68328/head-de2.S
@@ -1,11 +1,5 @@
1 1
2#if defined(CONFIG_RAM32MB)
3#define MEM_END 0x02000000 /* Memory size 32Mb */
4#elif defined(CONFIG_RAM16MB)
5#define MEM_END 0x01000000 /* Memory size 16Mb */
6#else
7#define MEM_END 0x00800000 /* Memory size 8Mb */ 2#define MEM_END 0x00800000 /* Memory size 8Mb */
8#endif
9 3
10#undef CRT_DEBUG 4#undef CRT_DEBUG
11 5
diff --git a/arch/m68knommu/platform/68328/head-ram.S b/arch/m68knommu/platform/68328/head-ram.S
index 252b80b02038..7f1aeeacb219 100644
--- a/arch/m68knommu/platform/68328/head-ram.S
+++ b/arch/m68knommu/platform/68328/head-ram.S
@@ -67,33 +67,6 @@ pclp1:
67 beq pclp1 67 beq pclp1
68#endif /* DEBUG */ 68#endif /* DEBUG */
69 69
70#ifdef CONFIG_RELOCATE
71 /* Copy me to RAM */
72 moveal #__rom_start, %a0
73 moveal #_stext, %a1
74 moveal #_edata, %a2
75
76 /* Copy %a0 to %a1 until %a1 == %a2 */
77LD1:
78 movel %a0@+, %d0
79 movel %d0, %a1@+
80 cmpal %a1, %a2
81 bhi LD1
82
83#ifdef DEBUG
84 moveq #74, %d7 /* 'J' */
85 moveb %d7,0xfffff907 /* No absolute addresses */
86pclp2:
87 movew 0xfffff906, %d7
88 andw #0x2000, %d7
89 beq pclp2
90#endif /* DEBUG */
91 /* jump into the RAM copy */
92 jmp ram_jump
93ram_jump:
94
95#endif /* CONFIG_RELOCATE */
96
97#ifdef DEBUG 70#ifdef DEBUG
98 moveq #82, %d7 /* 'R' */ 71 moveq #82, %d7 /* 'R' */
99 moveb %d7,0xfffff907 /* No absolute addresses */ 72 moveb %d7,0xfffff907 /* No absolute addresses */
diff --git a/arch/m68knommu/platform/68328/ints.c b/arch/m68knommu/platform/68328/ints.c
index b91ee85d4b5d..865852806a17 100644
--- a/arch/m68knommu/platform/68328/ints.c
+++ b/arch/m68knommu/platform/68328/ints.c
@@ -179,10 +179,8 @@ void __init init_IRQ(void)
179 IMR = ~0; 179 IMR = ~0;
180 180
181 for (i = 0; (i < NR_IRQS); i++) { 181 for (i = 0; (i < NR_IRQS); i++) {
182 irq_desc[i].status = IRQ_DISABLED; 182 set_irq_chip(irq, &intc_irq_chip);
183 irq_desc[i].action = NULL; 183 set_irq_handler(irq, handle_level_irq);
184 irq_desc[i].depth = 1;
185 irq_desc[i].chip = &intc_irq_chip;
186 } 184 }
187} 185}
188 186
diff --git a/arch/m68knommu/platform/68360/entry.S b/arch/m68knommu/platform/68360/entry.S
index 6d3460a39cac..c131c6e1d92d 100644
--- a/arch/m68knommu/platform/68360/entry.S
+++ b/arch/m68knommu/platform/68360/entry.S
@@ -42,7 +42,7 @@ do_trace:
42 movel #-ENOSYS,%sp@(PT_OFF_D0) /* needed for strace*/ 42 movel #-ENOSYS,%sp@(PT_OFF_D0) /* needed for strace*/
43 subql #4,%sp 43 subql #4,%sp
44 SAVE_SWITCH_STACK 44 SAVE_SWITCH_STACK
45 jbsr syscall_trace 45 jbsr syscall_trace_enter
46 RESTORE_SWITCH_STACK 46 RESTORE_SWITCH_STACK
47 addql #4,%sp 47 addql #4,%sp
48 movel %sp@(PT_OFF_ORIG_D0),%d1 48 movel %sp@(PT_OFF_ORIG_D0),%d1
@@ -56,7 +56,7 @@ do_trace:
561: movel %d0,%sp@(PT_OFF_D0) /* save the return value */ 561: movel %d0,%sp@(PT_OFF_D0) /* save the return value */
57 subql #4,%sp /* dummy return address */ 57 subql #4,%sp /* dummy return address */
58 SAVE_SWITCH_STACK 58 SAVE_SWITCH_STACK
59 jbsr syscall_trace 59 jbsr syscall_trace_leave
60 60
61ret_from_signal: 61ret_from_signal:
62 RESTORE_SWITCH_STACK 62 RESTORE_SWITCH_STACK
@@ -71,7 +71,12 @@ ENTRY(system_call)
71 jbsr set_esp0 71 jbsr set_esp0
72 addql #4,%sp 72 addql #4,%sp
73 73
74 btst #PF_TRACESYS_BIT,%a2@(TASK_FLAGS+PF_TRACESYS_OFF) 74 movel %sp@(PT_OFF_ORIG_D0),%d0
75
76 movel %sp,%d1 /* get thread_info pointer */
77 andl #-THREAD_SIZE,%d1
78 movel %d1,%a2
79 btst #(TIF_SYSCALL_TRACE%8),%a2@(TI_FLAGS+(31-TIF_SYSCALL_TRACE)/8)
75 jne do_trace 80 jne do_trace
76 cmpl #NR_syscalls,%d0 81 cmpl #NR_syscalls,%d0
77 jcc badsys 82 jcc badsys
@@ -124,7 +129,7 @@ Lreturn:
124 */ 129 */
125inthandler: 130inthandler:
126 SAVE_ALL 131 SAVE_ALL
127 movew %sp@(PT_OFF_VECTOR), %d0 132 movew %sp@(PT_OFF_FORMATVEC), %d0
128 and.l #0x3ff, %d0 133 and.l #0x3ff, %d0
129 lsr.l #0x02, %d0 134 lsr.l #0x02, %d0
130 135
diff --git a/arch/m68knommu/platform/68360/ints.c b/arch/m68knommu/platform/68360/ints.c
index 6f22970d8c20..ad96ab1051f0 100644
--- a/arch/m68knommu/platform/68360/ints.c
+++ b/arch/m68knommu/platform/68360/ints.c
@@ -132,10 +132,8 @@ void init_IRQ(void)
132 pquicc->intr_cimr = 0x00000000; 132 pquicc->intr_cimr = 0x00000000;
133 133
134 for (i = 0; (i < NR_IRQS); i++) { 134 for (i = 0; (i < NR_IRQS); i++) {
135 irq_desc[i].status = IRQ_DISABLED; 135 set_irq_chip(irq, &intc_irq_chip);
136 irq_desc[i].action = NULL; 136 set_irq_handler(irq, handle_level_irq);
137 irq_desc[i].depth = 1;
138 irq_desc[i].chip = &intc_irq_chip;
139 } 137 }
140} 138}
141 139
diff --git a/arch/m68knommu/platform/68VZ328/config.c b/arch/m68knommu/platform/68VZ328/config.c
index fc5c63054e98..eabaabe8af36 100644
--- a/arch/m68knommu/platform/68VZ328/config.c
+++ b/arch/m68knommu/platform/68VZ328/config.c
@@ -90,11 +90,6 @@ static void init_hardware(char *command, int size)
90 PDIQEG &= ~PD(1); 90 PDIQEG &= ~PD(1);
91 PDIRQEN |= PD(1); /* IRQ enabled */ 91 PDIRQEN |= PD(1); /* IRQ enabled */
92 92
93#ifdef CONFIG_68328_SERIAL_UART2
94 /* Enable RXD TXD port bits to enable UART2 */
95 PJSEL &= ~(PJ(5) | PJ(4));
96#endif
97
98#ifdef CONFIG_INIT_LCD 93#ifdef CONFIG_INIT_LCD
99 /* initialize LCD controller */ 94 /* initialize LCD controller */
100 LSSA = (long) screen_bits; 95 LSSA = (long) screen_bits;
diff --git a/arch/m68knommu/platform/coldfire/Makefile b/arch/m68knommu/platform/coldfire/Makefile
index f72a0e5d9996..45f501fa4525 100644
--- a/arch/m68knommu/platform/coldfire/Makefile
+++ b/arch/m68knommu/platform/coldfire/Makefile
@@ -8,8 +8,8 @@
8# on the console port whenever a DBG interrupt occurs. You have to 8# on the console port whenever a DBG interrupt occurs. You have to
9# set up you HW breakpoints to trigger a DBG interrupt: 9# set up you HW breakpoints to trigger a DBG interrupt:
10# 10#
11# EXTRA_CFLAGS += -DTRAP_DBG_INTERRUPT 11# ccflags-y := -DTRAP_DBG_INTERRUPT
12# EXTRA_AFLAGS += -DTRAP_DBG_INTERRUPT 12# asflags-y := -DTRAP_DBG_INTERRUPT
13# 13#
14 14
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
@@ -26,6 +26,7 @@ obj-$(CONFIG_M528x) += pit.o intc-2.o
26obj-$(CONFIG_M5307) += timers.o intc.o 26obj-$(CONFIG_M5307) += timers.o intc.o
27obj-$(CONFIG_M532x) += timers.o intc-simr.o 27obj-$(CONFIG_M532x) += timers.o intc-simr.o
28obj-$(CONFIG_M5407) += timers.o intc.o 28obj-$(CONFIG_M5407) += timers.o intc.o
29obj-$(CONFIG_M548x) += sltimers.o intc-2.o
29 30
30obj-y += pinmux.o gpio.o 31obj-y += pinmux.o gpio.o
31extra-y := head.o 32extra-y := head.o
diff --git a/arch/m68knommu/platform/coldfire/entry.S b/arch/m68knommu/platform/coldfire/entry.S
index cd79d7e92ce6..5e92bed94b7e 100644
--- a/arch/m68knommu/platform/coldfire/entry.S
+++ b/arch/m68knommu/platform/coldfire/entry.S
@@ -88,7 +88,7 @@ ENTRY(system_call)
88 movel %d2,PT_OFF_D0(%sp) /* on syscall entry */ 88 movel %d2,PT_OFF_D0(%sp) /* on syscall entry */
89 subql #4,%sp 89 subql #4,%sp
90 SAVE_SWITCH_STACK 90 SAVE_SWITCH_STACK
91 jbsr syscall_trace 91 jbsr syscall_trace_enter
92 RESTORE_SWITCH_STACK 92 RESTORE_SWITCH_STACK
93 addql #4,%sp 93 addql #4,%sp
94 movel %d3,%a0 94 movel %d3,%a0
@@ -96,7 +96,7 @@ ENTRY(system_call)
96 movel %d0,%sp@(PT_OFF_D0) /* save the return value */ 96 movel %d0,%sp@(PT_OFF_D0) /* save the return value */
97 subql #4,%sp /* dummy return address */ 97 subql #4,%sp /* dummy return address */
98 SAVE_SWITCH_STACK 98 SAVE_SWITCH_STACK
99 jbsr syscall_trace 99 jbsr syscall_trace_leave
100 100
101ret_from_signal: 101ret_from_signal:
102 RESTORE_SWITCH_STACK 102 RESTORE_SWITCH_STACK
diff --git a/arch/m68knommu/platform/coldfire/intc-2.c b/arch/m68knommu/platform/coldfire/intc-2.c
index 5598c8b8661f..85daa2b3001a 100644
--- a/arch/m68knommu/platform/coldfire/intc-2.c
+++ b/arch/m68knommu/platform/coldfire/intc-2.c
@@ -1,5 +1,11 @@
1/* 1/*
2 * intc-1.c 2 * intc-2.c
3 *
4 * General interrupt controller code for the many ColdFire cores that use
5 * interrupt controllers with 63 interrupt sources, organized as 56 fully-
6 * programmable + 7 fixed-level interrupt sources. This includes the 523x
7 * family, the 5270, 5271, 5274, 5275, and the 528x family which have two such
8 * controllers, and the 547x and 548x families which have only one of them.
3 * 9 *
4 * (C) Copyright 2009, Greg Ungerer <gerg@snapgear.com> 10 * (C) Copyright 2009, Greg Ungerer <gerg@snapgear.com>
5 * 11 *
@@ -19,21 +25,37 @@
19#include <asm/traps.h> 25#include <asm/traps.h>
20 26
21/* 27/*
22 * Each vector needs a unique priority and level asscoiated with it. 28 * Bit definitions for the ICR family of registers.
29 */
30#define MCFSIM_ICR_LEVEL(l) ((l)<<3) /* Level l intr */
31#define MCFSIM_ICR_PRI(p) (p) /* Priority p intr */
32
33/*
34 * Each vector needs a unique priority and level associated with it.
23 * We don't really care so much what they are, we don't rely on the 35 * We don't really care so much what they are, we don't rely on the
24 * tranditional priority interrupt scheme of the m68k/ColdFire. 36 * traditional priority interrupt scheme of the m68k/ColdFire.
25 */ 37 */
26static u8 intc_intpri = 0x36; 38static u8 intc_intpri = MCFSIM_ICR_LEVEL(6) | MCFSIM_ICR_PRI(6);
39
40#ifdef MCFICM_INTC1
41#define NR_VECS 128
42#else
43#define NR_VECS 64
44#endif
27 45
28static void intc_irq_mask(unsigned int irq) 46static void intc_irq_mask(unsigned int irq)
29{ 47{
30 if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECBASE + 128)) { 48 if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECBASE + NR_VECS)) {
31 unsigned long imraddr; 49 unsigned long imraddr;
32 u32 val, imrbit; 50 u32 val, imrbit;
33 51
34 irq -= MCFINT_VECBASE; 52 irq -= MCFINT_VECBASE;
35 imraddr = MCF_IPSBAR; 53 imraddr = MCF_IPSBAR;
54#ifdef MCFICM_INTC1
36 imraddr += (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0; 55 imraddr += (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0;
56#else
57 imraddr += MCFICM_INTC0;
58#endif
37 imraddr += (irq & 0x20) ? MCFINTC_IMRH : MCFINTC_IMRL; 59 imraddr += (irq & 0x20) ? MCFINTC_IMRH : MCFINTC_IMRL;
38 imrbit = 0x1 << (irq & 0x1f); 60 imrbit = 0x1 << (irq & 0x1f);
39 61
@@ -44,13 +66,17 @@ static void intc_irq_mask(unsigned int irq)
44 66
45static void intc_irq_unmask(unsigned int irq) 67static void intc_irq_unmask(unsigned int irq)
46{ 68{
47 if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECBASE + 128)) { 69 if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECBASE + NR_VECS)) {
48 unsigned long intaddr, imraddr, icraddr; 70 unsigned long intaddr, imraddr, icraddr;
49 u32 val, imrbit; 71 u32 val, imrbit;
50 72
51 irq -= MCFINT_VECBASE; 73 irq -= MCFINT_VECBASE;
52 intaddr = MCF_IPSBAR; 74 intaddr = MCF_IPSBAR;
75#ifdef MCFICM_INTC1
53 intaddr += (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0; 76 intaddr += (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0;
77#else
78 intaddr += MCFICM_INTC0;
79#endif
54 imraddr = intaddr + ((irq & 0x20) ? MCFINTC_IMRH : MCFINTC_IMRL); 80 imraddr = intaddr + ((irq & 0x20) ? MCFINTC_IMRH : MCFINTC_IMRL);
55 icraddr = intaddr + MCFINTC_ICR0 + (irq & 0x3f); 81 icraddr = intaddr + MCFINTC_ICR0 + (irq & 0x3f);
56 imrbit = 0x1 << (irq & 0x1f); 82 imrbit = 0x1 << (irq & 0x1f);
@@ -67,10 +93,16 @@ static void intc_irq_unmask(unsigned int irq)
67 } 93 }
68} 94}
69 95
96static int intc_irq_set_type(unsigned int irq, unsigned int type)
97{
98 return 0;
99}
100
70static struct irq_chip intc_irq_chip = { 101static struct irq_chip intc_irq_chip = {
71 .name = "CF-INTC", 102 .name = "CF-INTC",
72 .mask = intc_irq_mask, 103 .mask = intc_irq_mask,
73 .unmask = intc_irq_unmask, 104 .unmask = intc_irq_unmask,
105 .set_type = intc_irq_set_type,
74}; 106};
75 107
76void __init init_IRQ(void) 108void __init init_IRQ(void)
@@ -81,13 +113,14 @@ void __init init_IRQ(void)
81 113
82 /* Mask all interrupt sources */ 114 /* Mask all interrupt sources */
83 __raw_writel(0x1, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRL); 115 __raw_writel(0x1, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRL);
116#ifdef MCFICM_INTC1
84 __raw_writel(0x1, MCF_IPSBAR + MCFICM_INTC1 + MCFINTC_IMRL); 117 __raw_writel(0x1, MCF_IPSBAR + MCFICM_INTC1 + MCFINTC_IMRL);
118#endif
85 119
86 for (irq = 0; (irq < NR_IRQS); irq++) { 120 for (irq = 0; (irq < NR_IRQS); irq++) {
87 irq_desc[irq].status = IRQ_DISABLED; 121 set_irq_chip(irq, &intc_irq_chip);
88 irq_desc[irq].action = NULL; 122 set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH);
89 irq_desc[irq].depth = 1; 123 set_irq_handler(irq, handle_level_irq);
90 irq_desc[irq].chip = &intc_irq_chip;
91 } 124 }
92} 125}
93 126
diff --git a/arch/m68knommu/platform/coldfire/intc-simr.c b/arch/m68knommu/platform/coldfire/intc-simr.c
index 1b01e79c2f63..bb7048636140 100644
--- a/arch/m68knommu/platform/coldfire/intc-simr.c
+++ b/arch/m68knommu/platform/coldfire/intc-simr.c
@@ -1,6 +1,8 @@
1/* 1/*
2 * intc-simr.c 2 * intc-simr.c
3 * 3 *
4 * Interrupt controller code for the ColdFire 5208, 5207 & 532x parts.
5 *
4 * (C) Copyright 2009, Greg Ungerer <gerg@snapgear.com> 6 * (C) Copyright 2009, Greg Ungerer <gerg@snapgear.com>
5 * 7 *
6 * This file is subject to the terms and conditions of the GNU General Public 8 * This file is subject to the terms and conditions of the GNU General Public
@@ -68,11 +70,9 @@ void __init init_IRQ(void)
68 __raw_writeb(0xff, MCFINTC1_SIMR); 70 __raw_writeb(0xff, MCFINTC1_SIMR);
69 71
70 for (irq = 0; (irq < NR_IRQS); irq++) { 72 for (irq = 0; (irq < NR_IRQS); irq++) {
71 irq_desc[irq].status = IRQ_DISABLED; 73 set_irq_chip(irq, &intc_irq_chip);
72 irq_desc[irq].action = NULL; 74 set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH);
73 irq_desc[irq].depth = 1; 75 set_irq_handler(irq, handle_level_irq);
74 irq_desc[irq].chip = &intc_irq_chip;
75 intc_irq_set_type(irq, 0);
76 } 76 }
77} 77}
78 78
diff --git a/arch/m68knommu/platform/coldfire/intc.c b/arch/m68knommu/platform/coldfire/intc.c
index a4560c86db71..60d2fcbe182b 100644
--- a/arch/m68knommu/platform/coldfire/intc.c
+++ b/arch/m68knommu/platform/coldfire/intc.c
@@ -143,11 +143,9 @@ void __init init_IRQ(void)
143 mcf_maskimr(0xffffffff); 143 mcf_maskimr(0xffffffff);
144 144
145 for (irq = 0; (irq < NR_IRQS); irq++) { 145 for (irq = 0; (irq < NR_IRQS); irq++) {
146 irq_desc[irq].status = IRQ_DISABLED; 146 set_irq_chip(irq, &intc_irq_chip);
147 irq_desc[irq].action = NULL; 147 set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH);
148 irq_desc[irq].depth = 1; 148 set_irq_handler(irq, handle_level_irq);
149 irq_desc[irq].chip = &intc_irq_chip;
150 intc_irq_set_type(irq, 0);
151 } 149 }
152} 150}
153 151
diff --git a/arch/m68knommu/platform/coldfire/sltimers.c b/arch/m68knommu/platform/coldfire/sltimers.c
new file mode 100644
index 000000000000..0a1b937c3e18
--- /dev/null
+++ b/arch/m68knommu/platform/coldfire/sltimers.c
@@ -0,0 +1,145 @@
1/***************************************************************************/
2
3/*
4 * sltimers.c -- generic ColdFire slice timer support.
5 *
6 * Copyright (C) 2009-2010, Philippe De Muyter <phdm@macqel.be>
7 * based on
8 * timers.c -- generic ColdFire hardware timer support.
9 * Copyright (C) 1999-2008, Greg Ungerer <gerg@snapgear.com>
10 */
11
12/***************************************************************************/
13
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/sched.h>
17#include <linux/interrupt.h>
18#include <linux/irq.h>
19#include <linux/profile.h>
20#include <linux/clocksource.h>
21#include <asm/io.h>
22#include <asm/traps.h>
23#include <asm/machdep.h>
24#include <asm/coldfire.h>
25#include <asm/mcfslt.h>
26#include <asm/mcfsim.h>
27
28/***************************************************************************/
29
30#ifdef CONFIG_HIGHPROFILE
31
32/*
33 * By default use Slice Timer 1 as the profiler clock timer.
34 */
35#define PA(a) (MCF_MBAR + MCFSLT_TIMER1 + (a))
36
37/*
38 * Choose a reasonably fast profile timer. Make it an odd value to
39 * try and get good coverage of kernel operations.
40 */
41#define PROFILEHZ 1013
42
43irqreturn_t mcfslt_profile_tick(int irq, void *dummy)
44{
45 /* Reset Slice Timer 1 */
46 __raw_writel(MCFSLT_SSR_BE | MCFSLT_SSR_TE, PA(MCFSLT_SSR));
47 if (current->pid)
48 profile_tick(CPU_PROFILING);
49 return IRQ_HANDLED;
50}
51
52static struct irqaction mcfslt_profile_irq = {
53 .name = "profile timer",
54 .flags = IRQF_DISABLED | IRQF_TIMER,
55 .handler = mcfslt_profile_tick,
56};
57
58void mcfslt_profile_init(void)
59{
60 printk(KERN_INFO "PROFILE: lodging TIMER 1 @ %dHz as profile timer\n",
61 PROFILEHZ);
62
63 setup_irq(MCF_IRQ_PROFILER, &mcfslt_profile_irq);
64
65 /* Set up TIMER 2 as high speed profile clock */
66 __raw_writel(MCF_BUSCLK / PROFILEHZ - 1, PA(MCFSLT_STCNT));
67 __raw_writel(MCFSLT_SCR_RUN | MCFSLT_SCR_IEN | MCFSLT_SCR_TEN,
68 PA(MCFSLT_SCR));
69
70}
71
72#endif /* CONFIG_HIGHPROFILE */
73
74/***************************************************************************/
75
76/*
77 * By default use Slice Timer 0 as the system clock timer.
78 */
79#define TA(a) (MCF_MBAR + MCFSLT_TIMER0 + (a))
80
81static u32 mcfslt_cycles_per_jiffy;
82static u32 mcfslt_cnt;
83
84static irqreturn_t mcfslt_tick(int irq, void *dummy)
85{
86 /* Reset Slice Timer 0 */
87 __raw_writel(MCFSLT_SSR_BE | MCFSLT_SSR_TE, TA(MCFSLT_SSR));
88 mcfslt_cnt += mcfslt_cycles_per_jiffy;
89 return arch_timer_interrupt(irq, dummy);
90}
91
92static struct irqaction mcfslt_timer_irq = {
93 .name = "timer",
94 .flags = IRQF_DISABLED | IRQF_TIMER,
95 .handler = mcfslt_tick,
96};
97
98static cycle_t mcfslt_read_clk(struct clocksource *cs)
99{
100 unsigned long flags;
101 u32 cycles;
102 u16 scnt;
103
104 local_irq_save(flags);
105 scnt = __raw_readl(TA(MCFSLT_SCNT));
106 cycles = mcfslt_cnt;
107 local_irq_restore(flags);
108
109 /* substract because slice timers count down */
110 return cycles - scnt;
111}
112
113static struct clocksource mcfslt_clk = {
114 .name = "slt",
115 .rating = 250,
116 .read = mcfslt_read_clk,
117 .shift = 20,
118 .mask = CLOCKSOURCE_MASK(32),
119 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
120};
121
122void hw_timer_init(void)
123{
124 mcfslt_cycles_per_jiffy = MCF_BUSCLK / HZ;
125 /*
126 * The coldfire slice timer (SLT) runs from STCNT to 0 included,
127 * then STCNT again and so on. It counts thus actually
128 * STCNT + 1 steps for 1 tick, not STCNT. So if you want
129 * n cycles, initialize STCNT with n - 1.
130 */
131 __raw_writel(mcfslt_cycles_per_jiffy - 1, TA(MCFSLT_STCNT));
132 __raw_writel(MCFSLT_SCR_RUN | MCFSLT_SCR_IEN | MCFSLT_SCR_TEN,
133 TA(MCFSLT_SCR));
134 /* initialize mcfslt_cnt knowing that slice timers count down */
135 mcfslt_cnt = mcfslt_cycles_per_jiffy;
136
137 setup_irq(MCF_IRQ_TIMER, &mcfslt_timer_irq);
138
139 mcfslt_clk.mult = clocksource_hz2mult(MCF_BUSCLK, mcfslt_clk.shift);
140 clocksource_register(&mcfslt_clk);
141
142#ifdef CONFIG_HIGHPROFILE
143 mcfslt_profile_init();
144#endif
145}
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-22 21:21:17 -0500