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-rw-r--r--arch/m68knommu/include/asm/m5206sim.h131
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diff --git a/arch/m68knommu/include/asm/m5206sim.h b/arch/m68knommu/include/asm/m5206sim.h
deleted file mode 100644
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--- a/arch/m68knommu/include/asm/m5206sim.h
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@@ -1,131 +0,0 @@
1/****************************************************************************/
2
3/*
4 * m5206sim.h -- ColdFire 5206 System Integration Module support.
5 *
6 * (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com)
7 * (C) Copyright 2000, Lineo Inc. (www.lineo.com)
8 */
9
10/****************************************************************************/
11#ifndef m5206sim_h
12#define m5206sim_h
13/****************************************************************************/
14
15
16/*
17 * Define the 5206 SIM register set addresses.
18 */
19#define MCFSIM_SIMR 0x03 /* SIM Config reg (r/w) */
20#define MCFSIM_ICR1 0x14 /* Intr Ctrl reg 1 (r/w) */
21#define MCFSIM_ICR2 0x15 /* Intr Ctrl reg 2 (r/w) */
22#define MCFSIM_ICR3 0x16 /* Intr Ctrl reg 3 (r/w) */
23#define MCFSIM_ICR4 0x17 /* Intr Ctrl reg 4 (r/w) */
24#define MCFSIM_ICR5 0x18 /* Intr Ctrl reg 5 (r/w) */
25#define MCFSIM_ICR6 0x19 /* Intr Ctrl reg 6 (r/w) */
26#define MCFSIM_ICR7 0x1a /* Intr Ctrl reg 7 (r/w) */
27#define MCFSIM_ICR8 0x1b /* Intr Ctrl reg 8 (r/w) */
28#define MCFSIM_ICR9 0x1c /* Intr Ctrl reg 9 (r/w) */
29#define MCFSIM_ICR10 0x1d /* Intr Ctrl reg 10 (r/w) */
30#define MCFSIM_ICR11 0x1e /* Intr Ctrl reg 11 (r/w) */
31#define MCFSIM_ICR12 0x1f /* Intr Ctrl reg 12 (r/w) */
32#define MCFSIM_ICR13 0x20 /* Intr Ctrl reg 13 (r/w) */
33#ifdef CONFIG_M5206e
34#define MCFSIM_ICR14 0x21 /* Intr Ctrl reg 14 (r/w) */
35#define MCFSIM_ICR15 0x22 /* Intr Ctrl reg 15 (r/w) */
36#endif
37
38#define MCFSIM_IMR 0x36 /* Interrupt Mask reg (r/w) */
39#define MCFSIM_IPR 0x3a /* Interrupt Pend reg (r/w) */
40
41#define MCFSIM_RSR 0x40 /* Reset Status reg (r/w) */
42#define MCFSIM_SYPCR 0x41 /* System Protection reg (r/w)*/
43
44#define MCFSIM_SWIVR 0x42 /* SW Watchdog intr reg (r/w) */
45#define MCFSIM_SWSR 0x43 /* SW Watchdog service (r/w) */
46
47#define MCFSIM_DCRR 0x46 /* DRAM Refresh reg (r/w) */
48#define MCFSIM_DCTR 0x4a /* DRAM Timing reg (r/w) */
49#define MCFSIM_DAR0 0x4c /* DRAM 0 Address reg(r/w) */
50#define MCFSIM_DMR0 0x50 /* DRAM 0 Mask reg (r/w) */
51#define MCFSIM_DCR0 0x57 /* DRAM 0 Control reg (r/w) */
52#define MCFSIM_DAR1 0x58 /* DRAM 1 Address reg (r/w) */
53#define MCFSIM_DMR1 0x5c /* DRAM 1 Mask reg (r/w) */
54#define MCFSIM_DCR1 0x63 /* DRAM 1 Control reg (r/w) */
55
56#define MCFSIM_CSAR0 0x64 /* CS 0 Address 0 reg (r/w) */
57#define MCFSIM_CSMR0 0x68 /* CS 0 Mask 0 reg (r/w) */
58#define MCFSIM_CSCR0 0x6e /* CS 0 Control reg (r/w) */
59#define MCFSIM_CSAR1 0x70 /* CS 1 Address reg (r/w) */
60#define MCFSIM_CSMR1 0x74 /* CS 1 Mask reg (r/w) */
61#define MCFSIM_CSCR1 0x7a /* CS 1 Control reg (r/w) */
62#define MCFSIM_CSAR2 0x7c /* CS 2 Address reg (r/w) */
63#define MCFSIM_CSMR2 0x80 /* CS 2 Mask reg (r/w) */
64#define MCFSIM_CSCR2 0x86 /* CS 2 Control reg (r/w) */
65#define MCFSIM_CSAR3 0x88 /* CS 3 Address reg (r/w) */
66#define MCFSIM_CSMR3 0x8c /* CS 3 Mask reg (r/w) */
67#define MCFSIM_CSCR3 0x92 /* CS 3 Control reg (r/w) */
68#define MCFSIM_CSAR4 0x94 /* CS 4 Address reg (r/w) */
69#define MCFSIM_CSMR4 0x98 /* CS 4 Mask reg (r/w) */
70#define MCFSIM_CSCR4 0x9e /* CS 4 Control reg (r/w) */
71#define MCFSIM_CSAR5 0xa0 /* CS 5 Address reg (r/w) */
72#define MCFSIM_CSMR5 0xa4 /* CS 5 Mask reg (r/w) */
73#define MCFSIM_CSCR5 0xaa /* CS 5 Control reg (r/w) */
74#define MCFSIM_CSAR6 0xac /* CS 6 Address reg (r/w) */
75#define MCFSIM_CSMR6 0xb0 /* CS 6 Mask reg (r/w) */
76#define MCFSIM_CSCR6 0xb6 /* CS 6 Control reg (r/w) */
77#define MCFSIM_CSAR7 0xb8 /* CS 7 Address reg (r/w) */
78#define MCFSIM_CSMR7 0xbc /* CS 7 Mask reg (r/w) */
79#define MCFSIM_CSCR7 0xc2 /* CS 7 Control reg (r/w) */
80#define MCFSIM_DMCR 0xc6 /* Default control */
81
82#ifdef CONFIG_M5206e
83#define MCFSIM_PAR 0xca /* Pin Assignment reg (r/w) */
84#else
85#define MCFSIM_PAR 0xcb /* Pin Assignment reg (r/w) */
86#endif
87
88#define MCFSIM_PADDR 0x1c5 /* Parallel Direction (r/w) */
89#define MCFSIM_PADAT 0x1c9 /* Parallel Port Value (r/w) */
90
91/*
92 * Some symbol defines for the Parallel Port Pin Assignment Register
93 */
94#ifdef CONFIG_M5206e
95#define MCFSIM_PAR_DREQ0 0x100 /* Set to select DREQ0 input */
96 /* Clear to select T0 input */
97#define MCFSIM_PAR_DREQ1 0x200 /* Select DREQ1 input */
98 /* Clear to select T0 output */
99#endif
100
101/*
102 * Some symbol defines for the Interrupt Control Register
103 */
104#define MCFSIM_SWDICR MCFSIM_ICR8 /* Watchdog timer ICR */
105#define MCFSIM_TIMER1ICR MCFSIM_ICR9 /* Timer 1 ICR */
106#define MCFSIM_TIMER2ICR MCFSIM_ICR10 /* Timer 2 ICR */
107#define MCFSIM_UART1ICR MCFSIM_ICR12 /* UART 1 ICR */
108#define MCFSIM_UART2ICR MCFSIM_ICR13 /* UART 2 ICR */
109#ifdef CONFIG_M5206e
110#define MCFSIM_DMA1ICR MCFSIM_ICR14 /* DMA 1 ICR */
111#define MCFSIM_DMA2ICR MCFSIM_ICR15 /* DMA 2 ICR */
112#endif
113
114#if defined(CONFIG_M5206e)
115#define MCFSIM_IMR_MASKALL 0xfffe /* All SIM intr sources */
116#endif
117
118/*
119 * Macro to get and set IMR register. It is 16 bits on the 5206.
120 */
121#define mcf_getimr() \
122 *((volatile unsigned short *) (MCF_MBAR + MCFSIM_IMR))
123
124#define mcf_setimr(imr) \
125 *((volatile unsigned short *) (MCF_MBAR + MCFSIM_IMR)) = (imr)
126
127#define mcf_getipr() \
128 *((volatile unsigned short *) (MCF_MBAR + MCFSIM_IPR))
129
130/****************************************************************************/
131#endif /* m5206sim_h */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-05 05:28:42 -0500