aboutsummaryrefslogtreecommitdiffstats
path: root/arch/m68k
diff options
context:
space:
mode:
Diffstat (limited to 'arch/m68k')
-rw-r--r--arch/m68k/Kconfig7
-rw-r--r--arch/m68k/emu/nfcon.c1
-rw-r--r--arch/m68k/include/asm/m5206sim.h10
-rw-r--r--arch/m68k/include/asm/m520xsim.h33
-rw-r--r--arch/m68k/include/asm/m523xsim.h42
-rw-r--r--arch/m68k/include/asm/m5249sim.h18
-rw-r--r--arch/m68k/include/asm/m5272sim.h17
-rw-r--r--arch/m68k/include/asm/m527xsim.h53
-rw-r--r--arch/m68k/include/asm/m528xsim.h40
-rw-r--r--arch/m68k/include/asm/m5307sim.h10
-rw-r--r--arch/m68k/include/asm/m532xsim.h35
-rw-r--r--arch/m68k/include/asm/m5407sim.h6
-rw-r--r--arch/m68k/include/asm/m54xxsim.h16
-rw-r--r--arch/m68k/include/asm/machdep.h5
-rw-r--r--arch/m68k/include/asm/mcfqspi.h11
-rw-r--r--arch/m68k/include/asm/mcfuart.h5
-rw-r--r--arch/m68k/include/asm/socket.h4
-rw-r--r--arch/m68k/include/asm/system.h1
-rw-r--r--arch/m68k/kernel/process.c377
-rw-r--r--arch/m68k/kernel/process_mm.c369
-rw-r--r--arch/m68k/kernel/process_no.c406
-rw-r--r--arch/m68k/kernel/ptrace.c306
-rw-r--r--arch/m68k/kernel/ptrace_mm.c295
-rw-r--r--arch/m68k/kernel/ptrace_no.c255
-rw-r--r--arch/m68k/kernel/setup_no.c3
-rw-r--r--arch/m68k/kernel/time.c116
-rw-r--r--arch/m68k/kernel/time_mm.c114
-rw-r--r--arch/m68k/kernel/time_no.c90
-rw-r--r--arch/m68k/kernel/vmlinux-nommu.lds200
-rw-r--r--arch/m68k/platform/5206/config.c91
-rw-r--r--arch/m68k/platform/520x/config.c256
-rw-r--r--arch/m68k/platform/523x/config.c235
-rw-r--r--arch/m68k/platform/5249/config.c244
-rw-r--r--arch/m68k/platform/5272/config.c84
-rw-r--r--arch/m68k/platform/527x/config.c296
-rw-r--r--arch/m68k/platform/528x/config.c230
-rw-r--r--arch/m68k/platform/5307/config.c91
-rw-r--r--arch/m68k/platform/532x/config.c221
-rw-r--r--arch/m68k/platform/5407/config.c91
-rw-r--r--arch/m68k/platform/54xx/config.c77
-rw-r--r--arch/m68k/platform/68328/config.c5
-rw-r--r--arch/m68k/platform/68328/ints.c2
-rw-r--r--arch/m68k/platform/68328/timers.c18
-rw-r--r--arch/m68k/platform/68360/config.c8
-rw-r--r--arch/m68k/platform/68360/ints.c2
-rw-r--r--arch/m68k/platform/68EZ328/config.c5
-rw-r--r--arch/m68k/platform/68VZ328/config.c5
-rw-r--r--arch/m68k/platform/coldfire/Makefile22
-rw-r--r--arch/m68k/platform/coldfire/device.c318
-rw-r--r--arch/m68k/platform/coldfire/head.S4
-rw-r--r--arch/m68k/platform/coldfire/pit.c2
-rw-r--r--arch/m68k/platform/coldfire/reset.c50
-rw-r--r--arch/m68k/platform/coldfire/sltimers.c7
-rw-r--r--arch/m68k/platform/coldfire/timers.c27
-rw-r--r--arch/m68k/platform/coldfire/vectors.c2
-rw-r--r--arch/m68k/q40/config.c13
56 files changed, 1609 insertions, 3642 deletions
diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig
index ae413d4a8bb7..d318c606c888 100644
--- a/arch/m68k/Kconfig
+++ b/arch/m68k/Kconfig
@@ -7,6 +7,7 @@ config M68K
7 select GENERIC_IRQ_SHOW 7 select GENERIC_IRQ_SHOW
8 select ARCH_HAVE_NMI_SAFE_CMPXCHG if RMW_INSNS 8 select ARCH_HAVE_NMI_SAFE_CMPXCHG if RMW_INSNS
9 select GENERIC_CPU_DEVICES 9 select GENERIC_CPU_DEVICES
10 select FPU if MMU
10 11
11config RWSEM_GENERIC_SPINLOCK 12config RWSEM_GENERIC_SPINLOCK
12 bool 13 bool
@@ -24,9 +25,6 @@ config ARCH_HAS_ILOG2_U64
24config GENERIC_CLOCKEVENTS 25config GENERIC_CLOCKEVENTS
25 bool 26 bool
26 27
27config GENERIC_CMOS_UPDATE
28 def_bool !MMU
29
30config GENERIC_GPIO 28config GENERIC_GPIO
31 bool 29 bool
32 30
@@ -67,6 +65,9 @@ config CPU_HAS_NO_MULDIV64
67config CPU_HAS_ADDRESS_SPACES 65config CPU_HAS_ADDRESS_SPACES
68 bool 66 bool
69 67
68config FPU
69 bool
70
70config HZ 71config HZ
71 int 72 int
72 default 1000 if CLEOPATRA 73 default 1000 if CLEOPATRA
diff --git a/arch/m68k/emu/nfcon.c b/arch/m68k/emu/nfcon.c
index ab20dc0ff63b..8db25e806947 100644
--- a/arch/m68k/emu/nfcon.c
+++ b/arch/m68k/emu/nfcon.c
@@ -127,7 +127,6 @@ static int __init nfcon_init(void)
127 if (!nfcon_tty_driver) 127 if (!nfcon_tty_driver)
128 return -ENOMEM; 128 return -ENOMEM;
129 129
130 nfcon_tty_driver->owner = THIS_MODULE;
131 nfcon_tty_driver->driver_name = "nfcon"; 130 nfcon_tty_driver->driver_name = "nfcon";
132 nfcon_tty_driver->name = "nfcon"; 131 nfcon_tty_driver->name = "nfcon";
133 nfcon_tty_driver->type = TTY_DRIVER_TYPE_SYSTEM; 132 nfcon_tty_driver->type = TTY_DRIVER_TYPE_SYSTEM;
diff --git a/arch/m68k/include/asm/m5206sim.h b/arch/m68k/include/asm/m5206sim.h
index 9015eadd5c00..69722366b084 100644
--- a/arch/m68k/include/asm/m5206sim.h
+++ b/arch/m68k/include/asm/m5206sim.h
@@ -100,11 +100,11 @@
100#define MCFDMA_BASE1 (MCF_MBAR + 0x240) /* Base address DMA 1 */ 100#define MCFDMA_BASE1 (MCF_MBAR + 0x240) /* Base address DMA 1 */
101 101
102#if defined(CONFIG_NETtel) 102#if defined(CONFIG_NETtel)
103#define MCFUART_BASE1 0x180 /* Base address of UART1 */ 103#define MCFUART_BASE0 (MCF_MBAR + 0x180) /* Base address UART0 */
104#define MCFUART_BASE2 0x140 /* Base address of UART2 */ 104#define MCFUART_BASE1 (MCF_MBAR + 0x140) /* Base address UART1 */
105#else 105#else
106#define MCFUART_BASE1 0x140 /* Base address of UART1 */ 106#define MCFUART_BASE0 (MCF_MBAR + 0x140) /* Base address UART0 */
107#define MCFUART_BASE2 0x180 /* Base address of UART2 */ 107#define MCFUART_BASE1 (MCF_MBAR + 0x180) /* Base address UART1 */
108#endif 108#endif
109 109
110/* 110/*
@@ -112,6 +112,8 @@
112 */ 112 */
113#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */ 113#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */
114#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */ 114#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */
115#define MCF_IRQ_UART0 73 /* UART0 */
116#define MCF_IRQ_UART1 74 /* UART1 */
115 117
116/* 118/*
117 * Generic GPIO 119 * Generic GPIO
diff --git a/arch/m68k/include/asm/m520xsim.h b/arch/m68k/include/asm/m520xsim.h
index eda62de7e607..17f2aab9cf97 100644
--- a/arch/m68k/include/asm/m520xsim.h
+++ b/arch/m68k/include/asm/m520xsim.h
@@ -48,8 +48,21 @@
48#define MCFINT_UART1 27 /* Interrupt number for UART1 */ 48#define MCFINT_UART1 27 /* Interrupt number for UART1 */
49#define MCFINT_UART2 28 /* Interrupt number for UART2 */ 49#define MCFINT_UART2 28 /* Interrupt number for UART2 */
50#define MCFINT_QSPI 31 /* Interrupt number for QSPI */ 50#define MCFINT_QSPI 31 /* Interrupt number for QSPI */
51#define MCFINT_FECRX0 36 /* Interrupt number for FEC RX */
52#define MCFINT_FECTX0 40 /* Interrupt number for FEC RX */
53#define MCFINT_FECENTC0 42 /* Interrupt number for FEC RX */
51#define MCFINT_PIT1 4 /* Interrupt number for PIT1 (PIT0 in processor) */ 54#define MCFINT_PIT1 4 /* Interrupt number for PIT1 (PIT0 in processor) */
52 55
56#define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0)
57#define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1)
58#define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2)
59
60#define MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0)
61#define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0)
62#define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0)
63
64#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
65
53/* 66/*
54 * SDRAM configuration registers. 67 * SDRAM configuration registers.
55 */ 68 */
@@ -144,15 +157,25 @@
144/* 157/*
145 * UART module. 158 * UART module.
146 */ 159 */
147#define MCFUART_BASE1 0xFC060000 /* Base address of UART1 */ 160#define MCFUART_BASE0 0xFC060000 /* Base address of UART0 */
148#define MCFUART_BASE2 0xFC064000 /* Base address of UART2 */ 161#define MCFUART_BASE1 0xFC064000 /* Base address of UART1 */
149#define MCFUART_BASE3 0xFC068000 /* Base address of UART2 */ 162#define MCFUART_BASE2 0xFC068000 /* Base address of UART2 */
150 163
151/* 164/*
152 * FEC module. 165 * FEC module.
153 */ 166 */
154#define MCFFEC_BASE 0xFC030000 /* Base of FEC ethernet */ 167#define MCFFEC_BASE0 0xFC030000 /* Base of FEC ethernet */
155#define MCFFEC_SIZE 0x800 /* Register set size */ 168#define MCFFEC_SIZE0 0x800 /* Register set size */
169
170/*
171 * QSPI module.
172 */
173#define MCFQSPI_BASE 0xFC05C000 /* Base of QSPI module */
174#define MCFQSPI_SIZE 0x40 /* Register set size */
175
176#define MCFQSPI_CS0 46
177#define MCFQSPI_CS1 47
178#define MCFQSPI_CS2 27
156 179
157/* 180/*
158 * Reset Control Unit. 181 * Reset Control Unit.
diff --git a/arch/m68k/include/asm/m523xsim.h b/arch/m68k/include/asm/m523xsim.h
index 6235921eca4e..075062d4eecd 100644
--- a/arch/m68k/include/asm/m523xsim.h
+++ b/arch/m68k/include/asm/m523xsim.h
@@ -35,8 +35,23 @@
35 35
36#define MCFINT_VECBASE 64 /* Vector base number */ 36#define MCFINT_VECBASE 64 /* Vector base number */
37#define MCFINT_UART0 13 /* Interrupt number for UART0 */ 37#define MCFINT_UART0 13 /* Interrupt number for UART0 */
38#define MCFINT_PIT1 36 /* Interrupt number for PIT1 */ 38#define MCFINT_UART1 14 /* Interrupt number for UART1 */
39#define MCFINT_UART2 15 /* Interrupt number for UART2 */
39#define MCFINT_QSPI 18 /* Interrupt number for QSPI */ 40#define MCFINT_QSPI 18 /* Interrupt number for QSPI */
41#define MCFINT_FECRX0 23 /* Interrupt number for FEC */
42#define MCFINT_FECTX0 27 /* Interrupt number for FEC */
43#define MCFINT_FECENTC0 29 /* Interrupt number for FEC */
44#define MCFINT_PIT1 36 /* Interrupt number for PIT1 */
45
46#define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0)
47#define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1)
48#define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2)
49
50#define MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0)
51#define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0)
52#define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0)
53
54#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
40 55
41/* 56/*
42 * SDRAM configuration registers. 57 * SDRAM configuration registers.
@@ -50,8 +65,8 @@
50/* 65/*
51 * Reset Control Unit (relative to IPSBAR). 66 * Reset Control Unit (relative to IPSBAR).
52 */ 67 */
53#define MCF_RCR 0x110000 68#define MCF_RCR (MCF_IPSBAR + 0x110000)
54#define MCF_RSR 0x110001 69#define MCF_RSR (MCF_IPSBAR + 0x110001)
55 70
56#define MCF_RCR_SWRESET 0x80 /* Software reset bit */ 71#define MCF_RCR_SWRESET 0x80 /* Software reset bit */
57#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */ 72#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */
@@ -59,15 +74,26 @@
59/* 74/*
60 * UART module. 75 * UART module.
61 */ 76 */
62#define MCFUART_BASE1 (MCF_IPSBAR + 0x200) 77#define MCFUART_BASE0 (MCF_IPSBAR + 0x200)
63#define MCFUART_BASE2 (MCF_IPSBAR + 0x240) 78#define MCFUART_BASE1 (MCF_IPSBAR + 0x240)
64#define MCFUART_BASE3 (MCF_IPSBAR + 0x280) 79#define MCFUART_BASE2 (MCF_IPSBAR + 0x280)
65 80
66/* 81/*
67 * FEC ethernet module. 82 * FEC ethernet module.
68 */ 83 */
69#define MCFFEC_BASE (MCF_IPSBAR + 0x1000) 84#define MCFFEC_BASE0 (MCF_IPSBAR + 0x1000)
70#define MCFFEC_SIZE 0x800 85#define MCFFEC_SIZE0 0x800
86
87/*
88 * QSPI module.
89 */
90#define MCFQSPI_BASE (MCF_IPSBAR + 0x340)
91#define MCFQSPI_SIZE 0x40
92
93#define MCFQSPI_CS0 91
94#define MCFQSPI_CS1 92
95#define MCFQSPI_CS2 103
96#define MCFQSPI_CS3 99
71 97
72/* 98/*
73 * GPIO module. 99 * GPIO module.
diff --git a/arch/m68k/include/asm/m5249sim.h b/arch/m68k/include/asm/m5249sim.h
index 805714ca8d7d..7f0c2c3660fd 100644
--- a/arch/m68k/include/asm/m5249sim.h
+++ b/arch/m68k/include/asm/m5249sim.h
@@ -76,8 +76,19 @@
76/* 76/*
77 * UART module. 77 * UART module.
78 */ 78 */
79#define MCFUART_BASE1 0x1c0 /* Base address of UART1 */ 79#define MCFUART_BASE0 (MCF_MBAR + 0x1c0) /* Base address UART0 */
80#define MCFUART_BASE2 0x200 /* Base address of UART2 */ 80#define MCFUART_BASE1 (MCF_MBAR + 0x200) /* Base address UART1 */
81
82/*
83 * QSPI module.
84 */
85#define MCFQSPI_BASE (MCF_MBAR + 0x300) /* Base address QSPI */
86#define MCFQSPI_SIZE 0x40 /* Register set size */
87
88#define MCFQSPI_CS0 29
89#define MCFQSPI_CS1 24
90#define MCFQSPI_CS2 21
91#define MCFQSPI_CS3 22
81 92
82/* 93/*
83 * DMA unit base addresses. 94 * DMA unit base addresses.
@@ -108,6 +119,9 @@
108#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */ 119#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */
109#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */ 120#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */
110 121
122#define MCF_IRQ_UART0 73 /* UART0 */
123#define MCF_IRQ_UART1 74 /* UART1 */
124
111/* 125/*
112 * General purpose IO registers (in MBAR2). 126 * General purpose IO registers (in MBAR2).
113 */ 127 */
diff --git a/arch/m68k/include/asm/m5272sim.h b/arch/m68k/include/asm/m5272sim.h
index 759c2b07a994..a58f1760d858 100644
--- a/arch/m68k/include/asm/m5272sim.h
+++ b/arch/m68k/include/asm/m5272sim.h
@@ -68,8 +68,8 @@
68#define MCFSIM_DCMR1 0x5c /* DRAM 1 Mask reg (r/w) */ 68#define MCFSIM_DCMR1 0x5c /* DRAM 1 Mask reg (r/w) */
69#define MCFSIM_DCCR1 0x63 /* DRAM 1 Control reg (r/w) */ 69#define MCFSIM_DCCR1 0x63 /* DRAM 1 Control reg (r/w) */
70 70
71#define MCFUART_BASE1 0x100 /* Base address of UART1 */ 71#define MCFUART_BASE0 (MCF_MBAR + 0x100) /* Base address UART0 */
72#define MCFUART_BASE2 0x140 /* Base address of UART2 */ 72#define MCFUART_BASE1 (MCF_MBAR + 0x140) /* Base address UART1 */
73 73
74#define MCFSIM_PACNT (MCF_MBAR + 0x80) /* Port A Control (r/w) */ 74#define MCFSIM_PACNT (MCF_MBAR + 0x80) /* Port A Control (r/w) */
75#define MCFSIM_PADDR (MCF_MBAR + 0x84) /* Port A Direction (r/w) */ 75#define MCFSIM_PADDR (MCF_MBAR + 0x84) /* Port A Direction (r/w) */
@@ -88,6 +88,9 @@
88#define MCFTIMER_BASE3 (MCF_MBAR + 0x240) /* Base address TIMER4 */ 88#define MCFTIMER_BASE3 (MCF_MBAR + 0x240) /* Base address TIMER4 */
89#define MCFTIMER_BASE4 (MCF_MBAR + 0x260) /* Base address TIMER3 */ 89#define MCFTIMER_BASE4 (MCF_MBAR + 0x260) /* Base address TIMER3 */
90 90
91#define MCFFEC_BASE0 (MCF_MBAR + 0x840) /* Base FEC ethernet */
92#define MCFFEC_SIZE0 0x1d0
93
91/* 94/*
92 * Define system peripheral IRQ usage. 95 * Define system peripheral IRQ usage.
93 */ 96 */
@@ -101,8 +104,8 @@
101#define MCF_IRQ_TIMER2 70 /* Timer 2 */ 104#define MCF_IRQ_TIMER2 70 /* Timer 2 */
102#define MCF_IRQ_TIMER3 71 /* Timer 3 */ 105#define MCF_IRQ_TIMER3 71 /* Timer 3 */
103#define MCF_IRQ_TIMER4 72 /* Timer 4 */ 106#define MCF_IRQ_TIMER4 72 /* Timer 4 */
104#define MCF_IRQ_UART1 73 /* UART 1 */ 107#define MCF_IRQ_UART0 73 /* UART 0 */
105#define MCF_IRQ_UART2 74 /* UART 2 */ 108#define MCF_IRQ_UART1 74 /* UART 1 */
106#define MCF_IRQ_PLIP 75 /* PLIC 2Khz Periodic */ 109#define MCF_IRQ_PLIP 75 /* PLIC 2Khz Periodic */
107#define MCF_IRQ_PLIA 76 /* PLIC Asynchronous */ 110#define MCF_IRQ_PLIA 76 /* PLIC Asynchronous */
108#define MCF_IRQ_USB0 77 /* USB Endpoint 0 */ 111#define MCF_IRQ_USB0 77 /* USB Endpoint 0 */
@@ -114,9 +117,9 @@
114#define MCF_IRQ_USB6 83 /* USB Endpoint 6 */ 117#define MCF_IRQ_USB6 83 /* USB Endpoint 6 */
115#define MCF_IRQ_USB7 84 /* USB Endpoint 7 */ 118#define MCF_IRQ_USB7 84 /* USB Endpoint 7 */
116#define MCF_IRQ_DMA 85 /* DMA Controller */ 119#define MCF_IRQ_DMA 85 /* DMA Controller */
117#define MCF_IRQ_ERX 86 /* Ethernet Receiver */ 120#define MCF_IRQ_FECRX0 86 /* Ethernet Receiver */
118#define MCF_IRQ_ETX 87 /* Ethernet Transmitter */ 121#define MCF_IRQ_FECTX0 87 /* Ethernet Transmitter */
119#define MCF_IRQ_ENTC 88 /* Ethernet Non-Time Critical */ 122#define MCF_IRQ_FECENTC0 88 /* Ethernet Non-Time Critical */
120#define MCF_IRQ_QSPI 89 /* Queued Serial Interface */ 123#define MCF_IRQ_QSPI 89 /* Queued Serial Interface */
121#define MCF_IRQ_EINT5 90 /* External Interrupt 5 */ 124#define MCF_IRQ_EINT5 90 /* External Interrupt 5 */
122#define MCF_IRQ_EINT6 91 /* External Interrupt 6 */ 125#define MCF_IRQ_EINT6 91 /* External Interrupt 6 */
diff --git a/arch/m68k/include/asm/m527xsim.h b/arch/m68k/include/asm/m527xsim.h
index 758810ef91ec..83db8106f50a 100644
--- a/arch/m68k/include/asm/m527xsim.h
+++ b/arch/m68k/include/asm/m527xsim.h
@@ -38,8 +38,29 @@
38#define MCFINT_UART1 14 /* Interrupt number for UART1 */ 38#define MCFINT_UART1 14 /* Interrupt number for UART1 */
39#define MCFINT_UART2 15 /* Interrupt number for UART2 */ 39#define MCFINT_UART2 15 /* Interrupt number for UART2 */
40#define MCFINT_QSPI 18 /* Interrupt number for QSPI */ 40#define MCFINT_QSPI 18 /* Interrupt number for QSPI */
41#define MCFINT_FECRX0 23 /* Interrupt number for FEC0 */
42#define MCFINT_FECTX0 27 /* Interrupt number for FEC0 */
43#define MCFINT_FECENTC0 29 /* Interrupt number for FEC0 */
41#define MCFINT_PIT1 36 /* Interrupt number for PIT1 */ 44#define MCFINT_PIT1 36 /* Interrupt number for PIT1 */
42 45
46#define MCFINT2_VECBASE 128 /* Vector base number 2 */
47#define MCFINT2_FECRX1 23 /* Interrupt number for FEC1 */
48#define MCFINT2_FECTX1 27 /* Interrupt number for FEC1 */
49#define MCFINT2_FECENTC1 29 /* Interrupt number for FEC1 */
50
51#define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0)
52#define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1)
53#define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2)
54
55#define MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0)
56#define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0)
57#define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0)
58#define MCF_IRQ_FECRX1 (MCFINT2_VECBASE + MCFINT2_FECRX1)
59#define MCF_IRQ_FECTX1 (MCFINT2_VECBASE + MCFINT2_FECTX1)
60#define MCF_IRQ_FECENTC1 (MCFINT2_VECBASE + MCFINT2_FECENTC1)
61
62#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
63
43/* 64/*
44 * SDRAM configuration registers. 65 * SDRAM configuration registers.
45 */ 66 */
@@ -72,9 +93,9 @@
72/* 93/*
73 * UART module. 94 * UART module.
74 */ 95 */
75#define MCFUART_BASE1 (MCF_IPSBAR + 0x200) 96#define MCFUART_BASE0 (MCF_IPSBAR + 0x200)
76#define MCFUART_BASE2 (MCF_IPSBAR + 0x240) 97#define MCFUART_BASE1 (MCF_IPSBAR + 0x240)
77#define MCFUART_BASE3 (MCF_IPSBAR + 0x280) 98#define MCFUART_BASE2 (MCF_IPSBAR + 0x280)
78 99
79/* 100/*
80 * FEC ethernet module. 101 * FEC ethernet module.
@@ -84,6 +105,28 @@
84#define MCFFEC_BASE1 (MCF_IPSBAR + 0x1800) 105#define MCFFEC_BASE1 (MCF_IPSBAR + 0x1800)
85#define MCFFEC_SIZE1 0x800 106#define MCFFEC_SIZE1 0x800
86 107
108/*
109 * QSPI module.
110 */
111#define MCFQSPI_BASE (MCF_IPSBAR + 0x340)
112#define MCFQSPI_SIZE 0x40
113
114#ifdef CONFIG_M5271
115#define MCFQSPI_CS0 91
116#define MCFQSPI_CS1 92
117#define MCFQSPI_CS2 99
118#define MCFQSPI_CS3 103
119#endif
120#ifdef CONFIG_M5275
121#define MCFQSPI_CS0 59
122#define MCFQSPI_CS1 60
123#define MCFQSPI_CS2 61
124#define MCFQSPI_CS3 62
125#endif
126
127/*
128 * GPIO module.
129 */
87#ifdef CONFIG_M5271 130#ifdef CONFIG_M5271
88#define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100000) 131#define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100000)
89#define MCFGPIO_PODR_DATAH (MCF_IPSBAR + 0x100001) 132#define MCFGPIO_PODR_DATAH (MCF_IPSBAR + 0x100001)
@@ -285,8 +328,8 @@
285/* 328/*
286 * Reset Control Unit (relative to IPSBAR). 329 * Reset Control Unit (relative to IPSBAR).
287 */ 330 */
288#define MCF_RCR 0x110000 331#define MCF_RCR (MCF_IPSBAR + 0x110000)
289#define MCF_RSR 0x110001 332#define MCF_RSR (MCF_IPSBAR + 0x110001)
290 333
291#define MCF_RCR_SWRESET 0x80 /* Software reset bit */ 334#define MCF_RCR_SWRESET 0x80 /* Software reset bit */
292#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */ 335#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */
diff --git a/arch/m68k/include/asm/m528xsim.h b/arch/m68k/include/asm/m528xsim.h
index d798bd5df56c..569476fba18c 100644
--- a/arch/m68k/include/asm/m528xsim.h
+++ b/arch/m68k/include/asm/m528xsim.h
@@ -35,9 +35,24 @@
35 35
36#define MCFINT_VECBASE 64 /* Vector base number */ 36#define MCFINT_VECBASE 64 /* Vector base number */
37#define MCFINT_UART0 13 /* Interrupt number for UART0 */ 37#define MCFINT_UART0 13 /* Interrupt number for UART0 */
38#define MCFINT_UART1 14 /* Interrupt number for UART1 */
39#define MCFINT_UART2 15 /* Interrupt number for UART2 */
38#define MCFINT_QSPI 18 /* Interrupt number for QSPI */ 40#define MCFINT_QSPI 18 /* Interrupt number for QSPI */
41#define MCFINT_FECRX0 23 /* Interrupt number for FEC */
42#define MCFINT_FECTX0 27 /* Interrupt number for FEC */
43#define MCFINT_FECENTC0 29 /* Interrupt number for FEC */
39#define MCFINT_PIT1 55 /* Interrupt number for PIT1 */ 44#define MCFINT_PIT1 55 /* Interrupt number for PIT1 */
40 45
46#define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0)
47#define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1)
48#define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2)
49
50#define MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0)
51#define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0)
52#define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0)
53
54#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
55
41/* 56/*
42 * SDRAM configuration registers. 57 * SDRAM configuration registers.
43 */ 58 */
@@ -58,15 +73,26 @@
58/* 73/*
59 * UART module. 74 * UART module.
60 */ 75 */
61#define MCFUART_BASE1 (MCF_IPSBAR + 0x00000200) 76#define MCFUART_BASE0 (MCF_IPSBAR + 0x00000200)
62#define MCFUART_BASE2 (MCF_IPSBAR + 0x00000240) 77#define MCFUART_BASE1 (MCF_IPSBAR + 0x00000240)
63#define MCFUART_BASE3 (MCF_IPSBAR + 0x00000280) 78#define MCFUART_BASE2 (MCF_IPSBAR + 0x00000280)
64 79
65/* 80/*
66 * FEC ethernet module. 81 * FEC ethernet module.
67 */ 82 */
68#define MCFFEC_BASE (MCF_IPSBAR + 0x00001000) 83#define MCFFEC_BASE0 (MCF_IPSBAR + 0x00001000)
69#define MCFFEC_SIZE 0x800 84#define MCFFEC_SIZE0 0x800
85
86/*
87 * QSPI module.
88 */
89#define MCFQSPI_IOBASE (MCF_IPSBAR + 0x340)
90#define MCFQSPI_SIZE 0x40
91
92#define MCFQSPI_CS0 147
93#define MCFQSPI_CS1 148
94#define MCFQSPI_CS2 149
95#define MCFQSPI_CS3 150
70 96
71/* 97/*
72 * GPIO registers 98 * GPIO registers
@@ -246,8 +272,8 @@
246/* 272/*
247 * Reset Control Unit (relative to IPSBAR). 273 * Reset Control Unit (relative to IPSBAR).
248 */ 274 */
249#define MCF_RCR 0x110000 275#define MCF_RCR (MCF_IPSBAR + 0x110000)
250#define MCF_RSR 0x110001 276#define MCF_RSR (MCF_IPSBAR + 0x110001)
251 277
252#define MCF_RCR_SWRESET 0x80 /* Software reset bit */ 278#define MCF_RCR_SWRESET 0x80 /* Software reset bit */
253#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */ 279#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */
diff --git a/arch/m68k/include/asm/m5307sim.h b/arch/m68k/include/asm/m5307sim.h
index 8f8609fcc9b8..3bc3adaa7ee0 100644
--- a/arch/m68k/include/asm/m5307sim.h
+++ b/arch/m68k/include/asm/m5307sim.h
@@ -117,11 +117,11 @@
117 * UART module. 117 * UART module.
118 */ 118 */
119#if defined(CONFIG_NETtel) || defined(CONFIG_SECUREEDGEMP3) 119#if defined(CONFIG_NETtel) || defined(CONFIG_SECUREEDGEMP3)
120#define MCFUART_BASE1 0x200 /* Base address of UART1 */ 120#define MCFUART_BASE0 (MCF_MBAR + 0x200) /* Base address UART0 */
121#define MCFUART_BASE2 0x1c0 /* Base address of UART2 */ 121#define MCFUART_BASE1 (MCF_MBAR + 0x1c0) /* Base address UART1 */
122#else 122#else
123#define MCFUART_BASE1 0x1c0 /* Base address of UART1 */ 123#define MCFUART_BASE0 (MCF_MBAR + 0x1c0) /* Base address UART0 */
124#define MCFUART_BASE2 0x200 /* Base address of UART2 */ 124#define MCFUART_BASE1 (MCF_MBAR + 0x200) /* Base address UART1 */
125#endif 125#endif
126 126
127/* 127/*
@@ -176,6 +176,8 @@
176 */ 176 */
177#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */ 177#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */
178#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */ 178#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */
179#define MCF_IRQ_UART0 73 /* UART0 */
180#define MCF_IRQ_UART1 74 /* UART1 */
179 181
180/****************************************************************************/ 182/****************************************************************************/
181#endif /* m5307sim_h */ 183#endif /* m5307sim_h */
diff --git a/arch/m68k/include/asm/m532xsim.h b/arch/m68k/include/asm/m532xsim.h
index ba4cc784f574..29b66e21413a 100644
--- a/arch/m68k/include/asm/m532xsim.h
+++ b/arch/m68k/include/asm/m532xsim.h
@@ -24,6 +24,19 @@
24#define MCFINT_UART1 27 /* Interrupt number for UART1 */ 24#define MCFINT_UART1 27 /* Interrupt number for UART1 */
25#define MCFINT_UART2 28 /* Interrupt number for UART2 */ 25#define MCFINT_UART2 28 /* Interrupt number for UART2 */
26#define MCFINT_QSPI 31 /* Interrupt number for QSPI */ 26#define MCFINT_QSPI 31 /* Interrupt number for QSPI */
27#define MCFINT_FECRX0 36 /* Interrupt number for FEC */
28#define MCFINT_FECTX0 40 /* Interrupt number for FEC */
29#define MCFINT_FECENTC0 42 /* Interrupt number for FEC */
30
31#define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0)
32#define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1)
33#define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2)
34
35#define MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0)
36#define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0)
37#define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0)
38
39#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
27 40
28#define MCF_WTM_WCR MCF_REG16(0xFC098000) 41#define MCF_WTM_WCR MCF_REG16(0xFC098000)
29 42
@@ -82,9 +95,25 @@
82/* 95/*
83 * UART module. 96 * UART module.
84 */ 97 */
85#define MCFUART_BASE1 0xFC060000 /* Base address of UART1 */ 98#define MCFUART_BASE0 0xFC060000 /* Base address of UART1 */
86#define MCFUART_BASE2 0xFC064000 /* Base address of UART2 */ 99#define MCFUART_BASE1 0xFC064000 /* Base address of UART2 */
87#define MCFUART_BASE3 0xFC068000 /* Base address of UART3 */ 100#define MCFUART_BASE2 0xFC068000 /* Base address of UART3 */
101
102/*
103 * FEC module.
104 */
105#define MCFFEC_BASE0 0xFC030000 /* Base address of FEC0 */
106#define MCFFEC_SIZE0 0x800 /* Size of FEC0 region */
107
108/*
109 * QSPI module.
110 */
111#define MCFQSPI_BASE 0xFC058000 /* Base address of QSPI */
112#define MCFQSPI_SIZE 0x40 /* Size of QSPI region */
113
114#define MCFQSPI_CS0 84
115#define MCFQSPI_CS1 85
116#define MCFQSPI_CS2 86
88 117
89/* 118/*
90 * Timer module. 119 * Timer module.
diff --git a/arch/m68k/include/asm/m5407sim.h b/arch/m68k/include/asm/m5407sim.h
index 51e00b00b8a6..79f58dd6a83d 100644
--- a/arch/m68k/include/asm/m5407sim.h
+++ b/arch/m68k/include/asm/m5407sim.h
@@ -85,8 +85,8 @@
85#define MCFTIMER_BASE1 (MCF_MBAR + 0x140) /* Base of TIMER1 */ 85#define MCFTIMER_BASE1 (MCF_MBAR + 0x140) /* Base of TIMER1 */
86#define MCFTIMER_BASE2 (MCF_MBAR + 0x180) /* Base of TIMER2 */ 86#define MCFTIMER_BASE2 (MCF_MBAR + 0x180) /* Base of TIMER2 */
87 87
88#define MCFUART_BASE1 0x1c0 /* Base address of UART1 */ 88#define MCFUART_BASE0 (MCF_MBAR + 0x1c0) /* Base address UART0 */
89#define MCFUART_BASE2 0x200 /* Base address of UART2 */ 89#define MCFUART_BASE1 (MCF_MBAR + 0x200) /* Base address UART1 */
90 90
91#define MCFSIM_PADDR (MCF_MBAR + 0x244) 91#define MCFSIM_PADDR (MCF_MBAR + 0x244)
92#define MCFSIM_PADAT (MCF_MBAR + 0x248) 92#define MCFSIM_PADAT (MCF_MBAR + 0x248)
@@ -139,6 +139,8 @@
139 */ 139 */
140#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */ 140#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */
141#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */ 141#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */
142#define MCF_IRQ_UART0 73 /* UART0 */
143#define MCF_IRQ_UART1 74 /* UART1 */
142 144
143/****************************************************************************/ 145/****************************************************************************/
144#endif /* m5407sim_h */ 146#endif /* m5407sim_h */
diff --git a/arch/m68k/include/asm/m54xxsim.h b/arch/m68k/include/asm/m54xxsim.h
index 1ed8bfb02772..ae56b8848a9d 100644
--- a/arch/m68k/include/asm/m54xxsim.h
+++ b/arch/m68k/include/asm/m54xxsim.h
@@ -31,16 +31,20 @@
31/* 31/*
32 * UART module. 32 * UART module.
33 */ 33 */
34#define MCFUART_BASE1 0x8600 /* Base address of UART1 */ 34#define MCFUART_BASE0 (MCF_MBAR + 0x8600) /* Base address UART0 */
35#define MCFUART_BASE2 0x8700 /* Base address of UART2 */ 35#define MCFUART_BASE1 (MCF_MBAR + 0x8700) /* Base address UART1 */
36#define MCFUART_BASE3 0x8800 /* Base address of UART3 */ 36#define MCFUART_BASE2 (MCF_MBAR + 0x8800) /* Base address UART2 */
37#define MCFUART_BASE4 0x8900 /* Base address of UART4 */ 37#define MCFUART_BASE3 (MCF_MBAR + 0x8900) /* Base address UART3 */
38 38
39/* 39/*
40 * Define system peripheral IRQ usage. 40 * Define system peripheral IRQ usage.
41 */ 41 */
42#define MCF_IRQ_TIMER (64 + 54) /* Slice Timer 0 */ 42#define MCF_IRQ_TIMER (MCFINT_VECBASE + 54) /* Slice Timer 0 */
43#define MCF_IRQ_PROFILER (64 + 53) /* Slice Timer 1 */ 43#define MCF_IRQ_PROFILER (MCFINT_VECBASE + 53) /* Slice Timer 1 */
44#define MCF_IRQ_UART0 (MCFINT_VECBASE + 35)
45#define MCF_IRQ_UART1 (MCFINT_VECBASE + 34)
46#define MCF_IRQ_UART2 (MCFINT_VECBASE + 33)
47#define MCF_IRQ_UART3 (MCFINT_VECBASE + 32)
44 48
45/* 49/*
46 * Generic GPIO support 50 * Generic GPIO support
diff --git a/arch/m68k/include/asm/machdep.h b/arch/m68k/include/asm/machdep.h
index 789f3b2de0e9..825c1c813196 100644
--- a/arch/m68k/include/asm/machdep.h
+++ b/arch/m68k/include/asm/machdep.h
@@ -22,8 +22,6 @@ extern unsigned int (*mach_get_ss)(void);
22extern int (*mach_get_rtc_pll)(struct rtc_pll_info *); 22extern int (*mach_get_rtc_pll)(struct rtc_pll_info *);
23extern int (*mach_set_rtc_pll)(struct rtc_pll_info *); 23extern int (*mach_set_rtc_pll)(struct rtc_pll_info *);
24extern int (*mach_set_clock_mmss)(unsigned long); 24extern int (*mach_set_clock_mmss)(unsigned long);
25extern void (*mach_gettod)(int *year, int *mon, int *day, int *hour,
26 int *min, int *sec);
27extern void (*mach_reset)( void ); 25extern void (*mach_reset)( void );
28extern void (*mach_halt)( void ); 26extern void (*mach_halt)( void );
29extern void (*mach_power_off)( void ); 27extern void (*mach_power_off)( void );
@@ -35,9 +33,8 @@ extern void (*mach_l2_flush) (int);
35extern void (*mach_beep) (unsigned int, unsigned int); 33extern void (*mach_beep) (unsigned int, unsigned int);
36 34
37/* Hardware clock functions */ 35/* Hardware clock functions */
38extern void hw_timer_init(void); 36extern void hw_timer_init(irq_handler_t handler);
39extern unsigned long hw_timer_offset(void); 37extern unsigned long hw_timer_offset(void);
40extern irqreturn_t arch_timer_interrupt(int irq, void *dummy);
41 38
42extern void config_BSP(char *command, int len); 39extern void config_BSP(char *command, int len);
43 40
diff --git a/arch/m68k/include/asm/mcfqspi.h b/arch/m68k/include/asm/mcfqspi.h
index 7fe631972f1f..7b51416ccae2 100644
--- a/arch/m68k/include/asm/mcfqspi.h
+++ b/arch/m68k/include/asm/mcfqspi.h
@@ -21,17 +21,6 @@
21#ifndef mcfqspi_h 21#ifndef mcfqspi_h
22#define mcfqspi_h 22#define mcfqspi_h
23 23
24#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x)
25#define MCFQSPI_IOBASE (MCF_IPSBAR + 0x340)
26#elif defined(CONFIG_M5249)
27#define MCFQSPI_IOBASE (MCF_MBAR + 0x300)
28#elif defined(CONFIG_M520x)
29#define MCFQSPI_IOBASE 0xFC05C000
30#elif defined(CONFIG_M532x)
31#define MCFQSPI_IOBASE 0xFC058000
32#endif
33#define MCFQSPI_IOSIZE 0x40
34
35/** 24/**
36 * struct mcfqspi_cs_control - chip select control for the coldfire qspi driver 25 * struct mcfqspi_cs_control - chip select control for the coldfire qspi driver
37 * @setup: setup the control; allocate gpio's, etc. May be NULL. 26 * @setup: setup the control; allocate gpio's, etc. May be NULL.
diff --git a/arch/m68k/include/asm/mcfuart.h b/arch/m68k/include/asm/mcfuart.h
index 2abedff0a694..2d3bc774b3c5 100644
--- a/arch/m68k/include/asm/mcfuart.h
+++ b/arch/m68k/include/asm/mcfuart.h
@@ -41,7 +41,10 @@ struct mcf_platform_uart {
41#define MCFUART_UTF 0x28 /* Transmitter FIFO (r/w) */ 41#define MCFUART_UTF 0x28 /* Transmitter FIFO (r/w) */
42#define MCFUART_URF 0x2c /* Receiver FIFO (r/w) */ 42#define MCFUART_URF 0x2c /* Receiver FIFO (r/w) */
43#define MCFUART_UFPD 0x30 /* Frac Prec. Divider (r/w) */ 43#define MCFUART_UFPD 0x30 /* Frac Prec. Divider (r/w) */
44#else 44#endif
45#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
46 defined(CONFIG_M5249) || defined(CONFIG_M5307) || \
47 defined(CONFIG_M5407)
45#define MCFUART_UIVR 0x30 /* Interrupt Vector (r/w) */ 48#define MCFUART_UIVR 0x30 /* Interrupt Vector (r/w) */
46#endif 49#endif
47#define MCFUART_UIPR 0x34 /* Input Port (r) */ 50#define MCFUART_UIPR 0x34 /* Input Port (r) */
diff --git a/arch/m68k/include/asm/socket.h b/arch/m68k/include/asm/socket.h
index d4708ce466e0..d1be684edf97 100644
--- a/arch/m68k/include/asm/socket.h
+++ b/arch/m68k/include/asm/socket.h
@@ -64,5 +64,9 @@
64 64
65#define SO_WIFI_STATUS 41 65#define SO_WIFI_STATUS 41
66#define SCM_WIFI_STATUS SO_WIFI_STATUS 66#define SCM_WIFI_STATUS SO_WIFI_STATUS
67#define SO_PEEK_OFF 42
68
69/* Instruct lower device to use last 4-bytes of skb data as FCS */
70#define SO_NOFCS 43
67 71
68#endif /* _ASM_SOCKET_H */ 72#endif /* _ASM_SOCKET_H */
diff --git a/arch/m68k/include/asm/system.h b/arch/m68k/include/asm/system.h
index 47b01f4726bc..8dc68178716c 100644
--- a/arch/m68k/include/asm/system.h
+++ b/arch/m68k/include/asm/system.h
@@ -3,6 +3,7 @@
3 3
4#include <linux/linkage.h> 4#include <linux/linkage.h>
5#include <linux/kernel.h> 5#include <linux/kernel.h>
6#include <linux/bug.h>
6#include <linux/irqflags.h> 7#include <linux/irqflags.h>
7#include <asm/segment.h> 8#include <asm/segment.h>
8#include <asm/entry.h> 9#include <asm/entry.h>
diff --git a/arch/m68k/kernel/process.c b/arch/m68k/kernel/process.c
index 6cf4bd6e34f8..c54ef927e483 100644
--- a/arch/m68k/kernel/process.c
+++ b/arch/m68k/kernel/process.c
@@ -1,5 +1,378 @@
1/*
2 * linux/arch/m68k/kernel/process.c
3 *
4 * Copyright (C) 1995 Hamish Macdonald
5 *
6 * 68060 fixes by Jesper Skov
7 */
8
9/*
10 * This file handles the architecture-dependent parts of process handling..
11 */
12
13#include <linux/errno.h>
14#include <linux/module.h>
15#include <linux/sched.h>
16#include <linux/kernel.h>
17#include <linux/mm.h>
18#include <linux/slab.h>
19#include <linux/fs.h>
20#include <linux/smp.h>
21#include <linux/stddef.h>
22#include <linux/unistd.h>
23#include <linux/ptrace.h>
24#include <linux/user.h>
25#include <linux/reboot.h>
26#include <linux/init_task.h>
27#include <linux/mqueue.h>
28
29#include <asm/uaccess.h>
30#include <asm/system.h>
31#include <asm/traps.h>
32#include <asm/machdep.h>
33#include <asm/setup.h>
34#include <asm/pgtable.h>
35
36
37asmlinkage void ret_from_fork(void);
38
39
40/*
41 * Return saved PC from a blocked thread
42 */
43unsigned long thread_saved_pc(struct task_struct *tsk)
44{
45 struct switch_stack *sw = (struct switch_stack *)tsk->thread.ksp;
46 /* Check whether the thread is blocked in resume() */
47 if (in_sched_functions(sw->retpc))
48 return ((unsigned long *)sw->a6)[1];
49 else
50 return sw->retpc;
51}
52
53/*
54 * The idle loop on an m68k..
55 */
56static void default_idle(void)
57{
58 if (!need_resched())
59#if defined(MACH_ATARI_ONLY)
60 /* block out HSYNC on the atari (falcon) */
61 __asm__("stop #0x2200" : : : "cc");
62#else
63 __asm__("stop #0x2000" : : : "cc");
64#endif
65}
66
67void (*idle)(void) = default_idle;
68
69/*
70 * The idle thread. There's no useful work to be
71 * done, so just try to conserve power and have a
72 * low exit latency (ie sit in a loop waiting for
73 * somebody to say that they'd like to reschedule)
74 */
75void cpu_idle(void)
76{
77 /* endless idle loop with no priority at all */
78 while (1) {
79 while (!need_resched())
80 idle();
81 schedule_preempt_disabled();
82 }
83}
84
85void machine_restart(char * __unused)
86{
87 if (mach_reset)
88 mach_reset();
89 for (;;);
90}
91
92void machine_halt(void)
93{
94 if (mach_halt)
95 mach_halt();
96 for (;;);
97}
98
99void machine_power_off(void)
100{
101 if (mach_power_off)
102 mach_power_off();
103 for (;;);
104}
105
106void (*pm_power_off)(void) = machine_power_off;
107EXPORT_SYMBOL(pm_power_off);
108
109void show_regs(struct pt_regs * regs)
110{
111 printk("\n");
112 printk("Format %02x Vector: %04x PC: %08lx Status: %04x %s\n",
113 regs->format, regs->vector, regs->pc, regs->sr, print_tainted());
114 printk("ORIG_D0: %08lx D0: %08lx A2: %08lx A1: %08lx\n",
115 regs->orig_d0, regs->d0, regs->a2, regs->a1);
116 printk("A0: %08lx D5: %08lx D4: %08lx\n",
117 regs->a0, regs->d5, regs->d4);
118 printk("D3: %08lx D2: %08lx D1: %08lx\n",
119 regs->d3, regs->d2, regs->d1);
120 if (!(regs->sr & PS_S))
121 printk("USP: %08lx\n", rdusp());
122}
123
124/*
125 * Create a kernel thread
126 */
127int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags)
128{
129 int pid;
130 mm_segment_t fs;
131
132 fs = get_fs();
133 set_fs (KERNEL_DS);
134
135 {
136 register long retval __asm__ ("d0");
137 register long clone_arg __asm__ ("d1") = flags | CLONE_VM | CLONE_UNTRACED;
138
139 retval = __NR_clone;
140 __asm__ __volatile__
141 ("clrl %%d2\n\t"
142 "trap #0\n\t" /* Linux/m68k system call */
143 "tstl %0\n\t" /* child or parent */
144 "jne 1f\n\t" /* parent - jump */
145#ifdef CONFIG_MMU
146 "lea %%sp@(%c7),%6\n\t" /* reload current */
147 "movel %6@,%6\n\t"
148#endif
149 "movel %3,%%sp@-\n\t" /* push argument */
150 "jsr %4@\n\t" /* call fn */
151 "movel %0,%%d1\n\t" /* pass exit value */
152 "movel %2,%%d0\n\t" /* exit */
153 "trap #0\n"
154 "1:"
155 : "+d" (retval)
156 : "i" (__NR_clone), "i" (__NR_exit),
157 "r" (arg), "a" (fn), "d" (clone_arg), "r" (current),
158 "i" (-THREAD_SIZE)
159 : "d2");
160
161 pid = retval;
162 }
163
164 set_fs (fs);
165 return pid;
166}
167EXPORT_SYMBOL(kernel_thread);
168
169void flush_thread(void)
170{
171 current->thread.fs = __USER_DS;
172#ifdef CONFIG_FPU
173 if (!FPU_IS_EMU) {
174 unsigned long zero = 0;
175 asm volatile("frestore %0": :"m" (zero));
176 }
177#endif
178}
179
180/*
181 * "m68k_fork()".. By the time we get here, the
182 * non-volatile registers have also been saved on the
183 * stack. We do some ugly pointer stuff here.. (see
184 * also copy_thread)
185 */
186
187asmlinkage int m68k_fork(struct pt_regs *regs)
188{
1#ifdef CONFIG_MMU 189#ifdef CONFIG_MMU
2#include "process_mm.c" 190 return do_fork(SIGCHLD, rdusp(), regs, 0, NULL, NULL);
3#else 191#else
4#include "process_no.c" 192 return -EINVAL;
5#endif 193#endif
194}
195
196asmlinkage int m68k_vfork(struct pt_regs *regs)
197{
198 return do_fork(CLONE_VFORK | CLONE_VM | SIGCHLD, rdusp(), regs, 0,
199 NULL, NULL);
200}
201
202asmlinkage int m68k_clone(struct pt_regs *regs)
203{
204 unsigned long clone_flags;
205 unsigned long newsp;
206 int __user *parent_tidptr, *child_tidptr;
207
208 /* syscall2 puts clone_flags in d1 and usp in d2 */
209 clone_flags = regs->d1;
210 newsp = regs->d2;
211 parent_tidptr = (int __user *)regs->d3;
212 child_tidptr = (int __user *)regs->d4;
213 if (!newsp)
214 newsp = rdusp();
215 return do_fork(clone_flags, newsp, regs, 0,
216 parent_tidptr, child_tidptr);
217}
218
219int copy_thread(unsigned long clone_flags, unsigned long usp,
220 unsigned long unused,
221 struct task_struct * p, struct pt_regs * regs)
222{
223 struct pt_regs * childregs;
224 struct switch_stack * childstack, *stack;
225 unsigned long *retp;
226
227 childregs = (struct pt_regs *) (task_stack_page(p) + THREAD_SIZE) - 1;
228
229 *childregs = *regs;
230 childregs->d0 = 0;
231
232 retp = ((unsigned long *) regs);
233 stack = ((struct switch_stack *) retp) - 1;
234
235 childstack = ((struct switch_stack *) childregs) - 1;
236 *childstack = *stack;
237 childstack->retpc = (unsigned long)ret_from_fork;
238
239 p->thread.usp = usp;
240 p->thread.ksp = (unsigned long)childstack;
241
242 if (clone_flags & CLONE_SETTLS)
243 task_thread_info(p)->tp_value = regs->d5;
244
245 /*
246 * Must save the current SFC/DFC value, NOT the value when
247 * the parent was last descheduled - RGH 10-08-96
248 */
249 p->thread.fs = get_fs().seg;
250
251#ifdef CONFIG_FPU
252 if (!FPU_IS_EMU) {
253 /* Copy the current fpu state */
254 asm volatile ("fsave %0" : : "m" (p->thread.fpstate[0]) : "memory");
255
256 if (!CPU_IS_060 ? p->thread.fpstate[0] : p->thread.fpstate[2]) {
257 if (CPU_IS_COLDFIRE) {
258 asm volatile ("fmovemd %/fp0-%/fp7,%0\n\t"
259 "fmovel %/fpiar,%1\n\t"
260 "fmovel %/fpcr,%2\n\t"
261 "fmovel %/fpsr,%3"
262 :
263 : "m" (p->thread.fp[0]),
264 "m" (p->thread.fpcntl[0]),
265 "m" (p->thread.fpcntl[1]),
266 "m" (p->thread.fpcntl[2])
267 : "memory");
268 } else {
269 asm volatile ("fmovemx %/fp0-%/fp7,%0\n\t"
270 "fmoveml %/fpiar/%/fpcr/%/fpsr,%1"
271 :
272 : "m" (p->thread.fp[0]),
273 "m" (p->thread.fpcntl[0])
274 : "memory");
275 }
276 }
277
278 /* Restore the state in case the fpu was busy */
279 asm volatile ("frestore %0" : : "m" (p->thread.fpstate[0]));
280 }
281#endif /* CONFIG_FPU */
282
283 return 0;
284}
285
286/* Fill in the fpu structure for a core dump. */
287#ifdef CONFIG_FPU
288int dump_fpu (struct pt_regs *regs, struct user_m68kfp_struct *fpu)
289{
290 char fpustate[216];
291
292 if (FPU_IS_EMU) {
293 int i;
294
295 memcpy(fpu->fpcntl, current->thread.fpcntl, 12);
296 memcpy(fpu->fpregs, current->thread.fp, 96);
297 /* Convert internal fpu reg representation
298 * into long double format
299 */
300 for (i = 0; i < 24; i += 3)
301 fpu->fpregs[i] = ((fpu->fpregs[i] & 0xffff0000) << 15) |
302 ((fpu->fpregs[i] & 0x0000ffff) << 16);
303 return 1;
304 }
305
306 /* First dump the fpu context to avoid protocol violation. */
307 asm volatile ("fsave %0" :: "m" (fpustate[0]) : "memory");
308 if (!CPU_IS_060 ? !fpustate[0] : !fpustate[2])
309 return 0;
310
311 if (CPU_IS_COLDFIRE) {
312 asm volatile ("fmovel %/fpiar,%0\n\t"
313 "fmovel %/fpcr,%1\n\t"
314 "fmovel %/fpsr,%2\n\t"
315 "fmovemd %/fp0-%/fp7,%3"
316 :
317 : "m" (fpu->fpcntl[0]),
318 "m" (fpu->fpcntl[1]),
319 "m" (fpu->fpcntl[2]),
320 "m" (fpu->fpregs[0])
321 : "memory");
322 } else {
323 asm volatile ("fmovem %/fpiar/%/fpcr/%/fpsr,%0"
324 :
325 : "m" (fpu->fpcntl[0])
326 : "memory");
327 asm volatile ("fmovemx %/fp0-%/fp7,%0"
328 :
329 : "m" (fpu->fpregs[0])
330 : "memory");
331 }
332
333 return 1;
334}
335EXPORT_SYMBOL(dump_fpu);
336#endif /* CONFIG_FPU */
337
338/*
339 * sys_execve() executes a new program.
340 */
341asmlinkage int sys_execve(const char __user *name,
342 const char __user *const __user *argv,
343 const char __user *const __user *envp)
344{
345 int error;
346 char * filename;
347 struct pt_regs *regs = (struct pt_regs *) &name;
348
349 filename = getname(name);
350 error = PTR_ERR(filename);
351 if (IS_ERR(filename))
352 return error;
353 error = do_execve(filename, argv, envp, regs);
354 putname(filename);
355 return error;
356}
357
358unsigned long get_wchan(struct task_struct *p)
359{
360 unsigned long fp, pc;
361 unsigned long stack_page;
362 int count = 0;
363 if (!p || p == current || p->state == TASK_RUNNING)
364 return 0;
365
366 stack_page = (unsigned long)task_stack_page(p);
367 fp = ((struct switch_stack *)p->thread.ksp)->a6;
368 do {
369 if (fp < stack_page+sizeof(struct thread_info) ||
370 fp >= 8184+stack_page)
371 return 0;
372 pc = ((unsigned long *)fp)[1];
373 if (!in_sched_functions(pc))
374 return pc;
375 fp = *(unsigned long *) fp;
376 } while (count++ < 16);
377 return 0;
378}
diff --git a/arch/m68k/kernel/process_mm.c b/arch/m68k/kernel/process_mm.c
deleted file mode 100644
index 099283ee1a8f..000000000000
--- a/arch/m68k/kernel/process_mm.c
+++ /dev/null
@@ -1,369 +0,0 @@
1/*
2 * linux/arch/m68k/kernel/process.c
3 *
4 * Copyright (C) 1995 Hamish Macdonald
5 *
6 * 68060 fixes by Jesper Skov
7 */
8
9/*
10 * This file handles the architecture-dependent parts of process handling..
11 */
12
13#include <linux/errno.h>
14#include <linux/module.h>
15#include <linux/sched.h>
16#include <linux/kernel.h>
17#include <linux/mm.h>
18#include <linux/slab.h>
19#include <linux/fs.h>
20#include <linux/smp.h>
21#include <linux/stddef.h>
22#include <linux/unistd.h>
23#include <linux/ptrace.h>
24#include <linux/user.h>
25#include <linux/reboot.h>
26#include <linux/init_task.h>
27#include <linux/mqueue.h>
28
29#include <asm/uaccess.h>
30#include <asm/system.h>
31#include <asm/traps.h>
32#include <asm/machdep.h>
33#include <asm/setup.h>
34#include <asm/pgtable.h>
35
36
37asmlinkage void ret_from_fork(void);
38
39
40/*
41 * Return saved PC from a blocked thread
42 */
43unsigned long thread_saved_pc(struct task_struct *tsk)
44{
45 struct switch_stack *sw = (struct switch_stack *)tsk->thread.ksp;
46 /* Check whether the thread is blocked in resume() */
47 if (in_sched_functions(sw->retpc))
48 return ((unsigned long *)sw->a6)[1];
49 else
50 return sw->retpc;
51}
52
53/*
54 * The idle loop on an m68k..
55 */
56static void default_idle(void)
57{
58 if (!need_resched())
59#if defined(MACH_ATARI_ONLY)
60 /* block out HSYNC on the atari (falcon) */
61 __asm__("stop #0x2200" : : : "cc");
62#else
63 __asm__("stop #0x2000" : : : "cc");
64#endif
65}
66
67void (*idle)(void) = default_idle;
68
69/*
70 * The idle thread. There's no useful work to be
71 * done, so just try to conserve power and have a
72 * low exit latency (ie sit in a loop waiting for
73 * somebody to say that they'd like to reschedule)
74 */
75void cpu_idle(void)
76{
77 /* endless idle loop with no priority at all */
78 while (1) {
79 while (!need_resched())
80 idle();
81 preempt_enable_no_resched();
82 schedule();
83 preempt_disable();
84 }
85}
86
87void machine_restart(char * __unused)
88{
89 if (mach_reset)
90 mach_reset();
91 for (;;);
92}
93
94void machine_halt(void)
95{
96 if (mach_halt)
97 mach_halt();
98 for (;;);
99}
100
101void machine_power_off(void)
102{
103 if (mach_power_off)
104 mach_power_off();
105 for (;;);
106}
107
108void (*pm_power_off)(void) = machine_power_off;
109EXPORT_SYMBOL(pm_power_off);
110
111void show_regs(struct pt_regs * regs)
112{
113 printk("\n");
114 printk("Format %02x Vector: %04x PC: %08lx Status: %04x %s\n",
115 regs->format, regs->vector, regs->pc, regs->sr, print_tainted());
116 printk("ORIG_D0: %08lx D0: %08lx A2: %08lx A1: %08lx\n",
117 regs->orig_d0, regs->d0, regs->a2, regs->a1);
118 printk("A0: %08lx D5: %08lx D4: %08lx\n",
119 regs->a0, regs->d5, regs->d4);
120 printk("D3: %08lx D2: %08lx D1: %08lx\n",
121 regs->d3, regs->d2, regs->d1);
122 if (!(regs->sr & PS_S))
123 printk("USP: %08lx\n", rdusp());
124}
125
126/*
127 * Create a kernel thread
128 */
129int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags)
130{
131 int pid;
132 mm_segment_t fs;
133
134 fs = get_fs();
135 set_fs (KERNEL_DS);
136
137 {
138 register long retval __asm__ ("d0");
139 register long clone_arg __asm__ ("d1") = flags | CLONE_VM | CLONE_UNTRACED;
140
141 retval = __NR_clone;
142 __asm__ __volatile__
143 ("clrl %%d2\n\t"
144 "trap #0\n\t" /* Linux/m68k system call */
145 "tstl %0\n\t" /* child or parent */
146 "jne 1f\n\t" /* parent - jump */
147 "lea %%sp@(%c7),%6\n\t" /* reload current */
148 "movel %6@,%6\n\t"
149 "movel %3,%%sp@-\n\t" /* push argument */
150 "jsr %4@\n\t" /* call fn */
151 "movel %0,%%d1\n\t" /* pass exit value */
152 "movel %2,%%d0\n\t" /* exit */
153 "trap #0\n"
154 "1:"
155 : "+d" (retval)
156 : "i" (__NR_clone), "i" (__NR_exit),
157 "r" (arg), "a" (fn), "d" (clone_arg), "r" (current),
158 "i" (-THREAD_SIZE)
159 : "d2");
160
161 pid = retval;
162 }
163
164 set_fs (fs);
165 return pid;
166}
167EXPORT_SYMBOL(kernel_thread);
168
169void flush_thread(void)
170{
171 unsigned long zero = 0;
172
173 current->thread.fs = __USER_DS;
174 if (!FPU_IS_EMU)
175 asm volatile("frestore %0": :"m" (zero));
176}
177
178/*
179 * "m68k_fork()".. By the time we get here, the
180 * non-volatile registers have also been saved on the
181 * stack. We do some ugly pointer stuff here.. (see
182 * also copy_thread)
183 */
184
185asmlinkage int m68k_fork(struct pt_regs *regs)
186{
187 return do_fork(SIGCHLD, rdusp(), regs, 0, NULL, NULL);
188}
189
190asmlinkage int m68k_vfork(struct pt_regs *regs)
191{
192 return do_fork(CLONE_VFORK | CLONE_VM | SIGCHLD, rdusp(), regs, 0,
193 NULL, NULL);
194}
195
196asmlinkage int m68k_clone(struct pt_regs *regs)
197{
198 unsigned long clone_flags;
199 unsigned long newsp;
200 int __user *parent_tidptr, *child_tidptr;
201
202 /* syscall2 puts clone_flags in d1 and usp in d2 */
203 clone_flags = regs->d1;
204 newsp = regs->d2;
205 parent_tidptr = (int __user *)regs->d3;
206 child_tidptr = (int __user *)regs->d4;
207 if (!newsp)
208 newsp = rdusp();
209 return do_fork(clone_flags, newsp, regs, 0,
210 parent_tidptr, child_tidptr);
211}
212
213int copy_thread(unsigned long clone_flags, unsigned long usp,
214 unsigned long unused,
215 struct task_struct * p, struct pt_regs * regs)
216{
217 struct pt_regs * childregs;
218 struct switch_stack * childstack, *stack;
219 unsigned long *retp;
220
221 childregs = (struct pt_regs *) (task_stack_page(p) + THREAD_SIZE) - 1;
222
223 *childregs = *regs;
224 childregs->d0 = 0;
225
226 retp = ((unsigned long *) regs);
227 stack = ((struct switch_stack *) retp) - 1;
228
229 childstack = ((struct switch_stack *) childregs) - 1;
230 *childstack = *stack;
231 childstack->retpc = (unsigned long)ret_from_fork;
232
233 p->thread.usp = usp;
234 p->thread.ksp = (unsigned long)childstack;
235
236 if (clone_flags & CLONE_SETTLS)
237 task_thread_info(p)->tp_value = regs->d5;
238
239 /*
240 * Must save the current SFC/DFC value, NOT the value when
241 * the parent was last descheduled - RGH 10-08-96
242 */
243 p->thread.fs = get_fs().seg;
244
245 if (!FPU_IS_EMU) {
246 /* Copy the current fpu state */
247 asm volatile ("fsave %0" : : "m" (p->thread.fpstate[0]) : "memory");
248
249 if (!CPU_IS_060 ? p->thread.fpstate[0] : p->thread.fpstate[2]) {
250 if (CPU_IS_COLDFIRE) {
251 asm volatile ("fmovemd %/fp0-%/fp7,%0\n\t"
252 "fmovel %/fpiar,%1\n\t"
253 "fmovel %/fpcr,%2\n\t"
254 "fmovel %/fpsr,%3"
255 :
256 : "m" (p->thread.fp[0]),
257 "m" (p->thread.fpcntl[0]),
258 "m" (p->thread.fpcntl[1]),
259 "m" (p->thread.fpcntl[2])
260 : "memory");
261 } else {
262 asm volatile ("fmovemx %/fp0-%/fp7,%0\n\t"
263 "fmoveml %/fpiar/%/fpcr/%/fpsr,%1"
264 :
265 : "m" (p->thread.fp[0]),
266 "m" (p->thread.fpcntl[0])
267 : "memory");
268 }
269 }
270
271 /* Restore the state in case the fpu was busy */
272 asm volatile ("frestore %0" : : "m" (p->thread.fpstate[0]));
273 }
274
275 return 0;
276}
277
278/* Fill in the fpu structure for a core dump. */
279
280int dump_fpu (struct pt_regs *regs, struct user_m68kfp_struct *fpu)
281{
282 char fpustate[216];
283
284 if (FPU_IS_EMU) {
285 int i;
286
287 memcpy(fpu->fpcntl, current->thread.fpcntl, 12);
288 memcpy(fpu->fpregs, current->thread.fp, 96);
289 /* Convert internal fpu reg representation
290 * into long double format
291 */
292 for (i = 0; i < 24; i += 3)
293 fpu->fpregs[i] = ((fpu->fpregs[i] & 0xffff0000) << 15) |
294 ((fpu->fpregs[i] & 0x0000ffff) << 16);
295 return 1;
296 }
297
298 /* First dump the fpu context to avoid protocol violation. */
299 asm volatile ("fsave %0" :: "m" (fpustate[0]) : "memory");
300 if (!CPU_IS_060 ? !fpustate[0] : !fpustate[2])
301 return 0;
302
303 if (CPU_IS_COLDFIRE) {
304 asm volatile ("fmovel %/fpiar,%0\n\t"
305 "fmovel %/fpcr,%1\n\t"
306 "fmovel %/fpsr,%2\n\t"
307 "fmovemd %/fp0-%/fp7,%3"
308 :
309 : "m" (fpu->fpcntl[0]),
310 "m" (fpu->fpcntl[1]),
311 "m" (fpu->fpcntl[2]),
312 "m" (fpu->fpregs[0])
313 : "memory");
314 } else {
315 asm volatile ("fmovem %/fpiar/%/fpcr/%/fpsr,%0"
316 :
317 : "m" (fpu->fpcntl[0])
318 : "memory");
319 asm volatile ("fmovemx %/fp0-%/fp7,%0"
320 :
321 : "m" (fpu->fpregs[0])
322 : "memory");
323 }
324
325 return 1;
326}
327EXPORT_SYMBOL(dump_fpu);
328
329/*
330 * sys_execve() executes a new program.
331 */
332asmlinkage int sys_execve(const char __user *name,
333 const char __user *const __user *argv,
334 const char __user *const __user *envp)
335{
336 int error;
337 char * filename;
338 struct pt_regs *regs = (struct pt_regs *) &name;
339
340 filename = getname(name);
341 error = PTR_ERR(filename);
342 if (IS_ERR(filename))
343 return error;
344 error = do_execve(filename, argv, envp, regs);
345 putname(filename);
346 return error;
347}
348
349unsigned long get_wchan(struct task_struct *p)
350{
351 unsigned long fp, pc;
352 unsigned long stack_page;
353 int count = 0;
354 if (!p || p == current || p->state == TASK_RUNNING)
355 return 0;
356
357 stack_page = (unsigned long)task_stack_page(p);
358 fp = ((struct switch_stack *)p->thread.ksp)->a6;
359 do {
360 if (fp < stack_page+sizeof(struct thread_info) ||
361 fp >= 8184+stack_page)
362 return 0;
363 pc = ((unsigned long *)fp)[1];
364 if (!in_sched_functions(pc))
365 return pc;
366 fp = *(unsigned long *) fp;
367 } while (count++ < 16);
368 return 0;
369}
diff --git a/arch/m68k/kernel/process_no.c b/arch/m68k/kernel/process_no.c
deleted file mode 100644
index 5e1078cabe0e..000000000000
--- a/arch/m68k/kernel/process_no.c
+++ /dev/null
@@ -1,406 +0,0 @@
1/*
2 * linux/arch/m68knommu/kernel/process.c
3 *
4 * Copyright (C) 1995 Hamish Macdonald
5 *
6 * 68060 fixes by Jesper Skov
7 *
8 * uClinux changes
9 * Copyright (C) 2000-2002, David McCullough <davidm@snapgear.com>
10 */
11
12/*
13 * This file handles the architecture-dependent parts of process handling..
14 */
15
16#include <linux/module.h>
17#include <linux/errno.h>
18#include <linux/sched.h>
19#include <linux/kernel.h>
20#include <linux/mm.h>
21#include <linux/smp.h>
22#include <linux/stddef.h>
23#include <linux/unistd.h>
24#include <linux/ptrace.h>
25#include <linux/user.h>
26#include <linux/interrupt.h>
27#include <linux/reboot.h>
28#include <linux/fs.h>
29#include <linux/slab.h>
30
31#include <asm/uaccess.h>
32#include <asm/system.h>
33#include <asm/traps.h>
34#include <asm/machdep.h>
35#include <asm/setup.h>
36#include <asm/pgtable.h>
37
38asmlinkage void ret_from_fork(void);
39
40/*
41 * The following aren't currently used.
42 */
43void (*pm_idle)(void);
44EXPORT_SYMBOL(pm_idle);
45
46void (*pm_power_off)(void);
47EXPORT_SYMBOL(pm_power_off);
48
49/*
50 * The idle loop on an m68knommu..
51 */
52static void default_idle(void)
53{
54 local_irq_disable();
55 while (!need_resched()) {
56 /* This stop will re-enable interrupts */
57 __asm__("stop #0x2000" : : : "cc");
58 local_irq_disable();
59 }
60 local_irq_enable();
61}
62
63void (*idle)(void) = default_idle;
64
65/*
66 * The idle thread. There's no useful work to be
67 * done, so just try to conserve power and have a
68 * low exit latency (ie sit in a loop waiting for
69 * somebody to say that they'd like to reschedule)
70 */
71void cpu_idle(void)
72{
73 /* endless idle loop with no priority at all */
74 while (1) {
75 idle();
76 preempt_enable_no_resched();
77 schedule();
78 preempt_disable();
79 }
80}
81
82void machine_restart(char * __unused)
83{
84 if (mach_reset)
85 mach_reset();
86 for (;;);
87}
88
89void machine_halt(void)
90{
91 if (mach_halt)
92 mach_halt();
93 for (;;);
94}
95
96void machine_power_off(void)
97{
98 if (mach_power_off)
99 mach_power_off();
100 for (;;);
101}
102
103void show_regs(struct pt_regs * regs)
104{
105 printk(KERN_NOTICE "\n");
106 printk(KERN_NOTICE "Format %02x Vector: %04x PC: %08lx Status: %04x %s\n",
107 regs->format, regs->vector, regs->pc, regs->sr, print_tainted());
108 printk(KERN_NOTICE "ORIG_D0: %08lx D0: %08lx A2: %08lx A1: %08lx\n",
109 regs->orig_d0, regs->d0, regs->a2, regs->a1);
110 printk(KERN_NOTICE "A0: %08lx D5: %08lx D4: %08lx\n",
111 regs->a0, regs->d5, regs->d4);
112 printk(KERN_NOTICE "D3: %08lx D2: %08lx D1: %08lx\n",
113 regs->d3, regs->d2, regs->d1);
114 if (!(regs->sr & PS_S))
115 printk(KERN_NOTICE "USP: %08lx\n", rdusp());
116}
117
118/*
119 * Create a kernel thread
120 */
121int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags)
122{
123 int retval;
124 long clone_arg = flags | CLONE_VM;
125 mm_segment_t fs;
126
127 fs = get_fs();
128 set_fs(KERNEL_DS);
129
130 __asm__ __volatile__ (
131 "movel %%sp, %%d2\n\t"
132 "movel %5, %%d1\n\t"
133 "movel %1, %%d0\n\t"
134 "trap #0\n\t"
135 "cmpl %%sp, %%d2\n\t"
136 "jeq 1f\n\t"
137 "movel %3, %%sp@-\n\t"
138 "jsr %4@\n\t"
139 "movel %2, %%d0\n\t"
140 "trap #0\n"
141 "1:\n\t"
142 "movel %%d0, %0\n"
143 : "=d" (retval)
144 : "i" (__NR_clone),
145 "i" (__NR_exit),
146 "a" (arg),
147 "a" (fn),
148 "a" (clone_arg)
149 : "cc", "%d0", "%d1", "%d2");
150
151 set_fs(fs);
152 return retval;
153}
154EXPORT_SYMBOL(kernel_thread);
155
156void flush_thread(void)
157{
158#ifdef CONFIG_FPU
159 unsigned long zero = 0;
160#endif
161
162 current->thread.fs = __USER_DS;
163#ifdef CONFIG_FPU
164 if (!FPU_IS_EMU)
165 asm volatile (".chip 68k/68881\n\t"
166 "frestore %0\n\t"
167 ".chip 68k" : : "m" (zero));
168#endif
169}
170
171/*
172 * "m68k_fork()".. By the time we get here, the
173 * non-volatile registers have also been saved on the
174 * stack. We do some ugly pointer stuff here.. (see
175 * also copy_thread)
176 */
177
178asmlinkage int m68k_fork(struct pt_regs *regs)
179{
180 /* fork almost works, enough to trick you into looking elsewhere :-( */
181 return(-EINVAL);
182}
183
184asmlinkage int m68k_vfork(struct pt_regs *regs)
185{
186 return do_fork(CLONE_VFORK | CLONE_VM | SIGCHLD, rdusp(), regs, 0, NULL, NULL);
187}
188
189asmlinkage int m68k_clone(struct pt_regs *regs)
190{
191 unsigned long clone_flags;
192 unsigned long newsp;
193
194 /* syscall2 puts clone_flags in d1 and usp in d2 */
195 clone_flags = regs->d1;
196 newsp = regs->d2;
197 if (!newsp)
198 newsp = rdusp();
199 return do_fork(clone_flags, newsp, regs, 0, NULL, NULL);
200}
201
202int copy_thread(unsigned long clone_flags,
203 unsigned long usp, unsigned long topstk,
204 struct task_struct * p, struct pt_regs * regs)
205{
206 struct pt_regs * childregs;
207 struct switch_stack * childstack, *stack;
208 unsigned long *retp;
209
210 childregs = (struct pt_regs *) (task_stack_page(p) + THREAD_SIZE) - 1;
211
212 *childregs = *regs;
213 childregs->d0 = 0;
214
215 retp = ((unsigned long *) regs);
216 stack = ((struct switch_stack *) retp) - 1;
217
218 childstack = ((struct switch_stack *) childregs) - 1;
219 *childstack = *stack;
220 childstack->retpc = (unsigned long)ret_from_fork;
221
222 p->thread.usp = usp;
223 p->thread.ksp = (unsigned long)childstack;
224
225 if (clone_flags & CLONE_SETTLS)
226 task_thread_info(p)->tp_value = regs->d5;
227
228 /*
229 * Must save the current SFC/DFC value, NOT the value when
230 * the parent was last descheduled - RGH 10-08-96
231 */
232 p->thread.fs = get_fs().seg;
233
234#ifdef CONFIG_FPU
235 if (!FPU_IS_EMU) {
236 /* Copy the current fpu state */
237 asm volatile ("fsave %0" : : "m" (p->thread.fpstate[0]) : "memory");
238
239 if (p->thread.fpstate[0])
240 asm volatile ("fmovemx %/fp0-%/fp7,%0\n\t"
241 "fmoveml %/fpiar/%/fpcr/%/fpsr,%1"
242 : : "m" (p->thread.fp[0]), "m" (p->thread.fpcntl[0])
243 : "memory");
244 /* Restore the state in case the fpu was busy */
245 asm volatile ("frestore %0" : : "m" (p->thread.fpstate[0]));
246 }
247#endif
248
249 return 0;
250}
251
252/* Fill in the fpu structure for a core dump. */
253
254int dump_fpu(struct pt_regs *regs, struct user_m68kfp_struct *fpu)
255{
256#ifdef CONFIG_FPU
257 char fpustate[216];
258
259 if (FPU_IS_EMU) {
260 int i;
261
262 memcpy(fpu->fpcntl, current->thread.fpcntl, 12);
263 memcpy(fpu->fpregs, current->thread.fp, 96);
264 /* Convert internal fpu reg representation
265 * into long double format
266 */
267 for (i = 0; i < 24; i += 3)
268 fpu->fpregs[i] = ((fpu->fpregs[i] & 0xffff0000) << 15) |
269 ((fpu->fpregs[i] & 0x0000ffff) << 16);
270 return 1;
271 }
272
273 /* First dump the fpu context to avoid protocol violation. */
274 asm volatile ("fsave %0" :: "m" (fpustate[0]) : "memory");
275 if (!fpustate[0])
276 return 0;
277
278 asm volatile ("fmovem %/fpiar/%/fpcr/%/fpsr,%0"
279 :: "m" (fpu->fpcntl[0])
280 : "memory");
281 asm volatile ("fmovemx %/fp0-%/fp7,%0"
282 :: "m" (fpu->fpregs[0])
283 : "memory");
284#endif
285 return 1;
286}
287EXPORT_SYMBOL(dump_fpu);
288
289/*
290 * Generic dumping code. Used for panic and debug.
291 */
292void dump(struct pt_regs *fp)
293{
294 unsigned long *sp;
295 unsigned char *tp;
296 int i;
297
298 printk(KERN_EMERG "\nCURRENT PROCESS:\n\n");
299 printk(KERN_EMERG "COMM=%s PID=%d\n", current->comm, current->pid);
300
301 if (current->mm) {
302 printk(KERN_EMERG "TEXT=%08x-%08x DATA=%08x-%08x BSS=%08x-%08x\n",
303 (int) current->mm->start_code,
304 (int) current->mm->end_code,
305 (int) current->mm->start_data,
306 (int) current->mm->end_data,
307 (int) current->mm->end_data,
308 (int) current->mm->brk);
309 printk(KERN_EMERG "USER-STACK=%08x KERNEL-STACK=%08x\n\n",
310 (int) current->mm->start_stack,
311 (int)(((unsigned long) current) + THREAD_SIZE));
312 }
313
314 printk(KERN_EMERG "PC: %08lx\n", fp->pc);
315 printk(KERN_EMERG "SR: %08lx SP: %08lx\n", (long) fp->sr, (long) fp);
316 printk(KERN_EMERG "d0: %08lx d1: %08lx d2: %08lx d3: %08lx\n",
317 fp->d0, fp->d1, fp->d2, fp->d3);
318 printk(KERN_EMERG "d4: %08lx d5: %08lx a0: %08lx a1: %08lx\n",
319 fp->d4, fp->d5, fp->a0, fp->a1);
320 printk(KERN_EMERG "\nUSP: %08x TRAPFRAME: %p\n",
321 (unsigned int) rdusp(), fp);
322
323 printk(KERN_EMERG "\nCODE:");
324 tp = ((unsigned char *) fp->pc) - 0x20;
325 for (sp = (unsigned long *) tp, i = 0; (i < 0x40); i += 4) {
326 if ((i % 0x10) == 0)
327 printk(KERN_EMERG "%p: ", tp + i);
328 printk("%08x ", (int) *sp++);
329 }
330 printk(KERN_EMERG "\n");
331
332 printk(KERN_EMERG "KERNEL STACK:");
333 tp = ((unsigned char *) fp) - 0x40;
334 for (sp = (unsigned long *) tp, i = 0; (i < 0xc0); i += 4) {
335 if ((i % 0x10) == 0)
336 printk(KERN_EMERG "%p: ", tp + i);
337 printk("%08x ", (int) *sp++);
338 }
339 printk(KERN_EMERG "\n");
340
341 printk(KERN_EMERG "USER STACK:");
342 tp = (unsigned char *) (rdusp() - 0x10);
343 for (sp = (unsigned long *) tp, i = 0; (i < 0x80); i += 4) {
344 if ((i % 0x10) == 0)
345 printk(KERN_EMERG "%p: ", tp + i);
346 printk("%08x ", (int) *sp++);
347 }
348 printk(KERN_EMERG "\n");
349}
350
351/*
352 * sys_execve() executes a new program.
353 */
354asmlinkage int sys_execve(const char *name,
355 const char *const *argv,
356 const char *const *envp)
357{
358 int error;
359 char * filename;
360 struct pt_regs *regs = (struct pt_regs *) &name;
361
362 filename = getname(name);
363 error = PTR_ERR(filename);
364 if (IS_ERR(filename))
365 return error;
366 error = do_execve(filename, argv, envp, regs);
367 putname(filename);
368 return error;
369}
370
371unsigned long get_wchan(struct task_struct *p)
372{
373 unsigned long fp, pc;
374 unsigned long stack_page;
375 int count = 0;
376 if (!p || p == current || p->state == TASK_RUNNING)
377 return 0;
378
379 stack_page = (unsigned long)p;
380 fp = ((struct switch_stack *)p->thread.ksp)->a6;
381 do {
382 if (fp < stack_page+sizeof(struct thread_info) ||
383 fp >= THREAD_SIZE-8+stack_page)
384 return 0;
385 pc = ((unsigned long *)fp)[1];
386 if (!in_sched_functions(pc))
387 return pc;
388 fp = *(unsigned long *) fp;
389 } while (count++ < 16);
390 return 0;
391}
392
393/*
394 * Return saved PC of a blocked thread.
395 */
396unsigned long thread_saved_pc(struct task_struct *tsk)
397{
398 struct switch_stack *sw = (struct switch_stack *)tsk->thread.ksp;
399
400 /* Check whether the thread is blocked in resume() */
401 if (in_sched_functions(sw->retpc))
402 return ((unsigned long *)sw->a6)[1];
403 else
404 return sw->retpc;
405}
406
diff --git a/arch/m68k/kernel/ptrace.c b/arch/m68k/kernel/ptrace.c
index 07a417550e94..149a05f8b9ee 100644
--- a/arch/m68k/kernel/ptrace.c
+++ b/arch/m68k/kernel/ptrace.c
@@ -1,5 +1,305 @@
1/*
2 * linux/arch/m68k/kernel/ptrace.c
3 *
4 * Copyright (C) 1994 by Hamish Macdonald
5 * Taken from linux/kernel/ptrace.c and modified for M680x0.
6 * linux/kernel/ptrace.c is by Ross Biro 1/23/92, edited by Linus Torvalds
7 *
8 * This file is subject to the terms and conditions of the GNU General
9 * Public License. See the file COPYING in the main directory of
10 * this archive for more details.
11 */
12
13#include <linux/kernel.h>
14#include <linux/sched.h>
15#include <linux/mm.h>
16#include <linux/smp.h>
17#include <linux/errno.h>
18#include <linux/ptrace.h>
19#include <linux/user.h>
20#include <linux/signal.h>
21#include <linux/tracehook.h>
22
23#include <asm/uaccess.h>
24#include <asm/page.h>
25#include <asm/pgtable.h>
26#include <asm/system.h>
27#include <asm/processor.h>
28
29/*
30 * does not yet catch signals sent when the child dies.
31 * in exit.c or in signal.c.
32 */
33
34/* determines which bits in the SR the user has access to. */
35/* 1 = access 0 = no access */
36#define SR_MASK 0x001f
37
38/* sets the trace bits. */
39#define TRACE_BITS 0xC000
40#define T1_BIT 0x8000
41#define T0_BIT 0x4000
42
43/* Find the stack offset for a register, relative to thread.esp0. */
44#define PT_REG(reg) ((long)&((struct pt_regs *)0)->reg)
45#define SW_REG(reg) ((long)&((struct switch_stack *)0)->reg \
46 - sizeof(struct switch_stack))
47/* Mapping from PT_xxx to the stack offset at which the register is
48 saved. Notice that usp has no stack-slot and needs to be treated
49 specially (see get_reg/put_reg below). */
50static const int regoff[] = {
51 [0] = PT_REG(d1),
52 [1] = PT_REG(d2),
53 [2] = PT_REG(d3),
54 [3] = PT_REG(d4),
55 [4] = PT_REG(d5),
56 [5] = SW_REG(d6),
57 [6] = SW_REG(d7),
58 [7] = PT_REG(a0),
59 [8] = PT_REG(a1),
60 [9] = PT_REG(a2),
61 [10] = SW_REG(a3),
62 [11] = SW_REG(a4),
63 [12] = SW_REG(a5),
64 [13] = SW_REG(a6),
65 [14] = PT_REG(d0),
66 [15] = -1,
67 [16] = PT_REG(orig_d0),
68 [17] = PT_REG(sr),
69 [18] = PT_REG(pc),
70};
71
72/*
73 * Get contents of register REGNO in task TASK.
74 */
75static inline long get_reg(struct task_struct *task, int regno)
76{
77 unsigned long *addr;
78
79 if (regno == PT_USP)
80 addr = &task->thread.usp;
81 else if (regno < ARRAY_SIZE(regoff))
82 addr = (unsigned long *)(task->thread.esp0 + regoff[regno]);
83 else
84 return 0;
85 /* Need to take stkadj into account. */
86 if (regno == PT_SR || regno == PT_PC) {
87 long stkadj = *(long *)(task->thread.esp0 + PT_REG(stkadj));
88 addr = (unsigned long *) ((unsigned long)addr + stkadj);
89 /* The sr is actually a 16 bit register. */
90 if (regno == PT_SR)
91 return *(unsigned short *)addr;
92 }
93 return *addr;
94}
95
96/*
97 * Write contents of register REGNO in task TASK.
98 */
99static inline int put_reg(struct task_struct *task, int regno,
100 unsigned long data)
101{
102 unsigned long *addr;
103
104 if (regno == PT_USP)
105 addr = &task->thread.usp;
106 else if (regno < ARRAY_SIZE(regoff))
107 addr = (unsigned long *)(task->thread.esp0 + regoff[regno]);
108 else
109 return -1;
110 /* Need to take stkadj into account. */
111 if (regno == PT_SR || regno == PT_PC) {
112 long stkadj = *(long *)(task->thread.esp0 + PT_REG(stkadj));
113 addr = (unsigned long *) ((unsigned long)addr + stkadj);
114 /* The sr is actually a 16 bit register. */
115 if (regno == PT_SR) {
116 *(unsigned short *)addr = data;
117 return 0;
118 }
119 }
120 *addr = data;
121 return 0;
122}
123
124/*
125 * Make sure the single step bit is not set.
126 */
127static inline void singlestep_disable(struct task_struct *child)
128{
129 unsigned long tmp = get_reg(child, PT_SR) & ~TRACE_BITS;
130 put_reg(child, PT_SR, tmp);
131 clear_tsk_thread_flag(child, TIF_DELAYED_TRACE);
132}
133
134/*
135 * Called by kernel/ptrace.c when detaching..
136 */
137void ptrace_disable(struct task_struct *child)
138{
139 singlestep_disable(child);
140}
141
142void user_enable_single_step(struct task_struct *child)
143{
144 unsigned long tmp = get_reg(child, PT_SR) & ~TRACE_BITS;
145 put_reg(child, PT_SR, tmp | T1_BIT);
146 set_tsk_thread_flag(child, TIF_DELAYED_TRACE);
147}
148
1#ifdef CONFIG_MMU 149#ifdef CONFIG_MMU
2#include "ptrace_mm.c" 150void user_enable_block_step(struct task_struct *child)
3#else 151{
4#include "ptrace_no.c" 152 unsigned long tmp = get_reg(child, PT_SR) & ~TRACE_BITS;
153 put_reg(child, PT_SR, tmp | T0_BIT);
154}
5#endif 155#endif
156
157void user_disable_single_step(struct task_struct *child)
158{
159 singlestep_disable(child);
160}
161
162long arch_ptrace(struct task_struct *child, long request,
163 unsigned long addr, unsigned long data)
164{
165 unsigned long tmp;
166 int i, ret = 0;
167 int regno = addr >> 2; /* temporary hack. */
168 unsigned long __user *datap = (unsigned long __user *) data;
169
170 switch (request) {
171 /* read the word at location addr in the USER area. */
172 case PTRACE_PEEKUSR:
173 if (addr & 3)
174 goto out_eio;
175
176 if (regno >= 0 && regno < 19) {
177 tmp = get_reg(child, regno);
178 } else if (regno >= 21 && regno < 49) {
179 tmp = child->thread.fp[regno - 21];
180 /* Convert internal fpu reg representation
181 * into long double format
182 */
183 if (FPU_IS_EMU && (regno < 45) && !(regno % 3))
184 tmp = ((tmp & 0xffff0000) << 15) |
185 ((tmp & 0x0000ffff) << 16);
186#ifndef CONFIG_MMU
187 } else if (regno == 49) {
188 tmp = child->mm->start_code;
189 } else if (regno == 50) {
190 tmp = child->mm->start_data;
191 } else if (regno == 51) {
192 tmp = child->mm->end_code;
193#endif
194 } else
195 goto out_eio;
196 ret = put_user(tmp, datap);
197 break;
198
199 case PTRACE_POKEUSR:
200 /* write the word at location addr in the USER area */
201 if (addr & 3)
202 goto out_eio;
203
204 if (regno == PT_SR) {
205 data &= SR_MASK;
206 data |= get_reg(child, PT_SR) & ~SR_MASK;
207 }
208 if (regno >= 0 && regno < 19) {
209 if (put_reg(child, regno, data))
210 goto out_eio;
211 } else if (regno >= 21 && regno < 48) {
212 /* Convert long double format
213 * into internal fpu reg representation
214 */
215 if (FPU_IS_EMU && (regno < 45) && !(regno % 3)) {
216 data <<= 15;
217 data = (data & 0xffff0000) |
218 ((data & 0x0000ffff) >> 1);
219 }
220 child->thread.fp[regno - 21] = data;
221 } else
222 goto out_eio;
223 break;
224
225 case PTRACE_GETREGS: /* Get all gp regs from the child. */
226 for (i = 0; i < 19; i++) {
227 tmp = get_reg(child, i);
228 ret = put_user(tmp, datap);
229 if (ret)
230 break;
231 datap++;
232 }
233 break;
234
235 case PTRACE_SETREGS: /* Set all gp regs in the child. */
236 for (i = 0; i < 19; i++) {
237 ret = get_user(tmp, datap);
238 if (ret)
239 break;
240 if (i == PT_SR) {
241 tmp &= SR_MASK;
242 tmp |= get_reg(child, PT_SR) & ~SR_MASK;
243 }
244 put_reg(child, i, tmp);
245 datap++;
246 }
247 break;
248
249 case PTRACE_GETFPREGS: /* Get the child FPU state. */
250 if (copy_to_user(datap, &child->thread.fp,
251 sizeof(struct user_m68kfp_struct)))
252 ret = -EFAULT;
253 break;
254
255 case PTRACE_SETFPREGS: /* Set the child FPU state. */
256 if (copy_from_user(&child->thread.fp, datap,
257 sizeof(struct user_m68kfp_struct)))
258 ret = -EFAULT;
259 break;
260
261 case PTRACE_GET_THREAD_AREA:
262 ret = put_user(task_thread_info(child)->tp_value, datap);
263 break;
264
265 default:
266 ret = ptrace_request(child, request, addr, data);
267 break;
268 }
269
270 return ret;
271out_eio:
272 return -EIO;
273}
274
275asmlinkage void syscall_trace(void)
276{
277 ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD)
278 ? 0x80 : 0));
279 /*
280 * this isn't the same as continuing with a signal, but it will do
281 * for normal use. strace only continues with a signal if the
282 * stopping signal is not SIGTRAP. -brl
283 */
284 if (current->exit_code) {
285 send_sig(current->exit_code, current, 1);
286 current->exit_code = 0;
287 }
288}
289
290#ifdef CONFIG_COLDFIRE
291asmlinkage int syscall_trace_enter(void)
292{
293 int ret = 0;
294
295 if (test_thread_flag(TIF_SYSCALL_TRACE))
296 ret = tracehook_report_syscall_entry(task_pt_regs(current));
297 return ret;
298}
299
300asmlinkage void syscall_trace_leave(void)
301{
302 if (test_thread_flag(TIF_SYSCALL_TRACE))
303 tracehook_report_syscall_exit(task_pt_regs(current), 0);
304}
305#endif /* CONFIG_COLDFIRE */
diff --git a/arch/m68k/kernel/ptrace_mm.c b/arch/m68k/kernel/ptrace_mm.c
deleted file mode 100644
index 7bc999b73529..000000000000
--- a/arch/m68k/kernel/ptrace_mm.c
+++ /dev/null
@@ -1,295 +0,0 @@
1/*
2 * linux/arch/m68k/kernel/ptrace.c
3 *
4 * Copyright (C) 1994 by Hamish Macdonald
5 * Taken from linux/kernel/ptrace.c and modified for M680x0.
6 * linux/kernel/ptrace.c is by Ross Biro 1/23/92, edited by Linus Torvalds
7 *
8 * This file is subject to the terms and conditions of the GNU General
9 * Public License. See the file COPYING in the main directory of
10 * this archive for more details.
11 */
12
13#include <linux/kernel.h>
14#include <linux/sched.h>
15#include <linux/mm.h>
16#include <linux/smp.h>
17#include <linux/errno.h>
18#include <linux/ptrace.h>
19#include <linux/user.h>
20#include <linux/signal.h>
21#include <linux/tracehook.h>
22
23#include <asm/uaccess.h>
24#include <asm/page.h>
25#include <asm/pgtable.h>
26#include <asm/system.h>
27#include <asm/processor.h>
28
29/*
30 * does not yet catch signals sent when the child dies.
31 * in exit.c or in signal.c.
32 */
33
34/* determines which bits in the SR the user has access to. */
35/* 1 = access 0 = no access */
36#define SR_MASK 0x001f
37
38/* sets the trace bits. */
39#define TRACE_BITS 0xC000
40#define T1_BIT 0x8000
41#define T0_BIT 0x4000
42
43/* Find the stack offset for a register, relative to thread.esp0. */
44#define PT_REG(reg) ((long)&((struct pt_regs *)0)->reg)
45#define SW_REG(reg) ((long)&((struct switch_stack *)0)->reg \
46 - sizeof(struct switch_stack))
47/* Mapping from PT_xxx to the stack offset at which the register is
48 saved. Notice that usp has no stack-slot and needs to be treated
49 specially (see get_reg/put_reg below). */
50static const int regoff[] = {
51 [0] = PT_REG(d1),
52 [1] = PT_REG(d2),
53 [2] = PT_REG(d3),
54 [3] = PT_REG(d4),
55 [4] = PT_REG(d5),
56 [5] = SW_REG(d6),
57 [6] = SW_REG(d7),
58 [7] = PT_REG(a0),
59 [8] = PT_REG(a1),
60 [9] = PT_REG(a2),
61 [10] = SW_REG(a3),
62 [11] = SW_REG(a4),
63 [12] = SW_REG(a5),
64 [13] = SW_REG(a6),
65 [14] = PT_REG(d0),
66 [15] = -1,
67 [16] = PT_REG(orig_d0),
68 [17] = PT_REG(sr),
69 [18] = PT_REG(pc),
70};
71
72/*
73 * Get contents of register REGNO in task TASK.
74 */
75static inline long get_reg(struct task_struct *task, int regno)
76{
77 unsigned long *addr;
78
79 if (regno == PT_USP)
80 addr = &task->thread.usp;
81 else if (regno < ARRAY_SIZE(regoff))
82 addr = (unsigned long *)(task->thread.esp0 + regoff[regno]);
83 else
84 return 0;
85 /* Need to take stkadj into account. */
86 if (regno == PT_SR || regno == PT_PC) {
87 long stkadj = *(long *)(task->thread.esp0 + PT_REG(stkadj));
88 addr = (unsigned long *) ((unsigned long)addr + stkadj);
89 /* The sr is actually a 16 bit register. */
90 if (regno == PT_SR)
91 return *(unsigned short *)addr;
92 }
93 return *addr;
94}
95
96/*
97 * Write contents of register REGNO in task TASK.
98 */
99static inline int put_reg(struct task_struct *task, int regno,
100 unsigned long data)
101{
102 unsigned long *addr;
103
104 if (regno == PT_USP)
105 addr = &task->thread.usp;
106 else if (regno < ARRAY_SIZE(regoff))
107 addr = (unsigned long *)(task->thread.esp0 + regoff[regno]);
108 else
109 return -1;
110 /* Need to take stkadj into account. */
111 if (regno == PT_SR || regno == PT_PC) {
112 long stkadj = *(long *)(task->thread.esp0 + PT_REG(stkadj));
113 addr = (unsigned long *) ((unsigned long)addr + stkadj);
114 /* The sr is actually a 16 bit register. */
115 if (regno == PT_SR) {
116 *(unsigned short *)addr = data;
117 return 0;
118 }
119 }
120 *addr = data;
121 return 0;
122}
123
124/*
125 * Make sure the single step bit is not set.
126 */
127static inline void singlestep_disable(struct task_struct *child)
128{
129 unsigned long tmp = get_reg(child, PT_SR) & ~TRACE_BITS;
130 put_reg(child, PT_SR, tmp);
131 clear_tsk_thread_flag(child, TIF_DELAYED_TRACE);
132}
133
134/*
135 * Called by kernel/ptrace.c when detaching..
136 */
137void ptrace_disable(struct task_struct *child)
138{
139 singlestep_disable(child);
140}
141
142void user_enable_single_step(struct task_struct *child)
143{
144 unsigned long tmp = get_reg(child, PT_SR) & ~TRACE_BITS;
145 put_reg(child, PT_SR, tmp | T1_BIT);
146 set_tsk_thread_flag(child, TIF_DELAYED_TRACE);
147}
148
149void user_enable_block_step(struct task_struct *child)
150{
151 unsigned long tmp = get_reg(child, PT_SR) & ~TRACE_BITS;
152 put_reg(child, PT_SR, tmp | T0_BIT);
153}
154
155void user_disable_single_step(struct task_struct *child)
156{
157 singlestep_disable(child);
158}
159
160long arch_ptrace(struct task_struct *child, long request,
161 unsigned long addr, unsigned long data)
162{
163 unsigned long tmp;
164 int i, ret = 0;
165 int regno = addr >> 2; /* temporary hack. */
166 unsigned long __user *datap = (unsigned long __user *) data;
167
168 switch (request) {
169 /* read the word at location addr in the USER area. */
170 case PTRACE_PEEKUSR:
171 if (addr & 3)
172 goto out_eio;
173
174 if (regno >= 0 && regno < 19) {
175 tmp = get_reg(child, regno);
176 } else if (regno >= 21 && regno < 49) {
177 tmp = child->thread.fp[regno - 21];
178 /* Convert internal fpu reg representation
179 * into long double format
180 */
181 if (FPU_IS_EMU && (regno < 45) && !(regno % 3))
182 tmp = ((tmp & 0xffff0000) << 15) |
183 ((tmp & 0x0000ffff) << 16);
184 } else
185 goto out_eio;
186 ret = put_user(tmp, datap);
187 break;
188
189 case PTRACE_POKEUSR:
190 /* write the word at location addr in the USER area */
191 if (addr & 3)
192 goto out_eio;
193
194 if (regno == PT_SR) {
195 data &= SR_MASK;
196 data |= get_reg(child, PT_SR) & ~SR_MASK;
197 }
198 if (regno >= 0 && regno < 19) {
199 if (put_reg(child, regno, data))
200 goto out_eio;
201 } else if (regno >= 21 && regno < 48) {
202 /* Convert long double format
203 * into internal fpu reg representation
204 */
205 if (FPU_IS_EMU && (regno < 45) && !(regno % 3)) {
206 data <<= 15;
207 data = (data & 0xffff0000) |
208 ((data & 0x0000ffff) >> 1);
209 }
210 child->thread.fp[regno - 21] = data;
211 } else
212 goto out_eio;
213 break;
214
215 case PTRACE_GETREGS: /* Get all gp regs from the child. */
216 for (i = 0; i < 19; i++) {
217 tmp = get_reg(child, i);
218 ret = put_user(tmp, datap);
219 if (ret)
220 break;
221 datap++;
222 }
223 break;
224
225 case PTRACE_SETREGS: /* Set all gp regs in the child. */
226 for (i = 0; i < 19; i++) {
227 ret = get_user(tmp, datap);
228 if (ret)
229 break;
230 if (i == PT_SR) {
231 tmp &= SR_MASK;
232 tmp |= get_reg(child, PT_SR) & ~SR_MASK;
233 }
234 put_reg(child, i, tmp);
235 datap++;
236 }
237 break;
238
239 case PTRACE_GETFPREGS: /* Get the child FPU state. */
240 if (copy_to_user(datap, &child->thread.fp,
241 sizeof(struct user_m68kfp_struct)))
242 ret = -EFAULT;
243 break;
244
245 case PTRACE_SETFPREGS: /* Set the child FPU state. */
246 if (copy_from_user(&child->thread.fp, datap,
247 sizeof(struct user_m68kfp_struct)))
248 ret = -EFAULT;
249 break;
250
251 case PTRACE_GET_THREAD_AREA:
252 ret = put_user(task_thread_info(child)->tp_value, datap);
253 break;
254
255 default:
256 ret = ptrace_request(child, request, addr, data);
257 break;
258 }
259
260 return ret;
261out_eio:
262 return -EIO;
263}
264
265asmlinkage void syscall_trace(void)
266{
267 ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD)
268 ? 0x80 : 0));
269 /*
270 * this isn't the same as continuing with a signal, but it will do
271 * for normal use. strace only continues with a signal if the
272 * stopping signal is not SIGTRAP. -brl
273 */
274 if (current->exit_code) {
275 send_sig(current->exit_code, current, 1);
276 current->exit_code = 0;
277 }
278}
279
280#ifdef CONFIG_COLDFIRE
281asmlinkage int syscall_trace_enter(void)
282{
283 int ret = 0;
284
285 if (test_thread_flag(TIF_SYSCALL_TRACE))
286 ret = tracehook_report_syscall_entry(task_pt_regs(current));
287 return ret;
288}
289
290asmlinkage void syscall_trace_leave(void)
291{
292 if (test_thread_flag(TIF_SYSCALL_TRACE))
293 tracehook_report_syscall_exit(task_pt_regs(current), 0);
294}
295#endif /* CONFIG_COLDFIRE */
diff --git a/arch/m68k/kernel/ptrace_no.c b/arch/m68k/kernel/ptrace_no.c
deleted file mode 100644
index 6709fb707335..000000000000
--- a/arch/m68k/kernel/ptrace_no.c
+++ /dev/null
@@ -1,255 +0,0 @@
1/*
2 * linux/arch/m68knommu/kernel/ptrace.c
3 *
4 * Copyright (C) 1994 by Hamish Macdonald
5 * Taken from linux/kernel/ptrace.c and modified for M680x0.
6 * linux/kernel/ptrace.c is by Ross Biro 1/23/92, edited by Linus Torvalds
7 *
8 * This file is subject to the terms and conditions of the GNU General
9 * Public License. See the file COPYING in the main directory of
10 * this archive for more details.
11 */
12
13#include <linux/kernel.h>
14#include <linux/sched.h>
15#include <linux/mm.h>
16#include <linux/smp.h>
17#include <linux/errno.h>
18#include <linux/ptrace.h>
19#include <linux/user.h>
20#include <linux/signal.h>
21#include <linux/tracehook.h>
22
23#include <asm/uaccess.h>
24#include <asm/page.h>
25#include <asm/pgtable.h>
26#include <asm/system.h>
27#include <asm/processor.h>
28
29/*
30 * does not yet catch signals sent when the child dies.
31 * in exit.c or in signal.c.
32 */
33
34/* determines which bits in the SR the user has access to. */
35/* 1 = access 0 = no access */
36#define SR_MASK 0x001f
37
38/* sets the trace bits. */
39#define TRACE_BITS 0x8000
40
41/* Find the stack offset for a register, relative to thread.esp0. */
42#define PT_REG(reg) ((long)&((struct pt_regs *)0)->reg)
43#define SW_REG(reg) ((long)&((struct switch_stack *)0)->reg \
44 - sizeof(struct switch_stack))
45/* Mapping from PT_xxx to the stack offset at which the register is
46 saved. Notice that usp has no stack-slot and needs to be treated
47 specially (see get_reg/put_reg below). */
48static int regoff[] = {
49 PT_REG(d1), PT_REG(d2), PT_REG(d3), PT_REG(d4),
50 PT_REG(d5), SW_REG(d6), SW_REG(d7), PT_REG(a0),
51 PT_REG(a1), PT_REG(a2), SW_REG(a3), SW_REG(a4),
52 SW_REG(a5), SW_REG(a6), PT_REG(d0), -1,
53 PT_REG(orig_d0), PT_REG(sr), PT_REG(pc),
54};
55
56/*
57 * Get contents of register REGNO in task TASK.
58 */
59static inline long get_reg(struct task_struct *task, int regno)
60{
61 unsigned long *addr;
62
63 if (regno == PT_USP)
64 addr = &task->thread.usp;
65 else if (regno < ARRAY_SIZE(regoff))
66 addr = (unsigned long *)(task->thread.esp0 + regoff[regno]);
67 else
68 return 0;
69 return *addr;
70}
71
72/*
73 * Write contents of register REGNO in task TASK.
74 */
75static inline int put_reg(struct task_struct *task, int regno,
76 unsigned long data)
77{
78 unsigned long *addr;
79
80 if (regno == PT_USP)
81 addr = &task->thread.usp;
82 else if (regno < ARRAY_SIZE(regoff))
83 addr = (unsigned long *) (task->thread.esp0 + regoff[regno]);
84 else
85 return -1;
86 *addr = data;
87 return 0;
88}
89
90void user_enable_single_step(struct task_struct *task)
91{
92 unsigned long srflags;
93 srflags = get_reg(task, PT_SR) | (TRACE_BITS << 16);
94 put_reg(task, PT_SR, srflags);
95}
96
97void user_disable_single_step(struct task_struct *task)
98{
99 unsigned long srflags;
100 srflags = get_reg(task, PT_SR) & ~(TRACE_BITS << 16);
101 put_reg(task, PT_SR, srflags);
102}
103
104/*
105 * Called by kernel/ptrace.c when detaching..
106 *
107 * Make sure the single step bit is not set.
108 */
109void ptrace_disable(struct task_struct *child)
110{
111 /* make sure the single step bit is not set. */
112 user_disable_single_step(child);
113}
114
115long arch_ptrace(struct task_struct *child, long request,
116 unsigned long addr, unsigned long data)
117{
118 int ret;
119 int regno = addr >> 2;
120 unsigned long __user *datap = (unsigned long __user *) data;
121
122 switch (request) {
123 /* read the word at location addr in the USER area. */
124 case PTRACE_PEEKUSR: {
125 unsigned long tmp;
126
127 ret = -EIO;
128 if ((addr & 3) || addr > sizeof(struct user) - 3)
129 break;
130
131 tmp = 0; /* Default return condition */
132 ret = -EIO;
133 if (regno < 19) {
134 tmp = get_reg(child, regno);
135 if (regno == PT_SR)
136 tmp >>= 16;
137 } else if (regno >= 21 && regno < 49) {
138 tmp = child->thread.fp[regno - 21];
139 } else if (regno == 49) {
140 tmp = child->mm->start_code;
141 } else if (regno == 50) {
142 tmp = child->mm->start_data;
143 } else if (regno == 51) {
144 tmp = child->mm->end_code;
145 } else
146 break;
147 ret = put_user(tmp, datap);
148 break;
149 }
150
151 case PTRACE_POKEUSR: /* write the word at location addr in the USER area */
152 ret = -EIO;
153 if ((addr & 3) || addr > sizeof(struct user) - 3)
154 break;
155
156 if (regno == PT_SR) {
157 data &= SR_MASK;
158 data <<= 16;
159 data |= get_reg(child, PT_SR) & ~(SR_MASK << 16);
160 }
161 if (regno < 19) {
162 if (put_reg(child, regno, data))
163 break;
164 ret = 0;
165 break;
166 }
167 if (regno >= 21 && regno < 48)
168 {
169 child->thread.fp[regno - 21] = data;
170 ret = 0;
171 }
172 break;
173
174 case PTRACE_GETREGS: { /* Get all gp regs from the child. */
175 int i;
176 unsigned long tmp;
177 for (i = 0; i < 19; i++) {
178 tmp = get_reg(child, i);
179 if (i == PT_SR)
180 tmp >>= 16;
181 if (put_user(tmp, datap)) {
182 ret = -EFAULT;
183 break;
184 }
185 datap++;
186 }
187 ret = 0;
188 break;
189 }
190
191 case PTRACE_SETREGS: { /* Set all gp regs in the child. */
192 int i;
193 unsigned long tmp;
194 for (i = 0; i < 19; i++) {
195 if (get_user(tmp, datap)) {
196 ret = -EFAULT;
197 break;
198 }
199 if (i == PT_SR) {
200 tmp &= SR_MASK;
201 tmp <<= 16;
202 tmp |= get_reg(child, PT_SR) & ~(SR_MASK << 16);
203 }
204 put_reg(child, i, tmp);
205 datap++;
206 }
207 ret = 0;
208 break;
209 }
210
211#ifdef PTRACE_GETFPREGS
212 case PTRACE_GETFPREGS: { /* Get the child FPU state. */
213 ret = 0;
214 if (copy_to_user(datap, &child->thread.fp,
215 sizeof(struct user_m68kfp_struct)))
216 ret = -EFAULT;
217 break;
218 }
219#endif
220
221#ifdef PTRACE_SETFPREGS
222 case PTRACE_SETFPREGS: { /* Set the child FPU state. */
223 ret = 0;
224 if (copy_from_user(&child->thread.fp, datap,
225 sizeof(struct user_m68kfp_struct)))
226 ret = -EFAULT;
227 break;
228 }
229#endif
230
231 case PTRACE_GET_THREAD_AREA:
232 ret = put_user(task_thread_info(child)->tp_value, datap);
233 break;
234
235 default:
236 ret = ptrace_request(child, request, addr, data);
237 break;
238 }
239 return ret;
240}
241
242asmlinkage int syscall_trace_enter(void)
243{
244 int ret = 0;
245
246 if (test_thread_flag(TIF_SYSCALL_TRACE))
247 ret = tracehook_report_syscall_entry(task_pt_regs(current));
248 return ret;
249}
250
251asmlinkage void syscall_trace_leave(void)
252{
253 if (test_thread_flag(TIF_SYSCALL_TRACE))
254 tracehook_report_syscall_exit(task_pt_regs(current), 0);
255}
diff --git a/arch/m68k/kernel/setup_no.c b/arch/m68k/kernel/setup_no.c
index ca3df0dc7e88..7dc186b7a85f 100644
--- a/arch/m68k/kernel/setup_no.c
+++ b/arch/m68k/kernel/setup_no.c
@@ -31,6 +31,7 @@
31#include <linux/init.h> 31#include <linux/init.h>
32#include <linux/initrd.h> 32#include <linux/initrd.h>
33#include <linux/root_dev.h> 33#include <linux/root_dev.h>
34#include <linux/rtc.h>
34 35
35#include <asm/setup.h> 36#include <asm/setup.h>
36#include <asm/irq.h> 37#include <asm/irq.h>
@@ -47,7 +48,9 @@ EXPORT_SYMBOL(memory_end);
47char __initdata command_line[COMMAND_LINE_SIZE]; 48char __initdata command_line[COMMAND_LINE_SIZE];
48 49
49/* machine dependent timer functions */ 50/* machine dependent timer functions */
51void (*mach_sched_init)(irq_handler_t handler) __initdata = NULL;
50int (*mach_set_clock_mmss)(unsigned long); 52int (*mach_set_clock_mmss)(unsigned long);
53int (*mach_hwclk) (int, struct rtc_time*);
51 54
52/* machine dependent reboot functions */ 55/* machine dependent reboot functions */
53void (*mach_reset)(void); 56void (*mach_reset)(void);
diff --git a/arch/m68k/kernel/time.c b/arch/m68k/kernel/time.c
index 75ab79b3bdeb..d7deb7fc7eb5 100644
--- a/arch/m68k/kernel/time.c
+++ b/arch/m68k/kernel/time.c
@@ -1,5 +1,111 @@
1#if defined(CONFIG_MMU) && !defined(CONFIG_COLDFIRE) 1/*
2#include "time_mm.c" 2 * linux/arch/m68k/kernel/time.c
3#else 3 *
4#include "time_no.c" 4 * Copyright (C) 1991, 1992, 1995 Linus Torvalds
5#endif 5 *
6 * This file contains the m68k-specific time handling details.
7 * Most of the stuff is located in the machine specific files.
8 *
9 * 1997-09-10 Updated NTP code according to technical memorandum Jan '96
10 * "A Kernel Model for Precision Timekeeping" by Dave Mills
11 */
12
13#include <linux/errno.h>
14#include <linux/module.h>
15#include <linux/sched.h>
16#include <linux/kernel.h>
17#include <linux/param.h>
18#include <linux/string.h>
19#include <linux/mm.h>
20#include <linux/rtc.h>
21#include <linux/platform_device.h>
22
23#include <asm/machdep.h>
24#include <asm/io.h>
25#include <asm/irq_regs.h>
26
27#include <linux/time.h>
28#include <linux/timex.h>
29#include <linux/profile.h>
30
31/*
32 * timer_interrupt() needs to keep up the real-time clock,
33 * as well as call the "xtime_update()" routine every clocktick
34 */
35static irqreturn_t timer_interrupt(int irq, void *dummy)
36{
37 xtime_update(1);
38 update_process_times(user_mode(get_irq_regs()));
39 profile_tick(CPU_PROFILING);
40
41#ifdef CONFIG_HEARTBEAT
42 /* use power LED as a heartbeat instead -- much more useful
43 for debugging -- based on the version for PReP by Cort */
44 /* acts like an actual heart beat -- ie thump-thump-pause... */
45 if (mach_heartbeat) {
46 static unsigned cnt = 0, period = 0, dist = 0;
47
48 if (cnt == 0 || cnt == dist)
49 mach_heartbeat( 1 );
50 else if (cnt == 7 || cnt == dist+7)
51 mach_heartbeat( 0 );
52
53 if (++cnt > period) {
54 cnt = 0;
55 /* The hyperbolic function below modifies the heartbeat period
56 * length in dependency of the current (5min) load. It goes
57 * through the points f(0)=126, f(1)=86, f(5)=51,
58 * f(inf)->30. */
59 period = ((672<<FSHIFT)/(5*avenrun[0]+(7<<FSHIFT))) + 30;
60 dist = period / 4;
61 }
62 }
63#endif /* CONFIG_HEARTBEAT */
64 return IRQ_HANDLED;
65}
66
67void read_persistent_clock(struct timespec *ts)
68{
69 struct rtc_time time;
70 ts->tv_sec = 0;
71 ts->tv_nsec = 0;
72
73 if (mach_hwclk) {
74 mach_hwclk(0, &time);
75
76 if ((time.tm_year += 1900) < 1970)
77 time.tm_year += 100;
78 ts->tv_sec = mktime(time.tm_year, time.tm_mon, time.tm_mday,
79 time.tm_hour, time.tm_min, time.tm_sec);
80 }
81}
82
83void __init time_init(void)
84{
85 mach_sched_init(timer_interrupt);
86}
87
88#ifdef CONFIG_M68KCLASSIC
89
90u32 arch_gettimeoffset(void)
91{
92 return mach_gettimeoffset() * 1000;
93}
94
95static int __init rtc_init(void)
96{
97 struct platform_device *pdev;
98
99 if (!mach_hwclk)
100 return -ENODEV;
101
102 pdev = platform_device_register_simple("rtc-generic", -1, NULL, 0);
103 if (IS_ERR(pdev))
104 return PTR_ERR(pdev);
105
106 return 0;
107}
108
109module_init(rtc_init);
110
111#endif /* CONFIG_M68KCLASSIC */
diff --git a/arch/m68k/kernel/time_mm.c b/arch/m68k/kernel/time_mm.c
deleted file mode 100644
index 18b34ee5db3b..000000000000
--- a/arch/m68k/kernel/time_mm.c
+++ /dev/null
@@ -1,114 +0,0 @@
1/*
2 * linux/arch/m68k/kernel/time.c
3 *
4 * Copyright (C) 1991, 1992, 1995 Linus Torvalds
5 *
6 * This file contains the m68k-specific time handling details.
7 * Most of the stuff is located in the machine specific files.
8 *
9 * 1997-09-10 Updated NTP code according to technical memorandum Jan '96
10 * "A Kernel Model for Precision Timekeeping" by Dave Mills
11 */
12
13#include <linux/errno.h>
14#include <linux/module.h>
15#include <linux/sched.h>
16#include <linux/kernel.h>
17#include <linux/param.h>
18#include <linux/string.h>
19#include <linux/mm.h>
20#include <linux/rtc.h>
21#include <linux/platform_device.h>
22
23#include <asm/machdep.h>
24#include <asm/io.h>
25#include <asm/irq_regs.h>
26
27#include <linux/time.h>
28#include <linux/timex.h>
29#include <linux/profile.h>
30
31static inline int set_rtc_mmss(unsigned long nowtime)
32{
33 if (mach_set_clock_mmss)
34 return mach_set_clock_mmss (nowtime);
35 return -1;
36}
37
38/*
39 * timer_interrupt() needs to keep up the real-time clock,
40 * as well as call the "xtime_update()" routine every clocktick
41 */
42static irqreturn_t timer_interrupt(int irq, void *dummy)
43{
44 xtime_update(1);
45 update_process_times(user_mode(get_irq_regs()));
46 profile_tick(CPU_PROFILING);
47
48#ifdef CONFIG_HEARTBEAT
49 /* use power LED as a heartbeat instead -- much more useful
50 for debugging -- based on the version for PReP by Cort */
51 /* acts like an actual heart beat -- ie thump-thump-pause... */
52 if (mach_heartbeat) {
53 static unsigned cnt = 0, period = 0, dist = 0;
54
55 if (cnt == 0 || cnt == dist)
56 mach_heartbeat( 1 );
57 else if (cnt == 7 || cnt == dist+7)
58 mach_heartbeat( 0 );
59
60 if (++cnt > period) {
61 cnt = 0;
62 /* The hyperbolic function below modifies the heartbeat period
63 * length in dependency of the current (5min) load. It goes
64 * through the points f(0)=126, f(1)=86, f(5)=51,
65 * f(inf)->30. */
66 period = ((672<<FSHIFT)/(5*avenrun[0]+(7<<FSHIFT))) + 30;
67 dist = period / 4;
68 }
69 }
70#endif /* CONFIG_HEARTBEAT */
71 return IRQ_HANDLED;
72}
73
74void read_persistent_clock(struct timespec *ts)
75{
76 struct rtc_time time;
77 ts->tv_sec = 0;
78 ts->tv_nsec = 0;
79
80 if (mach_hwclk) {
81 mach_hwclk(0, &time);
82
83 if ((time.tm_year += 1900) < 1970)
84 time.tm_year += 100;
85 ts->tv_sec = mktime(time.tm_year, time.tm_mon, time.tm_mday,
86 time.tm_hour, time.tm_min, time.tm_sec);
87 }
88}
89
90void __init time_init(void)
91{
92 mach_sched_init(timer_interrupt);
93}
94
95u32 arch_gettimeoffset(void)
96{
97 return mach_gettimeoffset() * 1000;
98}
99
100static int __init rtc_init(void)
101{
102 struct platform_device *pdev;
103
104 if (!mach_hwclk)
105 return -ENODEV;
106
107 pdev = platform_device_register_simple("rtc-generic", -1, NULL, 0);
108 if (IS_ERR(pdev))
109 return PTR_ERR(pdev);
110
111 return 0;
112}
113
114module_init(rtc_init);
diff --git a/arch/m68k/kernel/time_no.c b/arch/m68k/kernel/time_no.c
deleted file mode 100644
index 3ef0f7768dcd..000000000000
--- a/arch/m68k/kernel/time_no.c
+++ /dev/null
@@ -1,90 +0,0 @@
1/*
2 * linux/arch/m68knommu/kernel/time.c
3 *
4 * Copyright (C) 1991, 1992, 1995 Linus Torvalds
5 *
6 * This file contains the m68k-specific time handling details.
7 * Most of the stuff is located in the machine specific files.
8 *
9 * 1997-09-10 Updated NTP code according to technical memorandum Jan '96
10 * "A Kernel Model for Precision Timekeeping" by Dave Mills
11 */
12
13#include <linux/errno.h>
14#include <linux/module.h>
15#include <linux/sched.h>
16#include <linux/kernel.h>
17#include <linux/param.h>
18#include <linux/string.h>
19#include <linux/mm.h>
20#include <linux/profile.h>
21#include <linux/time.h>
22#include <linux/timex.h>
23
24#include <asm/machdep.h>
25#include <asm/irq_regs.h>
26
27#define TICK_SIZE (tick_nsec / 1000)
28
29/* machine dependent timer functions */
30void (*mach_gettod)(int*, int*, int*, int*, int*, int*);
31
32static inline int set_rtc_mmss(unsigned long nowtime)
33{
34 if (mach_set_clock_mmss)
35 return mach_set_clock_mmss (nowtime);
36 return -1;
37}
38
39#ifndef CONFIG_GENERIC_CLOCKEVENTS
40/*
41 * timer_interrupt() needs to keep up the real-time clock,
42 * as well as call the "xtime_update()" routine every clocktick
43 */
44irqreturn_t arch_timer_interrupt(int irq, void *dummy)
45{
46
47 if (current->pid)
48 profile_tick(CPU_PROFILING);
49
50 xtime_update(1);
51
52 update_process_times(user_mode(get_irq_regs()));
53
54 return(IRQ_HANDLED);
55}
56#endif
57
58static unsigned long read_rtc_mmss(void)
59{
60 unsigned int year, mon, day, hour, min, sec;
61
62 if (mach_gettod) {
63 mach_gettod(&year, &mon, &day, &hour, &min, &sec);
64 if ((year += 1900) < 1970)
65 year += 100;
66 } else {
67 year = 1970;
68 mon = day = 1;
69 hour = min = sec = 0;
70 }
71
72
73 return mktime(year, mon, day, hour, min, sec);
74}
75
76void read_persistent_clock(struct timespec *ts)
77{
78 ts->tv_sec = read_rtc_mmss();
79 ts->tv_nsec = 0;
80}
81
82int update_persistent_clock(struct timespec now)
83{
84 return set_rtc_mmss(now.tv_sec);
85}
86
87void time_init(void)
88{
89 hw_timer_init();
90}
diff --git a/arch/m68k/kernel/vmlinux-nommu.lds b/arch/m68k/kernel/vmlinux-nommu.lds
index 8e66ccb0935e..40e02d9c38b4 100644
--- a/arch/m68k/kernel/vmlinux-nommu.lds
+++ b/arch/m68k/kernel/vmlinux-nommu.lds
@@ -1,195 +1,93 @@
1/* 1/*
2 * vmlinux.lds.S -- master linker script for m68knommu arch 2 * vmlinux.lds.S -- master linker script for m68knommu arch
3 * 3 *
4 * (C) Copyright 2002-2006, Greg Ungerer <gerg@snapgear.com> 4 * (C) Copyright 2002-2012, Greg Ungerer <gerg@snapgear.com>
5 * 5 *
6 * This linker script is equipped to build either ROM loaded or RAM 6 * This linker script is equipped to build either ROM loaded or RAM
7 * run kernels. 7 * run kernels.
8 */ 8 */
9 9
10#include <asm-generic/vmlinux.lds.h>
11#include <asm/page.h>
12#include <asm/thread_info.h>
13
14#if defined(CONFIG_RAMKERNEL) 10#if defined(CONFIG_RAMKERNEL)
15#define RAM_START CONFIG_KERNELBASE 11#define KTEXT_ADDR CONFIG_KERNELBASE
16#define RAM_LENGTH (CONFIG_RAMBASE + CONFIG_RAMSIZE - CONFIG_KERNELBASE)
17#define TEXT ram
18#define DATA ram
19#define INIT ram
20#define BSSS ram
21#endif
22#if defined(CONFIG_ROMKERNEL) || defined(CONFIG_HIMEMKERNEL)
23#define RAM_START CONFIG_RAMBASE
24#define RAM_LENGTH CONFIG_RAMSIZE
25#define ROMVEC_START CONFIG_ROMVEC
26#define ROMVEC_LENGTH CONFIG_ROMVECSIZE
27#define ROM_START CONFIG_ROMSTART
28#define ROM_LENGTH CONFIG_ROMSIZE
29#define TEXT rom
30#define DATA ram
31#define INIT ram
32#define BSSS ram
33#endif 12#endif
34 13#if defined(CONFIG_ROMKERNEL)
35#ifndef DATA_ADDR 14#define KTEXT_ADDR CONFIG_ROMSTART
36#define DATA_ADDR 15#define KDATA_ADDR CONFIG_KERNELBASE
16#define LOAD_OFFSET KDATA_ADDR + (ADDR(.text) + SIZEOF(.text))
37#endif 17#endif
38 18
19#include <asm/page.h>
20#include <asm/thread_info.h>
21#include <asm-generic/vmlinux.lds.h>
39 22
40OUTPUT_ARCH(m68k) 23OUTPUT_ARCH(m68k)
41ENTRY(_start) 24ENTRY(_start)
42 25
43MEMORY {
44 ram : ORIGIN = RAM_START, LENGTH = RAM_LENGTH
45#ifdef ROM_START
46 romvec : ORIGIN = ROMVEC_START, LENGTH = ROMVEC_LENGTH
47 rom : ORIGIN = ROM_START, LENGTH = ROM_LENGTH
48#endif
49}
50
51jiffies = jiffies_64 + 4; 26jiffies = jiffies_64 + 4;
52 27
53SECTIONS { 28SECTIONS {
54 29
55#ifdef ROMVEC_START 30#ifdef CONFIG_ROMVEC
56 . = ROMVEC_START ; 31 . = CONFIG_ROMVEC;
57 .romvec : { 32 .romvec : {
58 __rom_start = . ; 33 __rom_start = .;
59 _romvec = .; 34 _romvec = .;
35 *(.romvec)
60 *(.data..initvect) 36 *(.data..initvect)
61 } > romvec 37 }
62#endif 38#endif
63 39
40 . = KTEXT_ADDR;
41
42 _text = .;
43 _stext = .;
64 .text : { 44 .text : {
65 _text = .;
66 _stext = . ;
67 HEAD_TEXT 45 HEAD_TEXT
68 TEXT_TEXT 46 TEXT_TEXT
69 SCHED_TEXT 47 SCHED_TEXT
70 LOCK_TEXT 48 LOCK_TEXT
71 *(.text..lock)
72 *(.fixup) 49 *(.fixup)
50 . = ALIGN(16);
51 }
52 _etext = .;
53
54#ifdef KDATA_ADDR
55 . = KDATA_ADDR;
56#endif
57
58 _sdata = .;
59 RO_DATA_SECTION(PAGE_SIZE)
60 RW_DATA_SECTION(16, PAGE_SIZE, THREAD_SIZE)
61 _edata = .;
73 62
74 . = ALIGN(16); /* Exception table */ 63 EXCEPTION_TABLE(16)
75 __start___ex_table = .; 64 NOTES
76 *(__ex_table)
77 __stop___ex_table = .;
78
79 *(.rodata) *(.rodata.*)
80 *(__vermagic) /* Kernel version magic */
81 *(.rodata1)
82 *(.rodata.str1.1)
83
84 /* Kernel symbol table: Normal symbols */
85 . = ALIGN(4);
86 __start___ksymtab = .;
87 *(SORT(___ksymtab+*))
88 __stop___ksymtab = .;
89
90 /* Kernel symbol table: GPL-only symbols */
91 __start___ksymtab_gpl = .;
92 *(SORT(___ksymtab_gpl+*))
93 __stop___ksymtab_gpl = .;
94
95 /* Kernel symbol table: Normal unused symbols */
96 __start___ksymtab_unused = .;
97 *(SORT(___ksymtab_unused+*))
98 __stop___ksymtab_unused = .;
99
100 /* Kernel symbol table: GPL-only unused symbols */
101 __start___ksymtab_unused_gpl = .;
102 *(SORT(___ksymtab_unused_gpl+*))
103 __stop___ksymtab_unused_gpl = .;
104
105 /* Kernel symbol table: GPL-future symbols */
106 __start___ksymtab_gpl_future = .;
107 *(SORT(___ksymtab_gpl_future+*))
108 __stop___ksymtab_gpl_future = .;
109
110 /* Kernel symbol table: Normal symbols */
111 __start___kcrctab = .;
112 *(SORT(___kcrctab+*))
113 __stop___kcrctab = .;
114
115 /* Kernel symbol table: GPL-only symbols */
116 __start___kcrctab_gpl = .;
117 *(SORT(___kcrctab_gpl+*))
118 __stop___kcrctab_gpl = .;
119
120 /* Kernel symbol table: Normal unused symbols */
121 __start___kcrctab_unused = .;
122 *(SORT(___kcrctab_unused+*))
123 __stop___kcrctab_unused = .;
124
125 /* Kernel symbol table: GPL-only unused symbols */
126 __start___kcrctab_unused_gpl = .;
127 *(SORT(___kcrctab_unused_gpl+*))
128 __stop___kcrctab_unused_gpl = .;
129
130 /* Kernel symbol table: GPL-future symbols */
131 __start___kcrctab_gpl_future = .;
132 *(SORT(___kcrctab_gpl_future+*))
133 __stop___kcrctab_gpl_future = .;
134
135 /* Kernel symbol table: strings */
136 *(__ksymtab_strings)
137
138 /* Built-in module parameters */
139 . = ALIGN(4) ;
140 __start___param = .;
141 *(__param)
142 __stop___param = .;
143
144 /* Built-in module versions */
145 . = ALIGN(4) ;
146 __start___modver = .;
147 *(__modver)
148 __stop___modver = .;
149
150 . = ALIGN(4) ;
151 _etext = . ;
152 } > TEXT
153
154 .data DATA_ADDR : {
155 . = ALIGN(4);
156 _sdata = . ;
157 DATA_DATA
158 CACHELINE_ALIGNED_DATA(32)
159 PAGE_ALIGNED_DATA(PAGE_SIZE)
160 *(.data..shared_aligned)
161 INIT_TASK_DATA(THREAD_SIZE)
162 _edata = . ;
163 } > DATA
164 65
66 . = ALIGN(PAGE_SIZE);
67 __init_begin = .;
68 INIT_TEXT_SECTION(PAGE_SIZE)
69 INIT_DATA_SECTION(16)
70 PERCPU_SECTION(16)
165 .m68k_fixup : { 71 .m68k_fixup : {
166 __start_fixup = .; 72 __start_fixup = .;
167 *(.m68k_fixup) 73 *(.m68k_fixup)
168 __stop_fixup = .; 74 __stop_fixup = .;
169 } > DATA 75 }
170 NOTES > DATA
171
172 .init.text : {
173 . = ALIGN(PAGE_SIZE);
174 __init_begin = .;
175 } > INIT
176 INIT_TEXT_SECTION(PAGE_SIZE) > INIT
177 INIT_DATA_SECTION(16) > INIT
178 .init.data : { 76 .init.data : {
179 . = ALIGN(PAGE_SIZE); 77 . = ALIGN(PAGE_SIZE);
180 __init_end = .; 78 __init_end = .;
181 } > INIT 79 }
182 80
183 .bss : { 81 _sbss = .;
184 . = ALIGN(4); 82 BSS_SECTION(0, 0, 0)
185 _sbss = . ; 83 _ebss = .;
186 *(.bss) 84
187 *(COMMON) 85 _end = .;
188 . = ALIGN(4) ; 86
189 _ebss = . ; 87 STABS_DEBUG
190 _end = . ; 88 .comment 0 : { *(.comment) }
191 } > BSSS
192 89
90 /* Sections to be discarded */
193 DISCARDS 91 DISCARDS
194} 92}
195 93
diff --git a/arch/m68k/platform/5206/config.c b/arch/m68k/platform/5206/config.c
index 6fa3f800277a..6bfbeebd231b 100644
--- a/arch/m68k/platform/5206/config.c
+++ b/arch/m68k/platform/5206/config.c
@@ -16,83 +16,6 @@
16#include <asm/machdep.h> 16#include <asm/machdep.h>
17#include <asm/coldfire.h> 17#include <asm/coldfire.h>
18#include <asm/mcfsim.h> 18#include <asm/mcfsim.h>
19#include <asm/mcfuart.h>
20
21/***************************************************************************/
22
23static struct mcf_platform_uart m5206_uart_platform[] = {
24 {
25 .mapbase = MCF_MBAR + MCFUART_BASE1,
26 .irq = 73,
27 },
28 {
29 .mapbase = MCF_MBAR + MCFUART_BASE2,
30 .irq = 74,
31 },
32 { },
33};
34
35static struct platform_device m5206_uart = {
36 .name = "mcfuart",
37 .id = 0,
38 .dev.platform_data = m5206_uart_platform,
39};
40
41static struct platform_device *m5206_devices[] __initdata = {
42 &m5206_uart,
43};
44
45/***************************************************************************/
46
47static void __init m5206_uart_init_line(int line, int irq)
48{
49 if (line == 0) {
50 writel(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR);
51 writeb(irq, MCFUART_BASE1 + MCFUART_UIVR);
52 mcf_mapirq2imr(irq, MCFINTC_UART0);
53 } else if (line == 1) {
54 writel(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR);
55 writeb(irq, MCFUART_BASE2 + MCFUART_UIVR);
56 mcf_mapirq2imr(irq, MCFINTC_UART1);
57 }
58}
59
60static void __init m5206_uarts_init(void)
61{
62 const int nrlines = ARRAY_SIZE(m5206_uart_platform);
63 int line;
64
65 for (line = 0; (line < nrlines); line++)
66 m5206_uart_init_line(line, m5206_uart_platform[line].irq);
67}
68
69/***************************************************************************/
70
71static void __init m5206_timers_init(void)
72{
73 /* Timer1 is always used as system timer */
74 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3,
75 MCF_MBAR + MCFSIM_TIMER1ICR);
76 mcf_mapirq2imr(MCF_IRQ_TIMER, MCFINTC_TIMER1);
77
78#ifdef CONFIG_HIGHPROFILE
79 /* Timer2 is to be used as a high speed profile timer */
80 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3,
81 MCF_MBAR + MCFSIM_TIMER2ICR);
82 mcf_mapirq2imr(MCF_IRQ_PROFILER, MCFINTC_TIMER2);
83#endif
84}
85
86/***************************************************************************/
87
88void m5206_cpu_reset(void)
89{
90 local_irq_disable();
91 /* Set watchdog to soft reset, and enabled */
92 __raw_writeb(0xc0, MCF_MBAR + MCFSIM_SYPCR);
93 for (;;)
94 /* wait for watchdog to timeout */;
95}
96 19
97/***************************************************************************/ 20/***************************************************************************/
98 21
@@ -104,9 +27,7 @@ void __init config_BSP(char *commandp, int size)
104 commandp[size-1] = 0; 27 commandp[size-1] = 0;
105#endif /* CONFIG_NETtel */ 28#endif /* CONFIG_NETtel */
106 29
107 mach_reset = m5206_cpu_reset; 30 mach_sched_init = hw_timer_init;
108 m5206_timers_init();
109 m5206_uarts_init();
110 31
111 /* Only support the external interrupts on their primary level */ 32 /* Only support the external interrupts on their primary level */
112 mcf_mapirq2imr(25, MCFINTC_EINT1); 33 mcf_mapirq2imr(25, MCFINTC_EINT1);
@@ -115,13 +36,3 @@ void __init config_BSP(char *commandp, int size)
115} 36}
116 37
117/***************************************************************************/ 38/***************************************************************************/
118
119static int __init init_BSP(void)
120{
121 platform_add_devices(m5206_devices, ARRAY_SIZE(m5206_devices));
122 return 0;
123}
124
125arch_initcall(init_BSP);
126
127/***************************************************************************/
diff --git a/arch/m68k/platform/520x/config.c b/arch/m68k/platform/520x/config.c
index 8a98683f1b15..235947844f27 100644
--- a/arch/m68k/platform/520x/config.c
+++ b/arch/m68k/platform/520x/config.c
@@ -15,194 +15,14 @@
15#include <linux/param.h> 15#include <linux/param.h>
16#include <linux/init.h> 16#include <linux/init.h>
17#include <linux/io.h> 17#include <linux/io.h>
18#include <linux/spi/spi.h>
19#include <linux/gpio.h>
20#include <asm/machdep.h> 18#include <asm/machdep.h>
21#include <asm/coldfire.h> 19#include <asm/coldfire.h>
22#include <asm/mcfsim.h> 20#include <asm/mcfsim.h>
23#include <asm/mcfuart.h> 21#include <asm/mcfuart.h>
24#include <asm/mcfqspi.h>
25 22
26/***************************************************************************/ 23/***************************************************************************/
27 24
28static struct mcf_platform_uart m520x_uart_platform[] = { 25#ifdef CONFIG_SPI_COLDFIRE_QSPI
29 {
30 .mapbase = MCFUART_BASE1,
31 .irq = MCFINT_VECBASE + MCFINT_UART0,
32 },
33 {
34 .mapbase = MCFUART_BASE2,
35 .irq = MCFINT_VECBASE + MCFINT_UART1,
36 },
37 {
38 .mapbase = MCFUART_BASE3,
39 .irq = MCFINT_VECBASE + MCFINT_UART2,
40 },
41 { },
42};
43
44static struct platform_device m520x_uart = {
45 .name = "mcfuart",
46 .id = 0,
47 .dev.platform_data = m520x_uart_platform,
48};
49
50static struct resource m520x_fec_resources[] = {
51 {
52 .start = MCFFEC_BASE,
53 .end = MCFFEC_BASE + MCFFEC_SIZE - 1,
54 .flags = IORESOURCE_MEM,
55 },
56 {
57 .start = 64 + 36,
58 .end = 64 + 36,
59 .flags = IORESOURCE_IRQ,
60 },
61 {
62 .start = 64 + 40,
63 .end = 64 + 40,
64 .flags = IORESOURCE_IRQ,
65 },
66 {
67 .start = 64 + 42,
68 .end = 64 + 42,
69 .flags = IORESOURCE_IRQ,
70 },
71};
72
73static struct platform_device m520x_fec = {
74 .name = "fec",
75 .id = 0,
76 .num_resources = ARRAY_SIZE(m520x_fec_resources),
77 .resource = m520x_fec_resources,
78};
79
80#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
81static struct resource m520x_qspi_resources[] = {
82 {
83 .start = MCFQSPI_IOBASE,
84 .end = MCFQSPI_IOBASE + MCFQSPI_IOSIZE - 1,
85 .flags = IORESOURCE_MEM,
86 },
87 {
88 .start = MCFINT_VECBASE + MCFINT_QSPI,
89 .end = MCFINT_VECBASE + MCFINT_QSPI,
90 .flags = IORESOURCE_IRQ,
91 },
92};
93
94#define MCFQSPI_CS0 46
95#define MCFQSPI_CS1 47
96#define MCFQSPI_CS2 27
97
98static int m520x_cs_setup(struct mcfqspi_cs_control *cs_control)
99{
100 int status;
101
102 status = gpio_request(MCFQSPI_CS0, "MCFQSPI_CS0");
103 if (status) {
104 pr_debug("gpio_request for MCFQSPI_CS0 failed\n");
105 goto fail0;
106 }
107 status = gpio_direction_output(MCFQSPI_CS0, 1);
108 if (status) {
109 pr_debug("gpio_direction_output for MCFQSPI_CS0 failed\n");
110 goto fail1;
111 }
112
113 status = gpio_request(MCFQSPI_CS1, "MCFQSPI_CS1");
114 if (status) {
115 pr_debug("gpio_request for MCFQSPI_CS1 failed\n");
116 goto fail1;
117 }
118 status = gpio_direction_output(MCFQSPI_CS1, 1);
119 if (status) {
120 pr_debug("gpio_direction_output for MCFQSPI_CS1 failed\n");
121 goto fail2;
122 }
123
124 status = gpio_request(MCFQSPI_CS2, "MCFQSPI_CS2");
125 if (status) {
126 pr_debug("gpio_request for MCFQSPI_CS2 failed\n");
127 goto fail2;
128 }
129 status = gpio_direction_output(MCFQSPI_CS2, 1);
130 if (status) {
131 pr_debug("gpio_direction_output for MCFQSPI_CS2 failed\n");
132 goto fail3;
133 }
134
135 return 0;
136
137fail3:
138 gpio_free(MCFQSPI_CS2);
139fail2:
140 gpio_free(MCFQSPI_CS1);
141fail1:
142 gpio_free(MCFQSPI_CS0);
143fail0:
144 return status;
145}
146
147static void m520x_cs_teardown(struct mcfqspi_cs_control *cs_control)
148{
149 gpio_free(MCFQSPI_CS2);
150 gpio_free(MCFQSPI_CS1);
151 gpio_free(MCFQSPI_CS0);
152}
153
154static void m520x_cs_select(struct mcfqspi_cs_control *cs_control,
155 u8 chip_select, bool cs_high)
156{
157 switch (chip_select) {
158 case 0:
159 gpio_set_value(MCFQSPI_CS0, cs_high);
160 break;
161 case 1:
162 gpio_set_value(MCFQSPI_CS1, cs_high);
163 break;
164 case 2:
165 gpio_set_value(MCFQSPI_CS2, cs_high);
166 break;
167 }
168}
169
170static void m520x_cs_deselect(struct mcfqspi_cs_control *cs_control,
171 u8 chip_select, bool cs_high)
172{
173 switch (chip_select) {
174 case 0:
175 gpio_set_value(MCFQSPI_CS0, !cs_high);
176 break;
177 case 1:
178 gpio_set_value(MCFQSPI_CS1, !cs_high);
179 break;
180 case 2:
181 gpio_set_value(MCFQSPI_CS2, !cs_high);
182 break;
183 }
184}
185
186static struct mcfqspi_cs_control m520x_cs_control = {
187 .setup = m520x_cs_setup,
188 .teardown = m520x_cs_teardown,
189 .select = m520x_cs_select,
190 .deselect = m520x_cs_deselect,
191};
192
193static struct mcfqspi_platform_data m520x_qspi_data = {
194 .bus_num = 0,
195 .num_chipselect = 3,
196 .cs_control = &m520x_cs_control,
197};
198
199static struct platform_device m520x_qspi = {
200 .name = "mcfqspi",
201 .id = 0,
202 .num_resources = ARRAY_SIZE(m520x_qspi_resources),
203 .resource = m520x_qspi_resources,
204 .dev.platform_data = &m520x_qspi_data,
205};
206 26
207static void __init m520x_qspi_init(void) 27static void __init m520x_qspi_init(void)
208{ 28{
@@ -214,54 +34,28 @@ static void __init m520x_qspi_init(void)
214 par &= 0x00ff; 34 par &= 0x00ff;
215 writew(par, MCF_GPIO_PAR_UART); 35 writew(par, MCF_GPIO_PAR_UART);
216} 36}
217#endif /* defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) */
218
219 37
220static struct platform_device *m520x_devices[] __initdata = { 38#endif /* CONFIG_SPI_COLDFIRE_QSPI */
221 &m520x_uart,
222 &m520x_fec,
223#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
224 &m520x_qspi,
225#endif
226};
227 39
228/***************************************************************************/ 40/***************************************************************************/
229 41
230static void __init m520x_uart_init_line(int line, int irq) 42static void __init m520x_uarts_init(void)
231{ 43{
232 u16 par; 44 u16 par;
233 u8 par2; 45 u8 par2;
234 46
235 switch (line) { 47 /* UART0 and UART1 GPIO pin setup */
236 case 0: 48 par = readw(MCF_GPIO_PAR_UART);
237 par = readw(MCF_GPIO_PAR_UART); 49 par |= MCF_GPIO_PAR_UART_PAR_UTXD0 | MCF_GPIO_PAR_UART_PAR_URXD0;
238 par |= MCF_GPIO_PAR_UART_PAR_UTXD0 | 50 par |= MCF_GPIO_PAR_UART_PAR_UTXD1 | MCF_GPIO_PAR_UART_PAR_URXD1;
239 MCF_GPIO_PAR_UART_PAR_URXD0; 51 writew(par, MCF_GPIO_PAR_UART);
240 writew(par, MCF_GPIO_PAR_UART);
241 break;
242 case 1:
243 par = readw(MCF_GPIO_PAR_UART);
244 par |= MCF_GPIO_PAR_UART_PAR_UTXD1 |
245 MCF_GPIO_PAR_UART_PAR_URXD1;
246 writew(par, MCF_GPIO_PAR_UART);
247 break;
248 case 2:
249 par2 = readb(MCF_GPIO_PAR_FECI2C);
250 par2 &= ~0x0F;
251 par2 |= MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 |
252 MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2;
253 writeb(par2, MCF_GPIO_PAR_FECI2C);
254 break;
255 }
256}
257
258static void __init m520x_uarts_init(void)
259{
260 const int nrlines = ARRAY_SIZE(m520x_uart_platform);
261 int line;
262 52
263 for (line = 0; (line < nrlines); line++) 53 /* UART1 GPIO pin setup */
264 m520x_uart_init_line(line, m520x_uart_platform[line].irq); 54 par2 = readb(MCF_GPIO_PAR_FECI2C);
55 par2 &= ~0x0F;
56 par2 |= MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 |
57 MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2;
58 writeb(par2, MCF_GPIO_PAR_FECI2C);
265} 59}
266 60
267/***************************************************************************/ 61/***************************************************************************/
@@ -280,32 +74,14 @@ static void __init m520x_fec_init(void)
280 74
281/***************************************************************************/ 75/***************************************************************************/
282 76
283static void m520x_cpu_reset(void)
284{
285 local_irq_disable();
286 __raw_writeb(MCF_RCR_SWRESET, MCF_RCR);
287}
288
289/***************************************************************************/
290
291void __init config_BSP(char *commandp, int size) 77void __init config_BSP(char *commandp, int size)
292{ 78{
293 mach_reset = m520x_cpu_reset; 79 mach_sched_init = hw_timer_init;
294 m520x_uarts_init(); 80 m520x_uarts_init();
295 m520x_fec_init(); 81 m520x_fec_init();
296#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) 82#ifdef CONFIG_SPI_COLDFIRE_QSPI
297 m520x_qspi_init(); 83 m520x_qspi_init();
298#endif 84#endif
299} 85}
300 86
301/***************************************************************************/ 87/***************************************************************************/
302
303static int __init init_BSP(void)
304{
305 platform_add_devices(m520x_devices, ARRAY_SIZE(m520x_devices));
306 return 0;
307}
308
309arch_initcall(init_BSP);
310
311/***************************************************************************/
diff --git a/arch/m68k/platform/523x/config.c b/arch/m68k/platform/523x/config.c
index 71f4436ec809..c8b405d5a961 100644
--- a/arch/m68k/platform/523x/config.c
+++ b/arch/m68k/platform/523x/config.c
@@ -16,215 +16,13 @@
16#include <linux/param.h> 16#include <linux/param.h>
17#include <linux/init.h> 17#include <linux/init.h>
18#include <linux/io.h> 18#include <linux/io.h>
19#include <linux/spi/spi.h>
20#include <linux/gpio.h>
21#include <asm/machdep.h> 19#include <asm/machdep.h>
22#include <asm/coldfire.h> 20#include <asm/coldfire.h>
23#include <asm/mcfsim.h> 21#include <asm/mcfsim.h>
24#include <asm/mcfuart.h>
25#include <asm/mcfqspi.h>
26 22
27/***************************************************************************/ 23/***************************************************************************/
28 24
29static struct mcf_platform_uart m523x_uart_platform[] = { 25#ifdef CONFIG_SPI_COLDFIRE_QSPI
30 {
31 .mapbase = MCFUART_BASE1,
32 .irq = MCFINT_VECBASE + MCFINT_UART0,
33 },
34 {
35 .mapbase = MCFUART_BASE2,
36 .irq = MCFINT_VECBASE + MCFINT_UART0 + 1,
37 },
38 {
39 .mapbase = MCFUART_BASE3,
40 .irq = MCFINT_VECBASE + MCFINT_UART0 + 2,
41 },
42 { },
43};
44
45static struct platform_device m523x_uart = {
46 .name = "mcfuart",
47 .id = 0,
48 .dev.platform_data = m523x_uart_platform,
49};
50
51static struct resource m523x_fec_resources[] = {
52 {
53 .start = MCFFEC_BASE,
54 .end = MCFFEC_BASE + MCFFEC_SIZE - 1,
55 .flags = IORESOURCE_MEM,
56 },
57 {
58 .start = 64 + 23,
59 .end = 64 + 23,
60 .flags = IORESOURCE_IRQ,
61 },
62 {
63 .start = 64 + 27,
64 .end = 64 + 27,
65 .flags = IORESOURCE_IRQ,
66 },
67 {
68 .start = 64 + 29,
69 .end = 64 + 29,
70 .flags = IORESOURCE_IRQ,
71 },
72};
73
74static struct platform_device m523x_fec = {
75 .name = "fec",
76 .id = 0,
77 .num_resources = ARRAY_SIZE(m523x_fec_resources),
78 .resource = m523x_fec_resources,
79};
80
81#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
82static struct resource m523x_qspi_resources[] = {
83 {
84 .start = MCFQSPI_IOBASE,
85 .end = MCFQSPI_IOBASE + MCFQSPI_IOSIZE - 1,
86 .flags = IORESOURCE_MEM,
87 },
88 {
89 .start = MCFINT_VECBASE + MCFINT_QSPI,
90 .end = MCFINT_VECBASE + MCFINT_QSPI,
91 .flags = IORESOURCE_IRQ,
92 },
93};
94
95#define MCFQSPI_CS0 91
96#define MCFQSPI_CS1 92
97#define MCFQSPI_CS2 103
98#define MCFQSPI_CS3 99
99
100static int m523x_cs_setup(struct mcfqspi_cs_control *cs_control)
101{
102 int status;
103
104 status = gpio_request(MCFQSPI_CS0, "MCFQSPI_CS0");
105 if (status) {
106 pr_debug("gpio_request for MCFQSPI_CS0 failed\n");
107 goto fail0;
108 }
109 status = gpio_direction_output(MCFQSPI_CS0, 1);
110 if (status) {
111 pr_debug("gpio_direction_output for MCFQSPI_CS0 failed\n");
112 goto fail1;
113 }
114
115 status = gpio_request(MCFQSPI_CS1, "MCFQSPI_CS1");
116 if (status) {
117 pr_debug("gpio_request for MCFQSPI_CS1 failed\n");
118 goto fail1;
119 }
120 status = gpio_direction_output(MCFQSPI_CS1, 1);
121 if (status) {
122 pr_debug("gpio_direction_output for MCFQSPI_CS1 failed\n");
123 goto fail2;
124 }
125
126 status = gpio_request(MCFQSPI_CS2, "MCFQSPI_CS2");
127 if (status) {
128 pr_debug("gpio_request for MCFQSPI_CS2 failed\n");
129 goto fail2;
130 }
131 status = gpio_direction_output(MCFQSPI_CS2, 1);
132 if (status) {
133 pr_debug("gpio_direction_output for MCFQSPI_CS2 failed\n");
134 goto fail3;
135 }
136
137 status = gpio_request(MCFQSPI_CS3, "MCFQSPI_CS3");
138 if (status) {
139 pr_debug("gpio_request for MCFQSPI_CS3 failed\n");
140 goto fail3;
141 }
142 status = gpio_direction_output(MCFQSPI_CS3, 1);
143 if (status) {
144 pr_debug("gpio_direction_output for MCFQSPI_CS3 failed\n");
145 goto fail4;
146 }
147
148 return 0;
149
150fail4:
151 gpio_free(MCFQSPI_CS3);
152fail3:
153 gpio_free(MCFQSPI_CS2);
154fail2:
155 gpio_free(MCFQSPI_CS1);
156fail1:
157 gpio_free(MCFQSPI_CS0);
158fail0:
159 return status;
160}
161
162static void m523x_cs_teardown(struct mcfqspi_cs_control *cs_control)
163{
164 gpio_free(MCFQSPI_CS3);
165 gpio_free(MCFQSPI_CS2);
166 gpio_free(MCFQSPI_CS1);
167 gpio_free(MCFQSPI_CS0);
168}
169
170static void m523x_cs_select(struct mcfqspi_cs_control *cs_control,
171 u8 chip_select, bool cs_high)
172{
173 switch (chip_select) {
174 case 0:
175 gpio_set_value(MCFQSPI_CS0, cs_high);
176 break;
177 case 1:
178 gpio_set_value(MCFQSPI_CS1, cs_high);
179 break;
180 case 2:
181 gpio_set_value(MCFQSPI_CS2, cs_high);
182 break;
183 case 3:
184 gpio_set_value(MCFQSPI_CS3, cs_high);
185 break;
186 }
187}
188
189static void m523x_cs_deselect(struct mcfqspi_cs_control *cs_control,
190 u8 chip_select, bool cs_high)
191{
192 switch (chip_select) {
193 case 0:
194 gpio_set_value(MCFQSPI_CS0, !cs_high);
195 break;
196 case 1:
197 gpio_set_value(MCFQSPI_CS1, !cs_high);
198 break;
199 case 2:
200 gpio_set_value(MCFQSPI_CS2, !cs_high);
201 break;
202 case 3:
203 gpio_set_value(MCFQSPI_CS3, !cs_high);
204 break;
205 }
206}
207
208static struct mcfqspi_cs_control m523x_cs_control = {
209 .setup = m523x_cs_setup,
210 .teardown = m523x_cs_teardown,
211 .select = m523x_cs_select,
212 .deselect = m523x_cs_deselect,
213};
214
215static struct mcfqspi_platform_data m523x_qspi_data = {
216 .bus_num = 0,
217 .num_chipselect = 4,
218 .cs_control = &m523x_cs_control,
219};
220
221static struct platform_device m523x_qspi = {
222 .name = "mcfqspi",
223 .id = 0,
224 .num_resources = ARRAY_SIZE(m523x_qspi_resources),
225 .resource = m523x_qspi_resources,
226 .dev.platform_data = &m523x_qspi_data,
227};
228 26
229static void __init m523x_qspi_init(void) 27static void __init m523x_qspi_init(void)
230{ 28{
@@ -237,15 +35,8 @@ static void __init m523x_qspi_init(void)
237 par &= 0x3f3f; 35 par &= 0x3f3f;
238 writew(par, MCFGPIO_PAR_TIMER); 36 writew(par, MCFGPIO_PAR_TIMER);
239} 37}
240#endif /* defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) */
241 38
242static struct platform_device *m523x_devices[] __initdata = { 39#endif /* CONFIG_SPI_COLDFIRE_QSPI */
243 &m523x_uart,
244 &m523x_fec,
245#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
246 &m523x_qspi,
247#endif
248};
249 40
250/***************************************************************************/ 41/***************************************************************************/
251 42
@@ -263,31 +54,13 @@ static void __init m523x_fec_init(void)
263 54
264/***************************************************************************/ 55/***************************************************************************/
265 56
266static void m523x_cpu_reset(void)
267{
268 local_irq_disable();
269 __raw_writeb(MCF_RCR_SWRESET, MCF_IPSBAR + MCF_RCR);
270}
271
272/***************************************************************************/
273
274void __init config_BSP(char *commandp, int size) 57void __init config_BSP(char *commandp, int size)
275{ 58{
276 mach_reset = m523x_cpu_reset; 59 mach_sched_init = hw_timer_init;
277}
278
279/***************************************************************************/
280
281static int __init init_BSP(void)
282{
283 m523x_fec_init(); 60 m523x_fec_init();
284#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) 61#ifdef CONFIG_SPI_COLDFIRE_QSPI
285 m523x_qspi_init(); 62 m523x_qspi_init();
286#endif 63#endif
287 platform_add_devices(m523x_devices, ARRAY_SIZE(m523x_devices));
288 return 0;
289} 64}
290 65
291arch_initcall(init_BSP);
292
293/***************************************************************************/ 66/***************************************************************************/
diff --git a/arch/m68k/platform/5249/config.c b/arch/m68k/platform/5249/config.c
index ceb31e5744a6..bbf05135bb98 100644
--- a/arch/m68k/platform/5249/config.c
+++ b/arch/m68k/platform/5249/config.c
@@ -12,34 +12,13 @@
12#include <linux/param.h> 12#include <linux/param.h>
13#include <linux/init.h> 13#include <linux/init.h>
14#include <linux/io.h> 14#include <linux/io.h>
15#include <linux/spi/spi.h> 15#include <linux/platform_device.h>
16#include <linux/gpio.h>
17#include <asm/machdep.h> 16#include <asm/machdep.h>
18#include <asm/coldfire.h> 17#include <asm/coldfire.h>
19#include <asm/mcfsim.h> 18#include <asm/mcfsim.h>
20#include <asm/mcfuart.h>
21#include <asm/mcfqspi.h>
22 19
23/***************************************************************************/ 20/***************************************************************************/
24 21
25static struct mcf_platform_uart m5249_uart_platform[] = {
26 {
27 .mapbase = MCF_MBAR + MCFUART_BASE1,
28 .irq = 73,
29 },
30 {
31 .mapbase = MCF_MBAR + MCFUART_BASE2,
32 .irq = 74,
33 },
34 { },
35};
36
37static struct platform_device m5249_uart = {
38 .name = "mcfuart",
39 .id = 0,
40 .dev.platform_data = m5249_uart_platform,
41};
42
43#ifdef CONFIG_M5249C3 22#ifdef CONFIG_M5249C3
44 23
45static struct resource m5249_smc91x_resources[] = { 24static struct resource m5249_smc91x_resources[] = {
@@ -64,153 +43,15 @@ static struct platform_device m5249_smc91x = {
64 43
65#endif /* CONFIG_M5249C3 */ 44#endif /* CONFIG_M5249C3 */
66 45
67#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) 46static struct platform_device *m5249_devices[] __initdata = {
68static struct resource m5249_qspi_resources[] = { 47#ifdef CONFIG_M5249C3
69 { 48 &m5249_smc91x,
70 .start = MCFQSPI_IOBASE, 49#endif
71 .end = MCFQSPI_IOBASE + MCFQSPI_IOSIZE - 1,
72 .flags = IORESOURCE_MEM,
73 },
74 {
75 .start = MCF_IRQ_QSPI,
76 .end = MCF_IRQ_QSPI,
77 .flags = IORESOURCE_IRQ,
78 },
79};
80
81#define MCFQSPI_CS0 29
82#define MCFQSPI_CS1 24
83#define MCFQSPI_CS2 21
84#define MCFQSPI_CS3 22
85
86static int m5249_cs_setup(struct mcfqspi_cs_control *cs_control)
87{
88 int status;
89
90 status = gpio_request(MCFQSPI_CS0, "MCFQSPI_CS0");
91 if (status) {
92 pr_debug("gpio_request for MCFQSPI_CS0 failed\n");
93 goto fail0;
94 }
95 status = gpio_direction_output(MCFQSPI_CS0, 1);
96 if (status) {
97 pr_debug("gpio_direction_output for MCFQSPI_CS0 failed\n");
98 goto fail1;
99 }
100
101 status = gpio_request(MCFQSPI_CS1, "MCFQSPI_CS1");
102 if (status) {
103 pr_debug("gpio_request for MCFQSPI_CS1 failed\n");
104 goto fail1;
105 }
106 status = gpio_direction_output(MCFQSPI_CS1, 1);
107 if (status) {
108 pr_debug("gpio_direction_output for MCFQSPI_CS1 failed\n");
109 goto fail2;
110 }
111
112 status = gpio_request(MCFQSPI_CS2, "MCFQSPI_CS2");
113 if (status) {
114 pr_debug("gpio_request for MCFQSPI_CS2 failed\n");
115 goto fail2;
116 }
117 status = gpio_direction_output(MCFQSPI_CS2, 1);
118 if (status) {
119 pr_debug("gpio_direction_output for MCFQSPI_CS2 failed\n");
120 goto fail3;
121 }
122
123 status = gpio_request(MCFQSPI_CS3, "MCFQSPI_CS3");
124 if (status) {
125 pr_debug("gpio_request for MCFQSPI_CS3 failed\n");
126 goto fail3;
127 }
128 status = gpio_direction_output(MCFQSPI_CS3, 1);
129 if (status) {
130 pr_debug("gpio_direction_output for MCFQSPI_CS3 failed\n");
131 goto fail4;
132 }
133
134 return 0;
135
136fail4:
137 gpio_free(MCFQSPI_CS3);
138fail3:
139 gpio_free(MCFQSPI_CS2);
140fail2:
141 gpio_free(MCFQSPI_CS1);
142fail1:
143 gpio_free(MCFQSPI_CS0);
144fail0:
145 return status;
146}
147
148static void m5249_cs_teardown(struct mcfqspi_cs_control *cs_control)
149{
150 gpio_free(MCFQSPI_CS3);
151 gpio_free(MCFQSPI_CS2);
152 gpio_free(MCFQSPI_CS1);
153 gpio_free(MCFQSPI_CS0);
154}
155
156static void m5249_cs_select(struct mcfqspi_cs_control *cs_control,
157 u8 chip_select, bool cs_high)
158{
159 switch (chip_select) {
160 case 0:
161 gpio_set_value(MCFQSPI_CS0, cs_high);
162 break;
163 case 1:
164 gpio_set_value(MCFQSPI_CS1, cs_high);
165 break;
166 case 2:
167 gpio_set_value(MCFQSPI_CS2, cs_high);
168 break;
169 case 3:
170 gpio_set_value(MCFQSPI_CS3, cs_high);
171 break;
172 }
173}
174
175static void m5249_cs_deselect(struct mcfqspi_cs_control *cs_control,
176 u8 chip_select, bool cs_high)
177{
178 switch (chip_select) {
179 case 0:
180 gpio_set_value(MCFQSPI_CS0, !cs_high);
181 break;
182 case 1:
183 gpio_set_value(MCFQSPI_CS1, !cs_high);
184 break;
185 case 2:
186 gpio_set_value(MCFQSPI_CS2, !cs_high);
187 break;
188 case 3:
189 gpio_set_value(MCFQSPI_CS3, !cs_high);
190 break;
191 }
192}
193
194static struct mcfqspi_cs_control m5249_cs_control = {
195 .setup = m5249_cs_setup,
196 .teardown = m5249_cs_teardown,
197 .select = m5249_cs_select,
198 .deselect = m5249_cs_deselect,
199}; 50};
200 51
201static struct mcfqspi_platform_data m5249_qspi_data = { 52/***************************************************************************/
202 .bus_num = 0,
203 .num_chipselect = 4,
204 .cs_control = &m5249_cs_control,
205};
206 53
207static struct platform_device m5249_qspi = { 54#ifdef CONFIG_SPI_COLDFIRE_QSPI
208 .name = "mcfqspi",
209 .id = 0,
210 .num_resources = ARRAY_SIZE(m5249_qspi_resources),
211 .resource = m5249_qspi_resources,
212 .dev.platform_data = &m5249_qspi_data,
213};
214 55
215static void __init m5249_qspi_init(void) 56static void __init m5249_qspi_init(void)
216{ 57{
@@ -219,42 +60,8 @@ static void __init m5249_qspi_init(void)
219 MCF_MBAR + MCFSIM_QSPIICR); 60 MCF_MBAR + MCFSIM_QSPIICR);
220 mcf_mapirq2imr(MCF_IRQ_QSPI, MCFINTC_QSPI); 61 mcf_mapirq2imr(MCF_IRQ_QSPI, MCFINTC_QSPI);
221} 62}
222#endif /* defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) */
223 63
224 64#endif /* CONFIG_SPI_COLDFIRE_QSPI */
225static struct platform_device *m5249_devices[] __initdata = {
226 &m5249_uart,
227#ifdef CONFIG_M5249C3
228 &m5249_smc91x,
229#endif
230#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
231 &m5249_qspi,
232#endif
233};
234
235/***************************************************************************/
236
237static void __init m5249_uart_init_line(int line, int irq)
238{
239 if (line == 0) {
240 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR);
241 writeb(irq, MCF_MBAR + MCFUART_BASE1 + MCFUART_UIVR);
242 mcf_mapirq2imr(irq, MCFINTC_UART0);
243 } else if (line == 1) {
244 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR);
245 writeb(irq, MCF_MBAR + MCFUART_BASE2 + MCFUART_UIVR);
246 mcf_mapirq2imr(irq, MCFINTC_UART1);
247 }
248}
249
250static void __init m5249_uarts_init(void)
251{
252 const int nrlines = ARRAY_SIZE(m5249_uart_platform);
253 int line;
254
255 for (line = 0; (line < nrlines); line++)
256 m5249_uart_init_line(line, m5249_uart_platform[line].irq);
257}
258 65
259/***************************************************************************/ 66/***************************************************************************/
260 67
@@ -276,43 +83,14 @@ static void __init m5249_smc91x_init(void)
276 83
277/***************************************************************************/ 84/***************************************************************************/
278 85
279static void __init m5249_timers_init(void)
280{
281 /* Timer1 is always used as system timer */
282 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3,
283 MCF_MBAR + MCFSIM_TIMER1ICR);
284 mcf_mapirq2imr(MCF_IRQ_TIMER, MCFINTC_TIMER1);
285
286#ifdef CONFIG_HIGHPROFILE
287 /* Timer2 is to be used as a high speed profile timer */
288 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3,
289 MCF_MBAR + MCFSIM_TIMER2ICR);
290 mcf_mapirq2imr(MCF_IRQ_PROFILER, MCFINTC_TIMER2);
291#endif
292}
293
294/***************************************************************************/
295
296void m5249_cpu_reset(void)
297{
298 local_irq_disable();
299 /* Set watchdog to soft reset, and enabled */
300 __raw_writeb(0xc0, MCF_MBAR + MCFSIM_SYPCR);
301 for (;;)
302 /* wait for watchdog to timeout */;
303}
304
305/***************************************************************************/
306
307void __init config_BSP(char *commandp, int size) 86void __init config_BSP(char *commandp, int size)
308{ 87{
309 mach_reset = m5249_cpu_reset; 88 mach_sched_init = hw_timer_init;
310 m5249_timers_init(); 89
311 m5249_uarts_init();
312#ifdef CONFIG_M5249C3 90#ifdef CONFIG_M5249C3
313 m5249_smc91x_init(); 91 m5249_smc91x_init();
314#endif 92#endif
315#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) 93#ifdef CONFIG_SPI_COLDFIRE_QSPI
316 m5249_qspi_init(); 94 m5249_qspi_init();
317#endif 95#endif
318} 96}
diff --git a/arch/m68k/platform/5272/config.c b/arch/m68k/platform/5272/config.c
index 65bb582734e1..e68bc7a148eb 100644
--- a/arch/m68k/platform/5272/config.c
+++ b/arch/m68k/platform/5272/config.c
@@ -30,84 +30,18 @@ unsigned char ledbank = 0xff;
30 30
31/***************************************************************************/ 31/***************************************************************************/
32 32
33static struct mcf_platform_uart m5272_uart_platform[] = { 33static void __init m5272_uarts_init(void)
34 {
35 .mapbase = MCF_MBAR + MCFUART_BASE1,
36 .irq = MCF_IRQ_UART1,
37 },
38 {
39 .mapbase = MCF_MBAR + MCFUART_BASE2,
40 .irq = MCF_IRQ_UART2,
41 },
42 { },
43};
44
45static struct platform_device m5272_uart = {
46 .name = "mcfuart",
47 .id = 0,
48 .dev.platform_data = m5272_uart_platform,
49};
50
51static struct resource m5272_fec_resources[] = {
52 {
53 .start = MCF_MBAR + 0x840,
54 .end = MCF_MBAR + 0x840 + 0x1cf,
55 .flags = IORESOURCE_MEM,
56 },
57 {
58 .start = MCF_IRQ_ERX,
59 .end = MCF_IRQ_ERX,
60 .flags = IORESOURCE_IRQ,
61 },
62 {
63 .start = MCF_IRQ_ETX,
64 .end = MCF_IRQ_ETX,
65 .flags = IORESOURCE_IRQ,
66 },
67 {
68 .start = MCF_IRQ_ENTC,
69 .end = MCF_IRQ_ENTC,
70 .flags = IORESOURCE_IRQ,
71 },
72};
73
74static struct platform_device m5272_fec = {
75 .name = "fec",
76 .id = 0,
77 .num_resources = ARRAY_SIZE(m5272_fec_resources),
78 .resource = m5272_fec_resources,
79};
80
81static struct platform_device *m5272_devices[] __initdata = {
82 &m5272_uart,
83 &m5272_fec,
84};
85
86/***************************************************************************/
87
88static void __init m5272_uart_init_line(int line, int irq)
89{ 34{
90 u32 v; 35 u32 v;
91 36
92 if ((line >= 0) && (line < 2)) { 37 /* Enable the output lines for the serial ports */
93 /* Enable the output lines for the serial ports */ 38 v = readl(MCF_MBAR + MCFSIM_PBCNT);
94 v = readl(MCF_MBAR + MCFSIM_PBCNT); 39 v = (v & ~0x000000ff) | 0x00000055;
95 v = (v & ~0x000000ff) | 0x00000055; 40 writel(v, MCF_MBAR + MCFSIM_PBCNT);
96 writel(v, MCF_MBAR + MCFSIM_PBCNT);
97
98 v = readl(MCF_MBAR + MCFSIM_PDCNT);
99 v = (v & ~0x000003fc) | 0x000002a8;
100 writel(v, MCF_MBAR + MCFSIM_PDCNT);
101 }
102}
103
104static void __init m5272_uarts_init(void)
105{
106 const int nrlines = ARRAY_SIZE(m5272_uart_platform);
107 int line;
108 41
109 for (line = 0; (line < nrlines); line++) 42 v = readl(MCF_MBAR + MCFSIM_PDCNT);
110 m5272_uart_init_line(line, m5272_uart_platform[line].irq); 43 v = (v & ~0x000003fc) | 0x000002a8;
44 writel(v, MCF_MBAR + MCFSIM_PDCNT);
111} 45}
112 46
113/***************************************************************************/ 47/***************************************************************************/
@@ -146,6 +80,7 @@ void __init config_BSP(char *commandp, int size)
146#endif 80#endif
147 81
148 mach_reset = m5272_cpu_reset; 82 mach_reset = m5272_cpu_reset;
83 mach_sched_init = hw_timer_init;
149} 84}
150 85
151/***************************************************************************/ 86/***************************************************************************/
@@ -167,7 +102,6 @@ static int __init init_BSP(void)
167{ 102{
168 m5272_uarts_init(); 103 m5272_uarts_init();
169 fixed_phy_add(PHY_POLL, 0, &nettel_fixed_phy_status); 104 fixed_phy_add(PHY_POLL, 0, &nettel_fixed_phy_status);
170 platform_add_devices(m5272_devices, ARRAY_SIZE(m5272_devices));
171 return 0; 105 return 0;
172} 106}
173 107
diff --git a/arch/m68k/platform/527x/config.c b/arch/m68k/platform/527x/config.c
index 3ebc769cefda..7ed848c3b848 100644
--- a/arch/m68k/platform/527x/config.c
+++ b/arch/m68k/platform/527x/config.c
@@ -16,253 +16,14 @@
16#include <linux/param.h> 16#include <linux/param.h>
17#include <linux/init.h> 17#include <linux/init.h>
18#include <linux/io.h> 18#include <linux/io.h>
19#include <linux/spi/spi.h>
20#include <linux/gpio.h>
21#include <asm/machdep.h> 19#include <asm/machdep.h>
22#include <asm/coldfire.h> 20#include <asm/coldfire.h>
23#include <asm/mcfsim.h> 21#include <asm/mcfsim.h>
24#include <asm/mcfuart.h> 22#include <asm/mcfuart.h>
25#include <asm/mcfqspi.h>
26 23
27/***************************************************************************/ 24/***************************************************************************/
28 25
29static struct mcf_platform_uart m527x_uart_platform[] = { 26#ifdef CONFIG_SPI_COLDFIRE_QSPI
30 {
31 .mapbase = MCFUART_BASE1,
32 .irq = MCFINT_VECBASE + MCFINT_UART0,
33 },
34 {
35 .mapbase = MCFUART_BASE2,
36 .irq = MCFINT_VECBASE + MCFINT_UART1,
37 },
38 {
39 .mapbase = MCFUART_BASE3,
40 .irq = MCFINT_VECBASE + MCFINT_UART2,
41 },
42 { },
43};
44
45static struct platform_device m527x_uart = {
46 .name = "mcfuart",
47 .id = 0,
48 .dev.platform_data = m527x_uart_platform,
49};
50
51static struct resource m527x_fec0_resources[] = {
52 {
53 .start = MCFFEC_BASE0,
54 .end = MCFFEC_BASE0 + MCFFEC_SIZE0 - 1,
55 .flags = IORESOURCE_MEM,
56 },
57 {
58 .start = 64 + 23,
59 .end = 64 + 23,
60 .flags = IORESOURCE_IRQ,
61 },
62 {
63 .start = 64 + 27,
64 .end = 64 + 27,
65 .flags = IORESOURCE_IRQ,
66 },
67 {
68 .start = 64 + 29,
69 .end = 64 + 29,
70 .flags = IORESOURCE_IRQ,
71 },
72};
73
74static struct resource m527x_fec1_resources[] = {
75 {
76 .start = MCFFEC_BASE1,
77 .end = MCFFEC_BASE1 + MCFFEC_SIZE1 - 1,
78 .flags = IORESOURCE_MEM,
79 },
80 {
81 .start = 128 + 23,
82 .end = 128 + 23,
83 .flags = IORESOURCE_IRQ,
84 },
85 {
86 .start = 128 + 27,
87 .end = 128 + 27,
88 .flags = IORESOURCE_IRQ,
89 },
90 {
91 .start = 128 + 29,
92 .end = 128 + 29,
93 .flags = IORESOURCE_IRQ,
94 },
95};
96
97static struct platform_device m527x_fec[] = {
98 {
99 .name = "fec",
100 .id = 0,
101 .num_resources = ARRAY_SIZE(m527x_fec0_resources),
102 .resource = m527x_fec0_resources,
103 },
104 {
105 .name = "fec",
106 .id = 1,
107 .num_resources = ARRAY_SIZE(m527x_fec1_resources),
108 .resource = m527x_fec1_resources,
109 },
110};
111
112#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
113static struct resource m527x_qspi_resources[] = {
114 {
115 .start = MCFQSPI_IOBASE,
116 .end = MCFQSPI_IOBASE + MCFQSPI_IOSIZE - 1,
117 .flags = IORESOURCE_MEM,
118 },
119 {
120 .start = MCFINT_VECBASE + MCFINT_QSPI,
121 .end = MCFINT_VECBASE + MCFINT_QSPI,
122 .flags = IORESOURCE_IRQ,
123 },
124};
125
126#if defined(CONFIG_M5271)
127#define MCFQSPI_CS0 91
128#define MCFQSPI_CS1 92
129#define MCFQSPI_CS2 99
130#define MCFQSPI_CS3 103
131#elif defined(CONFIG_M5275)
132#define MCFQSPI_CS0 59
133#define MCFQSPI_CS1 60
134#define MCFQSPI_CS2 61
135#define MCFQSPI_CS3 62
136#endif
137
138static int m527x_cs_setup(struct mcfqspi_cs_control *cs_control)
139{
140 int status;
141
142 status = gpio_request(MCFQSPI_CS0, "MCFQSPI_CS0");
143 if (status) {
144 pr_debug("gpio_request for MCFQSPI_CS0 failed\n");
145 goto fail0;
146 }
147 status = gpio_direction_output(MCFQSPI_CS0, 1);
148 if (status) {
149 pr_debug("gpio_direction_output for MCFQSPI_CS0 failed\n");
150 goto fail1;
151 }
152
153 status = gpio_request(MCFQSPI_CS1, "MCFQSPI_CS1");
154 if (status) {
155 pr_debug("gpio_request for MCFQSPI_CS1 failed\n");
156 goto fail1;
157 }
158 status = gpio_direction_output(MCFQSPI_CS1, 1);
159 if (status) {
160 pr_debug("gpio_direction_output for MCFQSPI_CS1 failed\n");
161 goto fail2;
162 }
163
164 status = gpio_request(MCFQSPI_CS2, "MCFQSPI_CS2");
165 if (status) {
166 pr_debug("gpio_request for MCFQSPI_CS2 failed\n");
167 goto fail2;
168 }
169 status = gpio_direction_output(MCFQSPI_CS2, 1);
170 if (status) {
171 pr_debug("gpio_direction_output for MCFQSPI_CS2 failed\n");
172 goto fail3;
173 }
174
175 status = gpio_request(MCFQSPI_CS3, "MCFQSPI_CS3");
176 if (status) {
177 pr_debug("gpio_request for MCFQSPI_CS3 failed\n");
178 goto fail3;
179 }
180 status = gpio_direction_output(MCFQSPI_CS3, 1);
181 if (status) {
182 pr_debug("gpio_direction_output for MCFQSPI_CS3 failed\n");
183 goto fail4;
184 }
185
186 return 0;
187
188fail4:
189 gpio_free(MCFQSPI_CS3);
190fail3:
191 gpio_free(MCFQSPI_CS2);
192fail2:
193 gpio_free(MCFQSPI_CS1);
194fail1:
195 gpio_free(MCFQSPI_CS0);
196fail0:
197 return status;
198}
199
200static void m527x_cs_teardown(struct mcfqspi_cs_control *cs_control)
201{
202 gpio_free(MCFQSPI_CS3);
203 gpio_free(MCFQSPI_CS2);
204 gpio_free(MCFQSPI_CS1);
205 gpio_free(MCFQSPI_CS0);
206}
207
208static void m527x_cs_select(struct mcfqspi_cs_control *cs_control,
209 u8 chip_select, bool cs_high)
210{
211 switch (chip_select) {
212 case 0:
213 gpio_set_value(MCFQSPI_CS0, cs_high);
214 break;
215 case 1:
216 gpio_set_value(MCFQSPI_CS1, cs_high);
217 break;
218 case 2:
219 gpio_set_value(MCFQSPI_CS2, cs_high);
220 break;
221 case 3:
222 gpio_set_value(MCFQSPI_CS3, cs_high);
223 break;
224 }
225}
226
227static void m527x_cs_deselect(struct mcfqspi_cs_control *cs_control,
228 u8 chip_select, bool cs_high)
229{
230 switch (chip_select) {
231 case 0:
232 gpio_set_value(MCFQSPI_CS0, !cs_high);
233 break;
234 case 1:
235 gpio_set_value(MCFQSPI_CS1, !cs_high);
236 break;
237 case 2:
238 gpio_set_value(MCFQSPI_CS2, !cs_high);
239 break;
240 case 3:
241 gpio_set_value(MCFQSPI_CS3, !cs_high);
242 break;
243 }
244}
245
246static struct mcfqspi_cs_control m527x_cs_control = {
247 .setup = m527x_cs_setup,
248 .teardown = m527x_cs_teardown,
249 .select = m527x_cs_select,
250 .deselect = m527x_cs_deselect,
251};
252
253static struct mcfqspi_platform_data m527x_qspi_data = {
254 .bus_num = 0,
255 .num_chipselect = 4,
256 .cs_control = &m527x_cs_control,
257};
258
259static struct platform_device m527x_qspi = {
260 .name = "mcfqspi",
261 .id = 0,
262 .num_resources = ARRAY_SIZE(m527x_qspi_resources),
263 .resource = m527x_qspi_resources,
264 .dev.platform_data = &m527x_qspi_data,
265};
266 27
267static void __init m527x_qspi_init(void) 28static void __init m527x_qspi_init(void)
268{ 29{
@@ -280,50 +41,23 @@ static void __init m527x_qspi_init(void)
280 writew(0x003e, MCFGPIO_PAR_QSPI); 41 writew(0x003e, MCFGPIO_PAR_QSPI);
281#endif 42#endif
282} 43}
283#endif /* defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) */
284 44
285static struct platform_device *m527x_devices[] __initdata = { 45#endif /* CONFIG_SPI_COLDFIRE_QSPI */
286 &m527x_uart,
287 &m527x_fec[0],
288#ifdef CONFIG_FEC2
289 &m527x_fec[1],
290#endif
291#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
292 &m527x_qspi,
293#endif
294};
295 46
296/***************************************************************************/ 47/***************************************************************************/
297 48
298static void __init m527x_uart_init_line(int line, int irq) 49static void __init m527x_uarts_init(void)
299{ 50{
300 u16 sepmask; 51 u16 sepmask;
301 52
302 if ((line < 0) || (line > 2))
303 return;
304
305 /* 53 /*
306 * External Pin Mask Setting & Enable External Pin for Interface 54 * External Pin Mask Setting & Enable External Pin for Interface
307 */ 55 */
308 sepmask = readw(MCF_IPSBAR + MCF_GPIO_PAR_UART); 56 sepmask = readw(MCF_IPSBAR + MCF_GPIO_PAR_UART);
309 if (line == 0) 57 sepmask |= UART0_ENABLE_MASK | UART1_ENABLE_MASK | UART2_ENABLE_MASK;
310 sepmask |= UART0_ENABLE_MASK;
311 else if (line == 1)
312 sepmask |= UART1_ENABLE_MASK;
313 else if (line == 2)
314 sepmask |= UART2_ENABLE_MASK;
315 writew(sepmask, MCF_IPSBAR + MCF_GPIO_PAR_UART); 58 writew(sepmask, MCF_IPSBAR + MCF_GPIO_PAR_UART);
316} 59}
317 60
318static void __init m527x_uarts_init(void)
319{
320 const int nrlines = ARRAY_SIZE(m527x_uart_platform);
321 int line;
322
323 for (line = 0; (line < nrlines); line++)
324 m527x_uart_init_line(line, m527x_uart_platform[line].irq);
325}
326
327/***************************************************************************/ 61/***************************************************************************/
328 62
329static void __init m527x_fec_init(void) 63static void __init m527x_fec_init(void)
@@ -353,32 +87,14 @@ static void __init m527x_fec_init(void)
353 87
354/***************************************************************************/ 88/***************************************************************************/
355 89
356static void m527x_cpu_reset(void)
357{
358 local_irq_disable();
359 __raw_writeb(MCF_RCR_SWRESET, MCF_IPSBAR + MCF_RCR);
360}
361
362/***************************************************************************/
363
364void __init config_BSP(char *commandp, int size) 90void __init config_BSP(char *commandp, int size)
365{ 91{
366 mach_reset = m527x_cpu_reset; 92 mach_sched_init = hw_timer_init;
367 m527x_uarts_init(); 93 m527x_uarts_init();
368 m527x_fec_init(); 94 m527x_fec_init();
369#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) 95#ifdef CONFIG_SPI_COLDFIRE_QSPI
370 m527x_qspi_init(); 96 m527x_qspi_init();
371#endif 97#endif
372} 98}
373 99
374/***************************************************************************/ 100/***************************************************************************/
375
376static int __init init_BSP(void)
377{
378 platform_add_devices(m527x_devices, ARRAY_SIZE(m527x_devices));
379 return 0;
380}
381
382arch_initcall(init_BSP);
383
384/***************************************************************************/
diff --git a/arch/m68k/platform/528x/config.c b/arch/m68k/platform/528x/config.c
index 7abe77a2f3e3..d4492926614c 100644
--- a/arch/m68k/platform/528x/config.c
+++ b/arch/m68k/platform/528x/config.c
@@ -17,229 +17,33 @@
17#include <linux/init.h> 17#include <linux/init.h>
18#include <linux/platform_device.h> 18#include <linux/platform_device.h>
19#include <linux/io.h> 19#include <linux/io.h>
20#include <linux/spi/spi.h>
21#include <linux/gpio.h>
22#include <asm/machdep.h> 20#include <asm/machdep.h>
23#include <asm/coldfire.h> 21#include <asm/coldfire.h>
24#include <asm/mcfsim.h> 22#include <asm/mcfsim.h>
25#include <asm/mcfuart.h> 23#include <asm/mcfuart.h>
26#include <asm/mcfqspi.h>
27 24
28/***************************************************************************/ 25/***************************************************************************/
29 26
30static struct mcf_platform_uart m528x_uart_platform[] = { 27#ifdef CONFIG_SPI_COLDFIRE_QSPI
31 {
32 .mapbase = MCFUART_BASE1,
33 .irq = MCFINT_VECBASE + MCFINT_UART0,
34 },
35 {
36 .mapbase = MCFUART_BASE2,
37 .irq = MCFINT_VECBASE + MCFINT_UART0 + 1,
38 },
39 {
40 .mapbase = MCFUART_BASE3,
41 .irq = MCFINT_VECBASE + MCFINT_UART0 + 2,
42 },
43 { },
44};
45
46static struct platform_device m528x_uart = {
47 .name = "mcfuart",
48 .id = 0,
49 .dev.platform_data = m528x_uart_platform,
50};
51
52static struct resource m528x_fec_resources[] = {
53 {
54 .start = MCFFEC_BASE,
55 .end = MCFFEC_BASE + MCFFEC_SIZE - 1,
56 .flags = IORESOURCE_MEM,
57 },
58 {
59 .start = 64 + 23,
60 .end = 64 + 23,
61 .flags = IORESOURCE_IRQ,
62 },
63 {
64 .start = 64 + 27,
65 .end = 64 + 27,
66 .flags = IORESOURCE_IRQ,
67 },
68 {
69 .start = 64 + 29,
70 .end = 64 + 29,
71 .flags = IORESOURCE_IRQ,
72 },
73};
74
75static struct platform_device m528x_fec = {
76 .name = "fec",
77 .id = 0,
78 .num_resources = ARRAY_SIZE(m528x_fec_resources),
79 .resource = m528x_fec_resources,
80};
81
82#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
83static struct resource m528x_qspi_resources[] = {
84 {
85 .start = MCFQSPI_IOBASE,
86 .end = MCFQSPI_IOBASE + MCFQSPI_IOSIZE - 1,
87 .flags = IORESOURCE_MEM,
88 },
89 {
90 .start = MCFINT_VECBASE + MCFINT_QSPI,
91 .end = MCFINT_VECBASE + MCFINT_QSPI,
92 .flags = IORESOURCE_IRQ,
93 },
94};
95
96#define MCFQSPI_CS0 147
97#define MCFQSPI_CS1 148
98#define MCFQSPI_CS2 149
99#define MCFQSPI_CS3 150
100
101static int m528x_cs_setup(struct mcfqspi_cs_control *cs_control)
102{
103 int status;
104
105 status = gpio_request(MCFQSPI_CS0, "MCFQSPI_CS0");
106 if (status) {
107 pr_debug("gpio_request for MCFQSPI_CS0 failed\n");
108 goto fail0;
109 }
110 status = gpio_direction_output(MCFQSPI_CS0, 1);
111 if (status) {
112 pr_debug("gpio_direction_output for MCFQSPI_CS0 failed\n");
113 goto fail1;
114 }
115
116 status = gpio_request(MCFQSPI_CS1, "MCFQSPI_CS1");
117 if (status) {
118 pr_debug("gpio_request for MCFQSPI_CS1 failed\n");
119 goto fail1;
120 }
121 status = gpio_direction_output(MCFQSPI_CS1, 1);
122 if (status) {
123 pr_debug("gpio_direction_output for MCFQSPI_CS1 failed\n");
124 goto fail2;
125 }
126
127 status = gpio_request(MCFQSPI_CS2, "MCFQSPI_CS2");
128 if (status) {
129 pr_debug("gpio_request for MCFQSPI_CS2 failed\n");
130 goto fail2;
131 }
132 status = gpio_direction_output(MCFQSPI_CS2, 1);
133 if (status) {
134 pr_debug("gpio_direction_output for MCFQSPI_CS2 failed\n");
135 goto fail3;
136 }
137
138 status = gpio_request(MCFQSPI_CS3, "MCFQSPI_CS3");
139 if (status) {
140 pr_debug("gpio_request for MCFQSPI_CS3 failed\n");
141 goto fail3;
142 }
143 status = gpio_direction_output(MCFQSPI_CS3, 1);
144 if (status) {
145 pr_debug("gpio_direction_output for MCFQSPI_CS3 failed\n");
146 goto fail4;
147 }
148
149 return 0;
150
151fail4:
152 gpio_free(MCFQSPI_CS3);
153fail3:
154 gpio_free(MCFQSPI_CS2);
155fail2:
156 gpio_free(MCFQSPI_CS1);
157fail1:
158 gpio_free(MCFQSPI_CS0);
159fail0:
160 return status;
161}
162
163static void m528x_cs_teardown(struct mcfqspi_cs_control *cs_control)
164{
165 gpio_free(MCFQSPI_CS3);
166 gpio_free(MCFQSPI_CS2);
167 gpio_free(MCFQSPI_CS1);
168 gpio_free(MCFQSPI_CS0);
169}
170
171static void m528x_cs_select(struct mcfqspi_cs_control *cs_control,
172 u8 chip_select, bool cs_high)
173{
174 gpio_set_value(MCFQSPI_CS0 + chip_select, cs_high);
175}
176
177static void m528x_cs_deselect(struct mcfqspi_cs_control *cs_control,
178 u8 chip_select, bool cs_high)
179{
180 gpio_set_value(MCFQSPI_CS0 + chip_select, !cs_high);
181}
182
183static struct mcfqspi_cs_control m528x_cs_control = {
184 .setup = m528x_cs_setup,
185 .teardown = m528x_cs_teardown,
186 .select = m528x_cs_select,
187 .deselect = m528x_cs_deselect,
188};
189
190static struct mcfqspi_platform_data m528x_qspi_data = {
191 .bus_num = 0,
192 .num_chipselect = 4,
193 .cs_control = &m528x_cs_control,
194};
195
196static struct platform_device m528x_qspi = {
197 .name = "mcfqspi",
198 .id = 0,
199 .num_resources = ARRAY_SIZE(m528x_qspi_resources),
200 .resource = m528x_qspi_resources,
201 .dev.platform_data = &m528x_qspi_data,
202};
203 28
204static void __init m528x_qspi_init(void) 29static void __init m528x_qspi_init(void)
205{ 30{
206 /* setup Port QS for QSPI with gpio CS control */ 31 /* setup Port QS for QSPI with gpio CS control */
207 __raw_writeb(0x07, MCFGPIO_PQSPAR); 32 __raw_writeb(0x07, MCFGPIO_PQSPAR);
208} 33}
209#endif /* defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) */
210 34
211static struct platform_device *m528x_devices[] __initdata = { 35#endif /* CONFIG_SPI_COLDFIRE_QSPI */
212 &m528x_uart,
213 &m528x_fec,
214#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
215 &m528x_qspi,
216#endif
217};
218 36
219/***************************************************************************/ 37/***************************************************************************/
220 38
221static void __init m528x_uart_init_line(int line, int irq) 39static void __init m528x_uarts_init(void)
222{ 40{
223 u8 port; 41 u8 port;
224 42
225 if ((line < 0) || (line > 2))
226 return;
227
228 /* make sure PUAPAR is set for UART0 and UART1 */ 43 /* make sure PUAPAR is set for UART0 and UART1 */
229 if (line < 2) { 44 port = readb(MCF5282_GPIO_PUAPAR);
230 port = readb(MCF5282_GPIO_PUAPAR); 45 port |= 0x03 | (0x03 << 2);
231 port |= (0x03 << (line * 2)); 46 writeb(port, MCF5282_GPIO_PUAPAR);
232 writeb(port, MCF5282_GPIO_PUAPAR);
233 }
234}
235
236static void __init m528x_uarts_init(void)
237{
238 const int nrlines = ARRAY_SIZE(m528x_uart_platform);
239 int line;
240
241 for (line = 0; (line < nrlines); line++)
242 m528x_uart_init_line(line, m528x_uart_platform[line].irq);
243} 47}
244 48
245/***************************************************************************/ 49/***************************************************************************/
@@ -256,14 +60,6 @@ static void __init m528x_fec_init(void)
256 60
257/***************************************************************************/ 61/***************************************************************************/
258 62
259static void m528x_cpu_reset(void)
260{
261 local_irq_disable();
262 __raw_writeb(MCF_RCR_SWRESET, MCF_IPSBAR + MCF_RCR);
263}
264
265/***************************************************************************/
266
267#ifdef CONFIG_WILDFIRE 63#ifdef CONFIG_WILDFIRE
268void wildfire_halt(void) 64void wildfire_halt(void)
269{ 65{
@@ -299,22 +95,12 @@ void __init config_BSP(char *commandp, int size)
299#ifdef CONFIG_WILDFIREMOD 95#ifdef CONFIG_WILDFIREMOD
300 mach_halt = wildfiremod_halt; 96 mach_halt = wildfiremod_halt;
301#endif 97#endif
302} 98 mach_sched_init = hw_timer_init;
303
304/***************************************************************************/
305
306static int __init init_BSP(void)
307{
308 mach_reset = m528x_cpu_reset;
309 m528x_uarts_init(); 99 m528x_uarts_init();
310 m528x_fec_init(); 100 m528x_fec_init();
311#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) 101#ifdef CONFIG_SPI_COLDFIRE_QSPI
312 m528x_qspi_init(); 102 m528x_qspi_init();
313#endif 103#endif
314 platform_add_devices(m528x_devices, ARRAY_SIZE(m528x_devices));
315 return 0;
316} 104}
317 105
318arch_initcall(init_BSP);
319
320/***************************************************************************/ 106/***************************************************************************/
diff --git a/arch/m68k/platform/5307/config.c b/arch/m68k/platform/5307/config.c
index 00900ac06a9c..a568d2870d15 100644
--- a/arch/m68k/platform/5307/config.c
+++ b/arch/m68k/platform/5307/config.c
@@ -16,7 +16,6 @@
16#include <asm/machdep.h> 16#include <asm/machdep.h>
17#include <asm/coldfire.h> 17#include <asm/coldfire.h>
18#include <asm/mcfsim.h> 18#include <asm/mcfsim.h>
19#include <asm/mcfuart.h>
20#include <asm/mcfwdebug.h> 19#include <asm/mcfwdebug.h>
21 20
22/***************************************************************************/ 21/***************************************************************************/
@@ -29,82 +28,6 @@ unsigned char ledbank = 0xff;
29 28
30/***************************************************************************/ 29/***************************************************************************/
31 30
32static struct mcf_platform_uart m5307_uart_platform[] = {
33 {
34 .mapbase = MCF_MBAR + MCFUART_BASE1,
35 .irq = 73,
36 },
37 {
38 .mapbase = MCF_MBAR + MCFUART_BASE2,
39 .irq = 74,
40 },
41 { },
42};
43
44static struct platform_device m5307_uart = {
45 .name = "mcfuart",
46 .id = 0,
47 .dev.platform_data = m5307_uart_platform,
48};
49
50static struct platform_device *m5307_devices[] __initdata = {
51 &m5307_uart,
52};
53
54/***************************************************************************/
55
56static void __init m5307_uart_init_line(int line, int irq)
57{
58 if (line == 0) {
59 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR);
60 writeb(irq, MCF_MBAR + MCFUART_BASE1 + MCFUART_UIVR);
61 mcf_mapirq2imr(irq, MCFINTC_UART0);
62 } else if (line == 1) {
63 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR);
64 writeb(irq, MCF_MBAR + MCFUART_BASE2 + MCFUART_UIVR);
65 mcf_mapirq2imr(irq, MCFINTC_UART1);
66 }
67}
68
69static void __init m5307_uarts_init(void)
70{
71 const int nrlines = ARRAY_SIZE(m5307_uart_platform);
72 int line;
73
74 for (line = 0; (line < nrlines); line++)
75 m5307_uart_init_line(line, m5307_uart_platform[line].irq);
76}
77
78/***************************************************************************/
79
80static void __init m5307_timers_init(void)
81{
82 /* Timer1 is always used as system timer */
83 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3,
84 MCF_MBAR + MCFSIM_TIMER1ICR);
85 mcf_mapirq2imr(MCF_IRQ_TIMER, MCFINTC_TIMER1);
86
87#ifdef CONFIG_HIGHPROFILE
88 /* Timer2 is to be used as a high speed profile timer */
89 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3,
90 MCF_MBAR + MCFSIM_TIMER2ICR);
91 mcf_mapirq2imr(MCF_IRQ_PROFILER, MCFINTC_TIMER2);
92#endif
93}
94
95/***************************************************************************/
96
97void m5307_cpu_reset(void)
98{
99 local_irq_disable();
100 /* Set watchdog to soft reset, and enabled */
101 __raw_writeb(0xc0, MCF_MBAR + MCFSIM_SYPCR);
102 for (;;)
103 /* wait for watchdog to timeout */;
104}
105
106/***************************************************************************/
107
108void __init config_BSP(char *commandp, int size) 31void __init config_BSP(char *commandp, int size)
109{ 32{
110#if defined(CONFIG_NETtel) || \ 33#if defined(CONFIG_NETtel) || \
@@ -114,9 +37,7 @@ void __init config_BSP(char *commandp, int size)
114 commandp[size-1] = 0; 37 commandp[size-1] = 0;
115#endif 38#endif
116 39
117 mach_reset = m5307_cpu_reset; 40 mach_sched_init = hw_timer_init;
118 m5307_timers_init();
119 m5307_uarts_init();
120 41
121 /* Only support the external interrupts on their primary level */ 42 /* Only support the external interrupts on their primary level */
122 mcf_mapirq2imr(25, MCFINTC_EINT1); 43 mcf_mapirq2imr(25, MCFINTC_EINT1);
@@ -135,13 +56,3 @@ void __init config_BSP(char *commandp, int size)
135} 56}
136 57
137/***************************************************************************/ 58/***************************************************************************/
138
139static int __init init_BSP(void)
140{
141 platform_add_devices(m5307_devices, ARRAY_SIZE(m5307_devices));
142 return 0;
143}
144
145arch_initcall(init_BSP);
146
147/***************************************************************************/
diff --git a/arch/m68k/platform/532x/config.c b/arch/m68k/platform/532x/config.c
index ca51323f957b..2bec3477b739 100644
--- a/arch/m68k/platform/532x/config.c
+++ b/arch/m68k/platform/532x/config.c
@@ -21,214 +21,33 @@
21#include <linux/param.h> 21#include <linux/param.h>
22#include <linux/init.h> 22#include <linux/init.h>
23#include <linux/io.h> 23#include <linux/io.h>
24#include <linux/spi/spi.h>
25#include <linux/gpio.h>
26#include <asm/machdep.h> 24#include <asm/machdep.h>
27#include <asm/coldfire.h> 25#include <asm/coldfire.h>
28#include <asm/mcfsim.h> 26#include <asm/mcfsim.h>
29#include <asm/mcfuart.h> 27#include <asm/mcfuart.h>
30#include <asm/mcfdma.h> 28#include <asm/mcfdma.h>
31#include <asm/mcfwdebug.h> 29#include <asm/mcfwdebug.h>
32#include <asm/mcfqspi.h>
33 30
34/***************************************************************************/ 31/***************************************************************************/
35 32
36static struct mcf_platform_uart m532x_uart_platform[] = { 33#ifdef CONFIG_SPI_COLDFIRE_QSPI
37 {
38 .mapbase = MCFUART_BASE1,
39 .irq = MCFINT_VECBASE + MCFINT_UART0,
40 },
41 {
42 .mapbase = MCFUART_BASE2,
43 .irq = MCFINT_VECBASE + MCFINT_UART1,
44 },
45 {
46 .mapbase = MCFUART_BASE3,
47 .irq = MCFINT_VECBASE + MCFINT_UART2,
48 },
49 { },
50};
51
52static struct platform_device m532x_uart = {
53 .name = "mcfuart",
54 .id = 0,
55 .dev.platform_data = m532x_uart_platform,
56};
57
58static struct resource m532x_fec_resources[] = {
59 {
60 .start = 0xfc030000,
61 .end = 0xfc0307ff,
62 .flags = IORESOURCE_MEM,
63 },
64 {
65 .start = 64 + 36,
66 .end = 64 + 36,
67 .flags = IORESOURCE_IRQ,
68 },
69 {
70 .start = 64 + 40,
71 .end = 64 + 40,
72 .flags = IORESOURCE_IRQ,
73 },
74 {
75 .start = 64 + 42,
76 .end = 64 + 42,
77 .flags = IORESOURCE_IRQ,
78 },
79};
80
81static struct platform_device m532x_fec = {
82 .name = "fec",
83 .id = 0,
84 .num_resources = ARRAY_SIZE(m532x_fec_resources),
85 .resource = m532x_fec_resources,
86};
87
88#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
89static struct resource m532x_qspi_resources[] = {
90 {
91 .start = MCFQSPI_IOBASE,
92 .end = MCFQSPI_IOBASE + MCFQSPI_IOSIZE - 1,
93 .flags = IORESOURCE_MEM,
94 },
95 {
96 .start = MCFINT_VECBASE + MCFINT_QSPI,
97 .end = MCFINT_VECBASE + MCFINT_QSPI,
98 .flags = IORESOURCE_IRQ,
99 },
100};
101
102#define MCFQSPI_CS0 84
103#define MCFQSPI_CS1 85
104#define MCFQSPI_CS2 86
105
106static int m532x_cs_setup(struct mcfqspi_cs_control *cs_control)
107{
108 int status;
109
110 status = gpio_request(MCFQSPI_CS0, "MCFQSPI_CS0");
111 if (status) {
112 pr_debug("gpio_request for MCFQSPI_CS0 failed\n");
113 goto fail0;
114 }
115 status = gpio_direction_output(MCFQSPI_CS0, 1);
116 if (status) {
117 pr_debug("gpio_direction_output for MCFQSPI_CS0 failed\n");
118 goto fail1;
119 }
120
121 status = gpio_request(MCFQSPI_CS1, "MCFQSPI_CS1");
122 if (status) {
123 pr_debug("gpio_request for MCFQSPI_CS1 failed\n");
124 goto fail1;
125 }
126 status = gpio_direction_output(MCFQSPI_CS1, 1);
127 if (status) {
128 pr_debug("gpio_direction_output for MCFQSPI_CS1 failed\n");
129 goto fail2;
130 }
131
132 status = gpio_request(MCFQSPI_CS2, "MCFQSPI_CS2");
133 if (status) {
134 pr_debug("gpio_request for MCFQSPI_CS2 failed\n");
135 goto fail2;
136 }
137 status = gpio_direction_output(MCFQSPI_CS2, 1);
138 if (status) {
139 pr_debug("gpio_direction_output for MCFQSPI_CS2 failed\n");
140 goto fail3;
141 }
142
143 return 0;
144
145fail3:
146 gpio_free(MCFQSPI_CS2);
147fail2:
148 gpio_free(MCFQSPI_CS1);
149fail1:
150 gpio_free(MCFQSPI_CS0);
151fail0:
152 return status;
153}
154
155static void m532x_cs_teardown(struct mcfqspi_cs_control *cs_control)
156{
157 gpio_free(MCFQSPI_CS2);
158 gpio_free(MCFQSPI_CS1);
159 gpio_free(MCFQSPI_CS0);
160}
161
162static void m532x_cs_select(struct mcfqspi_cs_control *cs_control,
163 u8 chip_select, bool cs_high)
164{
165 gpio_set_value(MCFQSPI_CS0 + chip_select, cs_high);
166}
167
168static void m532x_cs_deselect(struct mcfqspi_cs_control *cs_control,
169 u8 chip_select, bool cs_high)
170{
171 gpio_set_value(MCFQSPI_CS0 + chip_select, !cs_high);
172}
173
174static struct mcfqspi_cs_control m532x_cs_control = {
175 .setup = m532x_cs_setup,
176 .teardown = m532x_cs_teardown,
177 .select = m532x_cs_select,
178 .deselect = m532x_cs_deselect,
179};
180
181static struct mcfqspi_platform_data m532x_qspi_data = {
182 .bus_num = 0,
183 .num_chipselect = 3,
184 .cs_control = &m532x_cs_control,
185};
186
187static struct platform_device m532x_qspi = {
188 .name = "mcfqspi",
189 .id = 0,
190 .num_resources = ARRAY_SIZE(m532x_qspi_resources),
191 .resource = m532x_qspi_resources,
192 .dev.platform_data = &m532x_qspi_data,
193};
194 34
195static void __init m532x_qspi_init(void) 35static void __init m532x_qspi_init(void)
196{ 36{
197 /* setup QSPS pins for QSPI with gpio CS control */ 37 /* setup QSPS pins for QSPI with gpio CS control */
198 writew(0x01f0, MCF_GPIO_PAR_QSPI); 38 writew(0x01f0, MCF_GPIO_PAR_QSPI);
199} 39}
200#endif /* defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) */
201 40
202 41#endif /* CONFIG_SPI_COLDFIRE_QSPI */
203static struct platform_device *m532x_devices[] __initdata = {
204 &m532x_uart,
205 &m532x_fec,
206#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
207 &m532x_qspi,
208#endif
209};
210 42
211/***************************************************************************/ 43/***************************************************************************/
212 44
213static void __init m532x_uart_init_line(int line, int irq)
214{
215 if (line == 0) {
216 /* GPIO initialization */
217 MCF_GPIO_PAR_UART |= 0x000F;
218 } else if (line == 1) {
219 /* GPIO initialization */
220 MCF_GPIO_PAR_UART |= 0x0FF0;
221 }
222}
223
224static void __init m532x_uarts_init(void) 45static void __init m532x_uarts_init(void)
225{ 46{
226 const int nrlines = ARRAY_SIZE(m532x_uart_platform); 47 /* UART GPIO initialization */
227 int line; 48 MCF_GPIO_PAR_UART |= 0x0FFF;
228
229 for (line = 0; (line < nrlines); line++)
230 m532x_uart_init_line(line, m532x_uart_platform[line].irq);
231} 49}
50
232/***************************************************************************/ 51/***************************************************************************/
233 52
234static void __init m532x_fec_init(void) 53static void __init m532x_fec_init(void)
@@ -242,14 +61,6 @@ static void __init m532x_fec_init(void)
242 61
243/***************************************************************************/ 62/***************************************************************************/
244 63
245static void m532x_cpu_reset(void)
246{
247 local_irq_disable();
248 __raw_writeb(MCF_RCR_SWRESET, MCF_RCR);
249}
250
251/***************************************************************************/
252
253void __init config_BSP(char *commandp, int size) 64void __init config_BSP(char *commandp, int size)
254{ 65{
255#if !defined(CONFIG_BOOTPARAM) 66#if !defined(CONFIG_BOOTPARAM)
@@ -263,6 +74,13 @@ void __init config_BSP(char *commandp, int size)
263 } 74 }
264#endif 75#endif
265 76
77 mach_sched_init = hw_timer_init;
78 m532x_uarts_init();
79 m532x_fec_init();
80#ifdef CONFIG_SPI_COLDFIRE_QSPI
81 m532x_qspi_init();
82#endif
83
266#ifdef CONFIG_BDM_DISABLE 84#ifdef CONFIG_BDM_DISABLE
267 /* 85 /*
268 * Disable the BDM clocking. This also turns off most of the rest of 86 * Disable the BDM clocking. This also turns off most of the rest of
@@ -274,21 +92,6 @@ void __init config_BSP(char *commandp, int size)
274} 92}
275 93
276/***************************************************************************/ 94/***************************************************************************/
277
278static int __init init_BSP(void)
279{
280 m532x_uarts_init();
281 m532x_fec_init();
282#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
283 m532x_qspi_init();
284#endif
285 platform_add_devices(m532x_devices, ARRAY_SIZE(m532x_devices));
286 return 0;
287}
288
289arch_initcall(init_BSP);
290
291/***************************************************************************/
292/* Board initialization */ 95/* Board initialization */
293/***************************************************************************/ 96/***************************************************************************/
294/* 97/*
diff --git a/arch/m68k/platform/5407/config.c b/arch/m68k/platform/5407/config.c
index 70ea789a400c..bb6c746ae819 100644
--- a/arch/m68k/platform/5407/config.c
+++ b/arch/m68k/platform/5407/config.c
@@ -16,91 +16,12 @@
16#include <asm/machdep.h> 16#include <asm/machdep.h>
17#include <asm/coldfire.h> 17#include <asm/coldfire.h>
18#include <asm/mcfsim.h> 18#include <asm/mcfsim.h>
19#include <asm/mcfuart.h>
20
21/***************************************************************************/
22
23static struct mcf_platform_uart m5407_uart_platform[] = {
24 {
25 .mapbase = MCF_MBAR + MCFUART_BASE1,
26 .irq = 73,
27 },
28 {
29 .mapbase = MCF_MBAR + MCFUART_BASE2,
30 .irq = 74,
31 },
32 { },
33};
34
35static struct platform_device m5407_uart = {
36 .name = "mcfuart",
37 .id = 0,
38 .dev.platform_data = m5407_uart_platform,
39};
40
41static struct platform_device *m5407_devices[] __initdata = {
42 &m5407_uart,
43};
44
45/***************************************************************************/
46
47static void __init m5407_uart_init_line(int line, int irq)
48{
49 if (line == 0) {
50 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR);
51 writeb(irq, MCF_MBAR + MCFUART_BASE1 + MCFUART_UIVR);
52 mcf_mapirq2imr(irq, MCFINTC_UART0);
53 } else if (line == 1) {
54 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR);
55 writeb(irq, MCF_MBAR + MCFUART_BASE2 + MCFUART_UIVR);
56 mcf_mapirq2imr(irq, MCFINTC_UART1);
57 }
58}
59
60static void __init m5407_uarts_init(void)
61{
62 const int nrlines = ARRAY_SIZE(m5407_uart_platform);
63 int line;
64
65 for (line = 0; (line < nrlines); line++)
66 m5407_uart_init_line(line, m5407_uart_platform[line].irq);
67}
68
69/***************************************************************************/
70
71static void __init m5407_timers_init(void)
72{
73 /* Timer1 is always used as system timer */
74 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3,
75 MCF_MBAR + MCFSIM_TIMER1ICR);
76 mcf_mapirq2imr(MCF_IRQ_TIMER, MCFINTC_TIMER1);
77
78#ifdef CONFIG_HIGHPROFILE
79 /* Timer2 is to be used as a high speed profile timer */
80 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3,
81 MCF_MBAR + MCFSIM_TIMER2ICR);
82 mcf_mapirq2imr(MCF_IRQ_PROFILER, MCFINTC_TIMER2);
83#endif
84}
85
86/***************************************************************************/
87
88void m5407_cpu_reset(void)
89{
90 local_irq_disable();
91 /* set watchdog to soft reset, and enabled */
92 __raw_writeb(0xc0, MCF_MBAR + MCFSIM_SYPCR);
93 for (;;)
94 /* wait for watchdog to timeout */;
95}
96 19
97/***************************************************************************/ 20/***************************************************************************/
98 21
99void __init config_BSP(char *commandp, int size) 22void __init config_BSP(char *commandp, int size)
100{ 23{
101 mach_reset = m5407_cpu_reset; 24 mach_sched_init = hw_timer_init;
102 m5407_timers_init();
103 m5407_uarts_init();
104 25
105 /* Only support the external interrupts on their primary level */ 26 /* Only support the external interrupts on their primary level */
106 mcf_mapirq2imr(25, MCFINTC_EINT1); 27 mcf_mapirq2imr(25, MCFINTC_EINT1);
@@ -110,13 +31,3 @@ void __init config_BSP(char *commandp, int size)
110} 31}
111 32
112/***************************************************************************/ 33/***************************************************************************/
113
114static int __init init_BSP(void)
115{
116 platform_add_devices(m5407_devices, ARRAY_SIZE(m5407_devices));
117 return 0;
118}
119
120arch_initcall(init_BSP);
121
122/***************************************************************************/
diff --git a/arch/m68k/platform/54xx/config.c b/arch/m68k/platform/54xx/config.c
index ee043540bfa2..2081c6cbb3de 100644
--- a/arch/m68k/platform/54xx/config.c
+++ b/arch/m68k/platform/54xx/config.c
@@ -27,64 +27,17 @@
27 27
28/***************************************************************************/ 28/***************************************************************************/
29 29
30static struct mcf_platform_uart m54xx_uart_platform[] = {
31 {
32 .mapbase = MCF_MBAR + MCFUART_BASE1,
33 .irq = 64 + 35,
34 },
35 {
36 .mapbase = MCF_MBAR + MCFUART_BASE2,
37 .irq = 64 + 34,
38 },
39 {
40 .mapbase = MCF_MBAR + MCFUART_BASE3,
41 .irq = 64 + 33,
42 },
43 {
44 .mapbase = MCF_MBAR + MCFUART_BASE4,
45 .irq = 64 + 32,
46 },
47};
48
49static struct platform_device m54xx_uart = {
50 .name = "mcfuart",
51 .id = 0,
52 .dev.platform_data = m54xx_uart_platform,
53};
54
55static struct platform_device *m54xx_devices[] __initdata = {
56 &m54xx_uart,
57};
58
59
60/***************************************************************************/
61
62static void __init m54xx_uart_init_line(int line, int irq)
63{
64 int rts_cts;
65
66 /* enable io pins */
67 switch (line) {
68 case 0:
69 rts_cts = 0; break;
70 case 1:
71 rts_cts = MCF_PAR_PSC_RTS_RTS; break;
72 case 2:
73 rts_cts = MCF_PAR_PSC_RTS_RTS | MCF_PAR_PSC_CTS_CTS; break;
74 case 3:
75 rts_cts = 0; break;
76 }
77 __raw_writeb(MCF_PAR_PSC_TXD | rts_cts | MCF_PAR_PSC_RXD,
78 MCF_MBAR + MCF_PAR_PSC(line));
79}
80
81static void __init m54xx_uarts_init(void) 30static void __init m54xx_uarts_init(void)
82{ 31{
83 const int nrlines = ARRAY_SIZE(m54xx_uart_platform); 32 /* enable io pins */
84 int line; 33 __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD,
85 34 MCF_MBAR + MCF_PAR_PSC(0));
86 for (line = 0; (line < nrlines); line++) 35 __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD | MCF_PAR_PSC_RTS_RTS,
87 m54xx_uart_init_line(line, m54xx_uart_platform[line].irq); 36 MCF_MBAR + MCF_PAR_PSC(1));
37 __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD | MCF_PAR_PSC_RTS_RTS |
38 MCF_PAR_PSC_CTS_CTS, MCF_MBAR + MCF_PAR_PSC(2));
39 __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD,
40 MCF_MBAR + MCF_PAR_PSC(3));
88} 41}
89 42
90/***************************************************************************/ 43/***************************************************************************/
@@ -145,18 +98,8 @@ void __init config_BSP(char *commandp, int size)
145 mmu_context_init(); 98 mmu_context_init();
146#endif 99#endif
147 mach_reset = mcf54xx_reset; 100 mach_reset = mcf54xx_reset;
101 mach_sched_init = hw_timer_init;
148 m54xx_uarts_init(); 102 m54xx_uarts_init();
149} 103}
150 104
151/***************************************************************************/ 105/***************************************************************************/
152
153static int __init init_BSP(void)
154{
155
156 platform_add_devices(m54xx_devices, ARRAY_SIZE(m54xx_devices));
157 return 0;
158}
159
160arch_initcall(init_BSP);
161
162/***************************************************************************/
diff --git a/arch/m68k/platform/68328/config.c b/arch/m68k/platform/68328/config.c
index d70bf2623db1..44b866544314 100644
--- a/arch/m68k/platform/68328/config.c
+++ b/arch/m68k/platform/68328/config.c
@@ -17,6 +17,7 @@
17 17
18#include <linux/types.h> 18#include <linux/types.h>
19#include <linux/kernel.h> 19#include <linux/kernel.h>
20#include <linux/rtc.h>
20#include <asm/system.h> 21#include <asm/system.h>
21#include <asm/machdep.h> 22#include <asm/machdep.h>
22#include <asm/MC68328.h> 23#include <asm/MC68328.h>
@@ -26,7 +27,7 @@
26 27
27/***************************************************************************/ 28/***************************************************************************/
28 29
29void m68328_timer_gettod(int *year, int *mon, int *day, int *hour, int *min, int *sec); 30int m68328_hwclk(int set, struct rtc_time *t);
30 31
31/***************************************************************************/ 32/***************************************************************************/
32 33
@@ -48,7 +49,7 @@ void config_BSP(char *command, int len)
48 printk(KERN_INFO "68328 support Kenneth Albanowski <kjahds@kjshds.com>\n"); 49 printk(KERN_INFO "68328 support Kenneth Albanowski <kjahds@kjshds.com>\n");
49 printk(KERN_INFO "68328/Pilot support Bernhard Kuhn <kuhn@lpr.e-technik.tu-muenchen.de>\n"); 50 printk(KERN_INFO "68328/Pilot support Bernhard Kuhn <kuhn@lpr.e-technik.tu-muenchen.de>\n");
50 51
51 mach_gettod = m68328_timer_gettod; 52 mach_hwclk = m68328_hwclk;
52 mach_reset = m68328_reset; 53 mach_reset = m68328_reset;
53} 54}
54 55
diff --git a/arch/m68k/platform/68328/ints.c b/arch/m68k/platform/68328/ints.c
index 4bd456531f91..b3810febb3e3 100644
--- a/arch/m68k/platform/68328/ints.c
+++ b/arch/m68k/platform/68328/ints.c
@@ -68,8 +68,6 @@ asmlinkage irqreturn_t inthandler5(void);
68asmlinkage irqreturn_t inthandler6(void); 68asmlinkage irqreturn_t inthandler6(void);
69asmlinkage irqreturn_t inthandler7(void); 69asmlinkage irqreturn_t inthandler7(void);
70 70
71extern e_vector *_ramvec;
72
73/* The 68k family did not have a good way to determine the source 71/* The 68k family did not have a good way to determine the source
74 * of interrupts until later in the family. The EC000 core does 72 * of interrupts until later in the family. The EC000 core does
75 * not provide the vector number on the stack, we vector everything 73 * not provide the vector number on the stack, we vector everything
diff --git a/arch/m68k/platform/68328/timers.c b/arch/m68k/platform/68328/timers.c
index f2678866067b..b15ddef1ec76 100644
--- a/arch/m68k/platform/68328/timers.c
+++ b/arch/m68k/platform/68328/timers.c
@@ -20,6 +20,7 @@
20#include <linux/interrupt.h> 20#include <linux/interrupt.h>
21#include <linux/irq.h> 21#include <linux/irq.h>
22#include <linux/clocksource.h> 22#include <linux/clocksource.h>
23#include <linux/rtc.h>
23#include <asm/setup.h> 24#include <asm/setup.h>
24#include <asm/system.h> 25#include <asm/system.h>
25#include <asm/pgtable.h> 26#include <asm/pgtable.h>
@@ -119,14 +120,17 @@ void hw_timer_init(void)
119 120
120/***************************************************************************/ 121/***************************************************************************/
121 122
122void m68328_timer_gettod(int *year, int *mon, int *day, int *hour, int *min, int *sec) 123int m68328_hwclk(int set, struct rtc_time *t)
123{ 124{
124 long now = RTCTIME; 125 if (!set) {
125 126 long now = RTCTIME;
126 *year = *mon = *day = 1; 127 t->tm_year = t->tm_mon = t->tm_mday = 1;
127 *hour = (now >> 24) % 24; 128 t->tm_hour = (now >> 24) % 24;
128 *min = (now >> 16) % 60; 129 t->tm_min = (now >> 16) % 60;
129 *sec = now % 60; 130 t->tm_sec = now % 60;
131 }
132
133 return 0;
130} 134}
131 135
132/***************************************************************************/ 136/***************************************************************************/
diff --git a/arch/m68k/platform/68360/config.c b/arch/m68k/platform/68360/config.c
index 9dd5bca38749..599a5949f320 100644
--- a/arch/m68k/platform/68360/config.c
+++ b/arch/m68k/platform/68360/config.c
@@ -103,11 +103,6 @@ void hw_timer_init(void)
103 pquicc->timer_tgcr = tgcr_save; 103 pquicc->timer_tgcr = tgcr_save;
104} 104}
105 105
106void BSP_gettod (int *yearp, int *monp, int *dayp,
107 int *hourp, int *minp, int *secp)
108{
109}
110
111int BSP_set_clock_mmss(unsigned long nowtime) 106int BSP_set_clock_mmss(unsigned long nowtime)
112{ 107{
113#if 0 108#if 0
@@ -181,6 +176,5 @@ void config_BSP(char *command, int len)
181 scc1_hwaddr = "\00\01\02\03\04\05"; 176 scc1_hwaddr = "\00\01\02\03\04\05";
182#endif 177#endif
183 178
184 mach_gettod = BSP_gettod; 179 mach_reset = BSP_reset;
185 mach_reset = BSP_reset;
186} 180}
diff --git a/arch/m68k/platform/68360/ints.c b/arch/m68k/platform/68360/ints.c
index 7b40202d9638..8cd42692331b 100644
--- a/arch/m68k/platform/68360/ints.c
+++ b/arch/m68k/platform/68360/ints.c
@@ -32,8 +32,6 @@ asmlinkage void trap(void);
32asmlinkage void bad_interrupt(void); 32asmlinkage void bad_interrupt(void);
33asmlinkage void inthandler(void); 33asmlinkage void inthandler(void);
34 34
35extern void *_ramvec[];
36
37static void intc_irq_unmask(struct irq_data *d) 35static void intc_irq_unmask(struct irq_data *d)
38{ 36{
39 pquicc->intr_cimr |= (1 << d->irq); 37 pquicc->intr_cimr |= (1 << d->irq);
diff --git a/arch/m68k/platform/68EZ328/config.c b/arch/m68k/platform/68EZ328/config.c
index 1be1a16f6896..dd2c53554341 100644
--- a/arch/m68k/platform/68EZ328/config.c
+++ b/arch/m68k/platform/68EZ328/config.c
@@ -15,6 +15,7 @@
15 15
16#include <linux/types.h> 16#include <linux/types.h>
17#include <linux/kernel.h> 17#include <linux/kernel.h>
18#include <linux/rtc.h>
18#include <asm/system.h> 19#include <asm/system.h>
19#include <asm/pgtable.h> 20#include <asm/pgtable.h>
20#include <asm/machdep.h> 21#include <asm/machdep.h>
@@ -25,7 +26,7 @@
25 26
26/***************************************************************************/ 27/***************************************************************************/
27 28
28void m68328_timer_gettod(int *year, int *mon, int *day, int *hour, int *min, int *sec); 29int m68328_hwclk(int set, struct rtc_time *t);
29 30
30/***************************************************************************/ 31/***************************************************************************/
31 32
@@ -69,7 +70,7 @@ void config_BSP(char *command, int len)
69 else command[0] = 0; 70 else command[0] = 0;
70#endif 71#endif
71 72
72 mach_gettod = m68328_timer_gettod; 73 mach_hwclk = m68328_hwclk;
73 mach_reset = m68ez328_reset; 74 mach_reset = m68ez328_reset;
74} 75}
75 76
diff --git a/arch/m68k/platform/68VZ328/config.c b/arch/m68k/platform/68VZ328/config.c
index eabaabe8af36..25ec673edc25 100644
--- a/arch/m68k/platform/68VZ328/config.c
+++ b/arch/m68k/platform/68VZ328/config.c
@@ -20,6 +20,7 @@
20#include <linux/netdevice.h> 20#include <linux/netdevice.h>
21#include <linux/interrupt.h> 21#include <linux/interrupt.h>
22#include <linux/irq.h> 22#include <linux/irq.h>
23#include <linux/rtc.h>
23 24
24#include <asm/system.h> 25#include <asm/system.h>
25#include <asm/pgtable.h> 26#include <asm/pgtable.h>
@@ -33,7 +34,7 @@
33 34
34/***************************************************************************/ 35/***************************************************************************/
35 36
36void m68328_timer_gettod(int *year, int *mon, int *day, int *hour, int *min, int *sec); 37int m68328_hwclk(int set, struct rtc_time *t);
37 38
38/***************************************************************************/ 39/***************************************************************************/
39/* Init Drangon Engine hardware */ 40/* Init Drangon Engine hardware */
@@ -181,7 +182,7 @@ void config_BSP(char *command, int size)
181 182
182 init_hardware(command, size); 183 init_hardware(command, size);
183 184
184 mach_gettod = m68328_timer_gettod; 185 mach_hwclk = m68328_hwclk;
185 mach_reset = m68vz328_reset; 186 mach_reset = m68vz328_reset;
186} 187}
187 188
diff --git a/arch/m68k/platform/coldfire/Makefile b/arch/m68k/platform/coldfire/Makefile
index a8967baabd72..a0815c61dec1 100644
--- a/arch/m68k/platform/coldfire/Makefile
+++ b/arch/m68k/platform/coldfire/Makefile
@@ -14,18 +14,18 @@
14 14
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
16 16
17obj-$(CONFIG_COLDFIRE) += cache.o clk.o dma.o entry.o vectors.o 17obj-$(CONFIG_COLDFIRE) += cache.o clk.o device.o dma.o entry.o vectors.o
18obj-$(CONFIG_M5206) += timers.o intc.o 18obj-$(CONFIG_M5206) += timers.o intc.o reset.o
19obj-$(CONFIG_M5206e) += timers.o intc.o 19obj-$(CONFIG_M5206e) += timers.o intc.o reset.o
20obj-$(CONFIG_M520x) += pit.o intc-simr.o 20obj-$(CONFIG_M520x) += pit.o intc-simr.o reset.o
21obj-$(CONFIG_M523x) += pit.o dma_timer.o intc-2.o 21obj-$(CONFIG_M523x) += pit.o dma_timer.o intc-2.o reset.o
22obj-$(CONFIG_M5249) += timers.o intc.o 22obj-$(CONFIG_M5249) += timers.o intc.o reset.o
23obj-$(CONFIG_M527x) += pit.o intc-2.o 23obj-$(CONFIG_M527x) += pit.o intc-2.o reset.o
24obj-$(CONFIG_M5272) += timers.o 24obj-$(CONFIG_M5272) += timers.o
25obj-$(CONFIG_M528x) += pit.o intc-2.o 25obj-$(CONFIG_M528x) += pit.o intc-2.o reset.o
26obj-$(CONFIG_M5307) += timers.o intc.o 26obj-$(CONFIG_M5307) += timers.o intc.o reset.o
27obj-$(CONFIG_M532x) += timers.o intc-simr.o 27obj-$(CONFIG_M532x) += timers.o intc-simr.o reset.o
28obj-$(CONFIG_M5407) += timers.o intc.o 28obj-$(CONFIG_M5407) += timers.o intc.o reset.o
29obj-$(CONFIG_M54xx) += sltimers.o intc-2.o 29obj-$(CONFIG_M54xx) += sltimers.o intc-2.o
30 30
31obj-y += pinmux.o gpio.o 31obj-y += pinmux.o gpio.o
diff --git a/arch/m68k/platform/coldfire/device.c b/arch/m68k/platform/coldfire/device.c
new file mode 100644
index 000000000000..fa50c48292ff
--- /dev/null
+++ b/arch/m68k/platform/coldfire/device.c
@@ -0,0 +1,318 @@
1/*
2 * device.c -- common ColdFire SoC device support
3 *
4 * (C) Copyright 2011, Greg Ungerer <gerg@uclinux.org>
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file COPYING in the main directory of this archive
8 * for more details.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/io.h>
14#include <linux/spi/spi.h>
15#include <linux/gpio.h>
16#include <asm/traps.h>
17#include <asm/coldfire.h>
18#include <asm/mcfsim.h>
19#include <asm/mcfuart.h>
20#include <asm/mcfqspi.h>
21
22/*
23 * All current ColdFire parts contain from 2, 3 or 4 UARTS.
24 */
25static struct mcf_platform_uart mcf_uart_platform_data[] = {
26 {
27 .mapbase = MCFUART_BASE0,
28 .irq = MCF_IRQ_UART0,
29 },
30 {
31 .mapbase = MCFUART_BASE1,
32 .irq = MCF_IRQ_UART1,
33 },
34#ifdef MCFUART_BASE2
35 {
36 .mapbase = MCFUART_BASE2,
37 .irq = MCF_IRQ_UART2,
38 },
39#endif
40#ifdef MCFUART_BASE3
41 {
42 .mapbase = MCFUART_BASE3,
43 .irq = MCF_IRQ_UART3,
44 },
45#endif
46 { },
47};
48
49static struct platform_device mcf_uart = {
50 .name = "mcfuart",
51 .id = 0,
52 .dev.platform_data = mcf_uart_platform_data,
53};
54
55#ifdef CONFIG_FEC
56/*
57 * Some ColdFire cores contain the Fast Ethernet Controller (FEC)
58 * block. It is Freescale's own hardware block. Some ColdFires
59 * have 2 of these.
60 */
61static struct resource mcf_fec0_resources[] = {
62 {
63 .start = MCFFEC_BASE0,
64 .end = MCFFEC_BASE0 + MCFFEC_SIZE0 - 1,
65 .flags = IORESOURCE_MEM,
66 },
67 {
68 .start = MCF_IRQ_FECRX0,
69 .end = MCF_IRQ_FECRX0,
70 .flags = IORESOURCE_IRQ,
71 },
72 {
73 .start = MCF_IRQ_FECTX0,
74 .end = MCF_IRQ_FECTX0,
75 .flags = IORESOURCE_IRQ,
76 },
77 {
78 .start = MCF_IRQ_FECENTC0,
79 .end = MCF_IRQ_FECENTC0,
80 .flags = IORESOURCE_IRQ,
81 },
82};
83
84static struct platform_device mcf_fec0 = {
85 .name = "fec",
86 .id = 0,
87 .num_resources = ARRAY_SIZE(mcf_fec0_resources),
88 .resource = mcf_fec0_resources,
89};
90
91#ifdef MCFFEC_BASE1
92static struct resource mcf_fec1_resources[] = {
93 {
94 .start = MCFFEC_BASE1,
95 .end = MCFFEC_BASE1 + MCFFEC_SIZE1 - 1,
96 .flags = IORESOURCE_MEM,
97 },
98 {
99 .start = MCF_IRQ_FECRX1,
100 .end = MCF_IRQ_FECRX1,
101 .flags = IORESOURCE_IRQ,
102 },
103 {
104 .start = MCF_IRQ_FECTX1,
105 .end = MCF_IRQ_FECTX1,
106 .flags = IORESOURCE_IRQ,
107 },
108 {
109 .start = MCF_IRQ_FECENTC1,
110 .end = MCF_IRQ_FECENTC1,
111 .flags = IORESOURCE_IRQ,
112 },
113};
114
115static struct platform_device mcf_fec1 = {
116 .name = "fec",
117 .id = 0,
118 .num_resources = ARRAY_SIZE(mcf_fec1_resources),
119 .resource = mcf_fec1_resources,
120};
121#endif /* MCFFEC_BASE1 */
122#endif /* CONFIG_FEC */
123
124#ifdef CONFIG_SPI_COLDFIRE_QSPI
125/*
126 * The ColdFire QSPI module is an SPI protocol hardware block used
127 * on a number of different ColdFire CPUs.
128 */
129static struct resource mcf_qspi_resources[] = {
130 {
131 .start = MCFQSPI_BASE,
132 .end = MCFQSPI_BASE + MCFQSPI_SIZE - 1,
133 .flags = IORESOURCE_MEM,
134 },
135 {
136 .start = MCF_IRQ_QSPI,
137 .end = MCF_IRQ_QSPI,
138 .flags = IORESOURCE_IRQ,
139 },
140};
141
142static int mcf_cs_setup(struct mcfqspi_cs_control *cs_control)
143{
144 int status;
145
146 status = gpio_request(MCFQSPI_CS0, "MCFQSPI_CS0");
147 if (status) {
148 pr_debug("gpio_request for MCFQSPI_CS0 failed\n");
149 goto fail0;
150 }
151 status = gpio_direction_output(MCFQSPI_CS0, 1);
152 if (status) {
153 pr_debug("gpio_direction_output for MCFQSPI_CS0 failed\n");
154 goto fail1;
155 }
156
157 status = gpio_request(MCFQSPI_CS1, "MCFQSPI_CS1");
158 if (status) {
159 pr_debug("gpio_request for MCFQSPI_CS1 failed\n");
160 goto fail1;
161 }
162 status = gpio_direction_output(MCFQSPI_CS1, 1);
163 if (status) {
164 pr_debug("gpio_direction_output for MCFQSPI_CS1 failed\n");
165 goto fail2;
166 }
167
168 status = gpio_request(MCFQSPI_CS2, "MCFQSPI_CS2");
169 if (status) {
170 pr_debug("gpio_request for MCFQSPI_CS2 failed\n");
171 goto fail2;
172 }
173 status = gpio_direction_output(MCFQSPI_CS2, 1);
174 if (status) {
175 pr_debug("gpio_direction_output for MCFQSPI_CS2 failed\n");
176 goto fail3;
177 }
178
179#ifdef MCFQSPI_CS3
180 status = gpio_request(MCFQSPI_CS3, "MCFQSPI_CS3");
181 if (status) {
182 pr_debug("gpio_request for MCFQSPI_CS3 failed\n");
183 goto fail3;
184 }
185 status = gpio_direction_output(MCFQSPI_CS3, 1);
186 if (status) {
187 pr_debug("gpio_direction_output for MCFQSPI_CS3 failed\n");
188 gpio_free(MCFQSPI_CS3);
189 goto fail3;
190 }
191#endif
192
193 return 0;
194
195fail3:
196 gpio_free(MCFQSPI_CS2);
197fail2:
198 gpio_free(MCFQSPI_CS1);
199fail1:
200 gpio_free(MCFQSPI_CS0);
201fail0:
202 return status;
203}
204
205static void mcf_cs_teardown(struct mcfqspi_cs_control *cs_control)
206{
207#ifdef MCFQSPI_CS3
208 gpio_free(MCFQSPI_CS3);
209#endif
210 gpio_free(MCFQSPI_CS2);
211 gpio_free(MCFQSPI_CS1);
212 gpio_free(MCFQSPI_CS0);
213}
214
215static void mcf_cs_select(struct mcfqspi_cs_control *cs_control,
216 u8 chip_select, bool cs_high)
217{
218 switch (chip_select) {
219 case 0:
220 gpio_set_value(MCFQSPI_CS0, cs_high);
221 break;
222 case 1:
223 gpio_set_value(MCFQSPI_CS1, cs_high);
224 break;
225 case 2:
226 gpio_set_value(MCFQSPI_CS2, cs_high);
227 break;
228#ifdef MCFQSPI_CS3
229 case 3:
230 gpio_set_value(MCFQSPI_CS3, cs_high);
231 break;
232#endif
233 }
234}
235
236static void mcf_cs_deselect(struct mcfqspi_cs_control *cs_control,
237 u8 chip_select, bool cs_high)
238{
239 switch (chip_select) {
240 case 0:
241 gpio_set_value(MCFQSPI_CS0, !cs_high);
242 break;
243 case 1:
244 gpio_set_value(MCFQSPI_CS1, !cs_high);
245 break;
246 case 2:
247 gpio_set_value(MCFQSPI_CS2, !cs_high);
248 break;
249#ifdef MCFQSPI_CS3
250 case 3:
251 gpio_set_value(MCFQSPI_CS3, !cs_high);
252 break;
253#endif
254 }
255}
256
257static struct mcfqspi_cs_control mcf_cs_control = {
258 .setup = mcf_cs_setup,
259 .teardown = mcf_cs_teardown,
260 .select = mcf_cs_select,
261 .deselect = mcf_cs_deselect,
262};
263
264static struct mcfqspi_platform_data mcf_qspi_data = {
265 .bus_num = 0,
266 .num_chipselect = 4,
267 .cs_control = &mcf_cs_control,
268};
269
270static struct platform_device mcf_qspi = {
271 .name = "mcfqspi",
272 .id = 0,
273 .num_resources = ARRAY_SIZE(mcf_qspi_resources),
274 .resource = mcf_qspi_resources,
275 .dev.platform_data = &mcf_qspi_data,
276};
277#endif /* CONFIG_SPI_COLDFIRE_QSPI */
278
279static struct platform_device *mcf_devices[] __initdata = {
280 &mcf_uart,
281#ifdef CONFIG_FEC
282 &mcf_fec0,
283#ifdef MCFFEC_BASE1
284 &mcf_fec1,
285#endif
286#endif
287#ifdef CONFIG_SPI_COLDFIRE_QSPI
288 &mcf_qspi,
289#endif
290};
291
292/*
293 * Some ColdFire UARTs let you set the IRQ line to use.
294 */
295static void __init mcf_uart_set_irq(void)
296{
297#ifdef MCFUART_UIVR
298 /* UART0 interrupt setup */
299 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR);
300 writeb(MCF_IRQ_UART0, MCFUART_BASE0 + MCFUART_UIVR);
301 mcf_mapirq2imr(MCF_IRQ_UART0, MCFINTC_UART0);
302
303 /* UART1 interrupt setup */
304 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR);
305 writeb(MCF_IRQ_UART1, MCFUART_BASE1 + MCFUART_UIVR);
306 mcf_mapirq2imr(MCF_IRQ_UART1, MCFINTC_UART1);
307#endif
308}
309
310static int __init mcf_init_devices(void)
311{
312 mcf_uart_set_irq();
313 platform_add_devices(mcf_devices, ARRAY_SIZE(mcf_devices));
314 return 0;
315}
316
317arch_initcall(mcf_init_devices);
318
diff --git a/arch/m68k/platform/coldfire/head.S b/arch/m68k/platform/coldfire/head.S
index 38f04a3f6207..c3db70ed33b3 100644
--- a/arch/m68k/platform/coldfire/head.S
+++ b/arch/m68k/platform/coldfire/head.S
@@ -158,6 +158,10 @@ _start:
158#if defined(CONFIG_UBOOT) 158#if defined(CONFIG_UBOOT)
159 movel %sp,_init_sp /* save initial stack pointer */ 159 movel %sp,_init_sp /* save initial stack pointer */
160#endif 160#endif
161#ifdef CONFIG_MBAR
162 movel #CONFIG_MBAR+1,%d0 /* configured MBAR address */
163 movec %d0,%MBAR /* set it */
164#endif
161 165
162 /* 166 /*
163 * Do any platform or board specific setup now. Most boards 167 * Do any platform or board specific setup now. Most boards
diff --git a/arch/m68k/platform/coldfire/pit.c b/arch/m68k/platform/coldfire/pit.c
index 02663d25822d..e62dbbcb10f6 100644
--- a/arch/m68k/platform/coldfire/pit.c
+++ b/arch/m68k/platform/coldfire/pit.c
@@ -149,7 +149,7 @@ static struct clocksource pit_clk = {
149 149
150/***************************************************************************/ 150/***************************************************************************/
151 151
152void hw_timer_init(void) 152void hw_timer_init(irq_handler_t handler)
153{ 153{
154 cf_pit_clockevent.cpumask = cpumask_of(smp_processor_id()); 154 cf_pit_clockevent.cpumask = cpumask_of(smp_processor_id());
155 cf_pit_clockevent.mult = div_sc(FREQ, NSEC_PER_SEC, 32); 155 cf_pit_clockevent.mult = div_sc(FREQ, NSEC_PER_SEC, 32);
diff --git a/arch/m68k/platform/coldfire/reset.c b/arch/m68k/platform/coldfire/reset.c
new file mode 100644
index 000000000000..933e54eacc69
--- /dev/null
+++ b/arch/m68k/platform/coldfire/reset.c
@@ -0,0 +1,50 @@
1/*
2 * reset.c -- common ColdFire SoC reset support
3 *
4 * (C) Copyright 2012, Greg Ungerer <gerg@uclinux.org>
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file COPYING in the main directory of this archive
8 * for more details.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/io.h>
14#include <asm/machdep.h>
15#include <asm/coldfire.h>
16#include <asm/mcfsim.h>
17
18/*
19 * There are 2 common methods amongst the ColdFure parts for reseting
20 * the CPU. But there are couple of exceptions, the 5272 and the 547x
21 * have something completely special to them, and we let their specific
22 * subarch code handle them.
23 */
24
25#ifdef MCFSIM_SYPCR
26static void mcf_cpu_reset(void)
27{
28 local_irq_disable();
29 /* Set watchdog to soft reset, and enabled */
30 __raw_writeb(0xc0, MCF_MBAR + MCFSIM_SYPCR);
31 for (;;)
32 /* wait for watchdog to timeout */;
33}
34#endif
35
36#ifdef MCF_RCR
37static void mcf_cpu_reset(void)
38{
39 local_irq_disable();
40 __raw_writeb(MCF_RCR_SWRESET, MCF_RCR);
41}
42#endif
43
44static int __init mcf_setup_reset(void)
45{
46 mach_reset = mcf_cpu_reset;
47 return 0;
48}
49
50arch_initcall(mcf_setup_reset);
diff --git a/arch/m68k/platform/coldfire/sltimers.c b/arch/m68k/platform/coldfire/sltimers.c
index 54e1452f853a..2027fc20b876 100644
--- a/arch/m68k/platform/coldfire/sltimers.c
+++ b/arch/m68k/platform/coldfire/sltimers.c
@@ -81,12 +81,14 @@ void mcfslt_profile_init(void)
81static u32 mcfslt_cycles_per_jiffy; 81static u32 mcfslt_cycles_per_jiffy;
82static u32 mcfslt_cnt; 82static u32 mcfslt_cnt;
83 83
84static irq_handler_t timer_interrupt;
85
84static irqreturn_t mcfslt_tick(int irq, void *dummy) 86static irqreturn_t mcfslt_tick(int irq, void *dummy)
85{ 87{
86 /* Reset Slice Timer 0 */ 88 /* Reset Slice Timer 0 */
87 __raw_writel(MCFSLT_SSR_BE | MCFSLT_SSR_TE, TA(MCFSLT_SSR)); 89 __raw_writel(MCFSLT_SSR_BE | MCFSLT_SSR_TE, TA(MCFSLT_SSR));
88 mcfslt_cnt += mcfslt_cycles_per_jiffy; 90 mcfslt_cnt += mcfslt_cycles_per_jiffy;
89 return arch_timer_interrupt(irq, dummy); 91 return timer_interrupt(irq, dummy);
90} 92}
91 93
92static struct irqaction mcfslt_timer_irq = { 94static struct irqaction mcfslt_timer_irq = {
@@ -121,7 +123,7 @@ static struct clocksource mcfslt_clk = {
121 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 123 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
122}; 124};
123 125
124void hw_timer_init(void) 126void hw_timer_init(irq_handler_t handler)
125{ 127{
126 mcfslt_cycles_per_jiffy = MCF_BUSCLK / HZ; 128 mcfslt_cycles_per_jiffy = MCF_BUSCLK / HZ;
127 /* 129 /*
@@ -136,6 +138,7 @@ void hw_timer_init(void)
136 /* initialize mcfslt_cnt knowing that slice timers count down */ 138 /* initialize mcfslt_cnt knowing that slice timers count down */
137 mcfslt_cnt = mcfslt_cycles_per_jiffy; 139 mcfslt_cnt = mcfslt_cycles_per_jiffy;
138 140
141 timer_interrupt = handler;
139 setup_irq(MCF_IRQ_TIMER, &mcfslt_timer_irq); 142 setup_irq(MCF_IRQ_TIMER, &mcfslt_timer_irq);
140 143
141 clocksource_register_hz(&mcfslt_clk, MCF_BUSCLK); 144 clocksource_register_hz(&mcfslt_clk, MCF_BUSCLK);
diff --git a/arch/m68k/platform/coldfire/timers.c b/arch/m68k/platform/coldfire/timers.c
index 0d90da32fcdb..ed96ce50d79f 100644
--- a/arch/m68k/platform/coldfire/timers.c
+++ b/arch/m68k/platform/coldfire/timers.c
@@ -47,6 +47,27 @@ void coldfire_profile_init(void);
47static u32 mcftmr_cycles_per_jiffy; 47static u32 mcftmr_cycles_per_jiffy;
48static u32 mcftmr_cnt; 48static u32 mcftmr_cnt;
49 49
50static irq_handler_t timer_interrupt;
51
52/***************************************************************************/
53
54static void init_timer_irq(void)
55{
56#ifdef MCFSIM_ICR_AUTOVEC
57 /* Timer1 is always used as system timer */
58 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3,
59 MCF_MBAR + MCFSIM_TIMER1ICR);
60 mcf_mapirq2imr(MCF_IRQ_TIMER, MCFINTC_TIMER1);
61
62#ifdef CONFIG_HIGHPROFILE
63 /* Timer2 is to be used as a high speed profile timer */
64 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3,
65 MCF_MBAR + MCFSIM_TIMER2ICR);
66 mcf_mapirq2imr(MCF_IRQ_PROFILER, MCFINTC_TIMER2);
67#endif
68#endif /* MCFSIM_ICR_AUTOVEC */
69}
70
50/***************************************************************************/ 71/***************************************************************************/
51 72
52static irqreturn_t mcftmr_tick(int irq, void *dummy) 73static irqreturn_t mcftmr_tick(int irq, void *dummy)
@@ -55,7 +76,7 @@ static irqreturn_t mcftmr_tick(int irq, void *dummy)
55 __raw_writeb(MCFTIMER_TER_CAP | MCFTIMER_TER_REF, TA(MCFTIMER_TER)); 76 __raw_writeb(MCFTIMER_TER_CAP | MCFTIMER_TER_REF, TA(MCFTIMER_TER));
56 77
57 mcftmr_cnt += mcftmr_cycles_per_jiffy; 78 mcftmr_cnt += mcftmr_cycles_per_jiffy;
58 return arch_timer_interrupt(irq, dummy); 79 return timer_interrupt(irq, dummy);
59} 80}
60 81
61/***************************************************************************/ 82/***************************************************************************/
@@ -94,7 +115,7 @@ static struct clocksource mcftmr_clk = {
94 115
95/***************************************************************************/ 116/***************************************************************************/
96 117
97void hw_timer_init(void) 118void hw_timer_init(irq_handler_t handler)
98{ 119{
99 __raw_writew(MCFTIMER_TMR_DISABLE, TA(MCFTIMER_TMR)); 120 __raw_writew(MCFTIMER_TMR_DISABLE, TA(MCFTIMER_TMR));
100 mcftmr_cycles_per_jiffy = FREQ / HZ; 121 mcftmr_cycles_per_jiffy = FREQ / HZ;
@@ -110,6 +131,8 @@ void hw_timer_init(void)
110 131
111 clocksource_register_hz(&mcftmr_clk, FREQ); 132 clocksource_register_hz(&mcftmr_clk, FREQ);
112 133
134 timer_interrupt = handler;
135 init_timer_irq();
113 setup_irq(MCF_IRQ_TIMER, &mcftmr_timer_irq); 136 setup_irq(MCF_IRQ_TIMER, &mcftmr_timer_irq);
114 137
115#ifdef CONFIG_HIGHPROFILE 138#ifdef CONFIG_HIGHPROFILE
diff --git a/arch/m68k/platform/coldfire/vectors.c b/arch/m68k/platform/coldfire/vectors.c
index 3a7cc524ecd3..a4dbdecbec7a 100644
--- a/arch/m68k/platform/coldfire/vectors.c
+++ b/arch/m68k/platform/coldfire/vectors.c
@@ -33,8 +33,6 @@ asmlinkage void dbginterrupt_c(struct frame *fp)
33 33
34/***************************************************************************/ 34/***************************************************************************/
35 35
36extern e_vector *_ramvec;
37
38/* Assembler routines */ 36/* Assembler routines */
39asmlinkage void buserr(void); 37asmlinkage void buserr(void);
40asmlinkage void trap(void); 38asmlinkage void trap(void);
diff --git a/arch/m68k/q40/config.c b/arch/m68k/q40/config.c
index ad10fecec2fe..be936480b964 100644
--- a/arch/m68k/q40/config.c
+++ b/arch/m68k/q40/config.c
@@ -24,6 +24,7 @@
24#include <linux/rtc.h> 24#include <linux/rtc.h>
25#include <linux/vt_kern.h> 25#include <linux/vt_kern.h>
26#include <linux/bcd.h> 26#include <linux/bcd.h>
27#include <linux/platform_device.h>
27 28
28#include <asm/io.h> 29#include <asm/io.h>
29#include <asm/rtc.h> 30#include <asm/rtc.h>
@@ -329,3 +330,15 @@ static int q40_set_rtc_pll(struct rtc_pll_info *pll)
329 } else 330 } else
330 return -EINVAL; 331 return -EINVAL;
331} 332}
333
334static __init int q40_add_kbd_device(void)
335{
336 struct platform_device *pdev;
337
338 pdev = platform_device_register_simple("q40kbd", -1, NULL, 0);
339 if (IS_ERR(pdev))
340 return PTR_ERR(pdev);
341
342 return 0;
343}
344arch_initcall(q40_add_kbd_device);
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-17 23:28:38 -0500