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-rw-r--r--arch/m68k/Kconfig2
-rw-r--r--arch/m68k/amiga/platform.c5
-rw-r--r--arch/m68k/configs/amiga_defconfig1
-rw-r--r--arch/m68k/configs/apollo_defconfig1
-rw-r--r--arch/m68k/configs/atari_defconfig1
-rw-r--r--arch/m68k/configs/bvme6000_defconfig1
-rw-r--r--arch/m68k/configs/hp300_defconfig1
-rw-r--r--arch/m68k/configs/mac_defconfig1
-rw-r--r--arch/m68k/configs/multi_defconfig1
-rw-r--r--arch/m68k/configs/mvme147_defconfig1
-rw-r--r--arch/m68k/configs/mvme16x_defconfig1
-rw-r--r--arch/m68k/configs/q40_defconfig1
-rw-r--r--arch/m68k/configs/sun3_defconfig1
-rw-r--r--arch/m68k/configs/sun3x_defconfig1
-rw-r--r--arch/m68k/emu/nfcon.c4
-rw-r--r--arch/m68k/include/asm/Kbuild1
-rw-r--r--arch/m68k/include/asm/apollohw.h12
-rw-r--r--arch/m68k/include/asm/cacheflush.h4
-rw-r--r--arch/m68k/include/asm/cacheflush_no.h19
-rw-r--r--arch/m68k/include/asm/elf.h3
-rw-r--r--arch/m68k/include/asm/io.h4
-rw-r--r--arch/m68k/include/asm/m5206sim.h98
-rw-r--r--arch/m68k/include/asm/m523xsim.h24
-rw-r--r--arch/m68k/include/asm/m5249sim.h98
-rw-r--r--arch/m68k/include/asm/m525xsim.h70
-rw-r--r--arch/m68k/include/asm/m5272sim.h99
-rw-r--r--arch/m68k/include/asm/m527xsim.h84
-rw-r--r--arch/m68k/include/asm/m528xsim.h51
-rw-r--r--arch/m68k/include/asm/m5307sim.h136
-rw-r--r--arch/m68k/include/asm/m532xsim.h1189
-rw-r--r--arch/m68k/include/asm/m5407sim.h110
-rw-r--r--arch/m68k/include/asm/m54xxgpt.h40
-rw-r--r--arch/m68k/include/asm/m54xxsim.h27
-rw-r--r--arch/m68k/include/asm/m68360.h8
-rw-r--r--arch/m68k/include/asm/m68360_enet.h2
-rw-r--r--arch/m68k/include/asm/mcfslt.h7
-rw-r--r--arch/m68k/include/asm/nettel.h9
-rw-r--r--arch/m68k/include/asm/page.h4
-rw-r--r--arch/m68k/include/asm/pgtable.h4
-rw-r--r--arch/m68k/include/asm/q40_master.h2
-rw-r--r--arch/m68k/include/asm/uaccess.h4
-rw-r--r--arch/m68k/include/uapi/asm/Kbuild3
-rw-r--r--arch/m68k/kernel/pcibios.c5
-rw-r--r--arch/m68k/kernel/process.c3
-rw-r--r--arch/m68k/kernel/time.c5
-rw-r--r--arch/m68k/mm/fault.c1
-rw-r--r--arch/m68k/platform/68VZ328/Makefile8
-rw-r--r--arch/m68k/platform/coldfire/clk.c6
-rw-r--r--arch/m68k/platform/coldfire/device.c4
-rw-r--r--arch/m68k/platform/coldfire/head.S2
-rw-r--r--arch/m68k/platform/coldfire/intc-5249.c10
-rw-r--r--arch/m68k/platform/coldfire/intc-5272.c20
-rw-r--r--arch/m68k/platform/coldfire/intc.c28
-rw-r--r--arch/m68k/platform/coldfire/m523x.c8
-rw-r--r--arch/m68k/platform/coldfire/m5249.c10
-rw-r--r--arch/m68k/platform/coldfire/m525x.c4
-rw-r--r--arch/m68k/platform/coldfire/m5272.c19
-rw-r--r--arch/m68k/platform/coldfire/m527x.c24
-rw-r--r--arch/m68k/platform/coldfire/m528x.c6
-rw-r--r--arch/m68k/platform/coldfire/m532x.c221
-rw-r--r--arch/m68k/platform/coldfire/m54xx.c16
-rw-r--r--arch/m68k/platform/coldfire/nettel.c4
-rw-r--r--arch/m68k/platform/coldfire/pci.c4
-rw-r--r--arch/m68k/platform/coldfire/reset.c2
-rw-r--r--arch/m68k/platform/coldfire/sltimers.c4
-rw-r--r--arch/m68k/platform/coldfire/timers.c4
-rw-r--r--arch/m68k/q40/config.c5
67 files changed, 727 insertions, 1831 deletions
diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig
index b22df9410dce..dae1e7e16a37 100644
--- a/arch/m68k/Kconfig
+++ b/arch/m68k/Kconfig
@@ -3,9 +3,11 @@ config M68K
3 default y 3 default y
4 select HAVE_IDE 4 select HAVE_IDE
5 select HAVE_AOUT if MMU 5 select HAVE_AOUT if MMU
6 select HAVE_DEBUG_BUGVERBOSE
6 select HAVE_GENERIC_HARDIRQS 7 select HAVE_GENERIC_HARDIRQS
7 select GENERIC_IRQ_SHOW 8 select GENERIC_IRQ_SHOW
8 select GENERIC_ATOMIC64 9 select GENERIC_ATOMIC64
10 select HAVE_UID16
9 select ARCH_HAVE_NMI_SAFE_CMPXCHG if RMW_INSNS 11 select ARCH_HAVE_NMI_SAFE_CMPXCHG if RMW_INSNS
10 select GENERIC_CPU_DEVICES 12 select GENERIC_CPU_DEVICES
11 select GENERIC_STRNCPY_FROM_USER if MMU 13 select GENERIC_STRNCPY_FROM_USER if MMU
diff --git a/arch/m68k/amiga/platform.c b/arch/m68k/amiga/platform.c
index 80076d368b7e..6083088c0cca 100644
--- a/arch/m68k/amiga/platform.c
+++ b/arch/m68k/amiga/platform.c
@@ -56,10 +56,7 @@ static int __init amiga_init_bus(void)
56 n = AMIGAHW_PRESENT(ZORRO3) ? 4 : 2; 56 n = AMIGAHW_PRESENT(ZORRO3) ? 4 : 2;
57 pdev = platform_device_register_simple("amiga-zorro", -1, 57 pdev = platform_device_register_simple("amiga-zorro", -1,
58 zorro_resources, n); 58 zorro_resources, n);
59 if (IS_ERR(pdev)) 59 return PTR_RET(pdev);
60 return PTR_ERR(pdev);
61
62 return 0;
63} 60}
64 61
65subsys_initcall(amiga_init_bus); 62subsys_initcall(amiga_init_bus);
diff --git a/arch/m68k/configs/amiga_defconfig b/arch/m68k/configs/amiga_defconfig
index e93fdae10b23..90d3109c82f4 100644
--- a/arch/m68k/configs/amiga_defconfig
+++ b/arch/m68k/configs/amiga_defconfig
@@ -67,7 +67,6 @@ CONFIG_NETFILTER_XT_TARGET_DSCP=m
67CONFIG_NETFILTER_XT_TARGET_MARK=m 67CONFIG_NETFILTER_XT_TARGET_MARK=m
68CONFIG_NETFILTER_XT_TARGET_NFLOG=m 68CONFIG_NETFILTER_XT_TARGET_NFLOG=m
69CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m 69CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
70CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
71CONFIG_NETFILTER_XT_TARGET_TRACE=m 70CONFIG_NETFILTER_XT_TARGET_TRACE=m
72CONFIG_NETFILTER_XT_TARGET_TCPMSS=m 71CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
73CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m 72CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
diff --git a/arch/m68k/configs/apollo_defconfig b/arch/m68k/configs/apollo_defconfig
index 66b26c1e848c..8f4f657fdbc6 100644
--- a/arch/m68k/configs/apollo_defconfig
+++ b/arch/m68k/configs/apollo_defconfig
@@ -67,7 +67,6 @@ CONFIG_NETFILTER_XT_TARGET_DSCP=m
67CONFIG_NETFILTER_XT_TARGET_MARK=m 67CONFIG_NETFILTER_XT_TARGET_MARK=m
68CONFIG_NETFILTER_XT_TARGET_NFLOG=m 68CONFIG_NETFILTER_XT_TARGET_NFLOG=m
69CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m 69CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
70CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
71CONFIG_NETFILTER_XT_TARGET_TRACE=m 70CONFIG_NETFILTER_XT_TARGET_TRACE=m
72CONFIG_NETFILTER_XT_TARGET_TCPMSS=m 71CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
73CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m 72CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
diff --git a/arch/m68k/configs/atari_defconfig b/arch/m68k/configs/atari_defconfig
index 151332515980..4571d33903fe 100644
--- a/arch/m68k/configs/atari_defconfig
+++ b/arch/m68k/configs/atari_defconfig
@@ -65,7 +65,6 @@ CONFIG_NETFILTER_XT_TARGET_DSCP=m
65CONFIG_NETFILTER_XT_TARGET_MARK=m 65CONFIG_NETFILTER_XT_TARGET_MARK=m
66CONFIG_NETFILTER_XT_TARGET_NFLOG=m 66CONFIG_NETFILTER_XT_TARGET_NFLOG=m
67CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m 67CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
68CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
69CONFIG_NETFILTER_XT_TARGET_TRACE=m 68CONFIG_NETFILTER_XT_TARGET_TRACE=m
70CONFIG_NETFILTER_XT_TARGET_TCPMSS=m 69CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
71CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m 70CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
diff --git a/arch/m68k/configs/bvme6000_defconfig b/arch/m68k/configs/bvme6000_defconfig
index 67bb6fc117f4..12f211733ba0 100644
--- a/arch/m68k/configs/bvme6000_defconfig
+++ b/arch/m68k/configs/bvme6000_defconfig
@@ -65,7 +65,6 @@ CONFIG_NETFILTER_XT_TARGET_DSCP=m
65CONFIG_NETFILTER_XT_TARGET_MARK=m 65CONFIG_NETFILTER_XT_TARGET_MARK=m
66CONFIG_NETFILTER_XT_TARGET_NFLOG=m 66CONFIG_NETFILTER_XT_TARGET_NFLOG=m
67CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m 67CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
68CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
69CONFIG_NETFILTER_XT_TARGET_TRACE=m 68CONFIG_NETFILTER_XT_TARGET_TRACE=m
70CONFIG_NETFILTER_XT_TARGET_TCPMSS=m 69CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
71CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m 70CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
diff --git a/arch/m68k/configs/hp300_defconfig b/arch/m68k/configs/hp300_defconfig
index 3e35ce5fa467..215389a5407f 100644
--- a/arch/m68k/configs/hp300_defconfig
+++ b/arch/m68k/configs/hp300_defconfig
@@ -66,7 +66,6 @@ CONFIG_NETFILTER_XT_TARGET_DSCP=m
66CONFIG_NETFILTER_XT_TARGET_MARK=m 66CONFIG_NETFILTER_XT_TARGET_MARK=m
67CONFIG_NETFILTER_XT_TARGET_NFLOG=m 67CONFIG_NETFILTER_XT_TARGET_NFLOG=m
68CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m 68CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
69CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
70CONFIG_NETFILTER_XT_TARGET_TRACE=m 69CONFIG_NETFILTER_XT_TARGET_TRACE=m
71CONFIG_NETFILTER_XT_TARGET_TCPMSS=m 70CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
72CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m 71CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
diff --git a/arch/m68k/configs/mac_defconfig b/arch/m68k/configs/mac_defconfig
index ae81e2d190c3..cb9dfb30b674 100644
--- a/arch/m68k/configs/mac_defconfig
+++ b/arch/m68k/configs/mac_defconfig
@@ -61,7 +61,6 @@ CONFIG_NETFILTER_XT_TARGET_DSCP=m
61CONFIG_NETFILTER_XT_TARGET_MARK=m 61CONFIG_NETFILTER_XT_TARGET_MARK=m
62CONFIG_NETFILTER_XT_TARGET_NFLOG=m 62CONFIG_NETFILTER_XT_TARGET_NFLOG=m
63CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m 63CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
64CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
65CONFIG_NETFILTER_XT_TARGET_TRACE=m 64CONFIG_NETFILTER_XT_TARGET_TRACE=m
66CONFIG_NETFILTER_XT_TARGET_TCPMSS=m 65CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
67CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m 66CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
diff --git a/arch/m68k/configs/multi_defconfig b/arch/m68k/configs/multi_defconfig
index 55d394edf633..8d5def4a31e0 100644
--- a/arch/m68k/configs/multi_defconfig
+++ b/arch/m68k/configs/multi_defconfig
@@ -80,7 +80,6 @@ CONFIG_NETFILTER_XT_TARGET_DSCP=m
80CONFIG_NETFILTER_XT_TARGET_MARK=m 80CONFIG_NETFILTER_XT_TARGET_MARK=m
81CONFIG_NETFILTER_XT_TARGET_NFLOG=m 81CONFIG_NETFILTER_XT_TARGET_NFLOG=m
82CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m 82CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
83CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
84CONFIG_NETFILTER_XT_TARGET_TRACE=m 83CONFIG_NETFILTER_XT_TARGET_TRACE=m
85CONFIG_NETFILTER_XT_TARGET_TCPMSS=m 84CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
86CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m 85CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
diff --git a/arch/m68k/configs/mvme147_defconfig b/arch/m68k/configs/mvme147_defconfig
index af773743ee11..e2af46f530c1 100644
--- a/arch/m68k/configs/mvme147_defconfig
+++ b/arch/m68k/configs/mvme147_defconfig
@@ -64,7 +64,6 @@ CONFIG_NETFILTER_XT_TARGET_DSCP=m
64CONFIG_NETFILTER_XT_TARGET_MARK=m 64CONFIG_NETFILTER_XT_TARGET_MARK=m
65CONFIG_NETFILTER_XT_TARGET_NFLOG=m 65CONFIG_NETFILTER_XT_TARGET_NFLOG=m
66CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m 66CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
67CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
68CONFIG_NETFILTER_XT_TARGET_TRACE=m 67CONFIG_NETFILTER_XT_TARGET_TRACE=m
69CONFIG_NETFILTER_XT_TARGET_TCPMSS=m 68CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
70CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m 69CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
diff --git a/arch/m68k/configs/mvme16x_defconfig b/arch/m68k/configs/mvme16x_defconfig
index cdb70d66e535..7c9402b2097f 100644
--- a/arch/m68k/configs/mvme16x_defconfig
+++ b/arch/m68k/configs/mvme16x_defconfig
@@ -65,7 +65,6 @@ CONFIG_NETFILTER_XT_TARGET_DSCP=m
65CONFIG_NETFILTER_XT_TARGET_MARK=m 65CONFIG_NETFILTER_XT_TARGET_MARK=m
66CONFIG_NETFILTER_XT_TARGET_NFLOG=m 66CONFIG_NETFILTER_XT_TARGET_NFLOG=m
67CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m 67CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
68CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
69CONFIG_NETFILTER_XT_TARGET_TRACE=m 68CONFIG_NETFILTER_XT_TARGET_TRACE=m
70CONFIG_NETFILTER_XT_TARGET_TCPMSS=m 69CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
71CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m 70CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
diff --git a/arch/m68k/configs/q40_defconfig b/arch/m68k/configs/q40_defconfig
index 46bed78d0656..19d23db690a4 100644
--- a/arch/m68k/configs/q40_defconfig
+++ b/arch/m68k/configs/q40_defconfig
@@ -61,7 +61,6 @@ CONFIG_NETFILTER_XT_TARGET_DSCP=m
61CONFIG_NETFILTER_XT_TARGET_MARK=m 61CONFIG_NETFILTER_XT_TARGET_MARK=m
62CONFIG_NETFILTER_XT_TARGET_NFLOG=m 62CONFIG_NETFILTER_XT_TARGET_NFLOG=m
63CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m 63CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
64CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
65CONFIG_NETFILTER_XT_TARGET_TRACE=m 64CONFIG_NETFILTER_XT_TARGET_TRACE=m
66CONFIG_NETFILTER_XT_TARGET_TCPMSS=m 65CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
67CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m 66CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
diff --git a/arch/m68k/configs/sun3_defconfig b/arch/m68k/configs/sun3_defconfig
index 86f7772bafbe..ca6c0b4cab77 100644
--- a/arch/m68k/configs/sun3_defconfig
+++ b/arch/m68k/configs/sun3_defconfig
@@ -62,7 +62,6 @@ CONFIG_NETFILTER_XT_TARGET_DSCP=m
62CONFIG_NETFILTER_XT_TARGET_MARK=m 62CONFIG_NETFILTER_XT_TARGET_MARK=m
63CONFIG_NETFILTER_XT_TARGET_NFLOG=m 63CONFIG_NETFILTER_XT_TARGET_NFLOG=m
64CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m 64CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
65CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
66CONFIG_NETFILTER_XT_TARGET_TRACE=m 65CONFIG_NETFILTER_XT_TARGET_TRACE=m
67CONFIG_NETFILTER_XT_TARGET_TCPMSS=m 66CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
68CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m 67CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
diff --git a/arch/m68k/configs/sun3x_defconfig b/arch/m68k/configs/sun3x_defconfig
index 288261456e1f..c80941c7759e 100644
--- a/arch/m68k/configs/sun3x_defconfig
+++ b/arch/m68k/configs/sun3x_defconfig
@@ -62,7 +62,6 @@ CONFIG_NETFILTER_XT_TARGET_DSCP=m
62CONFIG_NETFILTER_XT_TARGET_MARK=m 62CONFIG_NETFILTER_XT_TARGET_MARK=m
63CONFIG_NETFILTER_XT_TARGET_NFLOG=m 63CONFIG_NETFILTER_XT_TARGET_NFLOG=m
64CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m 64CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
65CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
66CONFIG_NETFILTER_XT_TARGET_TRACE=m 65CONFIG_NETFILTER_XT_TARGET_TRACE=m
67CONFIG_NETFILTER_XT_TARGET_TCPMSS=m 66CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
68CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m 67CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
diff --git a/arch/m68k/emu/nfcon.c b/arch/m68k/emu/nfcon.c
index 8db25e806947..16d170f53bfd 100644
--- a/arch/m68k/emu/nfcon.c
+++ b/arch/m68k/emu/nfcon.c
@@ -19,6 +19,7 @@
19#include <asm/natfeat.h> 19#include <asm/natfeat.h>
20 20
21static int stderr_id; 21static int stderr_id;
22static struct tty_port nfcon_tty_port;
22static struct tty_driver *nfcon_tty_driver; 23static struct tty_driver *nfcon_tty_driver;
23 24
24static void nfputs(const char *str, unsigned int count) 25static void nfputs(const char *str, unsigned int count)
@@ -119,6 +120,8 @@ static int __init nfcon_init(void)
119{ 120{
120 int res; 121 int res;
121 122
123 tty_port_init(&nfcon_tty_port);
124
122 stderr_id = nf_get_id("NF_STDERR"); 125 stderr_id = nf_get_id("NF_STDERR");
123 if (!stderr_id) 126 if (!stderr_id)
124 return -ENODEV; 127 return -ENODEV;
@@ -135,6 +138,7 @@ static int __init nfcon_init(void)
135 nfcon_tty_driver->flags = TTY_DRIVER_REAL_RAW; 138 nfcon_tty_driver->flags = TTY_DRIVER_REAL_RAW;
136 139
137 tty_set_operations(nfcon_tty_driver, &nfcon_tty_ops); 140 tty_set_operations(nfcon_tty_driver, &nfcon_tty_ops);
141 tty_port_link_device(&nfcon_tty_port, nfcon_tty_driver, 0);
138 res = tty_register_driver(nfcon_tty_driver); 142 res = tty_register_driver(nfcon_tty_driver);
139 if (res) { 143 if (res) {
140 pr_err("failed to register nfcon tty driver\n"); 144 pr_err("failed to register nfcon tty driver\n");
diff --git a/arch/m68k/include/asm/Kbuild b/arch/m68k/include/asm/Kbuild
index a9d1bf1400f8..ecb540810ab3 100644
--- a/arch/m68k/include/asm/Kbuild
+++ b/arch/m68k/include/asm/Kbuild
@@ -2,6 +2,7 @@ include include/asm-generic/Kbuild.asm
2header-y += cachectl.h 2header-y += cachectl.h
3 3
4generic-y += bitsperlong.h 4generic-y += bitsperlong.h
5generic-y += clkdev.h
5generic-y += cputime.h 6generic-y += cputime.h
6generic-y += device.h 7generic-y += device.h
7generic-y += emergency-restart.h 8generic-y += emergency-restart.h
diff --git a/arch/m68k/include/asm/apollohw.h b/arch/m68k/include/asm/apollohw.h
index 635ef4f89010..6c19e0c22411 100644
--- a/arch/m68k/include/asm/apollohw.h
+++ b/arch/m68k/include/asm/apollohw.h
@@ -46,18 +46,6 @@ struct SCN2681 {
46 46
47}; 47};
48 48
49#if 0
50struct mc146818 {
51
52 unsigned int second1:4, second2:4, alarm_second1:4, alarm_second2:4,
53 minute1:4, minute2:4, alarm_minute1:4, alarm_minute2:4;
54 unsigned int hours1:4, hours2:4, alarm_hours1:4, alarm_hours2:4,
55 day_of_week1:4, day_of_week2:4, day_of_month1:4, day_of_month2:4;
56 unsigned int month1:4, month2:4, year1:4, year2:4, :16;
57
58};
59#endif
60
61struct mc146818 { 49struct mc146818 {
62 unsigned char second, alarm_second; 50 unsigned char second, alarm_second;
63 unsigned char minute, alarm_minute; 51 unsigned char minute, alarm_minute;
diff --git a/arch/m68k/include/asm/cacheflush.h b/arch/m68k/include/asm/cacheflush.h
index a70d7319630a..4fc738209bd1 100644
--- a/arch/m68k/include/asm/cacheflush.h
+++ b/arch/m68k/include/asm/cacheflush.h
@@ -1,5 +1,5 @@
1#ifdef __uClinux__ 1#ifdef __uClinux__
2#include "cacheflush_no.h" 2#include <asm/cacheflush_no.h>
3#else 3#else
4#include "cacheflush_mm.h" 4#include <asm/cacheflush_mm.h>
5#endif 5#endif
diff --git a/arch/m68k/include/asm/cacheflush_no.h b/arch/m68k/include/asm/cacheflush_no.h
index 7cafb537d03c..d2b3935ae147 100644
--- a/arch/m68k/include/asm/cacheflush_no.h
+++ b/arch/m68k/include/asm/cacheflush_no.h
@@ -34,10 +34,9 @@ static inline void __clear_cache_all(void)
34{ 34{
35#ifdef CACHE_INVALIDATE 35#ifdef CACHE_INVALIDATE
36 __asm__ __volatile__ ( 36 __asm__ __volatile__ (
37 "movel %0, %%d0\n\t" 37 "movec %0, %%CACR\n\t"
38 "movec %%d0, %%CACR\n\t"
39 "nop\n\t" 38 "nop\n\t"
40 : : "i" (CACHE_INVALIDATE) : "d0" ); 39 : : "r" (CACHE_INVALIDATE) );
41#endif 40#endif
42} 41}
43 42
@@ -58,10 +57,9 @@ static inline void __flush_icache_all(void)
58{ 57{
59#ifdef CACHE_INVALIDATEI 58#ifdef CACHE_INVALIDATEI
60 __asm__ __volatile__ ( 59 __asm__ __volatile__ (
61 "movel %0, %%d0\n\t" 60 "movec %0, %%CACR\n\t"
62 "movec %%d0, %%CACR\n\t"
63 "nop\n\t" 61 "nop\n\t"
64 : : "i" (CACHE_INVALIDATEI) : "d0" ); 62 : : "r" (CACHE_INVALIDATEI) );
65#endif 63#endif
66} 64}
67 65
@@ -72,19 +70,18 @@ static inline void __flush_dcache_all(void)
72#endif 70#endif
73#ifdef CACHE_INVALIDATED 71#ifdef CACHE_INVALIDATED
74 __asm__ __volatile__ ( 72 __asm__ __volatile__ (
75 "movel %0, %%d0\n\t" 73 "movec %0, %%CACR\n\t"
76 "movec %%d0, %%CACR\n\t"
77 "nop\n\t" 74 "nop\n\t"
78 : : "i" (CACHE_INVALIDATED) : "d0" ); 75 : : "r" (CACHE_INVALIDATED) );
79#else 76#else
80 /* Flush the wrtite buffer */ 77 /* Flush the write buffer */
81 __asm__ __volatile__ ( "nop" ); 78 __asm__ __volatile__ ( "nop" );
82#endif 79#endif
83} 80}
84 81
85/* 82/*
86 * Push cache entries at supplied address. We want to write back any dirty 83 * Push cache entries at supplied address. We want to write back any dirty
87 * data and the invalidate the cache lines associated with this address. 84 * data and then invalidate the cache lines associated with this address.
88 */ 85 */
89static inline void cache_push(unsigned long paddr, int len) 86static inline void cache_push(unsigned long paddr, int len)
90{ 87{
diff --git a/arch/m68k/include/asm/elf.h b/arch/m68k/include/asm/elf.h
index e9b7cda59744..f83c1d0a87cf 100644
--- a/arch/m68k/include/asm/elf.h
+++ b/arch/m68k/include/asm/elf.h
@@ -113,6 +113,7 @@ typedef struct user_m68kfp_struct elf_fpregset_t;
113 113
114#define ELF_PLATFORM (NULL) 114#define ELF_PLATFORM (NULL)
115 115
116#define SET_PERSONALITY(ex) set_personality(PER_LINUX) 116#define SET_PERSONALITY(ex) \
117 set_personality(PER_LINUX | (current->personality & (~PER_MASK)))
117 118
118#endif 119#endif
diff --git a/arch/m68k/include/asm/io.h b/arch/m68k/include/asm/io.h
index c7210ba184ea..c70cc9155003 100644
--- a/arch/m68k/include/asm/io.h
+++ b/arch/m68k/include/asm/io.h
@@ -1,5 +1,5 @@
1#ifdef __uClinux__ 1#ifdef __uClinux__
2#include "io_no.h" 2#include <asm/io_no.h>
3#else 3#else
4#include "io_mm.h" 4#include <asm/io_mm.h>
5#endif 5#endif
diff --git a/arch/m68k/include/asm/m5206sim.h b/arch/m68k/include/asm/m5206sim.h
index 69722366b084..4cf864f5ea7a 100644
--- a/arch/m68k/include/asm/m5206sim.h
+++ b/arch/m68k/include/asm/m5206sim.h
@@ -21,33 +21,33 @@
21/* 21/*
22 * Define the 5206 SIM register set addresses. 22 * Define the 5206 SIM register set addresses.
23 */ 23 */
24#define MCFSIM_SIMR 0x03 /* SIM Config reg (r/w) */ 24#define MCFSIM_SIMR (MCF_MBAR + 0x03) /* SIM Config reg */
25#define MCFSIM_ICR1 0x14 /* Intr Ctrl reg 1 (r/w) */ 25#define MCFSIM_ICR1 (MCF_MBAR + 0x14) /* Intr Ctrl reg 1 */
26#define MCFSIM_ICR2 0x15 /* Intr Ctrl reg 2 (r/w) */ 26#define MCFSIM_ICR2 (MCF_MBAR + 0x15) /* Intr Ctrl reg 2 */
27#define MCFSIM_ICR3 0x16 /* Intr Ctrl reg 3 (r/w) */ 27#define MCFSIM_ICR3 (MCF_MBAR + 0x16) /* Intr Ctrl reg 3 */
28#define MCFSIM_ICR4 0x17 /* Intr Ctrl reg 4 (r/w) */ 28#define MCFSIM_ICR4 (MCF_MBAR + 0x17) /* Intr Ctrl reg 4 */
29#define MCFSIM_ICR5 0x18 /* Intr Ctrl reg 5 (r/w) */ 29#define MCFSIM_ICR5 (MCF_MBAR + 0x18) /* Intr Ctrl reg 5 */
30#define MCFSIM_ICR6 0x19 /* Intr Ctrl reg 6 (r/w) */ 30#define MCFSIM_ICR6 (MCF_MBAR + 0x19) /* Intr Ctrl reg 6 */
31#define MCFSIM_ICR7 0x1a /* Intr Ctrl reg 7 (r/w) */ 31#define MCFSIM_ICR7 (MCF_MBAR + 0x1a) /* Intr Ctrl reg 7 */
32#define MCFSIM_ICR8 0x1b /* Intr Ctrl reg 8 (r/w) */ 32#define MCFSIM_ICR8 (MCF_MBAR + 0x1b) /* Intr Ctrl reg 8 */
33#define MCFSIM_ICR9 0x1c /* Intr Ctrl reg 9 (r/w) */ 33#define MCFSIM_ICR9 (MCF_MBAR + 0x1c) /* Intr Ctrl reg 9 */
34#define MCFSIM_ICR10 0x1d /* Intr Ctrl reg 10 (r/w) */ 34#define MCFSIM_ICR10 (MCF_MBAR + 0x1d) /* Intr Ctrl reg 10 */
35#define MCFSIM_ICR11 0x1e /* Intr Ctrl reg 11 (r/w) */ 35#define MCFSIM_ICR11 (MCF_MBAR + 0x1e) /* Intr Ctrl reg 11 */
36#define MCFSIM_ICR12 0x1f /* Intr Ctrl reg 12 (r/w) */ 36#define MCFSIM_ICR12 (MCF_MBAR + 0x1f) /* Intr Ctrl reg 12 */
37#define MCFSIM_ICR13 0x20 /* Intr Ctrl reg 13 (r/w) */ 37#define MCFSIM_ICR13 (MCF_MBAR + 0x20) /* Intr Ctrl reg 13 */
38#ifdef CONFIG_M5206e 38#ifdef CONFIG_M5206e
39#define MCFSIM_ICR14 0x21 /* Intr Ctrl reg 14 (r/w) */ 39#define MCFSIM_ICR14 (MCF_MBAR + 0x21) /* Intr Ctrl reg 14 */
40#define MCFSIM_ICR15 0x22 /* Intr Ctrl reg 15 (r/w) */ 40#define MCFSIM_ICR15 (MCF_MBAR + 0x22) /* Intr Ctrl reg 15 */
41#endif 41#endif
42 42
43#define MCFSIM_IMR 0x36 /* Interrupt Mask reg (r/w) */ 43#define MCFSIM_IMR (MCF_MBAR + 0x36) /* Interrupt Mask */
44#define MCFSIM_IPR 0x3a /* Interrupt Pend reg (r/w) */ 44#define MCFSIM_IPR (MCF_MBAR + 0x3a) /* Interrupt Pending */
45 45
46#define MCFSIM_RSR 0x40 /* Reset Status reg (r/w) */ 46#define MCFSIM_RSR (MCF_MBAR + 0x40) /* Reset Status */
47#define MCFSIM_SYPCR 0x41 /* System Protection reg (r/w)*/ 47#define MCFSIM_SYPCR (MCF_MBAR + 0x41) /* System Protection */
48 48
49#define MCFSIM_SWIVR 0x42 /* SW Watchdog intr reg (r/w) */ 49#define MCFSIM_SWIVR (MCF_MBAR + 0x42) /* SW Watchdog intr */
50#define MCFSIM_SWSR 0x43 /* SW Watchdog service (r/w) */ 50#define MCFSIM_SWSR (MCF_MBAR + 0x43) /* SW Watchdog srv */
51 51
52#define MCFSIM_DCRR (MCF_MBAR + 0x46) /* DRAM Refresh reg (r/w) */ 52#define MCFSIM_DCRR (MCF_MBAR + 0x46) /* DRAM Refresh reg (r/w) */
53#define MCFSIM_DCTR (MCF_MBAR + 0x4a) /* DRAM Timing reg (r/w) */ 53#define MCFSIM_DCTR (MCF_MBAR + 0x4a) /* DRAM Timing reg (r/w) */
@@ -58,36 +58,36 @@
58#define MCFSIM_DMR1 (MCF_MBAR + 0x5c) /* DRAM 1 Mask reg (r/w) */ 58#define MCFSIM_DMR1 (MCF_MBAR + 0x5c) /* DRAM 1 Mask reg (r/w) */
59#define MCFSIM_DCR1 (MCF_MBAR + 0x63) /* DRAM 1 Control reg (r/w) */ 59#define MCFSIM_DCR1 (MCF_MBAR + 0x63) /* DRAM 1 Control reg (r/w) */
60 60
61#define MCFSIM_CSAR0 0x64 /* CS 0 Address 0 reg (r/w) */ 61#define MCFSIM_CSAR0 (MCF_MBAR + 0x64) /* CS 0 Address reg */
62#define MCFSIM_CSMR0 0x68 /* CS 0 Mask 0 reg (r/w) */ 62#define MCFSIM_CSMR0 (MCF_MBAR + 0x68) /* CS 0 Mask reg */
63#define MCFSIM_CSCR0 0x6e /* CS 0 Control reg (r/w) */ 63#define MCFSIM_CSCR0 (MCF_MBAR + 0x6e) /* CS 0 Control reg */
64#define MCFSIM_CSAR1 0x70 /* CS 1 Address reg (r/w) */ 64#define MCFSIM_CSAR1 (MCF_MBAR + 0x70) /* CS 1 Address reg */
65#define MCFSIM_CSMR1 0x74 /* CS 1 Mask reg (r/w) */ 65#define MCFSIM_CSMR1 (MCF_MBAR + 0x74) /* CS 1 Mask reg */
66#define MCFSIM_CSCR1 0x7a /* CS 1 Control reg (r/w) */ 66#define MCFSIM_CSCR1 (MCF_MBAR + 0x7a) /* CS 1 Control reg */
67#define MCFSIM_CSAR2 0x7c /* CS 2 Address reg (r/w) */ 67#define MCFSIM_CSAR2 (MCF_MBAR + 0x7c) /* CS 2 Address reg */
68#define MCFSIM_CSMR2 0x80 /* CS 2 Mask reg (r/w) */ 68#define MCFSIM_CSMR2 (MCF_MBAR + 0x80) /* CS 2 Mask reg */
69#define MCFSIM_CSCR2 0x86 /* CS 2 Control reg (r/w) */ 69#define MCFSIM_CSCR2 (MCF_MBAR + 0x86) /* CS 2 Control reg */
70#define MCFSIM_CSAR3 0x88 /* CS 3 Address reg (r/w) */ 70#define MCFSIM_CSAR3 (MCF_MBAR + 0x88) /* CS 3 Address reg */
71#define MCFSIM_CSMR3 0x8c /* CS 3 Mask reg (r/w) */ 71#define MCFSIM_CSMR3 (MCF_MBAR + 0x8c) /* CS 3 Mask reg */
72#define MCFSIM_CSCR3 0x92 /* CS 3 Control reg (r/w) */ 72#define MCFSIM_CSCR3 (MCF_MBAR + 0x92) /* CS 3 Control reg */
73#define MCFSIM_CSAR4 0x94 /* CS 4 Address reg (r/w) */ 73#define MCFSIM_CSAR4 (MCF_MBAR + 0x94) /* CS 4 Address reg */
74#define MCFSIM_CSMR4 0x98 /* CS 4 Mask reg (r/w) */ 74#define MCFSIM_CSMR4 (MCF_MBAR + 0x98) /* CS 4 Mask reg */
75#define MCFSIM_CSCR4 0x9e /* CS 4 Control reg (r/w) */ 75#define MCFSIM_CSCR4 (MCF_MBAR + 0x9e) /* CS 4 Control reg */
76#define MCFSIM_CSAR5 0xa0 /* CS 5 Address reg (r/w) */ 76#define MCFSIM_CSAR5 (MCF_MBAR + 0xa0) /* CS 5 Address reg */
77#define MCFSIM_CSMR5 0xa4 /* CS 5 Mask reg (r/w) */ 77#define MCFSIM_CSMR5 (MCF_MBAR + 0xa4) /* CS 5 Mask reg */
78#define MCFSIM_CSCR5 0xaa /* CS 5 Control reg (r/w) */ 78#define MCFSIM_CSCR5 (MCF_MBAR + 0xaa) /* CS 5 Control reg */
79#define MCFSIM_CSAR6 0xac /* CS 6 Address reg (r/w) */ 79#define MCFSIM_CSAR6 (MCF_MBAR + 0xac) /* CS 6 Address reg */
80#define MCFSIM_CSMR6 0xb0 /* CS 6 Mask reg (r/w) */ 80#define MCFSIM_CSMR6 (MCF_MBAR + 0xb0) /* CS 6 Mask reg */
81#define MCFSIM_CSCR6 0xb6 /* CS 6 Control reg (r/w) */ 81#define MCFSIM_CSCR6 (MCF_MBAR + 0xb6) /* CS 6 Control reg */
82#define MCFSIM_CSAR7 0xb8 /* CS 7 Address reg (r/w) */ 82#define MCFSIM_CSAR7 (MCF_MBAR + 0xb8) /* CS 7 Address reg */
83#define MCFSIM_CSMR7 0xbc /* CS 7 Mask reg (r/w) */ 83#define MCFSIM_CSMR7 (MCF_MBAR + 0xbc) /* CS 7 Mask reg */
84#define MCFSIM_CSCR7 0xc2 /* CS 7 Control reg (r/w) */ 84#define MCFSIM_CSCR7 (MCF_MBAR + 0xc2) /* CS 7 Control reg */
85#define MCFSIM_DMCR 0xc6 /* Default control */ 85#define MCFSIM_DMCR (MCF_MBAR + 0xc6) /* Default control */
86 86
87#ifdef CONFIG_M5206e 87#ifdef CONFIG_M5206e
88#define MCFSIM_PAR 0xca /* Pin Assignment reg (r/w) */ 88#define MCFSIM_PAR (MCF_MBAR + 0xca) /* Pin Assignment */
89#else 89#else
90#define MCFSIM_PAR 0xcb /* Pin Assignment reg (r/w) */ 90#define MCFSIM_PAR (MCF_MBAR + 0xcb) /* Pin Assignment */
91#endif 91#endif
92 92
93#define MCFTIMER_BASE1 (MCF_MBAR + 0x100) /* Base of TIMER1 */ 93#define MCFTIMER_BASE1 (MCF_MBAR + 0x100) /* Base of TIMER1 */
diff --git a/arch/m68k/include/asm/m523xsim.h b/arch/m68k/include/asm/m523xsim.h
index 91d3abc3f2a5..5e06b4eb57f3 100644
--- a/arch/m68k/include/asm/m523xsim.h
+++ b/arch/m68k/include/asm/m523xsim.h
@@ -176,21 +176,29 @@
176/* 176/*
177 * Generic GPIO support 177 * Generic GPIO support
178 */ 178 */
179#define MCFGPIO_PODR MCFGPIO_PODR_ADDR 179#define MCFGPIO_PODR MCFGPIO_PODR_ADDR
180#define MCFGPIO_PDDR MCFGPIO_PDDR_ADDR 180#define MCFGPIO_PDDR MCFGPIO_PDDR_ADDR
181#define MCFGPIO_PPDR MCFGPIO_PPDSDR_ADDR 181#define MCFGPIO_PPDR MCFGPIO_PPDSDR_ADDR
182#define MCFGPIO_SETR MCFGPIO_PPDSDR_ADDR 182#define MCFGPIO_SETR MCFGPIO_PPDSDR_ADDR
183#define MCFGPIO_CLRR MCFGPIO_PCLRR_ADDR 183#define MCFGPIO_CLRR MCFGPIO_PCLRR_ADDR
184 184
185#define MCFGPIO_PIN_MAX 107 185#define MCFGPIO_PIN_MAX 107
186#define MCFGPIO_IRQ_MAX 8 186#define MCFGPIO_IRQ_MAX 8
187#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE 187#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
188 188
189/* 189/*
190 * Pin Assignment 190 * Pin Assignment
191*/ 191*/
192#define MCFGPIO_PAR_AD (MCF_IPSBAR + 0x100040)
193#define MCFGPIO_PAR_BUSCTL (MCF_IPSBAR + 0x100042)
194#define MCFGPIO_PAR_BS (MCF_IPSBAR + 0x100044)
195#define MCFGPIO_PAR_CS (MCF_IPSBAR + 0x100045)
196#define MCFGPIO_PAR_SDRAM (MCF_IPSBAR + 0x100046)
197#define MCFGPIO_PAR_FECI2C (MCF_IPSBAR + 0x100047)
198#define MCFGPIO_PAR_UART (MCF_IPSBAR + 0x100048)
192#define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10004A) 199#define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10004A)
193#define MCFGPIO_PAR_TIMER (MCF_IPSBAR + 0x10004C) 200#define MCFGPIO_PAR_TIMER (MCF_IPSBAR + 0x10004C)
201#define MCFGPIO_PAR_ETPU (MCF_IPSBAR + 0x10004E)
194 202
195/* 203/*
196 * DMA unit base addresses. 204 * DMA unit base addresses.
diff --git a/arch/m68k/include/asm/m5249sim.h b/arch/m68k/include/asm/m5249sim.h
index 7f0c2c3660fd..fdf45e6807c9 100644
--- a/arch/m68k/include/asm/m5249sim.h
+++ b/arch/m68k/include/asm/m5249sim.h
@@ -25,41 +25,41 @@
25/* 25/*
26 * Define the 5249 SIM register set addresses. 26 * Define the 5249 SIM register set addresses.
27 */ 27 */
28#define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */ 28#define MCFSIM_RSR (MCF_MBAR + 0x00) /* Reset Status */
29#define MCFSIM_SYPCR 0x01 /* System Protection reg (r/w)*/ 29#define MCFSIM_SYPCR (MCF_MBAR + 0x01) /* System Protection */
30#define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */ 30#define MCFSIM_SWIVR (MCF_MBAR + 0x02) /* SW Watchdog intr */
31#define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */ 31#define MCFSIM_SWSR (MCF_MBAR + 0x03) /* SW Watchdog srv */
32#define MCFSIM_PAR 0x04 /* Pin Assignment reg (r/w) */ 32#define MCFSIM_PAR (MCF_MBAR + 0x04) /* Pin Assignment */
33#define MCFSIM_IRQPAR 0x06 /* Interrupt Assignment reg (r/w) */ 33#define MCFSIM_IRQPAR (MCF_MBAR + 0x06) /* Intr Assignment */
34#define MCFSIM_MPARK 0x0C /* BUS Master Control Reg*/ 34#define MCFSIM_MPARK (MCF_MBAR + 0x0C) /* BUS Master Ctrl */
35#define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */ 35#define MCFSIM_IPR (MCF_MBAR + 0x40) /* Interrupt Pending */
36#define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */ 36#define MCFSIM_IMR (MCF_MBAR + 0x44) /* Interrupt Mask */
37#define MCFSIM_AVR 0x4b /* Autovector Ctrl reg (r/w) */ 37#define MCFSIM_AVR (MCF_MBAR + 0x4b) /* Autovector Ctrl */
38#define MCFSIM_ICR0 0x4c /* Intr Ctrl reg 0 (r/w) */ 38#define MCFSIM_ICR0 (MCF_MBAR + 0x4c) /* Intr Ctrl reg 0 */
39#define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */ 39#define MCFSIM_ICR1 (MCF_MBAR + 0x4d) /* Intr Ctrl reg 1 */
40#define MCFSIM_ICR2 0x4e /* Intr Ctrl reg 2 (r/w) */ 40#define MCFSIM_ICR2 (MCF_MBAR + 0x4e) /* Intr Ctrl reg 2 */
41#define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */ 41#define MCFSIM_ICR3 (MCF_MBAR + 0x4f) /* Intr Ctrl reg 3 */
42#define MCFSIM_ICR4 0x50 /* Intr Ctrl reg 4 (r/w) */ 42#define MCFSIM_ICR4 (MCF_MBAR + 0x50) /* Intr Ctrl reg 4 */
43#define MCFSIM_ICR5 0x51 /* Intr Ctrl reg 5 (r/w) */ 43#define MCFSIM_ICR5 (MCF_MBAR + 0x51) /* Intr Ctrl reg 5 */
44#define MCFSIM_ICR6 0x52 /* Intr Ctrl reg 6 (r/w) */ 44#define MCFSIM_ICR6 (MCF_MBAR + 0x52) /* Intr Ctrl reg 6 */
45#define MCFSIM_ICR7 0x53 /* Intr Ctrl reg 7 (r/w) */ 45#define MCFSIM_ICR7 (MCF_MBAR + 0x53) /* Intr Ctrl reg 7 */
46#define MCFSIM_ICR8 0x54 /* Intr Ctrl reg 8 (r/w) */ 46#define MCFSIM_ICR8 (MCF_MBAR + 0x54) /* Intr Ctrl reg 8 */
47#define MCFSIM_ICR9 0x55 /* Intr Ctrl reg 9 (r/w) */ 47#define MCFSIM_ICR9 (MCF_MBAR + 0x55) /* Intr Ctrl reg 9 */
48#define MCFSIM_ICR10 0x56 /* Intr Ctrl reg 10 (r/w) */ 48#define MCFSIM_ICR10 (MCF_MBAR + 0x56) /* Intr Ctrl reg 10 */
49#define MCFSIM_ICR11 0x57 /* Intr Ctrl reg 11 (r/w) */ 49#define MCFSIM_ICR11 (MCF_MBAR + 0x57) /* Intr Ctrl reg 11 */
50 50
51#define MCFSIM_CSAR0 0x80 /* CS 0 Address 0 reg (r/w) */ 51#define MCFSIM_CSAR0 (MCF_MBAR + 0x80) /* CS 0 Address reg */
52#define MCFSIM_CSMR0 0x84 /* CS 0 Mask 0 reg (r/w) */ 52#define MCFSIM_CSMR0 (MCF_MBAR + 0x84) /* CS 0 Mask reg */
53#define MCFSIM_CSCR0 0x8a /* CS 0 Control reg (r/w) */ 53#define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */
54#define MCFSIM_CSAR1 0x8c /* CS 1 Address reg (r/w) */ 54#define MCFSIM_CSAR1 (MCF_MBAR + 0x8c) /* CS 1 Address reg */
55#define MCFSIM_CSMR1 0x90 /* CS 1 Mask reg (r/w) */ 55#define MCFSIM_CSMR1 (MCF_MBAR + 0x90) /* CS 1 Mask reg */
56#define MCFSIM_CSCR1 0x96 /* CS 1 Control reg (r/w) */ 56#define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */
57#define MCFSIM_CSAR2 0x98 /* CS 2 Address reg (r/w) */ 57#define MCFSIM_CSAR2 (MCF_MBAR + 0x98) /* CS 2 Address reg */
58#define MCFSIM_CSMR2 0x9c /* CS 2 Mask reg (r/w) */ 58#define MCFSIM_CSMR2 (MCF_MBAR + 0x9c) /* CS 2 Mask reg */
59#define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */ 59#define MCFSIM_CSCR2 (MCF_MBAR + 0xa2) /* CS 2 Control reg */
60#define MCFSIM_CSAR3 0xa4 /* CS 3 Address reg (r/w) */ 60#define MCFSIM_CSAR3 (MCF_MBAR + 0xa4) /* CS 3 Address reg */
61#define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */ 61#define MCFSIM_CSMR3 (MCF_MBAR + 0xa8) /* CS 3 Mask reg */
62#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */ 62#define MCFSIM_CSCR3 (MCF_MBAR + 0xae) /* CS 3 Control reg */
63 63
64#define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */ 64#define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */
65#define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM 0 Addr/Ctrl */ 65#define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM 0 Addr/Ctrl */
@@ -134,23 +134,23 @@
134#define MCFSIM2_GPIO1ENABLE (MCF_MBAR2 + 0x0B8) /* GPIO1 enabled */ 134#define MCFSIM2_GPIO1ENABLE (MCF_MBAR2 + 0x0B8) /* GPIO1 enabled */
135#define MCFSIM2_GPIO1FUNC (MCF_MBAR2 + 0x0BC) /* GPIO1 function */ 135#define MCFSIM2_GPIO1FUNC (MCF_MBAR2 + 0x0BC) /* GPIO1 function */
136 136
137#define MCFSIM2_GPIOINTSTAT 0xc0 /* GPIO interrupt status */ 137#define MCFSIM2_GPIOINTSTAT (MCF_MBAR2 + 0xc0) /* GPIO intr status */
138#define MCFSIM2_GPIOINTCLEAR 0xc0 /* GPIO interrupt clear */ 138#define MCFSIM2_GPIOINTCLEAR (MCF_MBAR2 + 0xc0) /* GPIO intr clear */
139#define MCFSIM2_GPIOINTENABLE 0xc4 /* GPIO interrupt enable */ 139#define MCFSIM2_GPIOINTENABLE (MCF_MBAR2 + 0xc4) /* GPIO intr enable */
140 140
141#define MCFSIM2_INTLEVEL1 0x140 /* Interrupt level reg 1 */ 141#define MCFSIM2_INTLEVEL1 (MCF_MBAR2 + 0x140) /* Intr level reg 1 */
142#define MCFSIM2_INTLEVEL2 0x144 /* Interrupt level reg 2 */ 142#define MCFSIM2_INTLEVEL2 (MCF_MBAR2 + 0x144) /* Intr level reg 2 */
143#define MCFSIM2_INTLEVEL3 0x148 /* Interrupt level reg 3 */ 143#define MCFSIM2_INTLEVEL3 (MCF_MBAR2 + 0x148) /* Intr level reg 3 */
144#define MCFSIM2_INTLEVEL4 0x14c /* Interrupt level reg 4 */ 144#define MCFSIM2_INTLEVEL4 (MCF_MBAR2 + 0x14c) /* Intr level reg 4 */
145#define MCFSIM2_INTLEVEL5 0x150 /* Interrupt level reg 5 */ 145#define MCFSIM2_INTLEVEL5 (MCF_MBAR2 + 0x150) /* Intr level reg 5 */
146#define MCFSIM2_INTLEVEL6 0x154 /* Interrupt level reg 6 */ 146#define MCFSIM2_INTLEVEL6 (MCF_MBAR2 + 0x154) /* Intr level reg 6 */
147#define MCFSIM2_INTLEVEL7 0x158 /* Interrupt level reg 7 */ 147#define MCFSIM2_INTLEVEL7 (MCF_MBAR2 + 0x158) /* Intr level reg 7 */
148#define MCFSIM2_INTLEVEL8 0x15c /* Interrupt level reg 8 */ 148#define MCFSIM2_INTLEVEL8 (MCF_MBAR2 + 0x15c) /* Intr level reg 8 */
149 149
150#define MCFSIM2_DMAROUTE 0x188 /* DMA routing */ 150#define MCFSIM2_DMAROUTE (MCF_MBAR2 + 0x188) /* DMA routing */
151 151
152#define MCFSIM2_IDECONFIG1 0x18c /* IDEconfig1 */ 152#define MCFSIM2_IDECONFIG1 (MCF_MBAR2 + 0x18c) /* IDEconfig1 */
153#define MCFSIM2_IDECONFIG2 0x190 /* IDEconfig2 */ 153#define MCFSIM2_IDECONFIG2 (MCF_MBAR2 + 0x190) /* IDEconfig2 */
154 154
155/* 155/*
156 * Define the base interrupt for the second interrupt controller. 156 * Define the base interrupt for the second interrupt controller.
diff --git a/arch/m68k/include/asm/m525xsim.h b/arch/m68k/include/asm/m525xsim.h
index 6da24f653902..acab61cb91ed 100644
--- a/arch/m68k/include/asm/m525xsim.h
+++ b/arch/m68k/include/asm/m525xsim.h
@@ -26,41 +26,41 @@
26/* 26/*
27 * Define the 525x SIM register set addresses. 27 * Define the 525x SIM register set addresses.
28 */ 28 */
29#define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */ 29#define MCFSIM_RSR (MCF_MBAR + 0x00) /* Reset Status */
30#define MCFSIM_SYPCR 0x01 /* System Protection reg (r/w)*/ 30#define MCFSIM_SYPCR (MCF_MBAR + 0x01) /* System Protection */
31#define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */ 31#define MCFSIM_SWIVR (MCF_MBAR + 0x02) /* SW Watchdog intr */
32#define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */ 32#define MCFSIM_SWSR (MCF_MBAR + 0x03) /* SW Watchdog srv */
33#define MCFSIM_MPARK 0x0C /* BUS Master Control Reg*/ 33#define MCFSIM_MPARK (MCF_MBAR + 0x0C) /* BUS Master Ctrl */
34#define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */ 34#define MCFSIM_IPR (MCF_MBAR + 0x40) /* Interrupt Pending */
35#define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */ 35#define MCFSIM_IMR (MCF_MBAR + 0x44) /* Interrupt Mask */
36#define MCFSIM_ICR0 0x4c /* Intr Ctrl reg 0 (r/w) */ 36#define MCFSIM_ICR0 (MCF_MBAR + 0x4c) /* Intr Ctrl reg 0 */
37#define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */ 37#define MCFSIM_ICR1 (MCF_MBAR + 0x4d) /* Intr Ctrl reg 1 */
38#define MCFSIM_ICR2 0x4e /* Intr Ctrl reg 2 (r/w) */ 38#define MCFSIM_ICR2 (MCF_MBAR + 0x4e) /* Intr Ctrl reg 2 */
39#define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */ 39#define MCFSIM_ICR3 (MCF_MBAR + 0x4f) /* Intr Ctrl reg 3 */
40#define MCFSIM_ICR4 0x50 /* Intr Ctrl reg 4 (r/w) */ 40#define MCFSIM_ICR4 (MCF_MBAR + 0x50) /* Intr Ctrl reg 4 */
41#define MCFSIM_ICR5 0x51 /* Intr Ctrl reg 5 (r/w) */ 41#define MCFSIM_ICR5 (MCF_MBAR + 0x51) /* Intr Ctrl reg 5 */
42#define MCFSIM_ICR6 0x52 /* Intr Ctrl reg 6 (r/w) */ 42#define MCFSIM_ICR6 (MCF_MBAR + 0x52) /* Intr Ctrl reg 6 */
43#define MCFSIM_ICR7 0x53 /* Intr Ctrl reg 7 (r/w) */ 43#define MCFSIM_ICR7 (MCF_MBAR + 0x53) /* Intr Ctrl reg 7 */
44#define MCFSIM_ICR8 0x54 /* Intr Ctrl reg 8 (r/w) */ 44#define MCFSIM_ICR8 (MCF_MBAR + 0x54) /* Intr Ctrl reg 8 */
45#define MCFSIM_ICR9 0x55 /* Intr Ctrl reg 9 (r/w) */ 45#define MCFSIM_ICR9 (MCF_MBAR + 0x55) /* Intr Ctrl reg 9 */
46#define MCFSIM_ICR10 0x56 /* Intr Ctrl reg 10 (r/w) */ 46#define MCFSIM_ICR10 (MCF_MBAR + 0x56) /* Intr Ctrl reg 10 */
47#define MCFSIM_ICR11 0x57 /* Intr Ctrl reg 11 (r/w) */ 47#define MCFSIM_ICR11 (MCF_MBAR + 0x57) /* Intr Ctrl reg 11 */
48 48
49#define MCFSIM_CSAR0 0x80 /* CS 0 Address 0 reg (r/w) */ 49#define MCFSIM_CSAR0 (MCF_MBAR + 0x80) /* CS 0 Address reg */
50#define MCFSIM_CSMR0 0x84 /* CS 0 Mask 0 reg (r/w) */ 50#define MCFSIM_CSMR0 (MCF_MBAR + 0x84) /* CS 0 Mask reg */
51#define MCFSIM_CSCR0 0x8a /* CS 0 Control reg (r/w) */ 51#define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */
52#define MCFSIM_CSAR1 0x8c /* CS 1 Address reg (r/w) */ 52#define MCFSIM_CSAR1 (MCF_MBAR + 0x8c) /* CS 1 Address reg */
53#define MCFSIM_CSMR1 0x90 /* CS 1 Mask reg (r/w) */ 53#define MCFSIM_CSMR1 (MCF_MBAR + 0x90) /* CS 1 Mask reg */
54#define MCFSIM_CSCR1 0x96 /* CS 1 Control reg (r/w) */ 54#define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */
55#define MCFSIM_CSAR2 0x98 /* CS 2 Address reg (r/w) */ 55#define MCFSIM_CSAR2 (MCF_MBAR + 0x98) /* CS 2 Address reg */
56#define MCFSIM_CSMR2 0x9c /* CS 2 Mask reg (r/w) */ 56#define MCFSIM_CSMR2 (MCF_MBAR + 0x9c) /* CS 2 Mask reg */
57#define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */ 57#define MCFSIM_CSCR2 (MCF_MBAR + 0xa2) /* CS 2 Control reg */
58#define MCFSIM_CSAR3 0xa4 /* CS 3 Address reg (r/w) */ 58#define MCFSIM_CSAR3 (MCF_MBAR + 0xa4) /* CS 3 Address reg */
59#define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */ 59#define MCFSIM_CSMR3 (MCF_MBAR + 0xa8) /* CS 3 Mask reg */
60#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */ 60#define MCFSIM_CSCR3 (MCF_MBAR + 0xae) /* CS 3 Control reg */
61#define MCFSIM_CSAR4 0xb0 /* CS 4 Address reg (r/w) */ 61#define MCFSIM_CSAR4 (MCF_MBAR + 0xb0) /* CS 4 Address reg */
62#define MCFSIM_CSMR4 0xb4 /* CS 4 Mask reg (r/w) */ 62#define MCFSIM_CSMR4 (MCF_MBAR + 0xb4) /* CS 4 Mask reg */
63#define MCFSIM_CSCR4 0xba /* CS 4 Control reg (r/w) */ 63#define MCFSIM_CSCR4 (MCF_MBAR + 0xba) /* CS 4 Control reg */
64 64
65#define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */ 65#define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */
66#define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM 0 Addr/Ctrl */ 66#define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM 0 Addr/Ctrl */
diff --git a/arch/m68k/include/asm/m5272sim.h b/arch/m68k/include/asm/m5272sim.h
index a58f1760d858..1fb01bb05d6c 100644
--- a/arch/m68k/include/asm/m5272sim.h
+++ b/arch/m68k/include/asm/m5272sim.h
@@ -21,52 +21,52 @@
21/* 21/*
22 * Define the 5272 SIM register set addresses. 22 * Define the 5272 SIM register set addresses.
23 */ 23 */
24#define MCFSIM_SCR 0x04 /* SIM Config reg (r/w) */ 24#define MCFSIM_SCR (MCF_MBAR + 0x04) /* SIM Config reg */
25#define MCFSIM_SPR 0x06 /* System Protection reg (r/w)*/ 25#define MCFSIM_SPR (MCF_MBAR + 0x06) /* System Protection */
26#define MCFSIM_PMR 0x08 /* Power Management reg (r/w) */ 26#define MCFSIM_PMR (MCF_MBAR + 0x08) /* Power Management */
27#define MCFSIM_APMR 0x0e /* Active Low Power reg (r/w) */ 27#define MCFSIM_APMR (MCF_MBAR + 0x0e) /* Active Low Power */
28#define MCFSIM_DIR 0x10 /* Device Identity reg (r/w) */ 28#define MCFSIM_DIR (MCF_MBAR + 0x10) /* Device Identity */
29 29
30#define MCFSIM_ICR1 0x20 /* Intr Ctrl reg 1 (r/w) */ 30#define MCFSIM_ICR1 (MCF_MBAR + 0x20) /* Intr Ctrl reg 1 */
31#define MCFSIM_ICR2 0x24 /* Intr Ctrl reg 2 (r/w) */ 31#define MCFSIM_ICR2 (MCF_MBAR + 0x24) /* Intr Ctrl reg 2 */
32#define MCFSIM_ICR3 0x28 /* Intr Ctrl reg 3 (r/w) */ 32#define MCFSIM_ICR3 (MCF_MBAR + 0x28) /* Intr Ctrl reg 3 */
33#define MCFSIM_ICR4 0x2c /* Intr Ctrl reg 4 (r/w) */ 33#define MCFSIM_ICR4 (MCF_MBAR + 0x2c) /* Intr Ctrl reg 4 */
34 34
35#define MCFSIM_ISR 0x30 /* Interrupt Source reg (r/w) */ 35#define MCFSIM_ISR (MCF_MBAR + 0x30) /* Intr Source */
36#define MCFSIM_PITR 0x34 /* Interrupt Transition (r/w) */ 36#define MCFSIM_PITR (MCF_MBAR + 0x34) /* Intr Transition */
37#define MCFSIM_PIWR 0x38 /* Interrupt Wakeup reg (r/w) */ 37#define MCFSIM_PIWR (MCF_MBAR + 0x38) /* Intr Wakeup */
38#define MCFSIM_PIVR 0x3f /* Interrupt Vector reg (r/w( */ 38#define MCFSIM_PIVR (MCF_MBAR + 0x3f) /* Intr Vector */
39 39
40#define MCFSIM_WRRR 0x280 /* Watchdog reference (r/w) */ 40#define MCFSIM_WRRR (MCF_MBAR + 0x280) /* Watchdog reference */
41#define MCFSIM_WIRR 0x284 /* Watchdog interrupt (r/w) */ 41#define MCFSIM_WIRR (MCF_MBAR + 0x284) /* Watchdog interrupt */
42#define MCFSIM_WCR 0x288 /* Watchdog counter (r/w) */ 42#define MCFSIM_WCR (MCF_MBAR + 0x288) /* Watchdog counter */
43#define MCFSIM_WER 0x28c /* Watchdog event (r/w) */ 43#define MCFSIM_WER (MCF_MBAR + 0x28c) /* Watchdog event */
44 44
45#define MCFSIM_CSBR0 0x40 /* CS0 Base Address (r/w) */ 45#define MCFSIM_CSBR0 (MCF_MBAR + 0x40) /* CS0 Base Address */
46#define MCFSIM_CSOR0 0x44 /* CS0 Option (r/w) */ 46#define MCFSIM_CSOR0 (MCF_MBAR + 0x44) /* CS0 Option */
47#define MCFSIM_CSBR1 0x48 /* CS1 Base Address (r/w) */ 47#define MCFSIM_CSBR1 (MCF_MBAR + 0x48) /* CS1 Base Address */
48#define MCFSIM_CSOR1 0x4c /* CS1 Option (r/w) */ 48#define MCFSIM_CSOR1 (MCF_MBAR + 0x4c) /* CS1 Option */
49#define MCFSIM_CSBR2 0x50 /* CS2 Base Address (r/w) */ 49#define MCFSIM_CSBR2 (MCF_MBAR + 0x50) /* CS2 Base Address */
50#define MCFSIM_CSOR2 0x54 /* CS2 Option (r/w) */ 50#define MCFSIM_CSOR2 (MCF_MBAR + 0x54) /* CS2 Option */
51#define MCFSIM_CSBR3 0x58 /* CS3 Base Address (r/w) */ 51#define MCFSIM_CSBR3 (MCF_MBAR + 0x58) /* CS3 Base Address */
52#define MCFSIM_CSOR3 0x5c /* CS3 Option (r/w) */ 52#define MCFSIM_CSOR3 (MCF_MBAR + 0x5c) /* CS3 Option */
53#define MCFSIM_CSBR4 0x60 /* CS4 Base Address (r/w) */ 53#define MCFSIM_CSBR4 (MCF_MBAR + 0x60) /* CS4 Base Address */
54#define MCFSIM_CSOR4 0x64 /* CS4 Option (r/w) */ 54#define MCFSIM_CSOR4 (MCF_MBAR + 0x64) /* CS4 Option */
55#define MCFSIM_CSBR5 0x68 /* CS5 Base Address (r/w) */ 55#define MCFSIM_CSBR5 (MCF_MBAR + 0x68) /* CS5 Base Address */
56#define MCFSIM_CSOR5 0x6c /* CS5 Option (r/w) */ 56#define MCFSIM_CSOR5 (MCF_MBAR + 0x6c) /* CS5 Option */
57#define MCFSIM_CSBR6 0x70 /* CS6 Base Address (r/w) */ 57#define MCFSIM_CSBR6 (MCF_MBAR + 0x70) /* CS6 Base Address */
58#define MCFSIM_CSOR6 0x74 /* CS6 Option (r/w) */ 58#define MCFSIM_CSOR6 (MCF_MBAR + 0x74) /* CS6 Option */
59#define MCFSIM_CSBR7 0x78 /* CS7 Base Address (r/w) */ 59#define MCFSIM_CSBR7 (MCF_MBAR + 0x78) /* CS7 Base Address */
60#define MCFSIM_CSOR7 0x7c /* CS7 Option (r/w) */ 60#define MCFSIM_CSOR7 (MCF_MBAR + 0x7c) /* CS7 Option */
61 61
62#define MCFSIM_SDCR 0x180 /* SDRAM Configuration (r/w) */ 62#define MCFSIM_SDCR (MCF_MBAR + 0x180) /* SDRAM Config */
63#define MCFSIM_SDTR 0x184 /* SDRAM Timing (r/w) */ 63#define MCFSIM_SDTR (MCF_MBAR + 0x184) /* SDRAM Timing */
64#define MCFSIM_DCAR0 0x4c /* DRAM 0 Address reg(r/w) */ 64#define MCFSIM_DCAR0 (MCF_MBAR + 0x4c) /* DRAM 0 Address */
65#define MCFSIM_DCMR0 0x50 /* DRAM 0 Mask reg (r/w) */ 65#define MCFSIM_DCMR0 (MCF_MBAR + 0x50) /* DRAM 0 Mask */
66#define MCFSIM_DCCR0 0x57 /* DRAM 0 Control reg (r/w) */ 66#define MCFSIM_DCCR0 (MCF_MBAR + 0x57) /* DRAM 0 Control */
67#define MCFSIM_DCAR1 0x58 /* DRAM 1 Address reg (r/w) */ 67#define MCFSIM_DCAR1 (MCF_MBAR + 0x58) /* DRAM 1 Address */
68#define MCFSIM_DCMR1 0x5c /* DRAM 1 Mask reg (r/w) */ 68#define MCFSIM_DCMR1 (MCF_MBAR + 0x5c) /* DRAM 1 Mask reg */
69#define MCFSIM_DCCR1 0x63 /* DRAM 1 Control reg (r/w) */ 69#define MCFSIM_DCCR1 (MCF_MBAR + 0x63) /* DRAM 1 Control */
70 70
71#define MCFUART_BASE0 (MCF_MBAR + 0x100) /* Base address UART0 */ 71#define MCFUART_BASE0 (MCF_MBAR + 0x100) /* Base address UART0 */
72#define MCFUART_BASE1 (MCF_MBAR + 0x140) /* Base address UART1 */ 72#define MCFUART_BASE1 (MCF_MBAR + 0x140) /* Base address UART1 */
@@ -132,8 +132,9 @@
132/* 132/*
133 * Generic GPIO support 133 * Generic GPIO support
134 */ 134 */
135#define MCFGPIO_PIN_MAX 48 135#define MCFGPIO_PIN_MAX 48
136#define MCFGPIO_IRQ_MAX -1 136#define MCFGPIO_IRQ_MAX -1
137#define MCFGPIO_IRQ_VECBASE -1 137#define MCFGPIO_IRQ_VECBASE -1
138
138/****************************************************************************/ 139/****************************************************************************/
139#endif /* m5272sim_h */ 140#endif /* m5272sim_h */
diff --git a/arch/m68k/include/asm/m527xsim.h b/arch/m68k/include/asm/m527xsim.h
index 71aa5104d3d6..1bebbe78055a 100644
--- a/arch/m68k/include/asm/m527xsim.h
+++ b/arch/m68k/include/asm/m527xsim.h
@@ -184,19 +184,33 @@
184/* 184/*
185 * Generic GPIO support 185 * Generic GPIO support
186 */ 186 */
187#define MCFGPIO_PODR MCFGPIO_PODR_ADDR 187#define MCFGPIO_PODR MCFGPIO_PODR_ADDR
188#define MCFGPIO_PDDR MCFGPIO_PDDR_ADDR 188#define MCFGPIO_PDDR MCFGPIO_PDDR_ADDR
189#define MCFGPIO_PPDR MCFGPIO_PPDSDR_ADDR 189#define MCFGPIO_PPDR MCFGPIO_PPDSDR_ADDR
190#define MCFGPIO_SETR MCFGPIO_PPDSDR_ADDR 190#define MCFGPIO_SETR MCFGPIO_PPDSDR_ADDR
191#define MCFGPIO_CLRR MCFGPIO_PCLRR_ADDR 191#define MCFGPIO_CLRR MCFGPIO_PCLRR_ADDR
192 192
193#define MCFGPIO_PIN_MAX 100 193#define MCFGPIO_PIN_MAX 100
194#define MCFGPIO_IRQ_MAX 8 194#define MCFGPIO_IRQ_MAX 8
195#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE 195#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
196 196
197/*
198 * Port Pin Assignment registers.
199 */
200#define MCFGPIO_PAR_AD (MCF_IPSBAR + 0x100040)
201#define MCFGPIO_PAR_BUSCTL (MCF_IPSBAR + 0x100042)
202#define MCFGPIO_PAR_BS (MCF_IPSBAR + 0x100044)
203#define MCFGPIO_PAR_CS (MCF_IPSBAR + 0x100045)
204#define MCFGPIO_PAR_SDRAM (MCF_IPSBAR + 0x100046)
205#define MCFGPIO_PAR_FECI2C (MCF_IPSBAR + 0x100047)
206#define MCFGPIO_PAR_UART (MCF_IPSBAR + 0x100048)
197#define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10004A) 207#define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10004A)
198#define MCFGPIO_PAR_TIMER (MCF_IPSBAR + 0x10004C) 208#define MCFGPIO_PAR_TIMER (MCF_IPSBAR + 0x10004C)
199#endif 209
210#define UART0_ENABLE_MASK 0x000f
211#define UART1_ENABLE_MASK 0x0ff0
212#define UART2_ENABLE_MASK 0x3000
213#endif /* CONFIG_M5271 */
200 214
201#ifdef CONFIG_M5275 215#ifdef CONFIG_M5275
202#define MCFGPIO_PODR_BUSCTL (MCF_IPSBAR + 0x100004) 216#define MCFGPIO_PODR_BUSCTL (MCF_IPSBAR + 0x100004)
@@ -279,18 +293,36 @@
279/* 293/*
280 * Generic GPIO support 294 * Generic GPIO support
281 */ 295 */
282#define MCFGPIO_PODR MCFGPIO_PODR_BUSCTL 296#define MCFGPIO_PODR MCFGPIO_PODR_BUSCTL
283#define MCFGPIO_PDDR MCFGPIO_PDDR_BUSCTL 297#define MCFGPIO_PDDR MCFGPIO_PDDR_BUSCTL
284#define MCFGPIO_PPDR MCFGPIO_PPDSDR_BUSCTL 298#define MCFGPIO_PPDR MCFGPIO_PPDSDR_BUSCTL
285#define MCFGPIO_SETR MCFGPIO_PPDSDR_BUSCTL 299#define MCFGPIO_SETR MCFGPIO_PPDSDR_BUSCTL
286#define MCFGPIO_CLRR MCFGPIO_PCLRR_BUSCTL 300#define MCFGPIO_CLRR MCFGPIO_PCLRR_BUSCTL
287 301
288#define MCFGPIO_PIN_MAX 148 302#define MCFGPIO_PIN_MAX 148
289#define MCFGPIO_IRQ_MAX 8 303#define MCFGPIO_IRQ_MAX 8
290#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE 304#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
291 305
306/*
307 * Port Pin Assignment registers.
308 */
309#define MCFGPIO_PAR_AD (MCF_IPSBAR + 0x100070)
310#define MCFGPIO_PAR_CS (MCF_IPSBAR + 0x100071)
311#define MCFGPIO_PAR_BUSCTL (MCF_IPSBAR + 0x100072)
312#define MCFGPIO_PAR_USB (MCF_IPSBAR + 0x100076)
313#define MCFGPIO_PAR_FEC0HL (MCF_IPSBAR + 0x100078)
314#define MCFGPIO_PAR_FEC1HL (MCF_IPSBAR + 0x100079)
315#define MCFGPIO_PAR_TIMER (MCF_IPSBAR + 0x10007A)
316#define MCFGPIO_PAR_UART (MCF_IPSBAR + 0x10007C)
292#define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10007E) 317#define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10007E)
293#endif 318#define MCFGPIO_PAR_SDRAM (MCF_IPSBAR + 0x100080)
319#define MCFGPIO_PAR_FECI2C (MCF_IPSBAR + 0x100082)
320#define MCFGPIO_PAR_BS (MCF_IPSBAR + 0x100084)
321
322#define UART0_ENABLE_MASK 0x000f
323#define UART1_ENABLE_MASK 0x00f0
324#define UART2_ENABLE_MASK 0x3f00
325#endif /* CONFIG_M5275 */
294 326
295/* 327/*
296 * PIT timer base addresses. 328 * PIT timer base addresses.
@@ -311,22 +343,6 @@
311#define MCFEPORT_EPFR (MCF_IPSBAR + 0x130006) 343#define MCFEPORT_EPFR (MCF_IPSBAR + 0x130006)
312 344
313/* 345/*
314 * GPIO pins setups to enable the UARTs.
315 */
316#ifdef CONFIG_M5271
317#define MCF_GPIO_PAR_UART 0x100048 /* PAR UART address */
318#define UART0_ENABLE_MASK 0x000f
319#define UART1_ENABLE_MASK 0x0ff0
320#define UART2_ENABLE_MASK 0x3000
321#endif
322#ifdef CONFIG_M5275
323#define MCF_GPIO_PAR_UART 0x10007c /* PAR UART address */
324#define UART0_ENABLE_MASK 0x000f
325#define UART1_ENABLE_MASK 0x00f0
326#define UART2_ENABLE_MASK 0x3f00
327#endif
328
329/*
330 * Reset Control Unit (relative to IPSBAR). 346 * Reset Control Unit (relative to IPSBAR).
331 */ 347 */
332#define MCF_RCR (MCF_IPSBAR + 0x110000) 348#define MCF_RCR (MCF_IPSBAR + 0x110000)
diff --git a/arch/m68k/include/asm/m528xsim.h b/arch/m68k/include/asm/m528xsim.h
index 4acb3c0a642e..cf68ca0ac3a5 100644
--- a/arch/m68k/include/asm/m528xsim.h
+++ b/arch/m68k/include/asm/m528xsim.h
@@ -233,23 +233,6 @@
233#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE 233#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
234#define MCFGPIO_PIN_MAX 180 234#define MCFGPIO_PIN_MAX 180
235 235
236
237/*
238 * Derek Cheung - 6 Feb 2005
239 * add I2C and QSPI register definition using Freescale's MCF5282
240 */
241/* set Port AS pin for I2C or UART */
242#define MCF5282_GPIO_PASPAR (volatile u16 *) (MCF_IPSBAR + 0x00100056)
243
244/* Port UA Pin Assignment Register (8 Bit) */
245#define MCF5282_GPIO_PUAPAR 0x10005C
246
247/* Interrupt Mask Register Register Low */
248#define MCF5282_INTC0_IMRL (volatile u32 *) (MCF_IPSBAR + 0x0C0C)
249/* Interrupt Control Register 7 */
250#define MCF5282_INTC0_ICR17 (volatile u8 *) (MCF_IPSBAR + 0x0C51)
251
252
253/* 236/*
254 * Reset Control Unit (relative to IPSBAR). 237 * Reset Control Unit (relative to IPSBAR).
255 */ 238 */
@@ -259,37 +242,5 @@
259#define MCF_RCR_SWRESET 0x80 /* Software reset bit */ 242#define MCF_RCR_SWRESET 0x80 /* Software reset bit */
260#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */ 243#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */
261 244
262/********************************************************************* 245/****************************************************************************/
263*
264* Inter-IC (I2C) Module
265*
266*********************************************************************/
267/* Read/Write access macros for general use */
268#define MCF5282_I2C_I2ADR (volatile u8 *) (MCF_IPSBAR + 0x0300) // Address
269#define MCF5282_I2C_I2FDR (volatile u8 *) (MCF_IPSBAR + 0x0304) // Freq Divider
270#define MCF5282_I2C_I2CR (volatile u8 *) (MCF_IPSBAR + 0x0308) // Control
271#define MCF5282_I2C_I2SR (volatile u8 *) (MCF_IPSBAR + 0x030C) // Status
272#define MCF5282_I2C_I2DR (volatile u8 *) (MCF_IPSBAR + 0x0310) // Data I/O
273
274/* Bit level definitions and macros */
275#define MCF5282_I2C_I2ADR_ADDR(x) (((x)&0x7F)<<0x01)
276
277#define MCF5282_I2C_I2FDR_IC(x) (((x)&0x3F))
278
279#define MCF5282_I2C_I2CR_IEN (0x80) // I2C enable
280#define MCF5282_I2C_I2CR_IIEN (0x40) // interrupt enable
281#define MCF5282_I2C_I2CR_MSTA (0x20) // master/slave mode
282#define MCF5282_I2C_I2CR_MTX (0x10) // transmit/receive mode
283#define MCF5282_I2C_I2CR_TXAK (0x08) // transmit acknowledge enable
284#define MCF5282_I2C_I2CR_RSTA (0x04) // repeat start
285
286#define MCF5282_I2C_I2SR_ICF (0x80) // data transfer bit
287#define MCF5282_I2C_I2SR_IAAS (0x40) // I2C addressed as a slave
288#define MCF5282_I2C_I2SR_IBB (0x20) // I2C bus busy
289#define MCF5282_I2C_I2SR_IAL (0x10) // aribitration lost
290#define MCF5282_I2C_I2SR_SRW (0x04) // slave read/write
291#define MCF5282_I2C_I2SR_IIF (0x02) // I2C interrupt
292#define MCF5282_I2C_I2SR_RXAK (0x01) // received acknowledge
293
294
295#endif /* m528xsim_h */ 246#endif /* m528xsim_h */
diff --git a/arch/m68k/include/asm/m5307sim.h b/arch/m68k/include/asm/m5307sim.h
index 3bc3adaa7ee0..5d0bb7ec31f8 100644
--- a/arch/m68k/include/asm/m5307sim.h
+++ b/arch/m68k/include/asm/m5307sim.h
@@ -23,71 +23,71 @@
23/* 23/*
24 * Define the 5307 SIM register set addresses. 24 * Define the 5307 SIM register set addresses.
25 */ 25 */
26#define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */ 26#define MCFSIM_RSR (MCF_MBAR + 0x00) /* Reset Status reg */
27#define MCFSIM_SYPCR 0x01 /* System Protection reg (r/w)*/ 27#define MCFSIM_SYPCR (MCF_MBAR + 0x01) /* System Protection */
28#define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */ 28#define MCFSIM_SWIVR (MCF_MBAR + 0x02) /* SW Watchdog intr */
29#define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */ 29#define MCFSIM_SWSR (MCF_MBAR + 0x03) /* SW Watchdog service*/
30#define MCFSIM_PAR 0x04 /* Pin Assignment reg (r/w) */ 30#define MCFSIM_PAR (MCF_MBAR + 0x04) /* Pin Assignment */
31#define MCFSIM_IRQPAR 0x06 /* Interrupt Assignment reg (r/w) */ 31#define MCFSIM_IRQPAR (MCF_MBAR + 0x06) /* Itr Assignment */
32#define MCFSIM_PLLCR 0x08 /* PLL Control Reg*/ 32#define MCFSIM_PLLCR (MCF_MBAR + 0x08) /* PLL Ctrl Reg */
33#define MCFSIM_MPARK 0x0C /* BUS Master Control Reg*/ 33#define MCFSIM_MPARK (MCF_MBAR + 0x0C) /* BUS Master Ctrl */
34#define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */ 34#define MCFSIM_IPR (MCF_MBAR + 0x40) /* Interrupt Pend */
35#define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */ 35#define MCFSIM_IMR (MCF_MBAR + 0x44) /* Interrupt Mask */
36#define MCFSIM_AVR 0x4b /* Autovector Ctrl reg (r/w) */ 36#define MCFSIM_AVR (MCF_MBAR + 0x4b) /* Autovector Ctrl */
37#define MCFSIM_ICR0 0x4c /* Intr Ctrl reg 0 (r/w) */ 37#define MCFSIM_ICR0 (MCF_MBAR + 0x4c) /* Intr Ctrl reg 0 */
38#define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */ 38#define MCFSIM_ICR1 (MCF_MBAR + 0x4d) /* Intr Ctrl reg 1 */
39#define MCFSIM_ICR2 0x4e /* Intr Ctrl reg 2 (r/w) */ 39#define MCFSIM_ICR2 (MCF_MBAR + 0x4e) /* Intr Ctrl reg 2 */
40#define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */ 40#define MCFSIM_ICR3 (MCF_MBAR + 0x4f) /* Intr Ctrl reg 3 */
41#define MCFSIM_ICR4 0x50 /* Intr Ctrl reg 4 (r/w) */ 41#define MCFSIM_ICR4 (MCF_MBAR + 0x50) /* Intr Ctrl reg 4 */
42#define MCFSIM_ICR5 0x51 /* Intr Ctrl reg 5 (r/w) */ 42#define MCFSIM_ICR5 (MCF_MBAR + 0x51) /* Intr Ctrl reg 5 */
43#define MCFSIM_ICR6 0x52 /* Intr Ctrl reg 6 (r/w) */ 43#define MCFSIM_ICR6 (MCF_MBAR + 0x52) /* Intr Ctrl reg 6 */
44#define MCFSIM_ICR7 0x53 /* Intr Ctrl reg 7 (r/w) */ 44#define MCFSIM_ICR7 (MCF_MBAR + 0x53) /* Intr Ctrl reg 7 */
45#define MCFSIM_ICR8 0x54 /* Intr Ctrl reg 8 (r/w) */ 45#define MCFSIM_ICR8 (MCF_MBAR + 0x54) /* Intr Ctrl reg 8 */
46#define MCFSIM_ICR9 0x55 /* Intr Ctrl reg 9 (r/w) */ 46#define MCFSIM_ICR9 (MCF_MBAR + 0x55) /* Intr Ctrl reg 9 */
47#define MCFSIM_ICR10 0x56 /* Intr Ctrl reg 10 (r/w) */ 47#define MCFSIM_ICR10 (MCF_MBAR + 0x56) /* Intr Ctrl reg 10 */
48#define MCFSIM_ICR11 0x57 /* Intr Ctrl reg 11 (r/w) */ 48#define MCFSIM_ICR11 (MCF_MBAR + 0x57) /* Intr Ctrl reg 11 */
49 49
50#define MCFSIM_CSAR0 0x80 /* CS 0 Address 0 reg (r/w) */ 50#define MCFSIM_CSAR0 (MCF_MBAR + 0x80) /* CS 0 Address reg */
51#define MCFSIM_CSMR0 0x84 /* CS 0 Mask 0 reg (r/w) */ 51#define MCFSIM_CSMR0 (MCF_MBAR + 0x84) /* CS 0 Mask reg */
52#define MCFSIM_CSCR0 0x8a /* CS 0 Control reg (r/w) */ 52#define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */
53#define MCFSIM_CSAR1 0x8c /* CS 1 Address reg (r/w) */ 53#define MCFSIM_CSAR1 (MCF_MBAR + 0x8c) /* CS 1 Address reg */
54#define MCFSIM_CSMR1 0x90 /* CS 1 Mask reg (r/w) */ 54#define MCFSIM_CSMR1 (MCF_MBAR + 0x90) /* CS 1 Mask reg */
55#define MCFSIM_CSCR1 0x96 /* CS 1 Control reg (r/w) */ 55#define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */
56 56
57#ifdef CONFIG_OLDMASK 57#ifdef CONFIG_OLDMASK
58#define MCFSIM_CSBAR 0x98 /* CS Base Address reg (r/w) */ 58#define MCFSIM_CSBAR (MCF_MBAR + 0x98) /* CS Base Address */
59#define MCFSIM_CSBAMR 0x9c /* CS Base Mask reg (r/w) */ 59#define MCFSIM_CSBAMR (MCF_MBAR + 0x9c) /* CS Base Mask */
60#define MCFSIM_CSMR2 0x9e /* CS 2 Mask reg (r/w) */ 60#define MCFSIM_CSMR2 (MCF_MBAR + 0x9e) /* CS 2 Mask reg */
61#define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */ 61#define MCFSIM_CSCR2 (MCF_MBAR + 0xa2) /* CS 2 Control reg */
62#define MCFSIM_CSMR3 0xaa /* CS 3 Mask reg (r/w) */ 62#define MCFSIM_CSMR3 (MCF_MBAR + 0xaa) /* CS 3 Mask reg */
63#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */ 63#define MCFSIM_CSCR3 (MCF_MBAR + 0xae) /* CS 3 Control reg */
64#define MCFSIM_CSMR4 0xb6 /* CS 4 Mask reg (r/w) */ 64#define MCFSIM_CSMR4 (MCF_MBAR + 0xb6) /* CS 4 Mask reg */
65#define MCFSIM_CSCR4 0xba /* CS 4 Control reg (r/w) */ 65#define MCFSIM_CSCR4 (MCF_MBAR + 0xba) /* CS 4 Control reg */
66#define MCFSIM_CSMR5 0xc2 /* CS 5 Mask reg (r/w) */ 66#define MCFSIM_CSMR5 (MCF_MBAR + 0xc2) /* CS 5 Mask reg */
67#define MCFSIM_CSCR5 0xc6 /* CS 5 Control reg (r/w) */ 67#define MCFSIM_CSCR5 (MCF_MBAR + 0xc6) /* CS 5 Control reg */
68#define MCFSIM_CSMR6 0xce /* CS 6 Mask reg (r/w) */ 68#define MCFSIM_CSMR6 (MCF_MBAR + 0xce) /* CS 6 Mask reg */
69#define MCFSIM_CSCR6 0xd2 /* CS 6 Control reg (r/w) */ 69#define MCFSIM_CSCR6 (MCF_MBAR + 0xd2) /* CS 6 Control reg */
70#define MCFSIM_CSMR7 0xda /* CS 7 Mask reg (r/w) */ 70#define MCFSIM_CSMR7 (MCF_MBAR + 0xda) /* CS 7 Mask reg */
71#define MCFSIM_CSCR7 0xde /* CS 7 Control reg (r/w) */ 71#define MCFSIM_CSCR7 (MCF_MBAR + 0xde) /* CS 7 Control reg */
72#else 72#else
73#define MCFSIM_CSAR2 0x98 /* CS 2 Address reg (r/w) */ 73#define MCFSIM_CSAR2 (MCF_MBAR + 0x98) /* CS 2 Address reg */
74#define MCFSIM_CSMR2 0x9c /* CS 2 Mask reg (r/w) */ 74#define MCFSIM_CSMR2 (MCF_MBAR + 0x9c) /* CS 2 Mask reg */
75#define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */ 75#define MCFSIM_CSCR2 (MCF_MBAR + 0xa2) /* CS 2 Control reg */
76#define MCFSIM_CSAR3 0xa4 /* CS 3 Address reg (r/w) */ 76#define MCFSIM_CSAR3 (MCF_MBAR + 0xa4) /* CS 3 Address reg */
77#define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */ 77#define MCFSIM_CSMR3 (MCF_MBAR + 0xa8) /* CS 3 Mask reg */
78#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */ 78#define MCFSIM_CSCR3 (MCF_MBAR + 0xae) /* CS 3 Control reg */
79#define MCFSIM_CSAR4 0xb0 /* CS 4 Address reg (r/w) */ 79#define MCFSIM_CSAR4 (MCF_MBAR + 0xb0) /* CS 4 Address reg */
80#define MCFSIM_CSMR4 0xb4 /* CS 4 Mask reg (r/w) */ 80#define MCFSIM_CSMR4 (MCF_MBAR + 0xb4) /* CS 4 Mask reg */
81#define MCFSIM_CSCR4 0xba /* CS 4 Control reg (r/w) */ 81#define MCFSIM_CSCR4 (MCF_MBAR + 0xba) /* CS 4 Control reg */
82#define MCFSIM_CSAR5 0xbc /* CS 5 Address reg (r/w) */ 82#define MCFSIM_CSAR5 (MCF_MBAR + 0xbc) /* CS 5 Address reg */
83#define MCFSIM_CSMR5 0xc0 /* CS 5 Mask reg (r/w) */ 83#define MCFSIM_CSMR5 (MCF_MBAR + 0xc0) /* CS 5 Mask reg */
84#define MCFSIM_CSCR5 0xc6 /* CS 5 Control reg (r/w) */ 84#define MCFSIM_CSCR5 (MCF_MBAR + 0xc6) /* CS 5 Control reg */
85#define MCFSIM_CSAR6 0xc8 /* CS 6 Address reg (r/w) */ 85#define MCFSIM_CSAR6 (MCF_MBAR + 0xc8) /* CS 6 Address reg */
86#define MCFSIM_CSMR6 0xcc /* CS 6 Mask reg (r/w) */ 86#define MCFSIM_CSMR6 (MCF_MBAR + 0xcc) /* CS 6 Mask reg */
87#define MCFSIM_CSCR6 0xd2 /* CS 6 Control reg (r/w) */ 87#define MCFSIM_CSCR6 (MCF_MBAR + 0xd2) /* CS 6 Control reg */
88#define MCFSIM_CSAR7 0xd4 /* CS 7 Address reg (r/w) */ 88#define MCFSIM_CSAR7 (MCF_MBAR + 0xd4) /* CS 7 Address reg */
89#define MCFSIM_CSMR7 0xd8 /* CS 7 Mask reg (r/w) */ 89#define MCFSIM_CSMR7 (MCF_MBAR + 0xd8) /* CS 7 Mask reg */
90#define MCFSIM_CSCR7 0xde /* CS 7 Control reg (r/w) */ 90#define MCFSIM_CSCR7 (MCF_MBAR + 0xde) /* CS 7 Control reg */
91#endif /* CONFIG_OLDMASK */ 91#endif /* CONFIG_OLDMASK */
92 92
93#define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */ 93#define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */
@@ -127,9 +127,9 @@
127/* 127/*
128 * Generic GPIO support 128 * Generic GPIO support
129 */ 129 */
130#define MCFGPIO_PIN_MAX 16 130#define MCFGPIO_PIN_MAX 16
131#define MCFGPIO_IRQ_MAX -1 131#define MCFGPIO_IRQ_MAX -1
132#define MCFGPIO_IRQ_VECBASE -1 132#define MCFGPIO_IRQ_VECBASE -1
133 133
134 134
135/* Definition offset address for CS2-7 -- old mask 5307 */ 135/* Definition offset address for CS2-7 -- old mask 5307 */
@@ -167,9 +167,9 @@
167/* 167/*
168 * Defines for the IRQPAR Register 168 * Defines for the IRQPAR Register
169 */ 169 */
170#define IRQ5_LEVEL4 0x80 170#define IRQ5_LEVEL4 0x80
171#define IRQ3_LEVEL6 0x40 171#define IRQ3_LEVEL6 0x40
172#define IRQ1_LEVEL2 0x20 172#define IRQ1_LEVEL2 0x20
173 173
174/* 174/*
175 * Define system peripheral IRQ usage. 175 * Define system peripheral IRQ usage.
diff --git a/arch/m68k/include/asm/m532xsim.h b/arch/m68k/include/asm/m532xsim.h
index 5ca7b298c6eb..8668e47ced0e 100644
--- a/arch/m68k/include/asm/m532xsim.h
+++ b/arch/m68k/include/asm/m532xsim.h
@@ -15,10 +15,6 @@
15 15
16#include <asm/m53xxacr.h> 16#include <asm/m53xxacr.h>
17 17
18#define MCF_REG32(x) (*(volatile unsigned long *)(x))
19#define MCF_REG16(x) (*(volatile unsigned short *)(x))
20#define MCF_REG08(x) (*(volatile unsigned char *)(x))
21
22#define MCFINT_VECBASE 64 18#define MCFINT_VECBASE 64
23#define MCFINT_UART0 26 /* Interrupt number for UART0 */ 19#define MCFINT_UART0 26 /* Interrupt number for UART0 */
24#define MCFINT_UART1 27 /* Interrupt number for UART1 */ 20#define MCFINT_UART1 27 /* Interrupt number for UART1 */
@@ -38,7 +34,7 @@
38 34
39#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI) 35#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
40 36
41#define MCF_WTM_WCR MCF_REG16(0xFC098000) 37#define MCF_WTM_WCR 0xFC098000
42 38
43/* 39/*
44 * Define the 532x SIM register set addresses. 40 * Define the 532x SIM register set addresses.
@@ -152,42 +148,6 @@
152#define MCFPM_PPMHR1 0xfc040038 148#define MCFPM_PPMHR1 0xfc040038
153#define MCFPM_LPCR 0xec090007 149#define MCFPM_LPCR 0xec090007
154 150
155/*********************************************************************
156 *
157 * Inter-IC (I2C) Module
158 *
159 *********************************************************************/
160
161/* Read/Write access macros for general use */
162#define MCF532x_I2C_I2ADR (volatile u8 *) (0xFC058000) // Address
163#define MCF532x_I2C_I2FDR (volatile u8 *) (0xFC058004) // Freq Divider
164#define MCF532x_I2C_I2CR (volatile u8 *) (0xFC058008) // Control
165#define MCF532x_I2C_I2SR (volatile u8 *) (0xFC05800C) // Status
166#define MCF532x_I2C_I2DR (volatile u8 *) (0xFC058010) // Data I/O
167
168/* Bit level definitions and macros */
169#define MCF532x_I2C_I2ADR_ADDR(x) (((x)&0x7F)<<0x01)
170
171#define MCF532x_I2C_I2FDR_IC(x) (((x)&0x3F))
172
173#define MCF532x_I2C_I2CR_IEN (0x80) // I2C enable
174#define MCF532x_I2C_I2CR_IIEN (0x40) // interrupt enable
175#define MCF532x_I2C_I2CR_MSTA (0x20) // master/slave mode
176#define MCF532x_I2C_I2CR_MTX (0x10) // transmit/receive mode
177#define MCF532x_I2C_I2CR_TXAK (0x08) // transmit acknowledge enable
178#define MCF532x_I2C_I2CR_RSTA (0x04) // repeat start
179
180#define MCF532x_I2C_I2SR_ICF (0x80) // data transfer bit
181#define MCF532x_I2C_I2SR_IAAS (0x40) // I2C addressed as a slave
182#define MCF532x_I2C_I2SR_IBB (0x20) // I2C bus busy
183#define MCF532x_I2C_I2SR_IAL (0x10) // aribitration lost
184#define MCF532x_I2C_I2SR_SRW (0x04) // slave read/write
185#define MCF532x_I2C_I2SR_IIF (0x02) // I2C interrupt
186#define MCF532x_I2C_I2SR_RXAK (0x01) // received acknowledge
187
188#define MCF532x_PAR_FECI2C (volatile u8 *) (0xFC0A4053)
189
190
191/* 151/*
192 * The M5329EVB board needs a help getting its devices initialized 152 * The M5329EVB board needs a help getting its devices initialized
193 * at kernel start time if dBUG doesn't set it up (for example 153 * at kernel start time if dBUG doesn't set it up (for example
@@ -217,13 +177,13 @@
217 *********************************************************************/ 177 *********************************************************************/
218 178
219/* Register read/write macros */ 179/* Register read/write macros */
220#define MCF_CCM_CCR MCF_REG16(0xFC0A0004) 180#define MCF_CCM_CCR 0xFC0A0004
221#define MCF_CCM_RCON MCF_REG16(0xFC0A0008) 181#define MCF_CCM_RCON 0xFC0A0008
222#define MCF_CCM_CIR MCF_REG16(0xFC0A000A) 182#define MCF_CCM_CIR 0xFC0A000A
223#define MCF_CCM_MISCCR MCF_REG16(0xFC0A0010) 183#define MCF_CCM_MISCCR 0xFC0A0010
224#define MCF_CCM_CDR MCF_REG16(0xFC0A0012) 184#define MCF_CCM_CDR 0xFC0A0012
225#define MCF_CCM_UHCSR MCF_REG16(0xFC0A0014) 185#define MCF_CCM_UHCSR 0xFC0A0014
226#define MCF_CCM_UOCSR MCF_REG16(0xFC0A0016) 186#define MCF_CCM_UOCSR 0xFC0A0016
227 187
228/* Bit definitions and macros for MCF_CCM_CCR */ 188/* Bit definitions and macros for MCF_CCM_CCR */
229#define MCF_CCM_CCR_RESERVED (0x0001) 189#define MCF_CCM_CCR_RESERVED (0x0001)
@@ -287,104 +247,29 @@
287 247
288/********************************************************************* 248/*********************************************************************
289 * 249 *
290 * DMA Timers (DTIM)
291 *
292 *********************************************************************/
293
294/* Register read/write macros */
295#define MCF_DTIM0_DTMR MCF_REG16(0xFC070000)
296#define MCF_DTIM0_DTXMR MCF_REG08(0xFC070002)
297#define MCF_DTIM0_DTER MCF_REG08(0xFC070003)
298#define MCF_DTIM0_DTRR MCF_REG32(0xFC070004)
299#define MCF_DTIM0_DTCR MCF_REG32(0xFC070008)
300#define MCF_DTIM0_DTCN MCF_REG32(0xFC07000C)
301#define MCF_DTIM1_DTMR MCF_REG16(0xFC074000)
302#define MCF_DTIM1_DTXMR MCF_REG08(0xFC074002)
303#define MCF_DTIM1_DTER MCF_REG08(0xFC074003)
304#define MCF_DTIM1_DTRR MCF_REG32(0xFC074004)
305#define MCF_DTIM1_DTCR MCF_REG32(0xFC074008)
306#define MCF_DTIM1_DTCN MCF_REG32(0xFC07400C)
307#define MCF_DTIM2_DTMR MCF_REG16(0xFC078000)
308#define MCF_DTIM2_DTXMR MCF_REG08(0xFC078002)
309#define MCF_DTIM2_DTER MCF_REG08(0xFC078003)
310#define MCF_DTIM2_DTRR MCF_REG32(0xFC078004)
311#define MCF_DTIM2_DTCR MCF_REG32(0xFC078008)
312#define MCF_DTIM2_DTCN MCF_REG32(0xFC07800C)
313#define MCF_DTIM3_DTMR MCF_REG16(0xFC07C000)
314#define MCF_DTIM3_DTXMR MCF_REG08(0xFC07C002)
315#define MCF_DTIM3_DTER MCF_REG08(0xFC07C003)
316#define MCF_DTIM3_DTRR MCF_REG32(0xFC07C004)
317#define MCF_DTIM3_DTCR MCF_REG32(0xFC07C008)
318#define MCF_DTIM3_DTCN MCF_REG32(0xFC07C00C)
319#define MCF_DTIM_DTMR(x) MCF_REG16(0xFC070000+((x)*0x4000))
320#define MCF_DTIM_DTXMR(x) MCF_REG08(0xFC070002+((x)*0x4000))
321#define MCF_DTIM_DTER(x) MCF_REG08(0xFC070003+((x)*0x4000))
322#define MCF_DTIM_DTRR(x) MCF_REG32(0xFC070004+((x)*0x4000))
323#define MCF_DTIM_DTCR(x) MCF_REG32(0xFC070008+((x)*0x4000))
324#define MCF_DTIM_DTCN(x) MCF_REG32(0xFC07000C+((x)*0x4000))
325
326/* Bit definitions and macros for MCF_DTIM_DTMR */
327#define MCF_DTIM_DTMR_RST (0x0001)
328#define MCF_DTIM_DTMR_CLK(x) (((x)&0x0003)<<1)
329#define MCF_DTIM_DTMR_FRR (0x0008)
330#define MCF_DTIM_DTMR_ORRI (0x0010)
331#define MCF_DTIM_DTMR_OM (0x0020)
332#define MCF_DTIM_DTMR_CE(x) (((x)&0x0003)<<6)
333#define MCF_DTIM_DTMR_PS(x) (((x)&0x00FF)<<8)
334#define MCF_DTIM_DTMR_CE_ANY (0x00C0)
335#define MCF_DTIM_DTMR_CE_FALL (0x0080)
336#define MCF_DTIM_DTMR_CE_RISE (0x0040)
337#define MCF_DTIM_DTMR_CE_NONE (0x0000)
338#define MCF_DTIM_DTMR_CLK_DTIN (0x0006)
339#define MCF_DTIM_DTMR_CLK_DIV16 (0x0004)
340#define MCF_DTIM_DTMR_CLK_DIV1 (0x0002)
341#define MCF_DTIM_DTMR_CLK_STOP (0x0000)
342
343/* Bit definitions and macros for MCF_DTIM_DTXMR */
344#define MCF_DTIM_DTXMR_MODE16 (0x01)
345#define MCF_DTIM_DTXMR_DMAEN (0x80)
346
347/* Bit definitions and macros for MCF_DTIM_DTER */
348#define MCF_DTIM_DTER_CAP (0x01)
349#define MCF_DTIM_DTER_REF (0x02)
350
351/* Bit definitions and macros for MCF_DTIM_DTRR */
352#define MCF_DTIM_DTRR_REF(x) (((x)&0xFFFFFFFF)<<0)
353
354/* Bit definitions and macros for MCF_DTIM_DTCR */
355#define MCF_DTIM_DTCR_CAP(x) (((x)&0xFFFFFFFF)<<0)
356
357/* Bit definitions and macros for MCF_DTIM_DTCN */
358#define MCF_DTIM_DTCN_CNT(x) (((x)&0xFFFFFFFF)<<0)
359
360/*********************************************************************
361 *
362 * FlexBus Chip Selects (FBCS) 250 * FlexBus Chip Selects (FBCS)
363 * 251 *
364 *********************************************************************/ 252 *********************************************************************/
365 253
366/* Register read/write macros */ 254/* Register read/write macros */
367#define MCF_FBCS0_CSAR MCF_REG32(0xFC008000) 255#define MCF_FBCS0_CSAR 0xFC008000
368#define MCF_FBCS0_CSMR MCF_REG32(0xFC008004) 256#define MCF_FBCS0_CSMR 0xFC008004
369#define MCF_FBCS0_CSCR MCF_REG32(0xFC008008) 257#define MCF_FBCS0_CSCR 0xFC008008
370#define MCF_FBCS1_CSAR MCF_REG32(0xFC00800C) 258#define MCF_FBCS1_CSAR 0xFC00800C
371#define MCF_FBCS1_CSMR MCF_REG32(0xFC008010) 259#define MCF_FBCS1_CSMR 0xFC008010
372#define MCF_FBCS1_CSCR MCF_REG32(0xFC008014) 260#define MCF_FBCS1_CSCR 0xFC008014
373#define MCF_FBCS2_CSAR MCF_REG32(0xFC008018) 261#define MCF_FBCS2_CSAR 0xFC008018
374#define MCF_FBCS2_CSMR MCF_REG32(0xFC00801C) 262#define MCF_FBCS2_CSMR 0xFC00801C
375#define MCF_FBCS2_CSCR MCF_REG32(0xFC008020) 263#define MCF_FBCS2_CSCR 0xFC008020
376#define MCF_FBCS3_CSAR MCF_REG32(0xFC008024) 264#define MCF_FBCS3_CSAR 0xFC008024
377#define MCF_FBCS3_CSMR MCF_REG32(0xFC008028) 265#define MCF_FBCS3_CSMR 0xFC008028
378#define MCF_FBCS3_CSCR MCF_REG32(0xFC00802C) 266#define MCF_FBCS3_CSCR 0xFC00802C
379#define MCF_FBCS4_CSAR MCF_REG32(0xFC008030) 267#define MCF_FBCS4_CSAR 0xFC008030
380#define MCF_FBCS4_CSMR MCF_REG32(0xFC008034) 268#define MCF_FBCS4_CSMR 0xFC008034
381#define MCF_FBCS4_CSCR MCF_REG32(0xFC008038) 269#define MCF_FBCS4_CSCR 0xFC008038
382#define MCF_FBCS5_CSAR MCF_REG32(0xFC00803C) 270#define MCF_FBCS5_CSAR 0xFC00803C
383#define MCF_FBCS5_CSMR MCF_REG32(0xFC008040) 271#define MCF_FBCS5_CSMR 0xFC008040
384#define MCF_FBCS5_CSCR MCF_REG32(0xFC008044) 272#define MCF_FBCS5_CSCR 0xFC008044
385#define MCF_FBCS_CSAR(x) MCF_REG32(0xFC008000+((x)*0x00C))
386#define MCF_FBCS_CSMR(x) MCF_REG32(0xFC008004+((x)*0x00C))
387#define MCF_FBCS_CSCR(x) MCF_REG32(0xFC008008+((x)*0x00C))
388 273
389/* Bit definitions and macros for MCF_FBCS_CSAR */ 274/* Bit definitions and macros for MCF_FBCS_CSAR */
390#define MCF_FBCS_CSAR_BA(x) ((x)&0xFFFF0000) 275#define MCF_FBCS_CSAR_BA(x) ((x)&0xFFFF0000)
@@ -501,32 +386,32 @@
501#define MCFGPIO_PCLRR_LCDDATAL (0xFC0A404B) 386#define MCFGPIO_PCLRR_LCDDATAL (0xFC0A404B)
502#define MCFGPIO_PCLRR_LCDCTLH (0xFC0A404C) 387#define MCFGPIO_PCLRR_LCDCTLH (0xFC0A404C)
503#define MCFGPIO_PCLRR_LCDCTLL (0xFC0A404D) 388#define MCFGPIO_PCLRR_LCDCTLL (0xFC0A404D)
504#define MCF_GPIO_PAR_FEC MCF_REG08(0xFC0A4050) 389#define MCFGPIO_PAR_FEC (0xFC0A4050)
505#define MCF_GPIO_PAR_PWM MCF_REG08(0xFC0A4051) 390#define MCFGPIO_PAR_PWM (0xFC0A4051)
506#define MCF_GPIO_PAR_BUSCTL MCF_REG08(0xFC0A4052) 391#define MCFGPIO_PAR_BUSCTL (0xFC0A4052)
507#define MCF_GPIO_PAR_FECI2C MCF_REG08(0xFC0A4053) 392#define MCFGPIO_PAR_FECI2C (0xFC0A4053)
508#define MCF_GPIO_PAR_BE MCF_REG08(0xFC0A4054) 393#define MCFGPIO_PAR_BE (0xFC0A4054)
509#define MCF_GPIO_PAR_CS MCF_REG08(0xFC0A4055) 394#define MCFGPIO_PAR_CS (0xFC0A4055)
510#define MCF_GPIO_PAR_SSI MCF_REG16(0xFC0A4056) 395#define MCFGPIO_PAR_SSI (0xFC0A4056)
511#define MCF_GPIO_PAR_UART MCF_REG16(0xFC0A4058) 396#define MCFGPIO_PAR_UART (0xFC0A4058)
512#define MCF_GPIO_PAR_QSPI MCF_REG16(0xFC0A405A) 397#define MCFGPIO_PAR_QSPI (0xFC0A405A)
513#define MCF_GPIO_PAR_TIMER MCF_REG08(0xFC0A405C) 398#define MCFGPIO_PAR_TIMER (0xFC0A405C)
514#define MCF_GPIO_PAR_LCDDATA MCF_REG08(0xFC0A405D) 399#define MCFGPIO_PAR_LCDDATA (0xFC0A405D)
515#define MCF_GPIO_PAR_LCDCTL MCF_REG16(0xFC0A405E) 400#define MCFGPIO_PAR_LCDCTL (0xFC0A405E)
516#define MCF_GPIO_PAR_IRQ MCF_REG16(0xFC0A4060) 401#define MCFGPIO_PAR_IRQ (0xFC0A4060)
517#define MCF_GPIO_MSCR_FLEXBUS MCF_REG08(0xFC0A4064) 402#define MCFGPIO_MSCR_FLEXBUS (0xFC0A4064)
518#define MCF_GPIO_MSCR_SDRAM MCF_REG08(0xFC0A4065) 403#define MCFGPIO_MSCR_SDRAM (0xFC0A4065)
519#define MCF_GPIO_DSCR_I2C MCF_REG08(0xFC0A4068) 404#define MCFGPIO_DSCR_I2C (0xFC0A4068)
520#define MCF_GPIO_DSCR_PWM MCF_REG08(0xFC0A4069) 405#define MCFGPIO_DSCR_PWM (0xFC0A4069)
521#define MCF_GPIO_DSCR_FEC MCF_REG08(0xFC0A406A) 406#define MCFGPIO_DSCR_FEC (0xFC0A406A)
522#define MCF_GPIO_DSCR_UART MCF_REG08(0xFC0A406B) 407#define MCFGPIO_DSCR_UART (0xFC0A406B)
523#define MCF_GPIO_DSCR_QSPI MCF_REG08(0xFC0A406C) 408#define MCFGPIO_DSCR_QSPI (0xFC0A406C)
524#define MCF_GPIO_DSCR_TIMER MCF_REG08(0xFC0A406D) 409#define MCFGPIO_DSCR_TIMER (0xFC0A406D)
525#define MCF_GPIO_DSCR_SSI MCF_REG08(0xFC0A406E) 410#define MCFGPIO_DSCR_SSI (0xFC0A406E)
526#define MCF_GPIO_DSCR_LCD MCF_REG08(0xFC0A406F) 411#define MCFGPIO_DSCR_LCD (0xFC0A406F)
527#define MCF_GPIO_DSCR_DEBUG MCF_REG08(0xFC0A4070) 412#define MCFGPIO_DSCR_DEBUG (0xFC0A4070)
528#define MCF_GPIO_DSCR_CLKRST MCF_REG08(0xFC0A4071) 413#define MCFGPIO_DSCR_CLKRST (0xFC0A4071)
529#define MCF_GPIO_DSCR_IRQ MCF_REG08(0xFC0A4072) 414#define MCFGPIO_DSCR_IRQ (0xFC0A4072)
530 415
531/* Bit definitions and macros for MCF_GPIO_PODR_FECH */ 416/* Bit definitions and macros for MCF_GPIO_PODR_FECH */
532#define MCF_GPIO_PODR_FECH_PODR_FECH0 (0x01) 417#define MCF_GPIO_PODR_FECH_PODR_FECH0 (0x01)
@@ -1215,709 +1100,6 @@
1215#define MCFGPIO_IRQ_MAX 8 1100#define MCFGPIO_IRQ_MAX 8
1216#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE 1101#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
1217 1102
1218
1219/*********************************************************************
1220 *
1221 * Interrupt Controller (INTC)
1222 *
1223 *********************************************************************/
1224
1225/* Register read/write macros */
1226#define MCF_INTC0_IPRH MCF_REG32(0xFC048000)
1227#define MCF_INTC0_IPRL MCF_REG32(0xFC048004)
1228#define MCF_INTC0_IMRH MCF_REG32(0xFC048008)
1229#define MCF_INTC0_IMRL MCF_REG32(0xFC04800C)
1230#define MCF_INTC0_INTFRCH MCF_REG32(0xFC048010)
1231#define MCF_INTC0_INTFRCL MCF_REG32(0xFC048014)
1232#define MCF_INTC0_ICONFIG MCF_REG16(0xFC04801A)
1233#define MCF_INTC0_SIMR MCF_REG08(0xFC04801C)
1234#define MCF_INTC0_CIMR MCF_REG08(0xFC04801D)
1235#define MCF_INTC0_CLMASK MCF_REG08(0xFC04801E)
1236#define MCF_INTC0_SLMASK MCF_REG08(0xFC04801F)
1237#define MCF_INTC0_ICR0 MCF_REG08(0xFC048040)
1238#define MCF_INTC0_ICR1 MCF_REG08(0xFC048041)
1239#define MCF_INTC0_ICR2 MCF_REG08(0xFC048042)
1240#define MCF_INTC0_ICR3 MCF_REG08(0xFC048043)
1241#define MCF_INTC0_ICR4 MCF_REG08(0xFC048044)
1242#define MCF_INTC0_ICR5 MCF_REG08(0xFC048045)
1243#define MCF_INTC0_ICR6 MCF_REG08(0xFC048046)
1244#define MCF_INTC0_ICR7 MCF_REG08(0xFC048047)
1245#define MCF_INTC0_ICR8 MCF_REG08(0xFC048048)
1246#define MCF_INTC0_ICR9 MCF_REG08(0xFC048049)
1247#define MCF_INTC0_ICR10 MCF_REG08(0xFC04804A)
1248#define MCF_INTC0_ICR11 MCF_REG08(0xFC04804B)
1249#define MCF_INTC0_ICR12 MCF_REG08(0xFC04804C)
1250#define MCF_INTC0_ICR13 MCF_REG08(0xFC04804D)
1251#define MCF_INTC0_ICR14 MCF_REG08(0xFC04804E)
1252#define MCF_INTC0_ICR15 MCF_REG08(0xFC04804F)
1253#define MCF_INTC0_ICR16 MCF_REG08(0xFC048050)
1254#define MCF_INTC0_ICR17 MCF_REG08(0xFC048051)
1255#define MCF_INTC0_ICR18 MCF_REG08(0xFC048052)
1256#define MCF_INTC0_ICR19 MCF_REG08(0xFC048053)
1257#define MCF_INTC0_ICR20 MCF_REG08(0xFC048054)
1258#define MCF_INTC0_ICR21 MCF_REG08(0xFC048055)
1259#define MCF_INTC0_ICR22 MCF_REG08(0xFC048056)
1260#define MCF_INTC0_ICR23 MCF_REG08(0xFC048057)
1261#define MCF_INTC0_ICR24 MCF_REG08(0xFC048058)
1262#define MCF_INTC0_ICR25 MCF_REG08(0xFC048059)
1263#define MCF_INTC0_ICR26 MCF_REG08(0xFC04805A)
1264#define MCF_INTC0_ICR27 MCF_REG08(0xFC04805B)
1265#define MCF_INTC0_ICR28 MCF_REG08(0xFC04805C)
1266#define MCF_INTC0_ICR29 MCF_REG08(0xFC04805D)
1267#define MCF_INTC0_ICR30 MCF_REG08(0xFC04805E)
1268#define MCF_INTC0_ICR31 MCF_REG08(0xFC04805F)
1269#define MCF_INTC0_ICR32 MCF_REG08(0xFC048060)
1270#define MCF_INTC0_ICR33 MCF_REG08(0xFC048061)
1271#define MCF_INTC0_ICR34 MCF_REG08(0xFC048062)
1272#define MCF_INTC0_ICR35 MCF_REG08(0xFC048063)
1273#define MCF_INTC0_ICR36 MCF_REG08(0xFC048064)
1274#define MCF_INTC0_ICR37 MCF_REG08(0xFC048065)
1275#define MCF_INTC0_ICR38 MCF_REG08(0xFC048066)
1276#define MCF_INTC0_ICR39 MCF_REG08(0xFC048067)
1277#define MCF_INTC0_ICR40 MCF_REG08(0xFC048068)
1278#define MCF_INTC0_ICR41 MCF_REG08(0xFC048069)
1279#define MCF_INTC0_ICR42 MCF_REG08(0xFC04806A)
1280#define MCF_INTC0_ICR43 MCF_REG08(0xFC04806B)
1281#define MCF_INTC0_ICR44 MCF_REG08(0xFC04806C)
1282#define MCF_INTC0_ICR45 MCF_REG08(0xFC04806D)
1283#define MCF_INTC0_ICR46 MCF_REG08(0xFC04806E)
1284#define MCF_INTC0_ICR47 MCF_REG08(0xFC04806F)
1285#define MCF_INTC0_ICR48 MCF_REG08(0xFC048070)
1286#define MCF_INTC0_ICR49 MCF_REG08(0xFC048071)
1287#define MCF_INTC0_ICR50 MCF_REG08(0xFC048072)
1288#define MCF_INTC0_ICR51 MCF_REG08(0xFC048073)
1289#define MCF_INTC0_ICR52 MCF_REG08(0xFC048074)
1290#define MCF_INTC0_ICR53 MCF_REG08(0xFC048075)
1291#define MCF_INTC0_ICR54 MCF_REG08(0xFC048076)
1292#define MCF_INTC0_ICR55 MCF_REG08(0xFC048077)
1293#define MCF_INTC0_ICR56 MCF_REG08(0xFC048078)
1294#define MCF_INTC0_ICR57 MCF_REG08(0xFC048079)
1295#define MCF_INTC0_ICR58 MCF_REG08(0xFC04807A)
1296#define MCF_INTC0_ICR59 MCF_REG08(0xFC04807B)
1297#define MCF_INTC0_ICR60 MCF_REG08(0xFC04807C)
1298#define MCF_INTC0_ICR61 MCF_REG08(0xFC04807D)
1299#define MCF_INTC0_ICR62 MCF_REG08(0xFC04807E)
1300#define MCF_INTC0_ICR63 MCF_REG08(0xFC04807F)
1301#define MCF_INTC0_ICR(x) MCF_REG08(0xFC048040+((x)*0x001))
1302#define MCF_INTC0_SWIACK MCF_REG08(0xFC0480E0)
1303#define MCF_INTC0_L1IACK MCF_REG08(0xFC0480E4)
1304#define MCF_INTC0_L2IACK MCF_REG08(0xFC0480E8)
1305#define MCF_INTC0_L3IACK MCF_REG08(0xFC0480EC)
1306#define MCF_INTC0_L4IACK MCF_REG08(0xFC0480F0)
1307#define MCF_INTC0_L5IACK MCF_REG08(0xFC0480F4)
1308#define MCF_INTC0_L6IACK MCF_REG08(0xFC0480F8)
1309#define MCF_INTC0_L7IACK MCF_REG08(0xFC0480FC)
1310#define MCF_INTC0_LIACK(x) MCF_REG08(0xFC0480E4+((x)*0x004))
1311#define MCF_INTC1_IPRH MCF_REG32(0xFC04C000)
1312#define MCF_INTC1_IPRL MCF_REG32(0xFC04C004)
1313#define MCF_INTC1_IMRH MCF_REG32(0xFC04C008)
1314#define MCF_INTC1_IMRL MCF_REG32(0xFC04C00C)
1315#define MCF_INTC1_INTFRCH MCF_REG32(0xFC04C010)
1316#define MCF_INTC1_INTFRCL MCF_REG32(0xFC04C014)
1317#define MCF_INTC1_ICONFIG MCF_REG16(0xFC04C01A)
1318#define MCF_INTC1_SIMR MCF_REG08(0xFC04C01C)
1319#define MCF_INTC1_CIMR MCF_REG08(0xFC04C01D)
1320#define MCF_INTC1_CLMASK MCF_REG08(0xFC04C01E)
1321#define MCF_INTC1_SLMASK MCF_REG08(0xFC04C01F)
1322#define MCF_INTC1_ICR0 MCF_REG08(0xFC04C040)
1323#define MCF_INTC1_ICR1 MCF_REG08(0xFC04C041)
1324#define MCF_INTC1_ICR2 MCF_REG08(0xFC04C042)
1325#define MCF_INTC1_ICR3 MCF_REG08(0xFC04C043)
1326#define MCF_INTC1_ICR4 MCF_REG08(0xFC04C044)
1327#define MCF_INTC1_ICR5 MCF_REG08(0xFC04C045)
1328#define MCF_INTC1_ICR6 MCF_REG08(0xFC04C046)
1329#define MCF_INTC1_ICR7 MCF_REG08(0xFC04C047)
1330#define MCF_INTC1_ICR8 MCF_REG08(0xFC04C048)
1331#define MCF_INTC1_ICR9 MCF_REG08(0xFC04C049)
1332#define MCF_INTC1_ICR10 MCF_REG08(0xFC04C04A)
1333#define MCF_INTC1_ICR11 MCF_REG08(0xFC04C04B)
1334#define MCF_INTC1_ICR12 MCF_REG08(0xFC04C04C)
1335#define MCF_INTC1_ICR13 MCF_REG08(0xFC04C04D)
1336#define MCF_INTC1_ICR14 MCF_REG08(0xFC04C04E)
1337#define MCF_INTC1_ICR15 MCF_REG08(0xFC04C04F)
1338#define MCF_INTC1_ICR16 MCF_REG08(0xFC04C050)
1339#define MCF_INTC1_ICR17 MCF_REG08(0xFC04C051)
1340#define MCF_INTC1_ICR18 MCF_REG08(0xFC04C052)
1341#define MCF_INTC1_ICR19 MCF_REG08(0xFC04C053)
1342#define MCF_INTC1_ICR20 MCF_REG08(0xFC04C054)
1343#define MCF_INTC1_ICR21 MCF_REG08(0xFC04C055)
1344#define MCF_INTC1_ICR22 MCF_REG08(0xFC04C056)
1345#define MCF_INTC1_ICR23 MCF_REG08(0xFC04C057)
1346#define MCF_INTC1_ICR24 MCF_REG08(0xFC04C058)
1347#define MCF_INTC1_ICR25 MCF_REG08(0xFC04C059)
1348#define MCF_INTC1_ICR26 MCF_REG08(0xFC04C05A)
1349#define MCF_INTC1_ICR27 MCF_REG08(0xFC04C05B)
1350#define MCF_INTC1_ICR28 MCF_REG08(0xFC04C05C)
1351#define MCF_INTC1_ICR29 MCF_REG08(0xFC04C05D)
1352#define MCF_INTC1_ICR30 MCF_REG08(0xFC04C05E)
1353#define MCF_INTC1_ICR31 MCF_REG08(0xFC04C05F)
1354#define MCF_INTC1_ICR32 MCF_REG08(0xFC04C060)
1355#define MCF_INTC1_ICR33 MCF_REG08(0xFC04C061)
1356#define MCF_INTC1_ICR34 MCF_REG08(0xFC04C062)
1357#define MCF_INTC1_ICR35 MCF_REG08(0xFC04C063)
1358#define MCF_INTC1_ICR36 MCF_REG08(0xFC04C064)
1359#define MCF_INTC1_ICR37 MCF_REG08(0xFC04C065)
1360#define MCF_INTC1_ICR38 MCF_REG08(0xFC04C066)
1361#define MCF_INTC1_ICR39 MCF_REG08(0xFC04C067)
1362#define MCF_INTC1_ICR40 MCF_REG08(0xFC04C068)
1363#define MCF_INTC1_ICR41 MCF_REG08(0xFC04C069)
1364#define MCF_INTC1_ICR42 MCF_REG08(0xFC04C06A)
1365#define MCF_INTC1_ICR43 MCF_REG08(0xFC04C06B)
1366#define MCF_INTC1_ICR44 MCF_REG08(0xFC04C06C)
1367#define MCF_INTC1_ICR45 MCF_REG08(0xFC04C06D)
1368#define MCF_INTC1_ICR46 MCF_REG08(0xFC04C06E)
1369#define MCF_INTC1_ICR47 MCF_REG08(0xFC04C06F)
1370#define MCF_INTC1_ICR48 MCF_REG08(0xFC04C070)
1371#define MCF_INTC1_ICR49 MCF_REG08(0xFC04C071)
1372#define MCF_INTC1_ICR50 MCF_REG08(0xFC04C072)
1373#define MCF_INTC1_ICR51 MCF_REG08(0xFC04C073)
1374#define MCF_INTC1_ICR52 MCF_REG08(0xFC04C074)
1375#define MCF_INTC1_ICR53 MCF_REG08(0xFC04C075)
1376#define MCF_INTC1_ICR54 MCF_REG08(0xFC04C076)
1377#define MCF_INTC1_ICR55 MCF_REG08(0xFC04C077)
1378#define MCF_INTC1_ICR56 MCF_REG08(0xFC04C078)
1379#define MCF_INTC1_ICR57 MCF_REG08(0xFC04C079)
1380#define MCF_INTC1_ICR58 MCF_REG08(0xFC04C07A)
1381#define MCF_INTC1_ICR59 MCF_REG08(0xFC04C07B)
1382#define MCF_INTC1_ICR60 MCF_REG08(0xFC04C07C)
1383#define MCF_INTC1_ICR61 MCF_REG08(0xFC04C07D)
1384#define MCF_INTC1_ICR62 MCF_REG08(0xFC04C07E)
1385#define MCF_INTC1_ICR63 MCF_REG08(0xFC04C07F)
1386#define MCF_INTC1_ICR(x) MCF_REG08(0xFC04C040+((x)*0x001))
1387#define MCF_INTC1_SWIACK MCF_REG08(0xFC04C0E0)
1388#define MCF_INTC1_L1IACK MCF_REG08(0xFC04C0E4)
1389#define MCF_INTC1_L2IACK MCF_REG08(0xFC04C0E8)
1390#define MCF_INTC1_L3IACK MCF_REG08(0xFC04C0EC)
1391#define MCF_INTC1_L4IACK MCF_REG08(0xFC04C0F0)
1392#define MCF_INTC1_L5IACK MCF_REG08(0xFC04C0F4)
1393#define MCF_INTC1_L6IACK MCF_REG08(0xFC04C0F8)
1394#define MCF_INTC1_L7IACK MCF_REG08(0xFC04C0FC)
1395#define MCF_INTC1_LIACK(x) MCF_REG08(0xFC04C0E4+((x)*0x004))
1396#define MCF_INTC_IPRH(x) MCF_REG32(0xFC048000+((x)*0x4000))
1397#define MCF_INTC_IPRL(x) MCF_REG32(0xFC048004+((x)*0x4000))
1398#define MCF_INTC_IMRH(x) MCF_REG32(0xFC048008+((x)*0x4000))
1399#define MCF_INTC_IMRL(x) MCF_REG32(0xFC04800C+((x)*0x4000))
1400#define MCF_INTC_INTFRCH(x) MCF_REG32(0xFC048010+((x)*0x4000))
1401#define MCF_INTC_INTFRCL(x) MCF_REG32(0xFC048014+((x)*0x4000))
1402#define MCF_INTC_ICONFIG(x) MCF_REG16(0xFC04801A+((x)*0x4000))
1403#define MCF_INTC_SIMR(x) MCF_REG08(0xFC04801C+((x)*0x4000))
1404#define MCF_INTC_CIMR(x) MCF_REG08(0xFC04801D+((x)*0x4000))
1405#define MCF_INTC_CLMASK(x) MCF_REG08(0xFC04801E+((x)*0x4000))
1406#define MCF_INTC_SLMASK(x) MCF_REG08(0xFC04801F+((x)*0x4000))
1407#define MCF_INTC_ICR0(x) MCF_REG08(0xFC048040+((x)*0x4000))
1408#define MCF_INTC_ICR1(x) MCF_REG08(0xFC048041+((x)*0x4000))
1409#define MCF_INTC_ICR2(x) MCF_REG08(0xFC048042+((x)*0x4000))
1410#define MCF_INTC_ICR3(x) MCF_REG08(0xFC048043+((x)*0x4000))
1411#define MCF_INTC_ICR4(x) MCF_REG08(0xFC048044+((x)*0x4000))
1412#define MCF_INTC_ICR5(x) MCF_REG08(0xFC048045+((x)*0x4000))
1413#define MCF_INTC_ICR6(x) MCF_REG08(0xFC048046+((x)*0x4000))
1414#define MCF_INTC_ICR7(x) MCF_REG08(0xFC048047+((x)*0x4000))
1415#define MCF_INTC_ICR8(x) MCF_REG08(0xFC048048+((x)*0x4000))
1416#define MCF_INTC_ICR9(x) MCF_REG08(0xFC048049+((x)*0x4000))
1417#define MCF_INTC_ICR10(x) MCF_REG08(0xFC04804A+((x)*0x4000))
1418#define MCF_INTC_ICR11(x) MCF_REG08(0xFC04804B+((x)*0x4000))
1419#define MCF_INTC_ICR12(x) MCF_REG08(0xFC04804C+((x)*0x4000))
1420#define MCF_INTC_ICR13(x) MCF_REG08(0xFC04804D+((x)*0x4000))
1421#define MCF_INTC_ICR14(x) MCF_REG08(0xFC04804E+((x)*0x4000))
1422#define MCF_INTC_ICR15(x) MCF_REG08(0xFC04804F+((x)*0x4000))
1423#define MCF_INTC_ICR16(x) MCF_REG08(0xFC048050+((x)*0x4000))
1424#define MCF_INTC_ICR17(x) MCF_REG08(0xFC048051+((x)*0x4000))
1425#define MCF_INTC_ICR18(x) MCF_REG08(0xFC048052+((x)*0x4000))
1426#define MCF_INTC_ICR19(x) MCF_REG08(0xFC048053+((x)*0x4000))
1427#define MCF_INTC_ICR20(x) MCF_REG08(0xFC048054+((x)*0x4000))
1428#define MCF_INTC_ICR21(x) MCF_REG08(0xFC048055+((x)*0x4000))
1429#define MCF_INTC_ICR22(x) MCF_REG08(0xFC048056+((x)*0x4000))
1430#define MCF_INTC_ICR23(x) MCF_REG08(0xFC048057+((x)*0x4000))
1431#define MCF_INTC_ICR24(x) MCF_REG08(0xFC048058+((x)*0x4000))
1432#define MCF_INTC_ICR25(x) MCF_REG08(0xFC048059+((x)*0x4000))
1433#define MCF_INTC_ICR26(x) MCF_REG08(0xFC04805A+((x)*0x4000))
1434#define MCF_INTC_ICR27(x) MCF_REG08(0xFC04805B+((x)*0x4000))
1435#define MCF_INTC_ICR28(x) MCF_REG08(0xFC04805C+((x)*0x4000))
1436#define MCF_INTC_ICR29(x) MCF_REG08(0xFC04805D+((x)*0x4000))
1437#define MCF_INTC_ICR30(x) MCF_REG08(0xFC04805E+((x)*0x4000))
1438#define MCF_INTC_ICR31(x) MCF_REG08(0xFC04805F+((x)*0x4000))
1439#define MCF_INTC_ICR32(x) MCF_REG08(0xFC048060+((x)*0x4000))
1440#define MCF_INTC_ICR33(x) MCF_REG08(0xFC048061+((x)*0x4000))
1441#define MCF_INTC_ICR34(x) MCF_REG08(0xFC048062+((x)*0x4000))
1442#define MCF_INTC_ICR35(x) MCF_REG08(0xFC048063+((x)*0x4000))
1443#define MCF_INTC_ICR36(x) MCF_REG08(0xFC048064+((x)*0x4000))
1444#define MCF_INTC_ICR37(x) MCF_REG08(0xFC048065+((x)*0x4000))
1445#define MCF_INTC_ICR38(x) MCF_REG08(0xFC048066+((x)*0x4000))
1446#define MCF_INTC_ICR39(x) MCF_REG08(0xFC048067+((x)*0x4000))
1447#define MCF_INTC_ICR40(x) MCF_REG08(0xFC048068+((x)*0x4000))
1448#define MCF_INTC_ICR41(x) MCF_REG08(0xFC048069+((x)*0x4000))
1449#define MCF_INTC_ICR42(x) MCF_REG08(0xFC04806A+((x)*0x4000))
1450#define MCF_INTC_ICR43(x) MCF_REG08(0xFC04806B+((x)*0x4000))
1451#define MCF_INTC_ICR44(x) MCF_REG08(0xFC04806C+((x)*0x4000))
1452#define MCF_INTC_ICR45(x) MCF_REG08(0xFC04806D+((x)*0x4000))
1453#define MCF_INTC_ICR46(x) MCF_REG08(0xFC04806E+((x)*0x4000))
1454#define MCF_INTC_ICR47(x) MCF_REG08(0xFC04806F+((x)*0x4000))
1455#define MCF_INTC_ICR48(x) MCF_REG08(0xFC048070+((x)*0x4000))
1456#define MCF_INTC_ICR49(x) MCF_REG08(0xFC048071+((x)*0x4000))
1457#define MCF_INTC_ICR50(x) MCF_REG08(0xFC048072+((x)*0x4000))
1458#define MCF_INTC_ICR51(x) MCF_REG08(0xFC048073+((x)*0x4000))
1459#define MCF_INTC_ICR52(x) MCF_REG08(0xFC048074+((x)*0x4000))
1460#define MCF_INTC_ICR53(x) MCF_REG08(0xFC048075+((x)*0x4000))
1461#define MCF_INTC_ICR54(x) MCF_REG08(0xFC048076+((x)*0x4000))
1462#define MCF_INTC_ICR55(x) MCF_REG08(0xFC048077+((x)*0x4000))
1463#define MCF_INTC_ICR56(x) MCF_REG08(0xFC048078+((x)*0x4000))
1464#define MCF_INTC_ICR57(x) MCF_REG08(0xFC048079+((x)*0x4000))
1465#define MCF_INTC_ICR58(x) MCF_REG08(0xFC04807A+((x)*0x4000))
1466#define MCF_INTC_ICR59(x) MCF_REG08(0xFC04807B+((x)*0x4000))
1467#define MCF_INTC_ICR60(x) MCF_REG08(0xFC04807C+((x)*0x4000))
1468#define MCF_INTC_ICR61(x) MCF_REG08(0xFC04807D+((x)*0x4000))
1469#define MCF_INTC_ICR62(x) MCF_REG08(0xFC04807E+((x)*0x4000))
1470#define MCF_INTC_ICR63(x) MCF_REG08(0xFC04807F+((x)*0x4000))
1471#define MCF_INTC_SWIACK(x) MCF_REG08(0xFC0480E0+((x)*0x4000))
1472#define MCF_INTC_L1IACK(x) MCF_REG08(0xFC0480E4+((x)*0x4000))
1473#define MCF_INTC_L2IACK(x) MCF_REG08(0xFC0480E8+((x)*0x4000))
1474#define MCF_INTC_L3IACK(x) MCF_REG08(0xFC0480EC+((x)*0x4000))
1475#define MCF_INTC_L4IACK(x) MCF_REG08(0xFC0480F0+((x)*0x4000))
1476#define MCF_INTC_L5IACK(x) MCF_REG08(0xFC0480F4+((x)*0x4000))
1477#define MCF_INTC_L6IACK(x) MCF_REG08(0xFC0480F8+((x)*0x4000))
1478#define MCF_INTC_L7IACK(x) MCF_REG08(0xFC0480FC+((x)*0x4000))
1479
1480/* Bit definitions and macros for MCF_INTC_IPRH */
1481#define MCF_INTC_IPRH_INT32 (0x00000001)
1482#define MCF_INTC_IPRH_INT33 (0x00000002)
1483#define MCF_INTC_IPRH_INT34 (0x00000004)
1484#define MCF_INTC_IPRH_INT35 (0x00000008)
1485#define MCF_INTC_IPRH_INT36 (0x00000010)
1486#define MCF_INTC_IPRH_INT37 (0x00000020)
1487#define MCF_INTC_IPRH_INT38 (0x00000040)
1488#define MCF_INTC_IPRH_INT39 (0x00000080)
1489#define MCF_INTC_IPRH_INT40 (0x00000100)
1490#define MCF_INTC_IPRH_INT41 (0x00000200)
1491#define MCF_INTC_IPRH_INT42 (0x00000400)
1492#define MCF_INTC_IPRH_INT43 (0x00000800)
1493#define MCF_INTC_IPRH_INT44 (0x00001000)
1494#define MCF_INTC_IPRH_INT45 (0x00002000)
1495#define MCF_INTC_IPRH_INT46 (0x00004000)
1496#define MCF_INTC_IPRH_INT47 (0x00008000)
1497#define MCF_INTC_IPRH_INT48 (0x00010000)
1498#define MCF_INTC_IPRH_INT49 (0x00020000)
1499#define MCF_INTC_IPRH_INT50 (0x00040000)
1500#define MCF_INTC_IPRH_INT51 (0x00080000)
1501#define MCF_INTC_IPRH_INT52 (0x00100000)
1502#define MCF_INTC_IPRH_INT53 (0x00200000)
1503#define MCF_INTC_IPRH_INT54 (0x00400000)
1504#define MCF_INTC_IPRH_INT55 (0x00800000)
1505#define MCF_INTC_IPRH_INT56 (0x01000000)
1506#define MCF_INTC_IPRH_INT57 (0x02000000)
1507#define MCF_INTC_IPRH_INT58 (0x04000000)
1508#define MCF_INTC_IPRH_INT59 (0x08000000)
1509#define MCF_INTC_IPRH_INT60 (0x10000000)
1510#define MCF_INTC_IPRH_INT61 (0x20000000)
1511#define MCF_INTC_IPRH_INT62 (0x40000000)
1512#define MCF_INTC_IPRH_INT63 (0x80000000)
1513
1514/* Bit definitions and macros for MCF_INTC_IPRL */
1515#define MCF_INTC_IPRL_INT0 (0x00000001)
1516#define MCF_INTC_IPRL_INT1 (0x00000002)
1517#define MCF_INTC_IPRL_INT2 (0x00000004)
1518#define MCF_INTC_IPRL_INT3 (0x00000008)
1519#define MCF_INTC_IPRL_INT4 (0x00000010)
1520#define MCF_INTC_IPRL_INT5 (0x00000020)
1521#define MCF_INTC_IPRL_INT6 (0x00000040)
1522#define MCF_INTC_IPRL_INT7 (0x00000080)
1523#define MCF_INTC_IPRL_INT8 (0x00000100)
1524#define MCF_INTC_IPRL_INT9 (0x00000200)
1525#define MCF_INTC_IPRL_INT10 (0x00000400)
1526#define MCF_INTC_IPRL_INT11 (0x00000800)
1527#define MCF_INTC_IPRL_INT12 (0x00001000)
1528#define MCF_INTC_IPRL_INT13 (0x00002000)
1529#define MCF_INTC_IPRL_INT14 (0x00004000)
1530#define MCF_INTC_IPRL_INT15 (0x00008000)
1531#define MCF_INTC_IPRL_INT16 (0x00010000)
1532#define MCF_INTC_IPRL_INT17 (0x00020000)
1533#define MCF_INTC_IPRL_INT18 (0x00040000)
1534#define MCF_INTC_IPRL_INT19 (0x00080000)
1535#define MCF_INTC_IPRL_INT20 (0x00100000)
1536#define MCF_INTC_IPRL_INT21 (0x00200000)
1537#define MCF_INTC_IPRL_INT22 (0x00400000)
1538#define MCF_INTC_IPRL_INT23 (0x00800000)
1539#define MCF_INTC_IPRL_INT24 (0x01000000)
1540#define MCF_INTC_IPRL_INT25 (0x02000000)
1541#define MCF_INTC_IPRL_INT26 (0x04000000)
1542#define MCF_INTC_IPRL_INT27 (0x08000000)
1543#define MCF_INTC_IPRL_INT28 (0x10000000)
1544#define MCF_INTC_IPRL_INT29 (0x20000000)
1545#define MCF_INTC_IPRL_INT30 (0x40000000)
1546#define MCF_INTC_IPRL_INT31 (0x80000000)
1547
1548/* Bit definitions and macros for MCF_INTC_IMRH */
1549#define MCF_INTC_IMRH_INT_MASK32 (0x00000001)
1550#define MCF_INTC_IMRH_INT_MASK33 (0x00000002)
1551#define MCF_INTC_IMRH_INT_MASK34 (0x00000004)
1552#define MCF_INTC_IMRH_INT_MASK35 (0x00000008)
1553#define MCF_INTC_IMRH_INT_MASK36 (0x00000010)
1554#define MCF_INTC_IMRH_INT_MASK37 (0x00000020)
1555#define MCF_INTC_IMRH_INT_MASK38 (0x00000040)
1556#define MCF_INTC_IMRH_INT_MASK39 (0x00000080)
1557#define MCF_INTC_IMRH_INT_MASK40 (0x00000100)
1558#define MCF_INTC_IMRH_INT_MASK41 (0x00000200)
1559#define MCF_INTC_IMRH_INT_MASK42 (0x00000400)
1560#define MCF_INTC_IMRH_INT_MASK43 (0x00000800)
1561#define MCF_INTC_IMRH_INT_MASK44 (0x00001000)
1562#define MCF_INTC_IMRH_INT_MASK45 (0x00002000)
1563#define MCF_INTC_IMRH_INT_MASK46 (0x00004000)
1564#define MCF_INTC_IMRH_INT_MASK47 (0x00008000)
1565#define MCF_INTC_IMRH_INT_MASK48 (0x00010000)
1566#define MCF_INTC_IMRH_INT_MASK49 (0x00020000)
1567#define MCF_INTC_IMRH_INT_MASK50 (0x00040000)
1568#define MCF_INTC_IMRH_INT_MASK51 (0x00080000)
1569#define MCF_INTC_IMRH_INT_MASK52 (0x00100000)
1570#define MCF_INTC_IMRH_INT_MASK53 (0x00200000)
1571#define MCF_INTC_IMRH_INT_MASK54 (0x00400000)
1572#define MCF_INTC_IMRH_INT_MASK55 (0x00800000)
1573#define MCF_INTC_IMRH_INT_MASK56 (0x01000000)
1574#define MCF_INTC_IMRH_INT_MASK57 (0x02000000)
1575#define MCF_INTC_IMRH_INT_MASK58 (0x04000000)
1576#define MCF_INTC_IMRH_INT_MASK59 (0x08000000)
1577#define MCF_INTC_IMRH_INT_MASK60 (0x10000000)
1578#define MCF_INTC_IMRH_INT_MASK61 (0x20000000)
1579#define MCF_INTC_IMRH_INT_MASK62 (0x40000000)
1580#define MCF_INTC_IMRH_INT_MASK63 (0x80000000)
1581
1582/* Bit definitions and macros for MCF_INTC_IMRL */
1583#define MCF_INTC_IMRL_INT_MASK0 (0x00000001)
1584#define MCF_INTC_IMRL_INT_MASK1 (0x00000002)
1585#define MCF_INTC_IMRL_INT_MASK2 (0x00000004)
1586#define MCF_INTC_IMRL_INT_MASK3 (0x00000008)
1587#define MCF_INTC_IMRL_INT_MASK4 (0x00000010)
1588#define MCF_INTC_IMRL_INT_MASK5 (0x00000020)
1589#define MCF_INTC_IMRL_INT_MASK6 (0x00000040)
1590#define MCF_INTC_IMRL_INT_MASK7 (0x00000080)
1591#define MCF_INTC_IMRL_INT_MASK8 (0x00000100)
1592#define MCF_INTC_IMRL_INT_MASK9 (0x00000200)
1593#define MCF_INTC_IMRL_INT_MASK10 (0x00000400)
1594#define MCF_INTC_IMRL_INT_MASK11 (0x00000800)
1595#define MCF_INTC_IMRL_INT_MASK12 (0x00001000)
1596#define MCF_INTC_IMRL_INT_MASK13 (0x00002000)
1597#define MCF_INTC_IMRL_INT_MASK14 (0x00004000)
1598#define MCF_INTC_IMRL_INT_MASK15 (0x00008000)
1599#define MCF_INTC_IMRL_INT_MASK16 (0x00010000)
1600#define MCF_INTC_IMRL_INT_MASK17 (0x00020000)
1601#define MCF_INTC_IMRL_INT_MASK18 (0x00040000)
1602#define MCF_INTC_IMRL_INT_MASK19 (0x00080000)
1603#define MCF_INTC_IMRL_INT_MASK20 (0x00100000)
1604#define MCF_INTC_IMRL_INT_MASK21 (0x00200000)
1605#define MCF_INTC_IMRL_INT_MASK22 (0x00400000)
1606#define MCF_INTC_IMRL_INT_MASK23 (0x00800000)
1607#define MCF_INTC_IMRL_INT_MASK24 (0x01000000)
1608#define MCF_INTC_IMRL_INT_MASK25 (0x02000000)
1609#define MCF_INTC_IMRL_INT_MASK26 (0x04000000)
1610#define MCF_INTC_IMRL_INT_MASK27 (0x08000000)
1611#define MCF_INTC_IMRL_INT_MASK28 (0x10000000)
1612#define MCF_INTC_IMRL_INT_MASK29 (0x20000000)
1613#define MCF_INTC_IMRL_INT_MASK30 (0x40000000)
1614#define MCF_INTC_IMRL_INT_MASK31 (0x80000000)
1615
1616/* Bit definitions and macros for MCF_INTC_INTFRCH */
1617#define MCF_INTC_INTFRCH_INTFRC32 (0x00000001)
1618#define MCF_INTC_INTFRCH_INTFRC33 (0x00000002)
1619#define MCF_INTC_INTFRCH_INTFRC34 (0x00000004)
1620#define MCF_INTC_INTFRCH_INTFRC35 (0x00000008)
1621#define MCF_INTC_INTFRCH_INTFRC36 (0x00000010)
1622#define MCF_INTC_INTFRCH_INTFRC37 (0x00000020)
1623#define MCF_INTC_INTFRCH_INTFRC38 (0x00000040)
1624#define MCF_INTC_INTFRCH_INTFRC39 (0x00000080)
1625#define MCF_INTC_INTFRCH_INTFRC40 (0x00000100)
1626#define MCF_INTC_INTFRCH_INTFRC41 (0x00000200)
1627#define MCF_INTC_INTFRCH_INTFRC42 (0x00000400)
1628#define MCF_INTC_INTFRCH_INTFRC43 (0x00000800)
1629#define MCF_INTC_INTFRCH_INTFRC44 (0x00001000)
1630#define MCF_INTC_INTFRCH_INTFRC45 (0x00002000)
1631#define MCF_INTC_INTFRCH_INTFRC46 (0x00004000)
1632#define MCF_INTC_INTFRCH_INTFRC47 (0x00008000)
1633#define MCF_INTC_INTFRCH_INTFRC48 (0x00010000)
1634#define MCF_INTC_INTFRCH_INTFRC49 (0x00020000)
1635#define MCF_INTC_INTFRCH_INTFRC50 (0x00040000)
1636#define MCF_INTC_INTFRCH_INTFRC51 (0x00080000)
1637#define MCF_INTC_INTFRCH_INTFRC52 (0x00100000)
1638#define MCF_INTC_INTFRCH_INTFRC53 (0x00200000)
1639#define MCF_INTC_INTFRCH_INTFRC54 (0x00400000)
1640#define MCF_INTC_INTFRCH_INTFRC55 (0x00800000)
1641#define MCF_INTC_INTFRCH_INTFRC56 (0x01000000)
1642#define MCF_INTC_INTFRCH_INTFRC57 (0x02000000)
1643#define MCF_INTC_INTFRCH_INTFRC58 (0x04000000)
1644#define MCF_INTC_INTFRCH_INTFRC59 (0x08000000)
1645#define MCF_INTC_INTFRCH_INTFRC60 (0x10000000)
1646#define MCF_INTC_INTFRCH_INTFRC61 (0x20000000)
1647#define MCF_INTC_INTFRCH_INTFRC62 (0x40000000)
1648#define MCF_INTC_INTFRCH_INTFRC63 (0x80000000)
1649
1650/* Bit definitions and macros for MCF_INTC_INTFRCL */
1651#define MCF_INTC_INTFRCL_INTFRC0 (0x00000001)
1652#define MCF_INTC_INTFRCL_INTFRC1 (0x00000002)
1653#define MCF_INTC_INTFRCL_INTFRC2 (0x00000004)
1654#define MCF_INTC_INTFRCL_INTFRC3 (0x00000008)
1655#define MCF_INTC_INTFRCL_INTFRC4 (0x00000010)
1656#define MCF_INTC_INTFRCL_INTFRC5 (0x00000020)
1657#define MCF_INTC_INTFRCL_INTFRC6 (0x00000040)
1658#define MCF_INTC_INTFRCL_INTFRC7 (0x00000080)
1659#define MCF_INTC_INTFRCL_INTFRC8 (0x00000100)
1660#define MCF_INTC_INTFRCL_INTFRC9 (0x00000200)
1661#define MCF_INTC_INTFRCL_INTFRC10 (0x00000400)
1662#define MCF_INTC_INTFRCL_INTFRC11 (0x00000800)
1663#define MCF_INTC_INTFRCL_INTFRC12 (0x00001000)
1664#define MCF_INTC_INTFRCL_INTFRC13 (0x00002000)
1665#define MCF_INTC_INTFRCL_INTFRC14 (0x00004000)
1666#define MCF_INTC_INTFRCL_INTFRC15 (0x00008000)
1667#define MCF_INTC_INTFRCL_INTFRC16 (0x00010000)
1668#define MCF_INTC_INTFRCL_INTFRC17 (0x00020000)
1669#define MCF_INTC_INTFRCL_INTFRC18 (0x00040000)
1670#define MCF_INTC_INTFRCL_INTFRC19 (0x00080000)
1671#define MCF_INTC_INTFRCL_INTFRC20 (0x00100000)
1672#define MCF_INTC_INTFRCL_INTFRC21 (0x00200000)
1673#define MCF_INTC_INTFRCL_INTFRC22 (0x00400000)
1674#define MCF_INTC_INTFRCL_INTFRC23 (0x00800000)
1675#define MCF_INTC_INTFRCL_INTFRC24 (0x01000000)
1676#define MCF_INTC_INTFRCL_INTFRC25 (0x02000000)
1677#define MCF_INTC_INTFRCL_INTFRC26 (0x04000000)
1678#define MCF_INTC_INTFRCL_INTFRC27 (0x08000000)
1679#define MCF_INTC_INTFRCL_INTFRC28 (0x10000000)
1680#define MCF_INTC_INTFRCL_INTFRC29 (0x20000000)
1681#define MCF_INTC_INTFRCL_INTFRC30 (0x40000000)
1682#define MCF_INTC_INTFRCL_INTFRC31 (0x80000000)
1683
1684/* Bit definitions and macros for MCF_INTC_ICONFIG */
1685#define MCF_INTC_ICONFIG_EMASK (0x0020)
1686#define MCF_INTC_ICONFIG_ELVLPRI1 (0x0200)
1687#define MCF_INTC_ICONFIG_ELVLPRI2 (0x0400)
1688#define MCF_INTC_ICONFIG_ELVLPRI3 (0x0800)
1689#define MCF_INTC_ICONFIG_ELVLPRI4 (0x1000)
1690#define MCF_INTC_ICONFIG_ELVLPRI5 (0x2000)
1691#define MCF_INTC_ICONFIG_ELVLPRI6 (0x4000)
1692#define MCF_INTC_ICONFIG_ELVLPRI7 (0x8000)
1693
1694/* Bit definitions and macros for MCF_INTC_SIMR */
1695#define MCF_INTC_SIMR_SIMR(x) (((x)&0x7F)<<0)
1696
1697/* Bit definitions and macros for MCF_INTC_CIMR */
1698#define MCF_INTC_CIMR_CIMR(x) (((x)&0x7F)<<0)
1699
1700/* Bit definitions and macros for MCF_INTC_CLMASK */
1701#define MCF_INTC_CLMASK_CLMASK(x) (((x)&0x0F)<<0)
1702
1703/* Bit definitions and macros for MCF_INTC_SLMASK */
1704#define MCF_INTC_SLMASK_SLMASK(x) (((x)&0x0F)<<0)
1705
1706/* Bit definitions and macros for MCF_INTC_ICR */
1707#define MCF_INTC_ICR_IL(x) (((x)&0x07)<<0)
1708
1709/* Bit definitions and macros for MCF_INTC_SWIACK */
1710#define MCF_INTC_SWIACK_VECTOR(x) (((x)&0xFF)<<0)
1711
1712/* Bit definitions and macros for MCF_INTC_LIACK */
1713#define MCF_INTC_LIACK_VECTOR(x) (((x)&0xFF)<<0)
1714
1715/********************************************************************/
1716/*********************************************************************
1717*
1718* LCD Controller (LCDC)
1719*
1720*********************************************************************/
1721
1722/* Register read/write macros */
1723#define MCF_LCDC_LSSAR MCF_REG32(0xFC0AC000)
1724#define MCF_LCDC_LSR MCF_REG32(0xFC0AC004)
1725#define MCF_LCDC_LVPWR MCF_REG32(0xFC0AC008)
1726#define MCF_LCDC_LCPR MCF_REG32(0xFC0AC00C)
1727#define MCF_LCDC_LCWHBR MCF_REG32(0xFC0AC010)
1728#define MCF_LCDC_LCCMR MCF_REG32(0xFC0AC014)
1729#define MCF_LCDC_LPCR MCF_REG32(0xFC0AC018)
1730#define MCF_LCDC_LHCR MCF_REG32(0xFC0AC01C)
1731#define MCF_LCDC_LVCR MCF_REG32(0xFC0AC020)
1732#define MCF_LCDC_LPOR MCF_REG32(0xFC0AC024)
1733#define MCF_LCDC_LSCR MCF_REG32(0xFC0AC028)
1734#define MCF_LCDC_LPCCR MCF_REG32(0xFC0AC02C)
1735#define MCF_LCDC_LDCR MCF_REG32(0xFC0AC030)
1736#define MCF_LCDC_LRMCR MCF_REG32(0xFC0AC034)
1737#define MCF_LCDC_LICR MCF_REG32(0xFC0AC038)
1738#define MCF_LCDC_LIER MCF_REG32(0xFC0AC03C)
1739#define MCF_LCDC_LISR MCF_REG32(0xFC0AC040)
1740#define MCF_LCDC_LGWSAR MCF_REG32(0xFC0AC050)
1741#define MCF_LCDC_LGWSR MCF_REG32(0xFC0AC054)
1742#define MCF_LCDC_LGWVPWR MCF_REG32(0xFC0AC058)
1743#define MCF_LCDC_LGWPOR MCF_REG32(0xFC0AC05C)
1744#define MCF_LCDC_LGWPR MCF_REG32(0xFC0AC060)
1745#define MCF_LCDC_LGWCR MCF_REG32(0xFC0AC064)
1746#define MCF_LCDC_LGWDCR MCF_REG32(0xFC0AC068)
1747#define MCF_LCDC_BPLUT_BASE MCF_REG32(0xFC0AC800)
1748#define MCF_LCDC_GWLUT_BASE MCF_REG32(0xFC0ACC00)
1749
1750/* Bit definitions and macros for MCF_LCDC_LSSAR */
1751#define MCF_LCDC_LSSAR_SSA(x) (((x)&0x3FFFFFFF)<<2)
1752
1753/* Bit definitions and macros for MCF_LCDC_LSR */
1754#define MCF_LCDC_LSR_YMAX(x) (((x)&0x000003FF)<<0)
1755#define MCF_LCDC_LSR_XMAX(x) (((x)&0x0000003F)<<20)
1756
1757/* Bit definitions and macros for MCF_LCDC_LVPWR */
1758#define MCF_LCDC_LVPWR_VPW(x) (((x)&0x000003FF)<<0)
1759
1760/* Bit definitions and macros for MCF_LCDC_LCPR */
1761#define MCF_LCDC_LCPR_CYP(x) (((x)&0x000003FF)<<0)
1762#define MCF_LCDC_LCPR_CXP(x) (((x)&0x000003FF)<<16)
1763#define MCF_LCDC_LCPR_OP (0x10000000)
1764#define MCF_LCDC_LCPR_CC(x) (((x)&0x00000003)<<30)
1765#define MCF_LCDC_LCPR_CC_TRANSPARENT (0x00000000)
1766#define MCF_LCDC_LCPR_CC_OR (0x40000000)
1767#define MCF_LCDC_LCPR_CC_XOR (0x80000000)
1768#define MCF_LCDC_LCPR_CC_AND (0xC0000000)
1769#define MCF_LCDC_LCPR_OP_ON (0x10000000)
1770#define MCF_LCDC_LCPR_OP_OFF (0x00000000)
1771
1772/* Bit definitions and macros for MCF_LCDC_LCWHBR */
1773#define MCF_LCDC_LCWHBR_BD(x) (((x)&0x000000FF)<<0)
1774#define MCF_LCDC_LCWHBR_CH(x) (((x)&0x0000001F)<<16)
1775#define MCF_LCDC_LCWHBR_CW(x) (((x)&0x0000001F)<<24)
1776#define MCF_LCDC_LCWHBR_BK_EN (0x80000000)
1777#define MCF_LCDC_LCWHBR_BK_EN_ON (0x80000000)
1778#define MCF_LCDC_LCWHBR_BK_EN_OFF (0x00000000)
1779
1780/* Bit definitions and macros for MCF_LCDC_LCCMR */
1781#define MCF_LCDC_LCCMR_CUR_COL_B(x) (((x)&0x0000003F)<<0)
1782#define MCF_LCDC_LCCMR_CUR_COL_G(x) (((x)&0x0000003F)<<6)
1783#define MCF_LCDC_LCCMR_CUR_COL_R(x) (((x)&0x0000003F)<<12)
1784
1785/* Bit definitions and macros for MCF_LCDC_LPCR */
1786#define MCF_LCDC_LPCR_PCD(x) (((x)&0x0000003F)<<0)
1787#define MCF_LCDC_LPCR_SHARP (0x00000040)
1788#define MCF_LCDC_LPCR_SCLKSEL (0x00000080)
1789#define MCF_LCDC_LPCR_ACD(x) (((x)&0x0000007F)<<8)
1790#define MCF_LCDC_LPCR_ACDSEL (0x00008000)
1791#define MCF_LCDC_LPCR_REV_VS (0x00010000)
1792#define MCF_LCDC_LPCR_SWAP_SEL (0x00020000)
1793#define MCF_LCDC_LPCR_ENDSEL (0x00040000)
1794#define MCF_LCDC_LPCR_SCLKIDLE (0x00080000)
1795#define MCF_LCDC_LPCR_OEPOL (0x00100000)
1796#define MCF_LCDC_LPCR_CLKPOL (0x00200000)
1797#define MCF_LCDC_LPCR_LPPOL (0x00400000)
1798#define MCF_LCDC_LPCR_FLM (0x00800000)
1799#define MCF_LCDC_LPCR_PIXPOL (0x01000000)
1800#define MCF_LCDC_LPCR_BPIX(x) (((x)&0x00000007)<<25)
1801#define MCF_LCDC_LPCR_PBSIZ(x) (((x)&0x00000003)<<28)
1802#define MCF_LCDC_LPCR_COLOR (0x40000000)
1803#define MCF_LCDC_LPCR_TFT (0x80000000)
1804#define MCF_LCDC_LPCR_MODE_MONOCGROME (0x00000000)
1805#define MCF_LCDC_LPCR_MODE_CSTN (0x40000000)
1806#define MCF_LCDC_LPCR_MODE_TFT (0xC0000000)
1807#define MCF_LCDC_LPCR_PBSIZ_1 (0x00000000)
1808#define MCF_LCDC_LPCR_PBSIZ_2 (0x10000000)
1809#define MCF_LCDC_LPCR_PBSIZ_4 (0x20000000)
1810#define MCF_LCDC_LPCR_PBSIZ_8 (0x30000000)
1811#define MCF_LCDC_LPCR_BPIX_1bpp (0x00000000)
1812#define MCF_LCDC_LPCR_BPIX_2bpp (0x02000000)
1813#define MCF_LCDC_LPCR_BPIX_4bpp (0x04000000)
1814#define MCF_LCDC_LPCR_BPIX_8bpp (0x06000000)
1815#define MCF_LCDC_LPCR_BPIX_12bpp (0x08000000)
1816#define MCF_LCDC_LPCR_BPIX_16bpp (0x0A000000)
1817#define MCF_LCDC_LPCR_BPIX_18bpp (0x0C000000)
1818
1819#define MCF_LCDC_LPCR_PANEL_TYPE(x) (((x)&0x00000003)<<30)
1820
1821/* Bit definitions and macros for MCF_LCDC_LHCR */
1822#define MCF_LCDC_LHCR_H_WAIT_2(x) (((x)&0x000000FF)<<0)
1823#define MCF_LCDC_LHCR_H_WAIT_1(x) (((x)&0x000000FF)<<8)
1824#define MCF_LCDC_LHCR_H_WIDTH(x) (((x)&0x0000003F)<<26)
1825
1826/* Bit definitions and macros for MCF_LCDC_LVCR */
1827#define MCF_LCDC_LVCR_V_WAIT_2(x) (((x)&0x000000FF)<<0)
1828#define MCF_LCDC_LVCR_V_WAIT_1(x) (((x)&0x000000FF)<<8)
1829#define MCF_LCDC_LVCR_V_WIDTH(x) (((x)&0x0000003F)<<26)
1830
1831/* Bit definitions and macros for MCF_LCDC_LPOR */
1832#define MCF_LCDC_LPOR_POS(x) (((x)&0x0000001F)<<0)
1833
1834/* Bit definitions and macros for MCF_LCDC_LPCCR */
1835#define MCF_LCDC_LPCCR_PW(x) (((x)&0x000000FF)<<0)
1836#define MCF_LCDC_LPCCR_CC_EN (0x00000100)
1837#define MCF_LCDC_LPCCR_SCR(x) (((x)&0x00000003)<<9)
1838#define MCF_LCDC_LPCCR_LDMSK (0x00008000)
1839#define MCF_LCDC_LPCCR_CLS_HI_WIDTH(x) (((x)&0x000001FF)<<16)
1840#define MCF_LCDC_LPCCR_SCR_LINEPULSE (0x00000000)
1841#define MCF_LCDC_LPCCR_SCR_PIXELCLK (0x00002000)
1842#define MCF_LCDC_LPCCR_SCR_LCDCLOCK (0x00004000)
1843
1844/* Bit definitions and macros for MCF_LCDC_LDCR */
1845#define MCF_LCDC_LDCR_TM(x) (((x)&0x0000001F)<<0)
1846#define MCF_LCDC_LDCR_HM(x) (((x)&0x0000001F)<<16)
1847#define MCF_LCDC_LDCR_BURST (0x80000000)
1848
1849/* Bit definitions and macros for MCF_LCDC_LRMCR */
1850#define MCF_LCDC_LRMCR_SEL_REF (0x00000001)
1851
1852/* Bit definitions and macros for MCF_LCDC_LICR */
1853#define MCF_LCDC_LICR_INTCON (0x00000001)
1854#define MCF_LCDC_LICR_INTSYN (0x00000004)
1855#define MCF_LCDC_LICR_GW_INT_CON (0x00000010)
1856
1857/* Bit definitions and macros for MCF_LCDC_LIER */
1858#define MCF_LCDC_LIER_BOF_EN (0x00000001)
1859#define MCF_LCDC_LIER_EOF_EN (0x00000002)
1860#define MCF_LCDC_LIER_ERR_RES_EN (0x00000004)
1861#define MCF_LCDC_LIER_UDR_ERR_EN (0x00000008)
1862#define MCF_LCDC_LIER_GW_BOF_EN (0x00000010)
1863#define MCF_LCDC_LIER_GW_EOF_EN (0x00000020)
1864#define MCF_LCDC_LIER_GW_ERR_RES_EN (0x00000040)
1865#define MCF_LCDC_LIER_GW_UDR_ERR_EN (0x00000080)
1866
1867/* Bit definitions and macros for MCF_LCDC_LISR */
1868#define MCF_LCDC_LISR_BOF (0x00000001)
1869#define MCF_LCDC_LISR_EOF (0x00000002)
1870#define MCF_LCDC_LISR_ERR_RES (0x00000004)
1871#define MCF_LCDC_LISR_UDR_ERR (0x00000008)
1872#define MCF_LCDC_LISR_GW_BOF (0x00000010)
1873#define MCF_LCDC_LISR_GW_EOF (0x00000020)
1874#define MCF_LCDC_LISR_GW_ERR_RES (0x00000040)
1875#define MCF_LCDC_LISR_GW_UDR_ERR (0x00000080)
1876
1877/* Bit definitions and macros for MCF_LCDC_LGWSAR */
1878#define MCF_LCDC_LGWSAR_GWSA(x) (((x)&0x3FFFFFFF)<<2)
1879
1880/* Bit definitions and macros for MCF_LCDC_LGWSR */
1881#define MCF_LCDC_LGWSR_GWH(x) (((x)&0x000003FF)<<0)
1882#define MCF_LCDC_LGWSR_GWW(x) (((x)&0x0000003F)<<20)
1883
1884/* Bit definitions and macros for MCF_LCDC_LGWVPWR */
1885#define MCF_LCDC_LGWVPWR_GWVPW(x) (((x)&0x000003FF)<<0)
1886
1887/* Bit definitions and macros for MCF_LCDC_LGWPOR */
1888#define MCF_LCDC_LGWPOR_GWPO(x) (((x)&0x0000001F)<<0)
1889
1890/* Bit definitions and macros for MCF_LCDC_LGWPR */
1891#define MCF_LCDC_LGWPR_GWYP(x) (((x)&0x000003FF)<<0)
1892#define MCF_LCDC_LGWPR_GWXP(x) (((x)&0x000003FF)<<16)
1893
1894/* Bit definitions and macros for MCF_LCDC_LGWCR */
1895#define MCF_LCDC_LGWCR_GWCKB(x) (((x)&0x0000003F)<<0)
1896#define MCF_LCDC_LGWCR_GWCKG(x) (((x)&0x0000003F)<<6)
1897#define MCF_LCDC_LGWCR_GWCKR(x) (((x)&0x0000003F)<<12)
1898#define MCF_LCDC_LGWCR_GW_RVS (0x00200000)
1899#define MCF_LCDC_LGWCR_GWE (0x00400000)
1900#define MCF_LCDC_LGWCR_GWCKE (0x00800000)
1901#define MCF_LCDC_LGWCR_GWAV(x) (((x)&0x000000FF)<<24)
1902
1903/* Bit definitions and macros for MCF_LCDC_LGWDCR */
1904#define MCF_LCDC_LGWDCR_GWTM(x) (((x)&0x0000001F)<<0)
1905#define MCF_LCDC_LGWDCR_GWHM(x) (((x)&0x0000001F)<<16)
1906#define MCF_LCDC_LGWDCR_GWBT (0x80000000)
1907
1908/* Bit definitions and macros for MCF_LCDC_LSCR */
1909#define MCF_LCDC_LSCR_PS_RISE_DELAY(x) (((x)&0x0000003F)<<26)
1910#define MCF_LCDC_LSCR_CLS_RISE_DELAY(x) (((x)&0x000000FF)<<16)
1911#define MCF_LCDC_LSCR_REV_TOGGLE_DELAY(x) (((x)&0x0000000F)<<8)
1912#define MCF_LCDC_LSCR_GRAY_2(x) (((x)&0x0000000F)<<4)
1913#define MCF_LCDC_LSCR_GRAY_1(x) (((x)&0x0000000F)<<0)
1914
1915/* Bit definitions and macros for MCF_LCDC_BPLUT_BASE */
1916#define MCF_LCDC_BPLUT_BASE_BASE(x) (((x)&0xFFFFFFFF)<<0)
1917
1918/* Bit definitions and macros for MCF_LCDC_GWLUT_BASE */
1919#define MCF_LCDC_GWLUT_BASE_BASE(x) (((x)&0xFFFFFFFF)<<0)
1920
1921/********************************************************************* 1103/*********************************************************************
1922 * 1104 *
1923 * Phase Locked Loop (PLL) 1105 * Phase Locked Loop (PLL)
@@ -1925,10 +1107,10 @@
1925 *********************************************************************/ 1107 *********************************************************************/
1926 1108
1927/* Register read/write macros */ 1109/* Register read/write macros */
1928#define MCF_PLL_PODR MCF_REG08(0xFC0C0000) 1110#define MCF_PLL_PODR 0xFC0C0000
1929#define MCF_PLL_PLLCR MCF_REG08(0xFC0C0004) 1111#define MCF_PLL_PLLCR 0xFC0C0004
1930#define MCF_PLL_PMDR MCF_REG08(0xFC0C0008) 1112#define MCF_PLL_PMDR 0xFC0C0008
1931#define MCF_PLL_PFDR MCF_REG08(0xFC0C000C) 1113#define MCF_PLL_PFDR 0xFC0C000C
1932 1114
1933/* Bit definitions and macros for MCF_PLL_PODR */ 1115/* Bit definitions and macros for MCF_PLL_PODR */
1934#define MCF_PLL_PODR_BUSDIV(x) (((x)&0x0F)<<0) 1116#define MCF_PLL_PODR_BUSDIV(x) (((x)&0x0F)<<0)
@@ -1951,15 +1133,15 @@
1951 *********************************************************************/ 1133 *********************************************************************/
1952 1134
1953/* Register read/write macros */ 1135/* Register read/write macros */
1954#define MCF_SCM_MPR MCF_REG32(0xFC000000) 1136#define MCF_SCM_MPR 0xFC000000
1955#define MCF_SCM_PACRA MCF_REG32(0xFC000020) 1137#define MCF_SCM_PACRA 0xFC000020
1956#define MCF_SCM_PACRB MCF_REG32(0xFC000024) 1138#define MCF_SCM_PACRB 0xFC000024
1957#define MCF_SCM_PACRC MCF_REG32(0xFC000028) 1139#define MCF_SCM_PACRC 0xFC000028
1958#define MCF_SCM_PACRD MCF_REG32(0xFC00002C) 1140#define MCF_SCM_PACRD 0xFC00002C
1959#define MCF_SCM_PACRE MCF_REG32(0xFC000040) 1141#define MCF_SCM_PACRE 0xFC000040
1960#define MCF_SCM_PACRF MCF_REG32(0xFC000044) 1142#define MCF_SCM_PACRF 0xFC000044
1961 1143
1962#define MCF_SCM_BCR MCF_REG32(0xFC040024) 1144#define MCF_SCM_BCR 0xFC040024
1963 1145
1964/********************************************************************* 1146/*********************************************************************
1965 * 1147 *
@@ -1968,17 +1150,16 @@
1968 *********************************************************************/ 1150 *********************************************************************/
1969 1151
1970/* Register read/write macros */ 1152/* Register read/write macros */
1971#define MCF_SDRAMC_SDMR MCF_REG32(0xFC0B8000) 1153#define MCF_SDRAMC_SDMR 0xFC0B8000
1972#define MCF_SDRAMC_SDCR MCF_REG32(0xFC0B8004) 1154#define MCF_SDRAMC_SDCR 0xFC0B8004
1973#define MCF_SDRAMC_SDCFG1 MCF_REG32(0xFC0B8008) 1155#define MCF_SDRAMC_SDCFG1 0xFC0B8008
1974#define MCF_SDRAMC_SDCFG2 MCF_REG32(0xFC0B800C) 1156#define MCF_SDRAMC_SDCFG2 0xFC0B800C
1975#define MCF_SDRAMC_LIMP_FIX MCF_REG32(0xFC0B8080) 1157#define MCF_SDRAMC_LIMP_FIX 0xFC0B8080
1976#define MCF_SDRAMC_SDDS MCF_REG32(0xFC0B8100) 1158#define MCF_SDRAMC_SDDS 0xFC0B8100
1977#define MCF_SDRAMC_SDCS0 MCF_REG32(0xFC0B8110) 1159#define MCF_SDRAMC_SDCS0 0xFC0B8110
1978#define MCF_SDRAMC_SDCS1 MCF_REG32(0xFC0B8114) 1160#define MCF_SDRAMC_SDCS1 0xFC0B8114
1979#define MCF_SDRAMC_SDCS2 MCF_REG32(0xFC0B8118) 1161#define MCF_SDRAMC_SDCS2 0xFC0B8118
1980#define MCF_SDRAMC_SDCS3 MCF_REG32(0xFC0B811C) 1162#define MCF_SDRAMC_SDCS3 0xFC0B811C
1981#define MCF_SDRAMC_SDCS(x) MCF_REG32(0xFC0B8110+((x)*0x004))
1982 1163
1983/* Bit definitions and macros for MCF_SDRAMC_SDMR */ 1164/* Bit definitions and macros for MCF_SDRAMC_SDMR */
1984#define MCF_SDRAMC_SDMR_CMD (0x00010000) 1165#define MCF_SDRAMC_SDMR_CMD (0x00010000)
@@ -2046,143 +1227,9 @@
2046#define MCF_SDRAMC_SDCS_CSSZ_2GBYTE (0x0000001E) 1227#define MCF_SDRAMC_SDCS_CSSZ_2GBYTE (0x0000001E)
2047#define MCF_SDRAMC_SDCS_CSSZ_4GBYTE (0x0000001F) 1228#define MCF_SDRAMC_SDCS_CSSZ_4GBYTE (0x0000001F)
2048 1229
2049/*********************************************************************
2050 *
2051 * FlexCAN module registers
2052 *
2053 *********************************************************************/
2054#define MCF_FLEXCAN_BASEADDR(x) (0xFC020000+(x)*0x0800)
2055#define MCF_FLEXCAN_CANMCR(x) MCF_REG32(0xFC020000+(x)*0x0800+0x00)
2056#define MCF_FLEXCAN_CANCTRL(x) MCF_REG32(0xFC020000+(x)*0x0800+0x04)
2057#define MCF_FLEXCAN_TIMER(x) MCF_REG32(0xFC020000+(x)*0x0800+0x08)
2058#define MCF_FLEXCAN_RXGMASK(x) MCF_REG32(0xFC020000+(x)*0x0800+0x10)
2059#define MCF_FLEXCAN_RX14MASK(x) MCF_REG32(0xFC020000+(x)*0x0800+0x14)
2060#define MCF_FLEXCAN_RX15MASK(x) MCF_REG32(0xFC020000+(x)*0x0800+0x18)
2061#define MCF_FLEXCAN_ERRCNT(x) MCF_REG32(0xFC020000+(x)*0x0800+0x1C)
2062#define MCF_FLEXCAN_ERRSTAT(x) MCF_REG32(0xFC020000+(x)*0x0800+0x20)
2063#define MCF_FLEXCAN_IMASK(x) MCF_REG32(0xFC020000+(x)*0x0800+0x28)
2064#define MCF_FLEXCAN_IFLAG(x) MCF_REG32(0xFC020000+(x)*0x0800+0x30)
2065
2066#define MCF_FLEXCAN_MB_CNT(x,y) MCF_REG32(0xFC020080+(x)*0x0800+(y)*0x10+0x0)
2067#define MCF_FLEXCAN_MB_ID(x,y) MCF_REG32(0xFC020080+(x)*0x0800+(y)*0x10+0x4)
2068#define MCF_FLEXCAN_MB_DB(x,y,z) MCF_REG08(0xFC020080+(x)*0x0800+(y)*0x10+0x8+(z)*0x1)
2069
2070/*
2071 * FlexCAN Module Configuration Register
2072 */
2073#define CANMCR_MDIS (0x80000000)
2074#define CANMCR_FRZ (0x40000000)
2075#define CANMCR_HALT (0x10000000)
2076#define CANMCR_SOFTRST (0x02000000)
2077#define CANMCR_FRZACK (0x01000000)
2078#define CANMCR_SUPV (0x00800000)
2079#define CANMCR_MAXMB(x) ((x)&0x0F)
2080
2081/*
2082 * FlexCAN Control Register
2083 */
2084#define CANCTRL_PRESDIV(x) (((x)&0xFF)<<24)
2085#define CANCTRL_RJW(x) (((x)&0x03)<<22)
2086#define CANCTRL_PSEG1(x) (((x)&0x07)<<19)
2087#define CANCTRL_PSEG2(x) (((x)&0x07)<<16)
2088#define CANCTRL_BOFFMSK (0x00008000)
2089#define CANCTRL_ERRMSK (0x00004000)
2090#define CANCTRL_CLKSRC (0x00002000)
2091#define CANCTRL_LPB (0x00001000)
2092#define CANCTRL_SAMP (0x00000080)
2093#define CANCTRL_BOFFREC (0x00000040)
2094#define CANCTRL_TSYNC (0x00000020)
2095#define CANCTRL_LBUF (0x00000010)
2096#define CANCTRL_LOM (0x00000008)
2097#define CANCTRL_PROPSEG(x) ((x)&0x07)
2098
2099/*
2100 * FlexCAN Error Counter Register
2101 */
2102#define ERRCNT_RXECTR(x) (((x)&0xFF)<<8)
2103#define ERRCNT_TXECTR(x) ((x)&0xFF)
2104
2105/*
2106 * FlexCAN Error and Status Register
2107 */
2108#define ERRSTAT_BITERR(x) (((x)&0x03)<<14)
2109#define ERRSTAT_ACKERR (0x00002000)
2110#define ERRSTAT_CRCERR (0x00001000)
2111#define ERRSTAT_FRMERR (0x00000800)
2112#define ERRSTAT_STFERR (0x00000400)
2113#define ERRSTAT_TXWRN (0x00000200)
2114#define ERRSTAT_RXWRN (0x00000100)
2115#define ERRSTAT_IDLE (0x00000080)
2116#define ERRSTAT_TXRX (0x00000040)
2117#define ERRSTAT_FLTCONF(x) (((x)&0x03)<<4)
2118#define ERRSTAT_BOFFINT (0x00000004)
2119#define ERRSTAT_ERRINT (0x00000002)
2120
2121/* 1230/*
2122 * Interrupt Mask Register
2123 */
2124#define IMASK_BUF15M (0x8000)
2125#define IMASK_BUF14M (0x4000)
2126#define IMASK_BUF13M (0x2000)
2127#define IMASK_BUF12M (0x1000)
2128#define IMASK_BUF11M (0x0800)
2129#define IMASK_BUF10M (0x0400)
2130#define IMASK_BUF9M (0x0200)
2131#define IMASK_BUF8M (0x0100)
2132#define IMASK_BUF7M (0x0080)
2133#define IMASK_BUF6M (0x0040)
2134#define IMASK_BUF5M (0x0020)
2135#define IMASK_BUF4M (0x0010)
2136#define IMASK_BUF3M (0x0008)
2137#define IMASK_BUF2M (0x0004)
2138#define IMASK_BUF1M (0x0002)
2139#define IMASK_BUF0M (0x0001)
2140#define IMASK_BUFnM(x) (0x1<<(x))
2141#define IMASK_BUFF_ENABLE_ALL (0x1111)
2142#define IMASK_BUFF_DISABLE_ALL (0x0000)
2143
2144/*
2145 * Interrupt Flag Register
2146 */
2147#define IFLAG_BUF15M (0x8000)
2148#define IFLAG_BUF14M (0x4000)
2149#define IFLAG_BUF13M (0x2000)
2150#define IFLAG_BUF12M (0x1000)
2151#define IFLAG_BUF11M (0x0800)
2152#define IFLAG_BUF10M (0x0400)
2153#define IFLAG_BUF9M (0x0200)
2154#define IFLAG_BUF8M (0x0100)
2155#define IFLAG_BUF7M (0x0080)
2156#define IFLAG_BUF6M (0x0040)
2157#define IFLAG_BUF5M (0x0020)
2158#define IFLAG_BUF4M (0x0010)
2159#define IFLAG_BUF3M (0x0008)
2160#define IFLAG_BUF2M (0x0004)
2161#define IFLAG_BUF1M (0x0002)
2162#define IFLAG_BUF0M (0x0001)
2163#define IFLAG_BUFF_SET_ALL (0xFFFF)
2164#define IFLAG_BUFF_CLEAR_ALL (0x0000)
2165#define IFLAG_BUFnM(x) (0x1<<(x))
2166
2167/*
2168 * Message Buffers
2169 */
2170#define MB_CNT_CODE(x) (((x)&0x0F)<<24)
2171#define MB_CNT_SRR (0x00400000)
2172#define MB_CNT_IDE (0x00200000)
2173#define MB_CNT_RTR (0x00100000)
2174#define MB_CNT_LENGTH(x) (((x)&0x0F)<<16)
2175#define MB_CNT_TIMESTAMP(x) ((x)&0xFFFF)
2176#define MB_ID_STD(x) (((x)&0x07FF)<<18)
2177#define MB_ID_EXT(x) ((x)&0x3FFFF)
2178
2179/*********************************************************************
2180 *
2181 * Edge Port Module (EPORT) 1231 * Edge Port Module (EPORT)
2182 * 1232 */
2183 *********************************************************************/
2184
2185/* Register read/write macros */
2186#define MCFEPORT_EPPAR (0xFC094000) 1233#define MCFEPORT_EPPAR (0xFC094000)
2187#define MCFEPORT_EPDDR (0xFC094002) 1234#define MCFEPORT_EPDDR (0xFC094002)
2188#define MCFEPORT_EPIER (0xFC094003) 1235#define MCFEPORT_EPIER (0xFC094003)
@@ -2190,91 +1237,5 @@
2190#define MCFEPORT_EPPDR (0xFC094005) 1237#define MCFEPORT_EPPDR (0xFC094005)
2191#define MCFEPORT_EPFR (0xFC094006) 1238#define MCFEPORT_EPFR (0xFC094006)
2192 1239
2193/* Bit definitions and macros for MCF_EPORT_EPPAR */
2194#define MCF_EPORT_EPPAR_EPPA1(x) (((x)&0x0003)<<2)
2195#define MCF_EPORT_EPPAR_EPPA2(x) (((x)&0x0003)<<4)
2196#define MCF_EPORT_EPPAR_EPPA3(x) (((x)&0x0003)<<6)
2197#define MCF_EPORT_EPPAR_EPPA4(x) (((x)&0x0003)<<8)
2198#define MCF_EPORT_EPPAR_EPPA5(x) (((x)&0x0003)<<10)
2199#define MCF_EPORT_EPPAR_EPPA6(x) (((x)&0x0003)<<12)
2200#define MCF_EPORT_EPPAR_EPPA7(x) (((x)&0x0003)<<14)
2201#define MCF_EPORT_EPPAR_LEVEL (0)
2202#define MCF_EPORT_EPPAR_RISING (1)
2203#define MCF_EPORT_EPPAR_FALLING (2)
2204#define MCF_EPORT_EPPAR_BOTH (3)
2205#define MCF_EPORT_EPPAR_EPPA7_LEVEL (0x0000)
2206#define MCF_EPORT_EPPAR_EPPA7_RISING (0x4000)
2207#define MCF_EPORT_EPPAR_EPPA7_FALLING (0x8000)
2208#define MCF_EPORT_EPPAR_EPPA7_BOTH (0xC000)
2209#define MCF_EPORT_EPPAR_EPPA6_LEVEL (0x0000)
2210#define MCF_EPORT_EPPAR_EPPA6_RISING (0x1000)
2211#define MCF_EPORT_EPPAR_EPPA6_FALLING (0x2000)
2212#define MCF_EPORT_EPPAR_EPPA6_BOTH (0x3000)
2213#define MCF_EPORT_EPPAR_EPPA5_LEVEL (0x0000)
2214#define MCF_EPORT_EPPAR_EPPA5_RISING (0x0400)
2215#define MCF_EPORT_EPPAR_EPPA5_FALLING (0x0800)
2216#define MCF_EPORT_EPPAR_EPPA5_BOTH (0x0C00)
2217#define MCF_EPORT_EPPAR_EPPA4_LEVEL (0x0000)
2218#define MCF_EPORT_EPPAR_EPPA4_RISING (0x0100)
2219#define MCF_EPORT_EPPAR_EPPA4_FALLING (0x0200)
2220#define MCF_EPORT_EPPAR_EPPA4_BOTH (0x0300)
2221#define MCF_EPORT_EPPAR_EPPA3_LEVEL (0x0000)
2222#define MCF_EPORT_EPPAR_EPPA3_RISING (0x0040)
2223#define MCF_EPORT_EPPAR_EPPA3_FALLING (0x0080)
2224#define MCF_EPORT_EPPAR_EPPA3_BOTH (0x00C0)
2225#define MCF_EPORT_EPPAR_EPPA2_LEVEL (0x0000)
2226#define MCF_EPORT_EPPAR_EPPA2_RISING (0x0010)
2227#define MCF_EPORT_EPPAR_EPPA2_FALLING (0x0020)
2228#define MCF_EPORT_EPPAR_EPPA2_BOTH (0x0030)
2229#define MCF_EPORT_EPPAR_EPPA1_LEVEL (0x0000)
2230#define MCF_EPORT_EPPAR_EPPA1_RISING (0x0004)
2231#define MCF_EPORT_EPPAR_EPPA1_FALLING (0x0008)
2232#define MCF_EPORT_EPPAR_EPPA1_BOTH (0x000C)
2233
2234/* Bit definitions and macros for MCF_EPORT_EPDDR */
2235#define MCF_EPORT_EPDDR_EPDD1 (0x02)
2236#define MCF_EPORT_EPDDR_EPDD2 (0x04)
2237#define MCF_EPORT_EPDDR_EPDD3 (0x08)
2238#define MCF_EPORT_EPDDR_EPDD4 (0x10)
2239#define MCF_EPORT_EPDDR_EPDD5 (0x20)
2240#define MCF_EPORT_EPDDR_EPDD6 (0x40)
2241#define MCF_EPORT_EPDDR_EPDD7 (0x80)
2242
2243/* Bit definitions and macros for MCF_EPORT_EPIER */
2244#define MCF_EPORT_EPIER_EPIE1 (0x02)
2245#define MCF_EPORT_EPIER_EPIE2 (0x04)
2246#define MCF_EPORT_EPIER_EPIE3 (0x08)
2247#define MCF_EPORT_EPIER_EPIE4 (0x10)
2248#define MCF_EPORT_EPIER_EPIE5 (0x20)
2249#define MCF_EPORT_EPIER_EPIE6 (0x40)
2250#define MCF_EPORT_EPIER_EPIE7 (0x80)
2251
2252/* Bit definitions and macros for MCF_EPORT_EPDR */
2253#define MCF_EPORT_EPDR_EPD1 (0x02)
2254#define MCF_EPORT_EPDR_EPD2 (0x04)
2255#define MCF_EPORT_EPDR_EPD3 (0x08)
2256#define MCF_EPORT_EPDR_EPD4 (0x10)
2257#define MCF_EPORT_EPDR_EPD5 (0x20)
2258#define MCF_EPORT_EPDR_EPD6 (0x40)
2259#define MCF_EPORT_EPDR_EPD7 (0x80)
2260
2261/* Bit definitions and macros for MCF_EPORT_EPPDR */
2262#define MCF_EPORT_EPPDR_EPPD1 (0x02)
2263#define MCF_EPORT_EPPDR_EPPD2 (0x04)
2264#define MCF_EPORT_EPPDR_EPPD3 (0x08)
2265#define MCF_EPORT_EPPDR_EPPD4 (0x10)
2266#define MCF_EPORT_EPPDR_EPPD5 (0x20)
2267#define MCF_EPORT_EPPDR_EPPD6 (0x40)
2268#define MCF_EPORT_EPPDR_EPPD7 (0x80)
2269
2270/* Bit definitions and macros for MCF_EPORT_EPFR */
2271#define MCF_EPORT_EPFR_EPF1 (0x02)
2272#define MCF_EPORT_EPFR_EPF2 (0x04)
2273#define MCF_EPORT_EPFR_EPF3 (0x08)
2274#define MCF_EPORT_EPFR_EPF4 (0x10)
2275#define MCF_EPORT_EPFR_EPF5 (0x20)
2276#define MCF_EPORT_EPFR_EPF6 (0x40)
2277#define MCF_EPORT_EPFR_EPF7 (0x80)
2278
2279/********************************************************************/ 1240/********************************************************************/
2280#endif /* m532xsim_h */ 1241#endif /* m532xsim_h */
diff --git a/arch/m68k/include/asm/m5407sim.h b/arch/m68k/include/asm/m5407sim.h
index 79f58dd6a83d..a7550bc5cd1e 100644
--- a/arch/m68k/include/asm/m5407sim.h
+++ b/arch/m68k/include/asm/m5407sim.h
@@ -23,55 +23,55 @@
23/* 23/*
24 * Define the 5407 SIM register set addresses. 24 * Define the 5407 SIM register set addresses.
25 */ 25 */
26#define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */ 26#define MCFSIM_RSR (MCF_MBAR + 0x00) /* Reset Status */
27#define MCFSIM_SYPCR 0x01 /* System Protection reg (r/w)*/ 27#define MCFSIM_SYPCR (MCF_MBAR + 0x01) /* System Protection */
28#define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */ 28#define MCFSIM_SWIVR (MCF_MBAR + 0x02) /* SW Watchdog intr */
29#define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */ 29#define MCFSIM_SWSR (MCF_MBAR + 0x03) /* SW Watchdog service*/
30#define MCFSIM_PAR 0x04 /* Pin Assignment reg (r/w) */ 30#define MCFSIM_PAR (MCF_MBAR + 0x04) /* Pin Assignment */
31#define MCFSIM_IRQPAR 0x06 /* Interrupt Assignment reg (r/w) */ 31#define MCFSIM_IRQPAR (MCF_MBAR + 0x06) /* Intr Assignment */
32#define MCFSIM_PLLCR 0x08 /* PLL Control Reg*/ 32#define MCFSIM_PLLCR (MCF_MBAR + 0x08) /* PLL Ctrl */
33#define MCFSIM_MPARK 0x0C /* BUS Master Control Reg*/ 33#define MCFSIM_MPARK (MCF_MBAR + 0x0C) /* BUS Master Ctrl */
34#define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */ 34#define MCFSIM_IPR (MCF_MBAR + 0x40) /* Interrupt Pending */
35#define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */ 35#define MCFSIM_IMR (MCF_MBAR + 0x44) /* Interrupt Mask */
36#define MCFSIM_AVR 0x4b /* Autovector Ctrl reg (r/w) */ 36#define MCFSIM_AVR (MCF_MBAR + 0x4b) /* Autovector Ctrl */
37#define MCFSIM_ICR0 0x4c /* Intr Ctrl reg 0 (r/w) */ 37#define MCFSIM_ICR0 (MCF_MBAR + 0x4c) /* Intr Ctrl reg 0 */
38#define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */ 38#define MCFSIM_ICR1 (MCF_MBAR + 0x4d) /* Intr Ctrl reg 1 */
39#define MCFSIM_ICR2 0x4e /* Intr Ctrl reg 2 (r/w) */ 39#define MCFSIM_ICR2 (MCF_MBAR + 0x4e) /* Intr Ctrl reg 2 */
40#define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */ 40#define MCFSIM_ICR3 (MCF_MBAR + 0x4f) /* Intr Ctrl reg 3 */
41#define MCFSIM_ICR4 0x50 /* Intr Ctrl reg 4 (r/w) */ 41#define MCFSIM_ICR4 (MCF_MBAR + 0x50) /* Intr Ctrl reg 4 */
42#define MCFSIM_ICR5 0x51 /* Intr Ctrl reg 5 (r/w) */ 42#define MCFSIM_ICR5 (MCF_MBAR + 0x51) /* Intr Ctrl reg 5 */
43#define MCFSIM_ICR6 0x52 /* Intr Ctrl reg 6 (r/w) */ 43#define MCFSIM_ICR6 (MCF_MBAR + 0x52) /* Intr Ctrl reg 6 */
44#define MCFSIM_ICR7 0x53 /* Intr Ctrl reg 7 (r/w) */ 44#define MCFSIM_ICR7 (MCF_MBAR + 0x53) /* Intr Ctrl reg 7 */
45#define MCFSIM_ICR8 0x54 /* Intr Ctrl reg 8 (r/w) */ 45#define MCFSIM_ICR8 (MCF_MBAR + 0x54) /* Intr Ctrl reg 8 */
46#define MCFSIM_ICR9 0x55 /* Intr Ctrl reg 9 (r/w) */ 46#define MCFSIM_ICR9 (MCF_MBAR + 0x55) /* Intr Ctrl reg 9 */
47#define MCFSIM_ICR10 0x56 /* Intr Ctrl reg 10 (r/w) */ 47#define MCFSIM_ICR10 (MCF_MBAR + 0x56) /* Intr Ctrl reg 10 */
48#define MCFSIM_ICR11 0x57 /* Intr Ctrl reg 11 (r/w) */ 48#define MCFSIM_ICR11 (MCF_MBAR + 0x57) /* Intr Ctrl reg 11 */
49 49
50#define MCFSIM_CSAR0 0x80 /* CS 0 Address 0 reg (r/w) */ 50#define MCFSIM_CSAR0 (MCF_MBAR + 0x80) /* CS 0 Address reg */
51#define MCFSIM_CSMR0 0x84 /* CS 0 Mask 0 reg (r/w) */ 51#define MCFSIM_CSMR0 (MCF_MBAR + 0x84) /* CS 0 Mask reg */
52#define MCFSIM_CSCR0 0x8a /* CS 0 Control reg (r/w) */ 52#define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */
53#define MCFSIM_CSAR1 0x8c /* CS 1 Address reg (r/w) */ 53#define MCFSIM_CSAR1 (MCF_MBAR + 0x8c) /* CS 1 Address reg */
54#define MCFSIM_CSMR1 0x90 /* CS 1 Mask reg (r/w) */ 54#define MCFSIM_CSMR1 (MCF_MBAR + 0x90) /* CS 1 Mask reg */
55#define MCFSIM_CSCR1 0x96 /* CS 1 Control reg (r/w) */ 55#define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */
56 56
57#define MCFSIM_CSAR2 0x98 /* CS 2 Address reg (r/w) */ 57#define MCFSIM_CSAR2 (MCF_MBAR + 0x98) /* CS 2 Address reg */
58#define MCFSIM_CSMR2 0x9c /* CS 2 Mask reg (r/w) */ 58#define MCFSIM_CSMR2 (MCF_MBAR + 0x9c) /* CS 2 Mask reg */
59#define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */ 59#define MCFSIM_CSCR2 (MCF_MBAR + 0xa2) /* CS 2 Control reg */
60#define MCFSIM_CSAR3 0xa4 /* CS 3 Address reg (r/w) */ 60#define MCFSIM_CSAR3 (MCF_MBAR + 0xa4) /* CS 3 Address reg */
61#define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */ 61#define MCFSIM_CSMR3 (MCF_MBAR + 0xa8) /* CS 3 Mask reg */
62#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */ 62#define MCFSIM_CSCR3 (MCF_MBAR + 0xae) /* CS 3 Control reg */
63#define MCFSIM_CSAR4 0xb0 /* CS 4 Address reg (r/w) */ 63#define MCFSIM_CSAR4 (MCF_MBAR + 0xb0) /* CS 4 Address reg */
64#define MCFSIM_CSMR4 0xb4 /* CS 4 Mask reg (r/w) */ 64#define MCFSIM_CSMR4 (MCF_MBAR + 0xb4) /* CS 4 Mask reg */
65#define MCFSIM_CSCR4 0xba /* CS 4 Control reg (r/w) */ 65#define MCFSIM_CSCR4 (MCF_MBAR + 0xba) /* CS 4 Control reg */
66#define MCFSIM_CSAR5 0xbc /* CS 5 Address reg (r/w) */ 66#define MCFSIM_CSAR5 (MCF_MBAR + 0xbc) /* CS 5 Address reg */
67#define MCFSIM_CSMR5 0xc0 /* CS 5 Mask reg (r/w) */ 67#define MCFSIM_CSMR5 (MCF_MBAR + 0xc0) /* CS 5 Mask reg */
68#define MCFSIM_CSCR5 0xc6 /* CS 5 Control reg (r/w) */ 68#define MCFSIM_CSCR5 (MCF_MBAR + 0xc6) /* CS 5 Control reg */
69#define MCFSIM_CSAR6 0xc8 /* CS 6 Address reg (r/w) */ 69#define MCFSIM_CSAR6 (MCF_MBAR + 0xc8) /* CS 6 Address reg */
70#define MCFSIM_CSMR6 0xcc /* CS 6 Mask reg (r/w) */ 70#define MCFSIM_CSMR6 (MCF_MBAR + 0xcc) /* CS 6 Mask reg */
71#define MCFSIM_CSCR6 0xd2 /* CS 6 Control reg (r/w) */ 71#define MCFSIM_CSCR6 (MCF_MBAR + 0xd2) /* CS 6 Control reg */
72#define MCFSIM_CSAR7 0xd4 /* CS 7 Address reg (r/w) */ 72#define MCFSIM_CSAR7 (MCF_MBAR + 0xd4) /* CS 7 Address reg */
73#define MCFSIM_CSMR7 0xd8 /* CS 7 Mask reg (r/w) */ 73#define MCFSIM_CSMR7 (MCF_MBAR + 0xd8) /* CS 7 Mask reg */
74#define MCFSIM_CSCR7 0xde /* CS 7 Control reg (r/w) */ 74#define MCFSIM_CSCR7 (MCF_MBAR + 0xde) /* CS 7 Control reg */
75 75
76#define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */ 76#define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */
77#define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM 0 Addr/Ctrl */ 77#define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM 0 Addr/Ctrl */
@@ -102,9 +102,9 @@
102/* 102/*
103 * Generic GPIO support 103 * Generic GPIO support
104 */ 104 */
105#define MCFGPIO_PIN_MAX 16 105#define MCFGPIO_PIN_MAX 16
106#define MCFGPIO_IRQ_MAX -1 106#define MCFGPIO_IRQ_MAX -1
107#define MCFGPIO_IRQ_VECBASE -1 107#define MCFGPIO_IRQ_VECBASE -1
108 108
109/* 109/*
110 * Some symbol defines for the above... 110 * Some symbol defines for the above...
@@ -130,9 +130,9 @@
130/* 130/*
131 * Defines for the IRQPAR Register 131 * Defines for the IRQPAR Register
132 */ 132 */
133#define IRQ5_LEVEL4 0x80 133#define IRQ5_LEVEL4 0x80
134#define IRQ3_LEVEL6 0x40 134#define IRQ3_LEVEL6 0x40
135#define IRQ1_LEVEL2 0x20 135#define IRQ1_LEVEL2 0x20
136 136
137/* 137/*
138 * Define system peripheral IRQ usage. 138 * Define system peripheral IRQ usage.
diff --git a/arch/m68k/include/asm/m54xxgpt.h b/arch/m68k/include/asm/m54xxgpt.h
index df75dd87ae7a..0b69cd1ed0ed 100644
--- a/arch/m68k/include/asm/m54xxgpt.h
+++ b/arch/m68k/include/asm/m54xxgpt.h
@@ -16,26 +16,26 @@
16*********************************************************************/ 16*********************************************************************/
17 17
18/* Register read/write macros */ 18/* Register read/write macros */
19#define MCF_GPT_GMS0 0x000800 19#define MCF_GPT_GMS0 (MCF_MBAR + 0x000800)
20#define MCF_GPT_GCIR0 0x000804 20#define MCF_GPT_GCIR0 (MCF_MBAR + 0x000804)
21#define MCF_GPT_GPWM0 0x000808 21#define MCF_GPT_GPWM0 (MCF_MBAR + 0x000808)
22#define MCF_GPT_GSR0 0x00080C 22#define MCF_GPT_GSR0 (MCF_MBAR + 0x00080C)
23#define MCF_GPT_GMS1 0x000810 23#define MCF_GPT_GMS1 (MCF_MBAR + 0x000810)
24#define MCF_GPT_GCIR1 0x000814 24#define MCF_GPT_GCIR1 (MCF_MBAR + 0x000814)
25#define MCF_GPT_GPWM1 0x000818 25#define MCF_GPT_GPWM1 (MCF_MBAR + 0x000818)
26#define MCF_GPT_GSR1 0x00081C 26#define MCF_GPT_GSR1 (MCF_MBAR + 0x00081C)
27#define MCF_GPT_GMS2 0x000820 27#define MCF_GPT_GMS2 (MCF_MBAR + 0x000820)
28#define MCF_GPT_GCIR2 0x000824 28#define MCF_GPT_GCIR2 (MCF_MBAR + 0x000824)
29#define MCF_GPT_GPWM2 0x000828 29#define MCF_GPT_GPWM2 (MCF_MBAR + 0x000828)
30#define MCF_GPT_GSR2 0x00082C 30#define MCF_GPT_GSR2 (MCF_MBAR + 0x00082C)
31#define MCF_GPT_GMS3 0x000830 31#define MCF_GPT_GMS3 (MCF_MBAR + 0x000830)
32#define MCF_GPT_GCIR3 0x000834 32#define MCF_GPT_GCIR3 (MCF_MBAR + 0x000834)
33#define MCF_GPT_GPWM3 0x000838 33#define MCF_GPT_GPWM3 (MCF_MBAR + 0x000838)
34#define MCF_GPT_GSR3 0x00083C 34#define MCF_GPT_GSR3 (MCF_MBAR + 0x00083C)
35#define MCF_GPT_GMS(x) (0x000800+((x)*0x010)) 35#define MCF_GPT_GMS(x) (MCF_MBAR + 0x000800 + ((x) * 0x010))
36#define MCF_GPT_GCIR(x) (0x000804+((x)*0x010)) 36#define MCF_GPT_GCIR(x) (MCF_MBAR + 0x000804 + ((x) * 0x010))
37#define MCF_GPT_GPWM(x) (0x000808+((x)*0x010)) 37#define MCF_GPT_GPWM(x) (MCF_MBAR + 0x000808 + ((x) * 0x010))
38#define MCF_GPT_GSR(x) (0x00080C+((x)*0x010)) 38#define MCF_GPT_GSR(x) (MCF_MBAR + 0x00080C + ((x) * 0x010))
39 39
40/* Bit definitions and macros for MCF_GPT_GMS */ 40/* Bit definitions and macros for MCF_GPT_GMS */
41#define MCF_GPT_GMS_TMS(x) (((x)&0x00000007)<<0) 41#define MCF_GPT_GMS_TMS(x) (((x)&0x00000007)<<0)
diff --git a/arch/m68k/include/asm/m54xxsim.h b/arch/m68k/include/asm/m54xxsim.h
index d3c5e0dbdadf..d3bd83887429 100644
--- a/arch/m68k/include/asm/m54xxsim.h
+++ b/arch/m68k/include/asm/m54xxsim.h
@@ -47,6 +47,12 @@
47#define MCF_IRQ_UART3 (MCFINT_VECBASE + 32) 47#define MCF_IRQ_UART3 (MCFINT_VECBASE + 32)
48 48
49/* 49/*
50 * Slice Timer support.
51 */
52#define MCFSLT_TIMER0 (MCF_MBAR + 0x900) /* Base addr TIMER0 */
53#define MCFSLT_TIMER1 (MCF_MBAR + 0x910) /* Base addr TIMER1 */
54
55/*
50 * Generic GPIO support 56 * Generic GPIO support
51 */ 57 */
52#define MCFGPIO_PIN_MAX 0 /* I am too lazy to count */ 58#define MCFGPIO_PIN_MAX 0 /* I am too lazy to count */
@@ -64,15 +70,25 @@
64#define MCFEPORT_EPFR (MCF_MBAR + 0xf0c) /* Flags */ 70#define MCFEPORT_EPFR (MCF_MBAR + 0xf0c) /* Flags */
65 71
66/* 72/*
67 * Some PSC related definitions 73 * Pin Assignment register definitions
68 */ 74 */
69#define MCF_PAR_PSC(x) (0x000A4F-((x)&0x3)) 75#define MCFGPIO_PAR_FBCTL (MCF_MBAR + 0xA40)
76#define MCFGPIO_PAR_FBCS (MCF_MBAR + 0xA42)
77#define MCFGPIO_PAR_DMA (MCF_MBAR + 0xA43)
78#define MCFGPIO_PAR_FECI2CIRQ (MCF_MBAR + 0xA44)
79#define MCFGPIO_PAR_PCIBG (MCF_MBAR + 0xA48) /* PCI bus grant */
80#define MCFGPIO_PAR_PCIBR (MCF_MBAR + 0xA4A) /* PCI */
81#define MCFGPIO_PAR_PSC0 (MCF_MBAR + 0xA4F)
82#define MCFGPIO_PAR_PSC1 (MCF_MBAR + 0xA4E)
83#define MCFGPIO_PAR_PSC2 (MCF_MBAR + 0xA4D)
84#define MCFGPIO_PAR_PSC3 (MCF_MBAR + 0xA4C)
85#define MCFGPIO_PAR_DSPI (MCF_MBAR + 0xA50)
86#define MCFGPIO_PAR_TIMER (MCF_MBAR + 0xA52)
87
70#define MCF_PAR_SDA (0x0008) 88#define MCF_PAR_SDA (0x0008)
71#define MCF_PAR_SCL (0x0004) 89#define MCF_PAR_SCL (0x0004)
72#define MCF_PAR_PSC_TXD (0x04) 90#define MCF_PAR_PSC_TXD (0x04)
73#define MCF_PAR_PSC_RXD (0x08) 91#define MCF_PAR_PSC_RXD (0x08)
74#define MCF_PAR_PSC_RTS(x) (((x)&0x03)<<4)
75#define MCF_PAR_PSC_CTS(x) (((x)&0x03)<<6)
76#define MCF_PAR_PSC_CTS_GPIO (0x00) 92#define MCF_PAR_PSC_CTS_GPIO (0x00)
77#define MCF_PAR_PSC_CTS_BCLK (0x80) 93#define MCF_PAR_PSC_CTS_BCLK (0x80)
78#define MCF_PAR_PSC_CTS_CTS (0xC0) 94#define MCF_PAR_PSC_CTS_CTS (0xC0)
@@ -81,7 +97,4 @@
81#define MCF_PAR_PSC_RTS_RTS (0x30) 97#define MCF_PAR_PSC_RTS_RTS (0x30)
82#define MCF_PAR_PSC_CANRX (0x40) 98#define MCF_PAR_PSC_CANRX (0x40)
83 99
84#define MCF_PAR_PCIBG (CONFIG_MBAR + 0xa48) /* PCI bus grant */
85#define MCF_PAR_PCIBR (CONFIG_MBAR + 0xa4a) /* PCI */
86
87#endif /* m54xxsim_h */ 100#endif /* m54xxsim_h */
diff --git a/arch/m68k/include/asm/m68360.h b/arch/m68k/include/asm/m68360.h
index eb7d39ef2855..4664180a3ab3 100644
--- a/arch/m68k/include/asm/m68360.h
+++ b/arch/m68k/include/asm/m68360.h
@@ -1,7 +1,7 @@
1#include "m68360_regs.h" 1#include <asm/m68360_regs.h>
2#include "m68360_pram.h" 2#include <asm/m68360_pram.h>
3#include "m68360_quicc.h" 3#include <asm/m68360_quicc.h>
4#include "m68360_enet.h" 4#include <asm/m68360_enet.h>
5 5
6#ifdef CONFIG_M68360 6#ifdef CONFIG_M68360
7 7
diff --git a/arch/m68k/include/asm/m68360_enet.h b/arch/m68k/include/asm/m68360_enet.h
index c36f4d059203..4d04037c78a2 100644
--- a/arch/m68k/include/asm/m68360_enet.h
+++ b/arch/m68k/include/asm/m68360_enet.h
@@ -10,7 +10,7 @@
10#ifndef __ETHER_H 10#ifndef __ETHER_H
11#define __ETHER_H 11#define __ETHER_H
12 12
13#include "quicc_simple.h" 13#include <asm/quicc_simple.h>
14 14
15/* 15/*
16 * transmit BD's 16 * transmit BD's
diff --git a/arch/m68k/include/asm/mcfslt.h b/arch/m68k/include/asm/mcfslt.h
index d0d0ecba5333..c2314b6f8caa 100644
--- a/arch/m68k/include/asm/mcfslt.h
+++ b/arch/m68k/include/asm/mcfslt.h
@@ -13,13 +13,6 @@
13/****************************************************************************/ 13/****************************************************************************/
14 14
15/* 15/*
16 * Get address specific defines for the 547x.
17 */
18#define MCFSLT_TIMER0 0x900 /* Base address of TIMER0 */
19#define MCFSLT_TIMER1 0x910 /* Base address of TIMER1 */
20
21
22/*
23 * Define the SLT timer register set addresses. 16 * Define the SLT timer register set addresses.
24 */ 17 */
25#define MCFSLT_STCNT 0x00 /* Terminal count */ 18#define MCFSLT_STCNT 0x00 /* Terminal count */
diff --git a/arch/m68k/include/asm/nettel.h b/arch/m68k/include/asm/nettel.h
index 4dec2d9fb994..2a7a7667d807 100644
--- a/arch/m68k/include/asm/nettel.h
+++ b/arch/m68k/include/asm/nettel.h
@@ -21,6 +21,7 @@
21#ifdef CONFIG_COLDFIRE 21#ifdef CONFIG_COLDFIRE
22#include <asm/coldfire.h> 22#include <asm/coldfire.h>
23#include <asm/mcfsim.h> 23#include <asm/mcfsim.h>
24#include <asm/io.h>
24#endif 25#endif
25 26
26/*---------------------------------------------------------------------------*/ 27/*---------------------------------------------------------------------------*/
@@ -86,16 +87,12 @@ static __inline__ void mcf_setppdata(unsigned int mask, unsigned int bits)
86 */ 87 */
87static __inline__ unsigned int mcf_getppdata(void) 88static __inline__ unsigned int mcf_getppdata(void)
88{ 89{
89 volatile unsigned short *pp; 90 return readw(MCFSIM_PBDAT);
90 pp = (volatile unsigned short *) (MCF_MBAR + MCFSIM_PBDAT);
91 return((unsigned int) *pp);
92} 91}
93 92
94static __inline__ void mcf_setppdata(unsigned int mask, unsigned int bits) 93static __inline__ void mcf_setppdata(unsigned int mask, unsigned int bits)
95{ 94{
96 volatile unsigned short *pp; 95 write((readw(MCFSIM_PBDAT) & ~mask) | bits, MCFSIM_PBDAT);
97 pp = (volatile unsigned short *) (MCF_MBAR + MCFSIM_PBDAT);
98 *pp = (*pp & ~mask) | bits;
99} 96}
100#endif 97#endif
101 98
diff --git a/arch/m68k/include/asm/page.h b/arch/m68k/include/asm/page.h
index 98baa82a8615..7c360dac00b7 100644
--- a/arch/m68k/include/asm/page.h
+++ b/arch/m68k/include/asm/page.h
@@ -43,9 +43,9 @@ extern unsigned long _ramend;
43#endif /* !__ASSEMBLY__ */ 43#endif /* !__ASSEMBLY__ */
44 44
45#ifdef CONFIG_MMU 45#ifdef CONFIG_MMU
46#include "page_mm.h" 46#include <asm/page_mm.h>
47#else 47#else
48#include "page_no.h" 48#include <asm/page_no.h>
49#endif 49#endif
50 50
51#include <asm-generic/getorder.h> 51#include <asm-generic/getorder.h>
diff --git a/arch/m68k/include/asm/pgtable.h b/arch/m68k/include/asm/pgtable.h
index ee6759eb445a..a3d733b524d2 100644
--- a/arch/m68k/include/asm/pgtable.h
+++ b/arch/m68k/include/asm/pgtable.h
@@ -1,5 +1,5 @@
1#ifdef __uClinux__ 1#ifdef __uClinux__
2#include "pgtable_no.h" 2#include <asm/pgtable_no.h>
3#else 3#else
4#include "pgtable_mm.h" 4#include <asm/pgtable_mm.h>
5#endif 5#endif
diff --git a/arch/m68k/include/asm/q40_master.h b/arch/m68k/include/asm/q40_master.h
index 3907a09d4fca..fc5b36278d04 100644
--- a/arch/m68k/include/asm/q40_master.h
+++ b/arch/m68k/include/asm/q40_master.h
@@ -60,7 +60,7 @@
60#define Q40_RTC_WRITE 128 60#define Q40_RTC_WRITE 128
61 61
62/* define some Q40 specific ints */ 62/* define some Q40 specific ints */
63#include "q40ints.h" 63#include <asm/q40ints.h>
64 64
65/* misc defs */ 65/* misc defs */
66#define DAC_LEFT ((unsigned char *)0xff008000) 66#define DAC_LEFT ((unsigned char *)0xff008000)
diff --git a/arch/m68k/include/asm/uaccess.h b/arch/m68k/include/asm/uaccess.h
index 38f92dbb9a45..639c731568b0 100644
--- a/arch/m68k/include/asm/uaccess.h
+++ b/arch/m68k/include/asm/uaccess.h
@@ -1,5 +1,5 @@
1#ifdef __uClinux__ 1#ifdef __uClinux__
2#include "uaccess_no.h" 2#include <asm/uaccess_no.h>
3#else 3#else
4#include "uaccess_mm.h" 4#include <asm/uaccess_mm.h>
5#endif 5#endif
diff --git a/arch/m68k/include/uapi/asm/Kbuild b/arch/m68k/include/uapi/asm/Kbuild
new file mode 100644
index 000000000000..baebb3da1d44
--- /dev/null
+++ b/arch/m68k/include/uapi/asm/Kbuild
@@ -0,0 +1,3 @@
1# UAPI Header export list
2include include/uapi/asm-generic/Kbuild.asm
3
diff --git a/arch/m68k/kernel/pcibios.c b/arch/m68k/kernel/pcibios.c
index b2988aa1840b..73fa0b56a06c 100644
--- a/arch/m68k/kernel/pcibios.c
+++ b/arch/m68k/kernel/pcibios.c
@@ -87,11 +87,6 @@ int pcibios_enable_device(struct pci_dev *dev, int mask)
87 return 0; 87 return 0;
88} 88}
89 89
90void pcibios_update_irq(struct pci_dev *dev, int irq)
91{
92 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
93}
94
95void __devinit pcibios_fixup_bus(struct pci_bus *bus) 90void __devinit pcibios_fixup_bus(struct pci_bus *bus)
96{ 91{
97 struct pci_dev *dev; 92 struct pci_dev *dev;
diff --git a/arch/m68k/kernel/process.c b/arch/m68k/kernel/process.c
index c488e3cfab53..ac2892e49c7c 100644
--- a/arch/m68k/kernel/process.c
+++ b/arch/m68k/kernel/process.c
@@ -25,6 +25,7 @@
25#include <linux/reboot.h> 25#include <linux/reboot.h>
26#include <linux/init_task.h> 26#include <linux/init_task.h>
27#include <linux/mqueue.h> 27#include <linux/mqueue.h>
28#include <linux/rcupdate.h>
28 29
29#include <asm/uaccess.h> 30#include <asm/uaccess.h>
30#include <asm/traps.h> 31#include <asm/traps.h>
@@ -75,8 +76,10 @@ void cpu_idle(void)
75{ 76{
76 /* endless idle loop with no priority at all */ 77 /* endless idle loop with no priority at all */
77 while (1) { 78 while (1) {
79 rcu_idle_enter();
78 while (!need_resched()) 80 while (!need_resched())
79 idle(); 81 idle();
82 rcu_idle_exit();
80 schedule_preempt_disabled(); 83 schedule_preempt_disabled();
81 } 84 }
82} 85}
diff --git a/arch/m68k/kernel/time.c b/arch/m68k/kernel/time.c
index 707f0573ec6b..5d0bcaad2e55 100644
--- a/arch/m68k/kernel/time.c
+++ b/arch/m68k/kernel/time.c
@@ -100,10 +100,7 @@ static int __init rtc_init(void)
100 return -ENODEV; 100 return -ENODEV;
101 101
102 pdev = platform_device_register_simple("rtc-generic", -1, NULL, 0); 102 pdev = platform_device_register_simple("rtc-generic", -1, NULL, 0);
103 if (IS_ERR(pdev)) 103 return PTR_RET(pdev);
104 return PTR_ERR(pdev);
105
106 return 0;
107} 104}
108 105
109module_init(rtc_init); 106module_init(rtc_init);
diff --git a/arch/m68k/mm/fault.c b/arch/m68k/mm/fault.c
index aeebbb7b30f0..a563727806bf 100644
--- a/arch/m68k/mm/fault.c
+++ b/arch/m68k/mm/fault.c
@@ -170,6 +170,7 @@ good_area:
170 /* Clear FAULT_FLAG_ALLOW_RETRY to avoid any risk 170 /* Clear FAULT_FLAG_ALLOW_RETRY to avoid any risk
171 * of starvation. */ 171 * of starvation. */
172 flags &= ~FAULT_FLAG_ALLOW_RETRY; 172 flags &= ~FAULT_FLAG_ALLOW_RETRY;
173 flags |= FAULT_FLAG_TRIED;
173 174
174 /* 175 /*
175 * No need to up_read(&mm->mmap_sem) as we would 176 * No need to up_read(&mm->mmap_sem) as we would
diff --git a/arch/m68k/platform/68VZ328/Makefile b/arch/m68k/platform/68VZ328/Makefile
index a49d75e65489..816674164682 100644
--- a/arch/m68k/platform/68VZ328/Makefile
+++ b/arch/m68k/platform/68VZ328/Makefile
@@ -1,11 +1,5 @@
1# 1#
2# Makefile for arch/m68knommu/platform/68VZ328. 2# Makefile for arch/m68k/platform/68VZ328.
3# 3#
4 4
5obj-y := config.o 5obj-y := config.o
6extra-$(DRAGEN2):= screen.h
7
8$(obj)/screen.h: $(src)/screen.xbm $(src)/xbm2lcd.pl
9 perl $(src)/xbm2lcd.pl < $(src)/screen.xbm > $(obj)/screen.h
10
11clean-files := $(obj)/screen.h
diff --git a/arch/m68k/platform/coldfire/clk.c b/arch/m68k/platform/coldfire/clk.c
index 75f9ee967ea7..9cd13b4ce42b 100644
--- a/arch/m68k/platform/coldfire/clk.c
+++ b/arch/m68k/platform/coldfire/clk.c
@@ -146,9 +146,3 @@ struct clk_ops clk_ops1 = {
146}; 146};
147#endif /* MCFPM_PPMCR1 */ 147#endif /* MCFPM_PPMCR1 */
148#endif /* MCFPM_PPMCR0 */ 148#endif /* MCFPM_PPMCR0 */
149
150struct clk *devm_clk_get(struct device *dev, const char *id)
151{
152 return NULL;
153}
154EXPORT_SYMBOL(devm_clk_get);
diff --git a/arch/m68k/platform/coldfire/device.c b/arch/m68k/platform/coldfire/device.c
index 81f0fb5e51cf..71ea4c02795d 100644
--- a/arch/m68k/platform/coldfire/device.c
+++ b/arch/m68k/platform/coldfire/device.c
@@ -347,12 +347,12 @@ static void __init mcf_uart_set_irq(void)
347{ 347{
348#ifdef MCFUART_UIVR 348#ifdef MCFUART_UIVR
349 /* UART0 interrupt setup */ 349 /* UART0 interrupt setup */
350 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR); 350 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCFSIM_UART1ICR);
351 writeb(MCF_IRQ_UART0, MCFUART_BASE0 + MCFUART_UIVR); 351 writeb(MCF_IRQ_UART0, MCFUART_BASE0 + MCFUART_UIVR);
352 mcf_mapirq2imr(MCF_IRQ_UART0, MCFINTC_UART0); 352 mcf_mapirq2imr(MCF_IRQ_UART0, MCFINTC_UART0);
353 353
354 /* UART1 interrupt setup */ 354 /* UART1 interrupt setup */
355 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR); 355 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCFSIM_UART2ICR);
356 writeb(MCF_IRQ_UART1, MCFUART_BASE1 + MCFUART_UIVR); 356 writeb(MCF_IRQ_UART1, MCFUART_BASE1 + MCFUART_UIVR);
357 mcf_mapirq2imr(MCF_IRQ_UART1, MCFINTC_UART1); 357 mcf_mapirq2imr(MCF_IRQ_UART1, MCFINTC_UART1);
358#endif 358#endif
diff --git a/arch/m68k/platform/coldfire/head.S b/arch/m68k/platform/coldfire/head.S
index b88f5716f357..fa31be297b85 100644
--- a/arch/m68k/platform/coldfire/head.S
+++ b/arch/m68k/platform/coldfire/head.S
@@ -60,7 +60,7 @@
60 60
61#elif defined(CONFIG_M5272) 61#elif defined(CONFIG_M5272)
62.macro GET_MEM_SIZE 62.macro GET_MEM_SIZE
63 movel MCF_MBAR+MCFSIM_CSOR7,%d0 /* get SDRAM address mask */ 63 movel MCFSIM_CSOR7,%d0 /* get SDRAM address mask */
64 andil #0xfffff000,%d0 /* mask out chip select options */ 64 andil #0xfffff000,%d0 /* mask out chip select options */
65 negl %d0 /* negate bits */ 65 negl %d0 /* negate bits */
66.endm 66.endm
diff --git a/arch/m68k/platform/coldfire/intc-5249.c b/arch/m68k/platform/coldfire/intc-5249.c
index f343bf7bf5b0..0864b836699a 100644
--- a/arch/m68k/platform/coldfire/intc-5249.c
+++ b/arch/m68k/platform/coldfire/intc-5249.c
@@ -20,22 +20,22 @@
20static void intc2_irq_gpio_mask(struct irq_data *d) 20static void intc2_irq_gpio_mask(struct irq_data *d)
21{ 21{
22 u32 imr; 22 u32 imr;
23 imr = readl(MCF_MBAR2 + MCFSIM2_GPIOINTENABLE); 23 imr = readl(MCFSIM2_GPIOINTENABLE);
24 imr &= ~(0x1 << (d->irq - MCFINTC2_GPIOIRQ0)); 24 imr &= ~(0x1 << (d->irq - MCFINTC2_GPIOIRQ0));
25 writel(imr, MCF_MBAR2 + MCFSIM2_GPIOINTENABLE); 25 writel(imr, MCFSIM2_GPIOINTENABLE);
26} 26}
27 27
28static void intc2_irq_gpio_unmask(struct irq_data *d) 28static void intc2_irq_gpio_unmask(struct irq_data *d)
29{ 29{
30 u32 imr; 30 u32 imr;
31 imr = readl(MCF_MBAR2 + MCFSIM2_GPIOINTENABLE); 31 imr = readl(MCFSIM2_GPIOINTENABLE);
32 imr |= (0x1 << (d->irq - MCFINTC2_GPIOIRQ0)); 32 imr |= (0x1 << (d->irq - MCFINTC2_GPIOIRQ0));
33 writel(imr, MCF_MBAR2 + MCFSIM2_GPIOINTENABLE); 33 writel(imr, MCFSIM2_GPIOINTENABLE);
34} 34}
35 35
36static void intc2_irq_gpio_ack(struct irq_data *d) 36static void intc2_irq_gpio_ack(struct irq_data *d)
37{ 37{
38 writel(0x1 << (d->irq - MCFINTC2_GPIOIRQ0), MCF_MBAR2 + MCFSIM2_GPIOINTCLEAR); 38 writel(0x1 << (d->irq - MCFINTC2_GPIOIRQ0), MCFSIM2_GPIOINTCLEAR);
39} 39}
40 40
41static struct irq_chip intc2_irq_gpio_chip = { 41static struct irq_chip intc2_irq_gpio_chip = {
diff --git a/arch/m68k/platform/coldfire/intc-5272.c b/arch/m68k/platform/coldfire/intc-5272.c
index 7160e618b0a9..d7b695629a7e 100644
--- a/arch/m68k/platform/coldfire/intc-5272.c
+++ b/arch/m68k/platform/coldfire/intc-5272.c
@@ -86,7 +86,7 @@ static void intc_irq_mask(struct irq_data *d)
86 u32 v; 86 u32 v;
87 irq -= MCFINT_VECBASE; 87 irq -= MCFINT_VECBASE;
88 v = 0x8 << intc_irqmap[irq].index; 88 v = 0x8 << intc_irqmap[irq].index;
89 writel(v, MCF_MBAR + intc_irqmap[irq].icr); 89 writel(v, intc_irqmap[irq].icr);
90 } 90 }
91} 91}
92 92
@@ -98,7 +98,7 @@ static void intc_irq_unmask(struct irq_data *d)
98 u32 v; 98 u32 v;
99 irq -= MCFINT_VECBASE; 99 irq -= MCFINT_VECBASE;
100 v = 0xd << intc_irqmap[irq].index; 100 v = 0xd << intc_irqmap[irq].index;
101 writel(v, MCF_MBAR + intc_irqmap[irq].icr); 101 writel(v, intc_irqmap[irq].icr);
102 } 102 }
103} 103}
104 104
@@ -111,10 +111,10 @@ static void intc_irq_ack(struct irq_data *d)
111 irq -= MCFINT_VECBASE; 111 irq -= MCFINT_VECBASE;
112 if (intc_irqmap[irq].ack) { 112 if (intc_irqmap[irq].ack) {
113 u32 v; 113 u32 v;
114 v = readl(MCF_MBAR + intc_irqmap[irq].icr); 114 v = readl(intc_irqmap[irq].icr);
115 v &= (0x7 << intc_irqmap[irq].index); 115 v &= (0x7 << intc_irqmap[irq].index);
116 v |= (0x8 << intc_irqmap[irq].index); 116 v |= (0x8 << intc_irqmap[irq].index);
117 writel(v, MCF_MBAR + intc_irqmap[irq].icr); 117 writel(v, intc_irqmap[irq].icr);
118 } 118 }
119 } 119 }
120} 120}
@@ -127,12 +127,12 @@ static int intc_irq_set_type(struct irq_data *d, unsigned int type)
127 irq -= MCFINT_VECBASE; 127 irq -= MCFINT_VECBASE;
128 if (intc_irqmap[irq].ack) { 128 if (intc_irqmap[irq].ack) {
129 u32 v; 129 u32 v;
130 v = readl(MCF_MBAR + MCFSIM_PITR); 130 v = readl(MCFSIM_PITR);
131 if (type == IRQ_TYPE_EDGE_FALLING) 131 if (type == IRQ_TYPE_EDGE_FALLING)
132 v &= ~(0x1 << (32 - irq)); 132 v &= ~(0x1 << (32 - irq));
133 else 133 else
134 v |= (0x1 << (32 - irq)); 134 v |= (0x1 << (32 - irq));
135 writel(v, MCF_MBAR + MCFSIM_PITR); 135 writel(v, MCFSIM_PITR);
136 } 136 }
137 } 137 }
138 return 0; 138 return 0;
@@ -163,10 +163,10 @@ void __init init_IRQ(void)
163 int irq, edge; 163 int irq, edge;
164 164
165 /* Mask all interrupt sources */ 165 /* Mask all interrupt sources */
166 writel(0x88888888, MCF_MBAR + MCFSIM_ICR1); 166 writel(0x88888888, MCFSIM_ICR1);
167 writel(0x88888888, MCF_MBAR + MCFSIM_ICR2); 167 writel(0x88888888, MCFSIM_ICR2);
168 writel(0x88888888, MCF_MBAR + MCFSIM_ICR3); 168 writel(0x88888888, MCFSIM_ICR3);
169 writel(0x88888888, MCF_MBAR + MCFSIM_ICR4); 169 writel(0x88888888, MCFSIM_ICR4);
170 170
171 for (irq = 0; (irq < NR_IRQS); irq++) { 171 for (irq = 0; (irq < NR_IRQS); irq++) {
172 irq_set_chip(irq, &intc_irq_chip); 172 irq_set_chip(irq, &intc_irq_chip);
diff --git a/arch/m68k/platform/coldfire/intc.c b/arch/m68k/platform/coldfire/intc.c
index 5c0c150b4067..cce257420388 100644
--- a/arch/m68k/platform/coldfire/intc.c
+++ b/arch/m68k/platform/coldfire/intc.c
@@ -45,23 +45,23 @@ unsigned char mcf_irq2imr[NR_IRQS];
45void mcf_setimr(int index) 45void mcf_setimr(int index)
46{ 46{
47 u16 imr; 47 u16 imr;
48 imr = __raw_readw(MCF_MBAR + MCFSIM_IMR); 48 imr = __raw_readw(MCFSIM_IMR);
49 __raw_writew(imr | (0x1 << index), MCF_MBAR + MCFSIM_IMR); 49 __raw_writew(imr | (0x1 << index), MCFSIM_IMR);
50} 50}
51 51
52void mcf_clrimr(int index) 52void mcf_clrimr(int index)
53{ 53{
54 u16 imr; 54 u16 imr;
55 imr = __raw_readw(MCF_MBAR + MCFSIM_IMR); 55 imr = __raw_readw(MCFSIM_IMR);
56 __raw_writew(imr & ~(0x1 << index), MCF_MBAR + MCFSIM_IMR); 56 __raw_writew(imr & ~(0x1 << index), MCFSIM_IMR);
57} 57}
58 58
59void mcf_maskimr(unsigned int mask) 59void mcf_maskimr(unsigned int mask)
60{ 60{
61 u16 imr; 61 u16 imr;
62 imr = __raw_readw(MCF_MBAR + MCFSIM_IMR); 62 imr = __raw_readw(MCFSIM_IMR);
63 imr |= mask; 63 imr |= mask;
64 __raw_writew(imr, MCF_MBAR + MCFSIM_IMR); 64 __raw_writew(imr, MCFSIM_IMR);
65} 65}
66 66
67#else 67#else
@@ -69,23 +69,23 @@ void mcf_maskimr(unsigned int mask)
69void mcf_setimr(int index) 69void mcf_setimr(int index)
70{ 70{
71 u32 imr; 71 u32 imr;
72 imr = __raw_readl(MCF_MBAR + MCFSIM_IMR); 72 imr = __raw_readl(MCFSIM_IMR);
73 __raw_writel(imr | (0x1 << index), MCF_MBAR + MCFSIM_IMR); 73 __raw_writel(imr | (0x1 << index), MCFSIM_IMR);
74} 74}
75 75
76void mcf_clrimr(int index) 76void mcf_clrimr(int index)
77{ 77{
78 u32 imr; 78 u32 imr;
79 imr = __raw_readl(MCF_MBAR + MCFSIM_IMR); 79 imr = __raw_readl(MCFSIM_IMR);
80 __raw_writel(imr & ~(0x1 << index), MCF_MBAR + MCFSIM_IMR); 80 __raw_writel(imr & ~(0x1 << index), MCFSIM_IMR);
81} 81}
82 82
83void mcf_maskimr(unsigned int mask) 83void mcf_maskimr(unsigned int mask)
84{ 84{
85 u32 imr; 85 u32 imr;
86 imr = __raw_readl(MCF_MBAR + MCFSIM_IMR); 86 imr = __raw_readl(MCFSIM_IMR);
87 imr |= mask; 87 imr |= mask;
88 __raw_writel(imr, MCF_MBAR + MCFSIM_IMR); 88 __raw_writel(imr, MCFSIM_IMR);
89} 89}
90 90
91#endif 91#endif
@@ -104,9 +104,9 @@ void mcf_autovector(int irq)
104#ifdef MCFSIM_AVR 104#ifdef MCFSIM_AVR
105 if ((irq >= EIRQ1) && (irq <= EIRQ7)) { 105 if ((irq >= EIRQ1) && (irq <= EIRQ7)) {
106 u8 avec; 106 u8 avec;
107 avec = __raw_readb(MCF_MBAR + MCFSIM_AVR); 107 avec = __raw_readb(MCFSIM_AVR);
108 avec |= (0x1 << (irq - EIRQ1 + 1)); 108 avec |= (0x1 << (irq - EIRQ1 + 1));
109 __raw_writeb(avec, MCF_MBAR + MCFSIM_AVR); 109 __raw_writeb(avec, MCFSIM_AVR);
110 } 110 }
111#endif 111#endif
112} 112}
diff --git a/arch/m68k/platform/coldfire/m523x.c b/arch/m68k/platform/coldfire/m523x.c
index d47dfd8f50a2..ff37fe9553ea 100644
--- a/arch/m68k/platform/coldfire/m523x.c
+++ b/arch/m68k/platform/coldfire/m523x.c
@@ -42,14 +42,8 @@ static void __init m523x_qspi_init(void)
42 42
43static void __init m523x_fec_init(void) 43static void __init m523x_fec_init(void)
44{ 44{
45 u16 par;
46 u8 v;
47
48 /* Set multi-function pins to ethernet use */ 45 /* Set multi-function pins to ethernet use */
49 par = readw(MCF_IPSBAR + 0x100082); 46 writeb(readb(MCFGPIO_PAR_FECI2C) | 0xf0, MCFGPIO_PAR_FECI2C);
50 writew(par | 0xf00, MCF_IPSBAR + 0x100082);
51 v = readb(MCF_IPSBAR + 0x100078);
52 writeb(v | 0xc0, MCF_IPSBAR + 0x100078);
53} 47}
54 48
55/***************************************************************************/ 49/***************************************************************************/
diff --git a/arch/m68k/platform/coldfire/m5249.c b/arch/m68k/platform/coldfire/m5249.c
index 300e729a58d0..23b19cb7ab50 100644
--- a/arch/m68k/platform/coldfire/m5249.c
+++ b/arch/m68k/platform/coldfire/m5249.c
@@ -57,7 +57,7 @@ static void __init m5249_qspi_init(void)
57{ 57{
58 /* QSPI irq setup */ 58 /* QSPI irq setup */
59 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL4 | MCFSIM_ICR_PRI0, 59 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL4 | MCFSIM_ICR_PRI0,
60 MCF_MBAR + MCFSIM_QSPIICR); 60 MCFSIM_QSPIICR);
61 mcf_mapirq2imr(MCF_IRQ_QSPI, MCFINTC_QSPI); 61 mcf_mapirq2imr(MCF_IRQ_QSPI, MCFINTC_QSPI);
62} 62}
63 63
@@ -72,11 +72,11 @@ static void __init m5249_smc91x_init(void)
72 u32 gpio; 72 u32 gpio;
73 73
74 /* Set the GPIO line as interrupt source for smc91x device */ 74 /* Set the GPIO line as interrupt source for smc91x device */
75 gpio = readl(MCF_MBAR2 + MCFSIM2_GPIOINTENABLE); 75 gpio = readl(MCFSIM2_GPIOINTENABLE);
76 writel(gpio | 0x40, MCF_MBAR2 + MCFSIM2_GPIOINTENABLE); 76 writel(gpio | 0x40, MCFSIM2_GPIOINTENABLE);
77 77
78 gpio = readl(MCF_MBAR2 + MCFSIM2_INTLEVEL5); 78 gpio = readl(MCFSIM2_INTLEVEL5);
79 writel(gpio | 0x04000000, MCF_MBAR2 + MCFSIM2_INTLEVEL5); 79 writel(gpio | 0x04000000, MCFSIM2_INTLEVEL5);
80} 80}
81 81
82#endif /* CONFIG_M5249C3 */ 82#endif /* CONFIG_M5249C3 */
diff --git a/arch/m68k/platform/coldfire/m525x.c b/arch/m68k/platform/coldfire/m525x.c
index 8ce905f9b84f..fce8f8a45bf0 100644
--- a/arch/m68k/platform/coldfire/m525x.c
+++ b/arch/m68k/platform/coldfire/m525x.c
@@ -30,7 +30,7 @@ static void __init m525x_qspi_init(void)
30 30
31 /* QSPI irq setup */ 31 /* QSPI irq setup */
32 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL4 | MCFSIM_ICR_PRI0, 32 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL4 | MCFSIM_ICR_PRI0,
33 MCF_MBAR + MCFSIM_QSPIICR); 33 MCFSIM_QSPIICR);
34 mcf_mapirq2imr(MCF_IRQ_QSPI, MCFINTC_QSPI); 34 mcf_mapirq2imr(MCF_IRQ_QSPI, MCFINTC_QSPI);
35#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */ 35#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
36} 36}
@@ -42,7 +42,7 @@ static void __init m525x_i2c_init(void)
42 42
43 /* first I2C controller uses regular irq setup */ 43 /* first I2C controller uses regular irq setup */
44 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI0, 44 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI0,
45 MCF_MBAR + MCFSIM_I2CICR); 45 MCFSIM_I2CICR);
46 mcf_mapirq2imr(MCF_IRQ_I2C0, MCFINTC_I2C); 46 mcf_mapirq2imr(MCF_IRQ_I2C0, MCFINTC_I2C);
47 47
48 /* second I2C controller is completely different */ 48 /* second I2C controller is completely different */
diff --git a/arch/m68k/platform/coldfire/m5272.c b/arch/m68k/platform/coldfire/m5272.c
index e68bc7a148eb..45b246d052ef 100644
--- a/arch/m68k/platform/coldfire/m5272.c
+++ b/arch/m68k/platform/coldfire/m5272.c
@@ -35,13 +35,13 @@ static void __init m5272_uarts_init(void)
35 u32 v; 35 u32 v;
36 36
37 /* Enable the output lines for the serial ports */ 37 /* Enable the output lines for the serial ports */
38 v = readl(MCF_MBAR + MCFSIM_PBCNT); 38 v = readl(MCFSIM_PBCNT);
39 v = (v & ~0x000000ff) | 0x00000055; 39 v = (v & ~0x000000ff) | 0x00000055;
40 writel(v, MCF_MBAR + MCFSIM_PBCNT); 40 writel(v, MCFSIM_PBCNT);
41 41
42 v = readl(MCF_MBAR + MCFSIM_PDCNT); 42 v = readl(MCFSIM_PDCNT);
43 v = (v & ~0x000003fc) | 0x000002a8; 43 v = (v & ~0x000003fc) | 0x000002a8;
44 writel(v, MCF_MBAR + MCFSIM_PDCNT); 44 writel(v, MCFSIM_PDCNT);
45} 45}
46 46
47/***************************************************************************/ 47/***************************************************************************/
@@ -50,9 +50,9 @@ static void m5272_cpu_reset(void)
50{ 50{
51 local_irq_disable(); 51 local_irq_disable();
52 /* Set watchdog to reset, and enabled */ 52 /* Set watchdog to reset, and enabled */
53 __raw_writew(0, MCF_MBAR + MCFSIM_WIRR); 53 __raw_writew(0, MCFSIM_WIRR);
54 __raw_writew(1, MCF_MBAR + MCFSIM_WRRR); 54 __raw_writew(1, MCFSIM_WRRR);
55 __raw_writew(0, MCF_MBAR + MCFSIM_WCR); 55 __raw_writew(0, MCFSIM_WCR);
56 for (;;) 56 for (;;)
57 /* wait for watchdog to timeout */; 57 /* wait for watchdog to timeout */;
58} 58}
@@ -62,11 +62,8 @@ static void m5272_cpu_reset(void)
62void __init config_BSP(char *commandp, int size) 62void __init config_BSP(char *commandp, int size)
63{ 63{
64#if defined (CONFIG_MOD5272) 64#if defined (CONFIG_MOD5272)
65 volatile unsigned char *pivrp;
66
67 /* Set base of device vectors to be 64 */ 65 /* Set base of device vectors to be 64 */
68 pivrp = (volatile unsigned char *) (MCF_MBAR + MCFSIM_PIVR); 66 writeb(0x40, MCFSIM_PIVR);
69 *pivrp = 0x40;
70#endif 67#endif
71 68
72#if defined(CONFIG_NETtel) || defined(CONFIG_SCALES) 69#if defined(CONFIG_NETtel) || defined(CONFIG_SCALES)
diff --git a/arch/m68k/platform/coldfire/m527x.c b/arch/m68k/platform/coldfire/m527x.c
index b3cb378c5e94..1431ba03c602 100644
--- a/arch/m68k/platform/coldfire/m527x.c
+++ b/arch/m68k/platform/coldfire/m527x.c
@@ -53,9 +53,9 @@ static void __init m527x_uarts_init(void)
53 /* 53 /*
54 * External Pin Mask Setting & Enable External Pin for Interface 54 * External Pin Mask Setting & Enable External Pin for Interface
55 */ 55 */
56 sepmask = readw(MCF_IPSBAR + MCF_GPIO_PAR_UART); 56 sepmask = readw(MCFGPIO_PAR_UART);
57 sepmask |= UART0_ENABLE_MASK | UART1_ENABLE_MASK | UART2_ENABLE_MASK; 57 sepmask |= UART0_ENABLE_MASK | UART1_ENABLE_MASK | UART2_ENABLE_MASK;
58 writew(sepmask, MCF_IPSBAR + MCF_GPIO_PAR_UART); 58 writew(sepmask, MCFGPIO_PAR_UART);
59} 59}
60 60
61/***************************************************************************/ 61/***************************************************************************/
@@ -67,19 +67,19 @@ static void __init m527x_fec_init(void)
67 67
68 /* Set multi-function pins to ethernet mode for fec0 */ 68 /* Set multi-function pins to ethernet mode for fec0 */
69#if defined(CONFIG_M5271) 69#if defined(CONFIG_M5271)
70 v = readb(MCF_IPSBAR + 0x100047); 70 v = readb(MCFGPIO_PAR_FECI2C);
71 writeb(v | 0xf0, MCF_IPSBAR + 0x100047); 71 writeb(v | 0xf0, MCFGPIO_PAR_FECI2C);
72#else 72#else
73 par = readw(MCF_IPSBAR + 0x100082); 73 par = readw(MCFGPIO_PAR_FECI2C);
74 writew(par | 0xf00, MCF_IPSBAR + 0x100082); 74 writew(par | 0xf00, MCFGPIO_PAR_FECI2C);
75 v = readb(MCF_IPSBAR + 0x100078); 75 v = readb(MCFGPIO_PAR_FEC0HL);
76 writeb(v | 0xc0, MCF_IPSBAR + 0x100078); 76 writeb(v | 0xc0, MCFGPIO_PAR_FEC0HL);
77 77
78 /* Set multi-function pins to ethernet mode for fec1 */ 78 /* Set multi-function pins to ethernet mode for fec1 */
79 par = readw(MCF_IPSBAR + 0x100082); 79 par = readw(MCFGPIO_PAR_FECI2C);
80 writew(par | 0xa0, MCF_IPSBAR + 0x100082); 80 writew(par | 0xa0, MCFGPIO_PAR_FECI2C);
81 v = readb(MCF_IPSBAR + 0x100079); 81 v = readb(MCFGPIO_PAR_FEC1HL);
82 writeb(v | 0xc0, MCF_IPSBAR + 0x100079); 82 writeb(v | 0xc0, MCFGPIO_PAR_FEC1HL);
83#endif 83#endif
84} 84}
85 85
diff --git a/arch/m68k/platform/coldfire/m528x.c b/arch/m68k/platform/coldfire/m528x.c
index f1319e5d2546..f9f7e6a13d04 100644
--- a/arch/m68k/platform/coldfire/m528x.c
+++ b/arch/m68k/platform/coldfire/m528x.c
@@ -53,9 +53,9 @@ static void __init m528x_fec_init(void)
53 u16 v16; 53 u16 v16;
54 54
55 /* Set multi-function pins to ethernet mode for fec0 */ 55 /* Set multi-function pins to ethernet mode for fec0 */
56 v16 = readw(MCF_IPSBAR + 0x100056); 56 v16 = readw(MCFGPIO_PASPAR);
57 writew(v16 | 0xf00, MCF_IPSBAR + 0x100056); 57 writew(v16 | 0xf00, MCFGPIO_PASPAR);
58 writeb(0xc0, MCF_IPSBAR + 0x100058); 58 writeb(0xc0, MCFGPIO_PEHLPAR);
59} 59}
60 60
61/***************************************************************************/ 61/***************************************************************************/
diff --git a/arch/m68k/platform/coldfire/m532x.c b/arch/m68k/platform/coldfire/m532x.c
index 4819a44991ed..7951d1d43357 100644
--- a/arch/m68k/platform/coldfire/m532x.c
+++ b/arch/m68k/platform/coldfire/m532x.c
@@ -172,7 +172,7 @@ static void __init m532x_clk_init(void)
172static void __init m532x_qspi_init(void) 172static void __init m532x_qspi_init(void)
173{ 173{
174 /* setup QSPS pins for QSPI with gpio CS control */ 174 /* setup QSPS pins for QSPI with gpio CS control */
175 writew(0x01f0, MCF_GPIO_PAR_QSPI); 175 writew(0x01f0, MCFGPIO_PAR_QSPI);
176} 176}
177 177
178#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */ 178#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
@@ -182,18 +182,24 @@ static void __init m532x_qspi_init(void)
182static void __init m532x_uarts_init(void) 182static void __init m532x_uarts_init(void)
183{ 183{
184 /* UART GPIO initialization */ 184 /* UART GPIO initialization */
185 MCF_GPIO_PAR_UART |= 0x0FFF; 185 writew(readw(MCFGPIO_PAR_UART) | 0x0FFF, MCFGPIO_PAR_UART);
186} 186}
187 187
188/***************************************************************************/ 188/***************************************************************************/
189 189
190static void __init m532x_fec_init(void) 190static void __init m532x_fec_init(void)
191{ 191{
192 u8 v;
193
192 /* Set multi-function pins to ethernet mode for fec0 */ 194 /* Set multi-function pins to ethernet mode for fec0 */
193 MCF_GPIO_PAR_FECI2C |= (MCF_GPIO_PAR_FECI2C_PAR_MDC_EMDC | 195 v = readb(MCFGPIO_PAR_FECI2C);
194 MCF_GPIO_PAR_FECI2C_PAR_MDIO_EMDIO); 196 v |= MCF_GPIO_PAR_FECI2C_PAR_MDC_EMDC |
195 MCF_GPIO_PAR_FEC = (MCF_GPIO_PAR_FEC_PAR_FEC_7W_FEC | 197 MCF_GPIO_PAR_FECI2C_PAR_MDIO_EMDIO;
196 MCF_GPIO_PAR_FEC_PAR_FEC_MII_FEC); 198 writeb(v, MCFGPIO_PAR_FECI2C);
199
200 v = readb(MCFGPIO_PAR_FEC);
201 v = MCF_GPIO_PAR_FEC_PAR_FEC_7W_FEC | MCF_GPIO_PAR_FEC_PAR_FEC_MII_FEC;
202 writeb(v, MCFGPIO_PAR_FEC);
197} 203}
198 204
199/***************************************************************************/ 205/***************************************************************************/
@@ -298,7 +304,7 @@ asmlinkage void __init sysinit(void)
298void wtm_init(void) 304void wtm_init(void)
299{ 305{
300 /* Disable watchdog timer */ 306 /* Disable watchdog timer */
301 MCF_WTM_WCR = 0; 307 writew(0, MCF_WTM_WCR);
302} 308}
303 309
304#define MCF_SCM_BCR_GBW (0x00000100) 310#define MCF_SCM_BCR_GBW (0x00000100)
@@ -307,53 +313,53 @@ void wtm_init(void)
307void scm_init(void) 313void scm_init(void)
308{ 314{
309 /* All masters are trusted */ 315 /* All masters are trusted */
310 MCF_SCM_MPR = 0x77777777; 316 writel(0x77777777, MCF_SCM_MPR);
311 317
312 /* Allow supervisor/user, read/write, and trusted/untrusted 318 /* Allow supervisor/user, read/write, and trusted/untrusted
313 access to all slaves */ 319 access to all slaves */
314 MCF_SCM_PACRA = 0; 320 writel(0, MCF_SCM_PACRA);
315 MCF_SCM_PACRB = 0; 321 writel(0, MCF_SCM_PACRB);
316 MCF_SCM_PACRC = 0; 322 writel(0, MCF_SCM_PACRC);
317 MCF_SCM_PACRD = 0; 323 writel(0, MCF_SCM_PACRD);
318 MCF_SCM_PACRE = 0; 324 writel(0, MCF_SCM_PACRE);
319 MCF_SCM_PACRF = 0; 325 writel(0, MCF_SCM_PACRF);
320 326
321 /* Enable bursts */ 327 /* Enable bursts */
322 MCF_SCM_BCR = (MCF_SCM_BCR_GBR | MCF_SCM_BCR_GBW); 328 writel(MCF_SCM_BCR_GBR | MCF_SCM_BCR_GBW, MCF_SCM_BCR);
323} 329}
324 330
325 331
326void fbcs_init(void) 332void fbcs_init(void)
327{ 333{
328 MCF_GPIO_PAR_CS = 0x0000003E; 334 writeb(0x3E, MCFGPIO_PAR_CS);
329 335
330 /* Latch chip select */ 336 /* Latch chip select */
331 MCF_FBCS1_CSAR = 0x10080000; 337 writel(0x10080000, MCF_FBCS1_CSAR);
332 338
333 MCF_FBCS1_CSCR = 0x002A3780; 339 writel(0x002A3780, MCF_FBCS1_CSCR);
334 MCF_FBCS1_CSMR = (MCF_FBCS_CSMR_BAM_2M | MCF_FBCS_CSMR_V); 340 writel(MCF_FBCS_CSMR_BAM_2M | MCF_FBCS_CSMR_V, MCF_FBCS1_CSMR);
335 341
336 /* Initialize latch to drive signals to inactive states */ 342 /* Initialize latch to drive signals to inactive states */
337 *((u16 *)(0x10080000)) = 0xFFFF; 343 writew(0xffff, 0x10080000);
338 344
339 /* External SRAM */ 345 /* External SRAM */
340 MCF_FBCS1_CSAR = EXT_SRAM_ADDRESS; 346 writel(EXT_SRAM_ADDRESS, MCF_FBCS1_CSAR);
341 MCF_FBCS1_CSCR = (MCF_FBCS_CSCR_PS_16 347 writel(MCF_FBCS_CSCR_PS_16 |
342 | MCF_FBCS_CSCR_AA 348 MCF_FBCS_CSCR_AA |
343 | MCF_FBCS_CSCR_SBM 349 MCF_FBCS_CSCR_SBM |
344 | MCF_FBCS_CSCR_WS(1)); 350 MCF_FBCS_CSCR_WS(1),
345 MCF_FBCS1_CSMR = (MCF_FBCS_CSMR_BAM_512K 351 MCF_FBCS1_CSCR);
346 | MCF_FBCS_CSMR_V); 352 writel(MCF_FBCS_CSMR_BAM_512K | MCF_FBCS_CSMR_V, MCF_FBCS1_CSMR);
347 353
348 /* Boot Flash connected to FBCS0 */ 354 /* Boot Flash connected to FBCS0 */
349 MCF_FBCS0_CSAR = FLASH_ADDRESS; 355 writel(FLASH_ADDRESS, MCF_FBCS0_CSAR);
350 MCF_FBCS0_CSCR = (MCF_FBCS_CSCR_PS_16 356 writel(MCF_FBCS_CSCR_PS_16 |
351 | MCF_FBCS_CSCR_BEM 357 MCF_FBCS_CSCR_BEM |
352 | MCF_FBCS_CSCR_AA 358 MCF_FBCS_CSCR_AA |
353 | MCF_FBCS_CSCR_SBM 359 MCF_FBCS_CSCR_SBM |
354 | MCF_FBCS_CSCR_WS(7)); 360 MCF_FBCS_CSCR_WS(7),
355 MCF_FBCS0_CSMR = (MCF_FBCS_CSMR_BAM_32M 361 MCF_FBCS0_CSCR);
356 | MCF_FBCS_CSMR_V); 362 writel(MCF_FBCS_CSMR_BAM_32M | MCF_FBCS_CSMR_V, MCF_FBCS0_CSMR);
357} 363}
358 364
359void sdramc_init(void) 365void sdramc_init(void)
@@ -362,102 +368,102 @@ void sdramc_init(void)
362 * Check to see if the SDRAM has already been initialized 368 * Check to see if the SDRAM has already been initialized
363 * by a run control tool 369 * by a run control tool
364 */ 370 */
365 if (!(MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF)) { 371 if (!(readl(MCF_SDRAMC_SDCR) & MCF_SDRAMC_SDCR_REF)) {
366 /* SDRAM chip select initialization */ 372 /* SDRAM chip select initialization */
367 373
368 /* Initialize SDRAM chip select */ 374 /* Initialize SDRAM chip select */
369 MCF_SDRAMC_SDCS0 = (0 375 writel(MCF_SDRAMC_SDCS_BA(SDRAM_ADDRESS) |
370 | MCF_SDRAMC_SDCS_BA(SDRAM_ADDRESS) 376 MCF_SDRAMC_SDCS_CSSZ(MCF_SDRAMC_SDCS_CSSZ_32MBYTE),
371 | MCF_SDRAMC_SDCS_CSSZ(MCF_SDRAMC_SDCS_CSSZ_32MBYTE)); 377 MCF_SDRAMC_SDCS0);
372 378
373 /* 379 /*
374 * Basic configuration and initialization 380 * Basic configuration and initialization
375 */ 381 */
376 MCF_SDRAMC_SDCFG1 = (0 382 writel(MCF_SDRAMC_SDCFG1_SRD2RW((int)((SDRAM_CASL + 2) + 0.5)) |
377 | MCF_SDRAMC_SDCFG1_SRD2RW((int)((SDRAM_CASL + 2) + 0.5 )) 383 MCF_SDRAMC_SDCFG1_SWT2RD(SDRAM_TWR + 1) |
378 | MCF_SDRAMC_SDCFG1_SWT2RD(SDRAM_TWR + 1) 384 MCF_SDRAMC_SDCFG1_RDLAT((int)((SDRAM_CASL * 2) + 2)) |
379 | MCF_SDRAMC_SDCFG1_RDLAT((int)((SDRAM_CASL*2) + 2)) 385 MCF_SDRAMC_SDCFG1_ACT2RW((int)(SDRAM_TRCD + 0.5)) |
380 | MCF_SDRAMC_SDCFG1_ACT2RW((int)((SDRAM_TRCD ) + 0.5)) 386 MCF_SDRAMC_SDCFG1_PRE2ACT((int)(SDRAM_TRP + 0.5)) |
381 | MCF_SDRAMC_SDCFG1_PRE2ACT((int)((SDRAM_TRP ) + 0.5)) 387 MCF_SDRAMC_SDCFG1_REF2ACT((int)(SDRAM_TRFC + 0.5)) |
382 | MCF_SDRAMC_SDCFG1_REF2ACT((int)(((SDRAM_TRFC) ) + 0.5)) 388 MCF_SDRAMC_SDCFG1_WTLAT(3),
383 | MCF_SDRAMC_SDCFG1_WTLAT(3)); 389 MCF_SDRAMC_SDCFG1);
384 MCF_SDRAMC_SDCFG2 = (0 390 writel(MCF_SDRAMC_SDCFG2_BRD2PRE(SDRAM_BL / 2 + 1) |
385 | MCF_SDRAMC_SDCFG2_BRD2PRE(SDRAM_BL/2 + 1) 391 MCF_SDRAMC_SDCFG2_BWT2RW(SDRAM_BL / 2 + SDRAM_TWR) |
386 | MCF_SDRAMC_SDCFG2_BWT2RW(SDRAM_BL/2 + SDRAM_TWR) 392 MCF_SDRAMC_SDCFG2_BRD2WT((int)((SDRAM_CASL + SDRAM_BL / 2 - 1.0) + 0.5)) |
387 | MCF_SDRAMC_SDCFG2_BRD2WT((int)((SDRAM_CASL+SDRAM_BL/2-1.0)+0.5)) 393 MCF_SDRAMC_SDCFG2_BL(SDRAM_BL - 1),
388 | MCF_SDRAMC_SDCFG2_BL(SDRAM_BL-1)); 394 MCF_SDRAMC_SDCFG2);
389 395
390 396
391 /* 397 /*
392 * Precharge and enable write to SDMR 398 * Precharge and enable write to SDMR
393 */ 399 */
394 MCF_SDRAMC_SDCR = (0 400 writel(MCF_SDRAMC_SDCR_MODE_EN |
395 | MCF_SDRAMC_SDCR_MODE_EN 401 MCF_SDRAMC_SDCR_CKE |
396 | MCF_SDRAMC_SDCR_CKE 402 MCF_SDRAMC_SDCR_DDR |
397 | MCF_SDRAMC_SDCR_DDR 403 MCF_SDRAMC_SDCR_MUX(1) |
398 | MCF_SDRAMC_SDCR_MUX(1) 404 MCF_SDRAMC_SDCR_RCNT((int)(((SDRAM_TREFI / (SYSTEM_PERIOD * 64)) - 1) + 0.5)) |
399 | MCF_SDRAMC_SDCR_RCNT((int)(((SDRAM_TREFI/(SYSTEM_PERIOD*64)) - 1) + 0.5)) 405 MCF_SDRAMC_SDCR_PS_16 |
400 | MCF_SDRAMC_SDCR_PS_16 406 MCF_SDRAMC_SDCR_IPALL,
401 | MCF_SDRAMC_SDCR_IPALL); 407 MCF_SDRAMC_SDCR);
402 408
403 /* 409 /*
404 * Write extended mode register 410 * Write extended mode register
405 */ 411 */
406 MCF_SDRAMC_SDMR = (0 412 writel(MCF_SDRAMC_SDMR_BNKAD_LEMR |
407 | MCF_SDRAMC_SDMR_BNKAD_LEMR 413 MCF_SDRAMC_SDMR_AD(0x0) |
408 | MCF_SDRAMC_SDMR_AD(0x0) 414 MCF_SDRAMC_SDMR_CMD,
409 | MCF_SDRAMC_SDMR_CMD); 415 MCF_SDRAMC_SDMR);
410 416
411 /* 417 /*
412 * Write mode register and reset DLL 418 * Write mode register and reset DLL
413 */ 419 */
414 MCF_SDRAMC_SDMR = (0 420 writel(MCF_SDRAMC_SDMR_BNKAD_LMR |
415 | MCF_SDRAMC_SDMR_BNKAD_LMR 421 MCF_SDRAMC_SDMR_AD(0x163) |
416 | MCF_SDRAMC_SDMR_AD(0x163) 422 MCF_SDRAMC_SDMR_CMD,
417 | MCF_SDRAMC_SDMR_CMD); 423 MCF_SDRAMC_SDMR);
418 424
419 /* 425 /*
420 * Execute a PALL command 426 * Execute a PALL command
421 */ 427 */
422 MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IPALL; 428 writel(readl(MCF_SDRAMC_SDCR) | MCF_SDRAMC_SDCR_IPALL, MCF_SDRAMC_SDCR);
423 429
424 /* 430 /*
425 * Perform two REF cycles 431 * Perform two REF cycles
426 */ 432 */
427 MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IREF; 433 writel(readl(MCF_SDRAMC_SDCR) | MCF_SDRAMC_SDCR_IREF, MCF_SDRAMC_SDCR);
428 MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IREF; 434 writel(readl(MCF_SDRAMC_SDCR) | MCF_SDRAMC_SDCR_IREF, MCF_SDRAMC_SDCR);
429 435
430 /* 436 /*
431 * Write mode register and clear reset DLL 437 * Write mode register and clear reset DLL
432 */ 438 */
433 MCF_SDRAMC_SDMR = (0 439 writel(MCF_SDRAMC_SDMR_BNKAD_LMR |
434 | MCF_SDRAMC_SDMR_BNKAD_LMR 440 MCF_SDRAMC_SDMR_AD(0x063) |
435 | MCF_SDRAMC_SDMR_AD(0x063) 441 MCF_SDRAMC_SDMR_CMD,
436 | MCF_SDRAMC_SDMR_CMD); 442 MCF_SDRAMC_SDMR);
437 443
438 /* 444 /*
439 * Enable auto refresh and lock SDMR 445 * Enable auto refresh and lock SDMR
440 */ 446 */
441 MCF_SDRAMC_SDCR &= ~MCF_SDRAMC_SDCR_MODE_EN; 447 writel(readl(MCF_SDRAMC_SDCR) & ~MCF_SDRAMC_SDCR_MODE_EN,
442 MCF_SDRAMC_SDCR |= (0 448 MCF_SDRAMC_SDCR);
443 | MCF_SDRAMC_SDCR_REF 449 writel(MCF_SDRAMC_SDCR_REF | MCF_SDRAMC_SDCR_DQS_OE(0xC),
444 | MCF_SDRAMC_SDCR_DQS_OE(0xC)); 450 MCF_SDRAMC_SDCR);
445 } 451 }
446} 452}
447 453
448void gpio_init(void) 454void gpio_init(void)
449{ 455{
450 /* Enable UART0 pins */ 456 /* Enable UART0 pins */
451 MCF_GPIO_PAR_UART = ( 0 457 writew(MCF_GPIO_PAR_UART_PAR_URXD0 | MCF_GPIO_PAR_UART_PAR_UTXD0,
452 | MCF_GPIO_PAR_UART_PAR_URXD0 458 MCFGPIO_PAR_UART);
453 | MCF_GPIO_PAR_UART_PAR_UTXD0);
454
455 /* Initialize TIN3 as a GPIO output to enable the write
456 half of the latch */
457 MCF_GPIO_PAR_TIMER = 0x00;
458 __raw_writeb(0x08, MCFGPIO_PDDR_TIMER);
459 __raw_writeb(0x00, MCFGPIO_PCLRR_TIMER);
460 459
460 /*
461 * Initialize TIN3 as a GPIO output to enable the write
462 * half of the latch.
463 */
464 writeb(0x00, MCFGPIO_PAR_TIMER);
465 writeb(0x08, MCFGPIO_PDDR_TIMER);
466 writeb(0x00, MCFGPIO_PCLRR_TIMER);
461} 467}
462 468
463int clock_pll(int fsys, int flags) 469int clock_pll(int fsys, int flags)
@@ -469,7 +475,7 @@ int clock_pll(int fsys, int flags)
469 475
470 if (fsys == 0) { 476 if (fsys == 0) {
471 /* Return current PLL output */ 477 /* Return current PLL output */
472 mfd = MCF_PLL_PFDR; 478 mfd = readb(MCF_PLL_PFDR);
473 479
474 return (fref * mfd / (BUSDIV * 4)); 480 return (fref * mfd / (BUSDIV * 4));
475 } 481 }
@@ -495,9 +501,10 @@ int clock_pll(int fsys, int flags)
495 * If it has then the SDRAM needs to be put into self refresh 501 * If it has then the SDRAM needs to be put into self refresh
496 * mode before reprogramming the PLL. 502 * mode before reprogramming the PLL.
497 */ 503 */
498 if (MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF) 504 if (readl(MCF_SDRAMC_SDCR) & MCF_SDRAMC_SDCR_REF)
499 /* Put SDRAM into self refresh mode */ 505 /* Put SDRAM into self refresh mode */
500 MCF_SDRAMC_SDCR &= ~MCF_SDRAMC_SDCR_CKE; 506 writel(readl(MCF_SDRAMC_SDCR) & ~MCF_SDRAMC_SDCR_CKE,
507 MCF_SDRAMC_SDCR);
501 508
502 /* 509 /*
503 * Initialize the PLL to generate the new system clock frequency. 510 * Initialize the PLL to generate the new system clock frequency.
@@ -508,11 +515,10 @@ int clock_pll(int fsys, int flags)
508 clock_limp(DEFAULT_LPD); 515 clock_limp(DEFAULT_LPD);
509 516
510 /* Reprogram PLL for desired fsys */ 517 /* Reprogram PLL for desired fsys */
511 MCF_PLL_PODR = (0 518 writeb(MCF_PLL_PODR_CPUDIV(BUSDIV/3) | MCF_PLL_PODR_BUSDIV(BUSDIV),
512 | MCF_PLL_PODR_CPUDIV(BUSDIV/3) 519 MCF_PLL_PODR);
513 | MCF_PLL_PODR_BUSDIV(BUSDIV));
514 520
515 MCF_PLL_PFDR = mfd; 521 writeb(mfd, MCF_PLL_PFDR);
516 522
517 /* Exit LIMP mode */ 523 /* Exit LIMP mode */
518 clock_exit_limp(); 524 clock_exit_limp();
@@ -520,12 +526,13 @@ int clock_pll(int fsys, int flags)
520 /* 526 /*
521 * Return the SDRAM to normal operation if it is in use. 527 * Return the SDRAM to normal operation if it is in use.
522 */ 528 */
523 if (MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF) 529 if (readl(MCF_SDRAMC_SDCR) & MCF_SDRAMC_SDCR_REF)
524 /* Exit self refresh mode */ 530 /* Exit self refresh mode */
525 MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_CKE; 531 writel(readl(MCF_SDRAMC_SDCR) | MCF_SDRAMC_SDCR_CKE,
532 MCF_SDRAMC_SDCR);
526 533
527 /* Errata - workaround for SDRAM opeartion after exiting LIMP mode */ 534 /* Errata - workaround for SDRAM opeartion after exiting LIMP mode */
528 MCF_SDRAMC_LIMP_FIX = MCF_SDRAMC_REFRESH; 535 writel(MCF_SDRAMC_REFRESH, MCF_SDRAMC_LIMP_FIX);
529 536
530 /* wait for DQS logic to relock */ 537 /* wait for DQS logic to relock */
531 for (i = 0; i < 0x200; i++) 538 for (i = 0; i < 0x200; i++)
@@ -546,14 +553,12 @@ int clock_limp(int div)
546 553
547 /* Save of the current value of the SSIDIV so we don't 554 /* Save of the current value of the SSIDIV so we don't
548 overwrite the value*/ 555 overwrite the value*/
549 temp = (MCF_CCM_CDR & MCF_CCM_CDR_SSIDIV(0xF)); 556 temp = readw(MCF_CCM_CDR) & MCF_CCM_CDR_SSIDIV(0xF);
550 557
551 /* Apply the divider to the system clock */ 558 /* Apply the divider to the system clock */
552 MCF_CCM_CDR = ( 0 559 writew(MCF_CCM_CDR_LPDIV(div) | MCF_CCM_CDR_SSIDIV(temp), MCF_CCM_CDR);
553 | MCF_CCM_CDR_LPDIV(div)
554 | MCF_CCM_CDR_SSIDIV(temp));
555 560
556 MCF_CCM_MISCCR |= MCF_CCM_MISCCR_LIMP; 561 writew(readw(MCF_CCM_MISCCR) | MCF_CCM_MISCCR_LIMP, MCF_CCM_MISCCR);
557 562
558 return (FREF/(3*(1 << div))); 563 return (FREF/(3*(1 << div)));
559} 564}
@@ -563,10 +568,10 @@ int clock_exit_limp(void)
563 int fout; 568 int fout;
564 569
565 /* Exit LIMP mode */ 570 /* Exit LIMP mode */
566 MCF_CCM_MISCCR = (MCF_CCM_MISCCR & ~ MCF_CCM_MISCCR_LIMP); 571 writew(readw(MCF_CCM_MISCCR) & ~MCF_CCM_MISCCR_LIMP, MCF_CCM_MISCCR);
567 572
568 /* Wait for PLL to lock */ 573 /* Wait for PLL to lock */
569 while (!(MCF_CCM_MISCCR & MCF_CCM_MISCCR_PLL_LOCK)) 574 while (!(readw(MCF_CCM_MISCCR) & MCF_CCM_MISCCR_PLL_LOCK))
570 ; 575 ;
571 576
572 fout = get_sys_clock(); 577 fout = get_sys_clock();
@@ -579,10 +584,10 @@ int get_sys_clock(void)
579 int divider; 584 int divider;
580 585
581 /* Test to see if device is in LIMP mode */ 586 /* Test to see if device is in LIMP mode */
582 if (MCF_CCM_MISCCR & MCF_CCM_MISCCR_LIMP) { 587 if (readw(MCF_CCM_MISCCR) & MCF_CCM_MISCCR_LIMP) {
583 divider = MCF_CCM_CDR & MCF_CCM_CDR_LPDIV(0xF); 588 divider = readw(MCF_CCM_CDR) & MCF_CCM_CDR_LPDIV(0xF);
584 return (FREF/(2 << divider)); 589 return (FREF/(2 << divider));
585 } 590 }
586 else 591 else
587 return ((FREF * MCF_PLL_PFDR) / (BUSDIV * 4)); 592 return (FREF * readb(MCF_PLL_PFDR)) / (BUSDIV * 4);
588} 593}
diff --git a/arch/m68k/platform/coldfire/m54xx.c b/arch/m68k/platform/coldfire/m54xx.c
index 2081c6cbb3de..b587bf35175b 100644
--- a/arch/m68k/platform/coldfire/m54xx.c
+++ b/arch/m68k/platform/coldfire/m54xx.c
@@ -30,14 +30,12 @@
30static void __init m54xx_uarts_init(void) 30static void __init m54xx_uarts_init(void)
31{ 31{
32 /* enable io pins */ 32 /* enable io pins */
33 __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD, 33 __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD, MCFGPIO_PAR_PSC0);
34 MCF_MBAR + MCF_PAR_PSC(0));
35 __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD | MCF_PAR_PSC_RTS_RTS, 34 __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD | MCF_PAR_PSC_RTS_RTS,
36 MCF_MBAR + MCF_PAR_PSC(1)); 35 MCFGPIO_PAR_PSC1);
37 __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD | MCF_PAR_PSC_RTS_RTS | 36 __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD | MCF_PAR_PSC_RTS_RTS |
38 MCF_PAR_PSC_CTS_CTS, MCF_MBAR + MCF_PAR_PSC(2)); 37 MCF_PAR_PSC_CTS_CTS, MCFGPIO_PAR_PSC2);
39 __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD, 38 __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD, MCFGPIO_PAR_PSC3);
40 MCF_MBAR + MCF_PAR_PSC(3));
41} 39}
42 40
43/***************************************************************************/ 41/***************************************************************************/
@@ -46,10 +44,10 @@ static void mcf54xx_reset(void)
46{ 44{
47 /* disable interrupts and enable the watchdog */ 45 /* disable interrupts and enable the watchdog */
48 asm("movew #0x2700, %sr\n"); 46 asm("movew #0x2700, %sr\n");
49 __raw_writel(0, MCF_MBAR + MCF_GPT_GMS0); 47 __raw_writel(0, MCF_GPT_GMS0);
50 __raw_writel(MCF_GPT_GCIR_CNT(1), MCF_MBAR + MCF_GPT_GCIR0); 48 __raw_writel(MCF_GPT_GCIR_CNT(1), MCF_GPT_GCIR0);
51 __raw_writel(MCF_GPT_GMS_WDEN | MCF_GPT_GMS_CE | MCF_GPT_GMS_TMS(4), 49 __raw_writel(MCF_GPT_GMS_WDEN | MCF_GPT_GMS_CE | MCF_GPT_GMS_TMS(4),
52 MCF_MBAR + MCF_GPT_GMS0); 50 MCF_GPT_GMS0);
53} 51}
54 52
55/***************************************************************************/ 53/***************************************************************************/
diff --git a/arch/m68k/platform/coldfire/nettel.c b/arch/m68k/platform/coldfire/nettel.c
index e925ea4602f8..ddc48ec1b800 100644
--- a/arch/m68k/platform/coldfire/nettel.c
+++ b/arch/m68k/platform/coldfire/nettel.c
@@ -121,14 +121,14 @@ static void __init nettel_smc91x_setmac(unsigned int ioaddr, unsigned int flasha
121 121
122static void __init nettel_smc91x_init(void) 122static void __init nettel_smc91x_init(void)
123{ 123{
124 writew(0x00ec, MCF_MBAR + MCFSIM_PADDR); 124 writew(0x00ec, MCFSIM_PADDR);
125 mcf_setppdata(0, 0x0080); 125 mcf_setppdata(0, 0x0080);
126 writew(1, NETTEL_SMC0_ADDR + SMC91xx_BANKSELECT); 126 writew(1, NETTEL_SMC0_ADDR + SMC91xx_BANKSELECT);
127 writew(0x0067, NETTEL_SMC0_ADDR + SMC91xx_BASEADDR); 127 writew(0x0067, NETTEL_SMC0_ADDR + SMC91xx_BASEADDR);
128 mcf_setppdata(0x0080, 0); 128 mcf_setppdata(0x0080, 0);
129 129
130 /* Set correct chip select timing for SMC9196 accesses */ 130 /* Set correct chip select timing for SMC9196 accesses */
131 writew(0x1180, MCF_MBAR + MCFSIM_CSCR3); 131 writew(0x1180, MCFSIM_CSCR3);
132 132
133 /* Set the SMC interrupts to be auto-vectored */ 133 /* Set the SMC interrupts to be auto-vectored */
134 mcf_autovector(NETTEL_SMC0_IRQ); 134 mcf_autovector(NETTEL_SMC0_IRQ);
diff --git a/arch/m68k/platform/coldfire/pci.c b/arch/m68k/platform/coldfire/pci.c
index 553210d3d4c1..8572246db84d 100644
--- a/arch/m68k/platform/coldfire/pci.c
+++ b/arch/m68k/platform/coldfire/pci.c
@@ -272,8 +272,8 @@ static int __init mcf_pci_init(void)
272 PACR_EXTMINTE(0x1f), PACR); 272 PACR_EXTMINTE(0x1f), PACR);
273 273
274 /* Set required multi-function pins for PCI bus use */ 274 /* Set required multi-function pins for PCI bus use */
275 __raw_writew(0x3ff, MCF_PAR_PCIBG); 275 __raw_writew(0x3ff, MCFGPIO_PAR_PCIBG);
276 __raw_writew(0x3ff, MCF_PAR_PCIBR); 276 __raw_writew(0x3ff, MCFGPIO_PAR_PCIBR);
277 277
278 /* Set up config space for local host bus controller */ 278 /* Set up config space for local host bus controller */
279 __raw_writel(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | 279 __raw_writel(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
diff --git a/arch/m68k/platform/coldfire/reset.c b/arch/m68k/platform/coldfire/reset.c
index 933e54eacc69..f30952f0cbe6 100644
--- a/arch/m68k/platform/coldfire/reset.c
+++ b/arch/m68k/platform/coldfire/reset.c
@@ -27,7 +27,7 @@ static void mcf_cpu_reset(void)
27{ 27{
28 local_irq_disable(); 28 local_irq_disable();
29 /* Set watchdog to soft reset, and enabled */ 29 /* Set watchdog to soft reset, and enabled */
30 __raw_writeb(0xc0, MCF_MBAR + MCFSIM_SYPCR); 30 __raw_writeb(0xc0, MCFSIM_SYPCR);
31 for (;;) 31 for (;;)
32 /* wait for watchdog to timeout */; 32 /* wait for watchdog to timeout */;
33} 33}
diff --git a/arch/m68k/platform/coldfire/sltimers.c b/arch/m68k/platform/coldfire/sltimers.c
index 2027fc20b876..bb5a25ada848 100644
--- a/arch/m68k/platform/coldfire/sltimers.c
+++ b/arch/m68k/platform/coldfire/sltimers.c
@@ -32,7 +32,7 @@
32/* 32/*
33 * By default use Slice Timer 1 as the profiler clock timer. 33 * By default use Slice Timer 1 as the profiler clock timer.
34 */ 34 */
35#define PA(a) (MCF_MBAR + MCFSLT_TIMER1 + (a)) 35#define PA(a) (MCFSLT_TIMER1 + (a))
36 36
37/* 37/*
38 * Choose a reasonably fast profile timer. Make it an odd value to 38 * Choose a reasonably fast profile timer. Make it an odd value to
@@ -76,7 +76,7 @@ void mcfslt_profile_init(void)
76/* 76/*
77 * By default use Slice Timer 0 as the system clock timer. 77 * By default use Slice Timer 0 as the system clock timer.
78 */ 78 */
79#define TA(a) (MCF_MBAR + MCFSLT_TIMER0 + (a)) 79#define TA(a) (MCFSLT_TIMER0 + (a))
80 80
81static u32 mcfslt_cycles_per_jiffy; 81static u32 mcfslt_cycles_per_jiffy;
82static u32 mcfslt_cnt; 82static u32 mcfslt_cnt;
diff --git a/arch/m68k/platform/coldfire/timers.c b/arch/m68k/platform/coldfire/timers.c
index 0a273e75408c..51f6d2af807f 100644
--- a/arch/m68k/platform/coldfire/timers.c
+++ b/arch/m68k/platform/coldfire/timers.c
@@ -56,13 +56,13 @@ static void init_timer_irq(void)
56#ifdef MCFSIM_ICR_AUTOVEC 56#ifdef MCFSIM_ICR_AUTOVEC
57 /* Timer1 is always used as system timer */ 57 /* Timer1 is always used as system timer */
58 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3, 58 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3,
59 MCF_MBAR + MCFSIM_TIMER1ICR); 59 MCFSIM_TIMER1ICR);
60 mcf_mapirq2imr(MCF_IRQ_TIMER, MCFINTC_TIMER1); 60 mcf_mapirq2imr(MCF_IRQ_TIMER, MCFINTC_TIMER1);
61 61
62#ifdef CONFIG_HIGHPROFILE 62#ifdef CONFIG_HIGHPROFILE
63 /* Timer2 is to be used as a high speed profile timer */ 63 /* Timer2 is to be used as a high speed profile timer */
64 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3, 64 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3,
65 MCF_MBAR + MCFSIM_TIMER2ICR); 65 MCFSIM_TIMER2ICR);
66 mcf_mapirq2imr(MCF_IRQ_PROFILER, MCFINTC_TIMER2); 66 mcf_mapirq2imr(MCF_IRQ_PROFILER, MCFINTC_TIMER2);
67#endif 67#endif
68#endif /* MCFSIM_ICR_AUTOVEC */ 68#endif /* MCFSIM_ICR_AUTOVEC */
diff --git a/arch/m68k/q40/config.c b/arch/m68k/q40/config.c
index 8a1ce327c963..1adb5b7b0d1a 100644
--- a/arch/m68k/q40/config.c
+++ b/arch/m68k/q40/config.c
@@ -338,9 +338,6 @@ static __init int q40_add_kbd_device(void)
338 return -ENODEV; 338 return -ENODEV;
339 339
340 pdev = platform_device_register_simple("q40kbd", -1, NULL, 0); 340 pdev = platform_device_register_simple("q40kbd", -1, NULL, 0);
341 if (IS_ERR(pdev)) 341 return PTR_RET(pdev);
342 return PTR_ERR(pdev);
343
344 return 0;
345} 342}
346arch_initcall(q40_add_kbd_device); 343arch_initcall(q40_add_kbd_device);
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-24 05:28:20 -0500