10 files changed, 208 insertions, 17 deletions
diff --git a/arch/m68k/include/asm/cacheflush_no.h b/arch/m68k/include/asm/cacheflush_no.h
index 89f195656be7..7085bd51668b 100644
--- a/arch/m68k/include/asm/cacheflush_no.h
+++ b/arch/m68k/include/asm/cacheflush_no.h
@@ -29,7 +29,7 @@
 static inline void __flush_cache_all(void)
 {
-#ifdef CONFIG_M5407
+#if defined(CONFIG_M5407) || defined(CONFIG_M548x)
        /*
         *      Use cpushl to push and invalidate all cache lines.
         *      Gas doesn't seem to know how to generate the ColdFire
diff --git a/arch/m68k/include/asm/coldfire.h b/arch/m68k/include/asm/coldfire.h
index 83a9fa4e618a..3b0a34d0fe33 100644
--- a/arch/m68k/include/asm/coldfire.h
+++ b/arch/m68k/include/asm/coldfire.h
@@ -32,7 +32,9 @@
 */
 #define MCF_MBAR        0x10000000
 #define MCF_MBAR2       0x80000000
-#if defined(CONFIG_M520x)
+#if defined(CONFIG_M548x)
+#define MCF_IPSBAR      MCF_MBAR
+#elif defined(CONFIG_M520x)
 #define MCF_IPSBAR      0xFC000000
 #else
 #define MCF_IPSBAR      0x40000000
diff --git a/arch/m68k/include/asm/gpio.h b/arch/m68k/include/asm/gpio.h
index 283214dc65a7..1b57adbafad5 100644
--- a/arch/m68k/include/asm/gpio.h
+++ b/arch/m68k/include/asm/gpio.h
@@ -36,7 +36,8 @@
 */
 #if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
    defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
-    defined(CONFIG_M527x) || defined(CONFIG_M528x) || defined(CONFIG_M532x)
+    defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
+    defined(CONFIG_M532x) || defined(CONFIG_M548x)
 /* These parts have GPIO organized by 8 bit ports */
@@ -136,6 +137,8 @@ static inline u32 __mcf_gpio_ppdr(unsigned gpio)
 #endif
        else
                return MCFGPIO_PPDR + mcfgpio_port(gpio - MCFGPIO_SCR_START);
+#else
+        return 0;
 #endif
 }
@@ -173,6 +176,8 @@ static inline u32 __mcf_gpio_podr(unsigned gpio)
 #endif
        else
                return MCFGPIO_PODR + mcfgpio_port(gpio - MCFGPIO_SCR_START);
+#else
+        return 0;
 #endif
 }
diff --git a/arch/m68k/include/asm/m548xgpt.h b/arch/m68k/include/asm/m548xgpt.h
new file mode 100644
index 000000000000..c8ef158a1c4e
--- /dev/null
+++ b/arch/m68k/include/asm/m548xgpt.h
@@ -0,0 +1,88 @@
+/*
+ * File:        m548xgpt.h
+ * Purpose:     Register and bit definitions for the MCF548X
+ *
+ * Notes:
+ *
+ */
+#ifndef m548xgpt_h
+#define m548xgpt_h
+/*********************************************************************
+*
+* General Purpose Timers (GPT)
+*
+*********************************************************************/
+/* Register read/write macros */
+#define MCF_GPT_GMS0       0x000800
+#define MCF_GPT_GCIR0      0x000804
+#define MCF_GPT_GPWM0      0x000808
+#define MCF_GPT_GSR0       0x00080C
+#define MCF_GPT_GMS1       0x000810
+#define MCF_GPT_GCIR1      0x000814
+#define MCF_GPT_GPWM1      0x000818
+#define MCF_GPT_GSR1       0x00081C
+#define MCF_GPT_GMS2       0x000820
+#define MCF_GPT_GCIR2      0x000824
+#define MCF_GPT_GPWM2      0x000828
+#define MCF_GPT_GSR2       0x00082C
+#define MCF_GPT_GMS3       0x000830
+#define MCF_GPT_GCIR3      0x000834
+#define MCF_GPT_GPWM3      0x000838
+#define MCF_GPT_GSR3       0x00083C
+#define MCF_GPT_GMS(x)     (0x000800+((x)*0x010))
+#define MCF_GPT_GCIR(x)    (0x000804+((x)*0x010))
+#define MCF_GPT_GPWM(x)    (0x000808+((x)*0x010))
+#define MCF_GPT_GSR(x)     (0x00080C+((x)*0x010))
+/* Bit definitions and macros for MCF_GPT_GMS */
+#define MCF_GPT_GMS_TMS(x)         (((x)&0x00000007)<<0)
+#define MCF_GPT_GMS_GPIO(x)        (((x)&0x00000003)<<4)
+#define MCF_GPT_GMS_IEN            (0x00000100)
+#define MCF_GPT_GMS_OD             (0x00000200)
+#define MCF_GPT_GMS_SC             (0x00000400)
+#define MCF_GPT_GMS_CE             (0x00001000)
+#define MCF_GPT_GMS_WDEN           (0x00008000)
+#define MCF_GPT_GMS_ICT(x)         (((x)&0x00000003)<<16)
+#define MCF_GPT_GMS_OCT(x)         (((x)&0x00000003)<<20)
+#define MCF_GPT_GMS_OCPW(x)        (((x)&0x000000FF)<<24)
+#define MCF_GPT_GMS_OCT_FRCLOW     (0x00000000)
+#define MCF_GPT_GMS_OCT_PULSEHI    (0x00100000)
+#define MCF_GPT_GMS_OCT_PULSELO    (0x00200000)
+#define MCF_GPT_GMS_OCT_TOGGLE     (0x00300000)
+#define MCF_GPT_GMS_ICT_ANY        (0x00000000)
+#define MCF_GPT_GMS_ICT_RISE       (0x00010000)
+#define MCF_GPT_GMS_ICT_FALL       (0x00020000)
+#define MCF_GPT_GMS_ICT_PULSE      (0x00030000)
+#define MCF_GPT_GMS_GPIO_INPUT     (0x00000000)
+#define MCF_GPT_GMS_GPIO_OUTLO     (0x00000020)
+#define MCF_GPT_GMS_GPIO_OUTHI     (0x00000030)
+#define MCF_GPT_GMS_TMS_DISABLE    (0x00000000)
+#define MCF_GPT_GMS_TMS_INCAPT     (0x00000001)
+#define MCF_GPT_GMS_TMS_OUTCAPT    (0x00000002)
+#define MCF_GPT_GMS_TMS_PWM        (0x00000003)
+#define MCF_GPT_GMS_TMS_GPIO       (0x00000004)
+/* Bit definitions and macros for MCF_GPT_GCIR */
+#define MCF_GPT_GCIR_CNT(x)        (((x)&0x0000FFFF)<<0)
+#define MCF_GPT_GCIR_PRE(x)        (((x)&0x0000FFFF)<<16)
+/* Bit definitions and macros for MCF_GPT_GPWM */
+#define MCF_GPT_GPWM_LOAD          (0x00000001)
+#define MCF_GPT_GPWM_PWMOP         (0x00000100)
+#define MCF_GPT_GPWM_WIDTH(x)      (((x)&0x0000FFFF)<<16)
+/* Bit definitions and macros for MCF_GPT_GSR */
+#define MCF_GPT_GSR_CAPT           (0x00000001)
+#define MCF_GPT_GSR_COMP           (0x00000002)
+#define MCF_GPT_GSR_PWMP           (0x00000004)
+#define MCF_GPT_GSR_TEXP           (0x00000008)
+#define MCF_GPT_GSR_PIN            (0x00000100)
+#define MCF_GPT_GSR_OVF(x)         (((x)&0x00000007)<<12)
+#define MCF_GPT_GSR_CAPTURE(x)     (((x)&0x0000FFFF)<<16)
+/********************************************************************/
+#endif /* m548xgpt_h */
diff --git a/arch/m68k/include/asm/m548xsim.h b/arch/m68k/include/asm/m548xsim.h
new file mode 100644
index 000000000000..149135ef30d2
--- /dev/null
+++ b/arch/m68k/include/asm/m548xsim.h
@@ -0,0 +1,55 @@
+/*
+ *      m548xsim.h -- ColdFire 547x/548x System Integration Unit support.
+ */
+#ifndef m548xsim_h
+#define m548xsim_h
+#define MCFINT_VECBASE      64
+/*
+ *      Interrupt Controller Registers
+ */
+#define MCFICM_INTC0            0x0700          /* Base for Interrupt Ctrl 0 */
+#define MCFINTC_IPRH            0x00            /* Interrupt pending 32-63 */
+#define MCFINTC_IPRL            0x04            /* Interrupt pending 1-31 */
+#define MCFINTC_IMRH            0x08            /* Interrupt mask 32-63 */
+#define MCFINTC_IMRL            0x0c            /* Interrupt mask 1-31 */
+#define MCFINTC_INTFRCH         0x10            /* Interrupt force 32-63 */
+#define MCFINTC_INTFRCL         0x14            /* Interrupt force 1-31 */
+#define MCFINTC_IRLR            0x18            /* */
+#define MCFINTC_IACKL           0x19            /* */
+#define MCFINTC_ICR0            0x40            /* Base ICR register */
+/*
+ *      Define system peripheral IRQ usage.
+ */
+#define MCF_IRQ_TIMER           (64 + 54)       /* Slice Timer 0 */
+#define MCF_IRQ_PROFILER        (64 + 53)       /* Slice Timer 1 */
+/*
+ *      Generic GPIO support
+ */
+#define MCFGPIO_PIN_MAX         0       /* I am too lazy to count */
+#define MCFGPIO_IRQ_MAX         -1
+#define MCFGPIO_IRQ_VECBASE     -1
+/*
+ *      Some PSC related definitions
+ */
+#define MCF_PAR_PSC(x)          (0x000A4F-((x)&0x3))
+#define MCF_PAR_SDA             (0x0008)
+#define MCF_PAR_SCL             (0x0004)
+#define MCF_PAR_PSC_TXD         (0x04)
+#define MCF_PAR_PSC_RXD         (0x08)
+#define MCF_PAR_PSC_RTS(x)      (((x)&0x03)<<4)
+#define MCF_PAR_PSC_CTS(x)      (((x)&0x03)<<6)
+#define MCF_PAR_PSC_CTS_GPIO    (0x00)
+#define MCF_PAR_PSC_CTS_BCLK    (0x80)
+#define MCF_PAR_PSC_CTS_CTS     (0xC0)
+#define MCF_PAR_PSC_RTS_GPIO    (0x00)
+#define MCF_PAR_PSC_RTS_FSYNC   (0x20)
+#define MCF_PAR_PSC_RTS_RTS     (0x30)
+#define MCF_PAR_PSC_CANRX       (0x40)
+#endif  /* m548xsim_h */
diff --git a/arch/m68k/include/asm/mcfcache.h b/arch/m68k/include/asm/mcfcache.h
index c042634fadaa..f49dfc09f70a 100644
--- a/arch/m68k/include/asm/mcfcache.h
+++ b/arch/m68k/include/asm/mcfcache.h
@@ -107,7 +107,7 @@
 .endm
 #endif /* CONFIG_M532x */
-#if defined(CONFIG_M5407)
+#if defined(CONFIG_M5407) || defined(CONFIG_M548x)
 /*
 *      Version 4 cores have a true harvard style separate instruction
 *      and data cache. Invalidate and enable cache, also enable write
diff --git a/arch/m68k/include/asm/mcfsim.h b/arch/m68k/include/asm/mcfsim.h
index 9c70a67bf85f..6901fd68165b 100644
--- a/arch/m68k/include/asm/mcfsim.h
+++ b/arch/m68k/include/asm/mcfsim.h
@@ -41,6 +41,8 @@
 #elif defined(CONFIG_M5407)
 #include <asm/m5407sim.h>
 #include <asm/mcfintc.h>
+#elif defined(CONFIG_M548x)
+#include <asm/m548xsim.h>
 #endif
 /****************************************************************************/
diff --git a/arch/m68k/include/asm/mcfslt.h b/arch/m68k/include/asm/mcfslt.h
new file mode 100644
index 000000000000..d0d0ecba5333
--- /dev/null
+++ b/arch/m68k/include/asm/mcfslt.h
@@ -0,0 +1,44 @@
+/****************************************************************************/
+/*
+ *      mcfslt.h -- ColdFire internal Slice (SLT) timer support defines.
+ *
+ *      (C) Copyright 2004, Greg Ungerer (gerg@snapgear.com)
+ *      (C) Copyright 2009, Philippe De Muyter (phdm@macqel.be)
+ */
+/****************************************************************************/
+#ifndef mcfslt_h
+#define mcfslt_h
+/****************************************************************************/
+/*
+ *      Get address specific defines for the 547x.
+ */
+#define MCFSLT_TIMER0           0x900   /* Base address of TIMER0 */
+#define MCFSLT_TIMER1           0x910   /* Base address of TIMER1 */
+/*
+ *      Define the SLT timer register set addresses.
+ */
+#define MCFSLT_STCNT            0x00    /* Terminal count */
+#define MCFSLT_SCR              0x04    /* Control */
+#define MCFSLT_SCNT             0x08    /* Current count */
+#define MCFSLT_SSR              0x0C    /* Status */
+/*
+ *      Bit definitions for the SCR control register.
+ */
+#define MCFSLT_SCR_RUN          0x04000000      /* Run mode (continuous) */
+#define MCFSLT_SCR_IEN          0x02000000      /* Interrupt enable */
+#define MCFSLT_SCR_TEN          0x01000000      /* Timer enable */
+/*
+ *      Bit definitions for the SSR status register.
+ */
+#define MCFSLT_SSR_BE           0x02000000      /* Bus error condition */
+#define MCFSLT_SSR_TE           0x01000000      /* Timeout condition */
+/****************************************************************************/
+#endif  /* mcfslt_h */
diff --git a/arch/m68k/include/asm/mcfuart.h b/arch/m68k/include/asm/mcfuart.h
index 01a8716c5fc5..db72e2b889ca 100644
--- a/arch/m68k/include/asm/mcfuart.h
+++ b/arch/m68k/include/asm/mcfuart.h
@@ -47,6 +47,11 @@
 #define MCFUART_BASE1           0xfc060000      /* Base address of UART1 */
 #define MCFUART_BASE2           0xfc064000      /* Base address of UART2 */
 #define MCFUART_BASE3           0xfc068000      /* Base address of UART3 */
+#elif defined(CONFIG_M548x)
+#define MCFUART_BASE1           0x8600          /* on M548x */
+#define MCFUART_BASE2           0x8700          /* on M548x */
+#define MCFUART_BASE3           0x8800          /* on M548x */
+#define MCFUART_BASE4           0x8900          /* on M548x */
 #endif
@@ -212,7 +217,9 @@ struct mcf_platform_uart {
 #define MCFUART_URF_RXS         0xc0            /* Receiver status */
 #endif
-#if defined(CONFIG_M5272)
+#if defined(CONFIG_M548x)
+#define MCFUART_TXFIFOSIZE      512
+#elif defined(CONFIG_M5272)
 #define MCFUART_TXFIFOSIZE      25
 #else
 #define MCFUART_TXFIFOSIZE      1
diff --git a/arch/m68k/kernel/asm-offsets.c b/arch/m68k/kernel/asm-offsets.c
index 73e5e581245b..78e59b82ebc3 100644
--- a/arch/m68k/kernel/asm-offsets.c
+++ b/arch/m68k/kernel/asm-offsets.c
@@ -22,13 +22,9 @@
 int main(void)
 {
        /* offsets into the task struct */
-        DEFINE(TASK_STATE, offsetof(struct task_struct, state));
-        DEFINE(TASK_FLAGS, offsetof(struct task_struct, flags));
-        DEFINE(TASK_PTRACE, offsetof(struct task_struct, ptrace));
        DEFINE(TASK_THREAD, offsetof(struct task_struct, thread));
        DEFINE(TASK_INFO, offsetof(struct task_struct, thread.info));
        DEFINE(TASK_MM, offsetof(struct task_struct, mm));
-        DEFINE(TASK_ACTIVE_MM, offsetof(struct task_struct, active_mm));
 #ifdef CONFIG_MMU
        DEFINE(TASK_TINFO, offsetof(struct task_struct, thread.info));
 #endif
@@ -64,14 +60,6 @@ int main(void)
        /* bitfields are a bit difficult */
        DEFINE(PT_OFF_FORMATVEC, offsetof(struct pt_regs, pc) + 4);
-        /* offsets into the irq_handler struct */
-        DEFINE(IRQ_HANDLER, offsetof(struct irq_node, handler));
-        DEFINE(IRQ_DEVID, offsetof(struct irq_node, dev_id));
-        DEFINE(IRQ_NEXT, offsetof(struct irq_node, next));
-        /* offsets into the kernel_stat struct */
-        DEFINE(STAT_IRQ, offsetof(struct kernel_stat, irqs));
        /* offsets into the irq_cpustat_t struct */
        DEFINE(CPUSTAT_SOFTIRQ_PENDING, offsetof(irq_cpustat_t, __softirq_pending));

diff --git a/arch/m68k/include/asm/cacheflush_no.h b/arch/m68k/include/asm/cacheflush_no.h index 89f195656be7..7085bd51668b 100644 --- a/arch/m68k/include/asm/cacheflush_no.h +++ b/arch/m68k/include/asm/cacheflush_no.h
@@ -29,7 +29,7 @@
29		29
30	static inline void __flush_cache_all(void)	30	static inline void __flush_cache_all(void)
31	{	31	{
32	#ifdef CONFIG_M5407	32	#if defined(CONFIG_M5407) \|\| defined(CONFIG_M548x)
33	/*	33	/*
34	* Use cpushl to push and invalidate all cache lines.	34	* Use cpushl to push and invalidate all cache lines.
35	* Gas doesn't seem to know how to generate the ColdFire	35	* Gas doesn't seem to know how to generate the ColdFire


diff --git a/arch/m68k/include/asm/coldfire.h b/arch/m68k/include/asm/coldfire.h index 83a9fa4e618a..3b0a34d0fe33 100644 --- a/arch/m68k/include/asm/coldfire.h +++ b/arch/m68k/include/asm/coldfire.h
@@ -32,7 +32,9 @@
32	*/	32	*/
33	#define MCF_MBAR 0x10000000	33	#define MCF_MBAR 0x10000000
34	#define MCF_MBAR2 0x80000000	34	#define MCF_MBAR2 0x80000000
35	#if defined(CONFIG_M520x)	35	#if defined(CONFIG_M548x)
		36	#define MCF_IPSBAR MCF_MBAR
		37	#elif defined(CONFIG_M520x)
36	#define MCF_IPSBAR 0xFC000000	38	#define MCF_IPSBAR 0xFC000000
37	#else	39	#else
38	#define MCF_IPSBAR 0x40000000	40	#define MCF_IPSBAR 0x40000000


diff --git a/arch/m68k/include/asm/gpio.h b/arch/m68k/include/asm/gpio.h index 283214dc65a7..1b57adbafad5 100644 --- a/arch/m68k/include/asm/gpio.h +++ b/arch/m68k/include/asm/gpio.h
@@ -36,7 +36,8 @@
36	*/	36	*/
37	#if defined(CONFIG_M5206) \|\| defined(CONFIG_M5206e) \|\| \	37	#if defined(CONFIG_M5206) \|\| defined(CONFIG_M5206e) \|\| \
38	defined(CONFIG_M520x) \|\| defined(CONFIG_M523x) \|\| \	38	defined(CONFIG_M520x) \|\| defined(CONFIG_M523x) \|\| \
39	defined(CONFIG_M527x) \|\| defined(CONFIG_M528x) \|\| defined(CONFIG_M532x)	39	defined(CONFIG_M527x) \|\| defined(CONFIG_M528x) \|\| \
		40	defined(CONFIG_M532x) \|\| defined(CONFIG_M548x)
40		41
41	/* These parts have GPIO organized by 8 bit ports */	42	/* These parts have GPIO organized by 8 bit ports */
42		43
@@ -136,6 +137,8 @@ static inline u32 __mcf_gpio_ppdr(unsigned gpio)
136	#endif	137	#endif
137	else	138	else
138	return MCFGPIO_PPDR + mcfgpio_port(gpio - MCFGPIO_SCR_START);	139	return MCFGPIO_PPDR + mcfgpio_port(gpio - MCFGPIO_SCR_START);
		140	#else
		141	return 0;
139	#endif	142	#endif
140	}	143	}
141		144
@@ -173,6 +176,8 @@ static inline u32 __mcf_gpio_podr(unsigned gpio)
173	#endif	176	#endif
174	else	177	else
175	return MCFGPIO_PODR + mcfgpio_port(gpio - MCFGPIO_SCR_START);	178	return MCFGPIO_PODR + mcfgpio_port(gpio - MCFGPIO_SCR_START);
		179	#else
		180	return 0;
176	#endif	181	#endif
177	}	182	}
178		183


diff --git a/arch/m68k/include/asm/m548xgpt.h b/arch/m68k/include/asm/m548xgpt.h new file mode 100644 index 000000000000..c8ef158a1c4e --- /dev/null +++ b/arch/m68k/include/asm/m548xgpt.h
@@ -0,0 +1,88 @@
		1	/*
		2	* File: m548xgpt.h
		3	* Purpose: Register and bit definitions for the MCF548X
		4	*
		5	* Notes:
		6	*
		7	*/
		8
		9	#ifndef m548xgpt_h
		10	#define m548xgpt_h
		11
		12	/*********************************************************************
		13	*
		14	* General Purpose Timers (GPT)
		15	*
		16	*********************************************************************/
		17
		18	/* Register read/write macros */
		19	#define MCF_GPT_GMS0 0x000800
		20	#define MCF_GPT_GCIR0 0x000804
		21	#define MCF_GPT_GPWM0 0x000808
		22	#define MCF_GPT_GSR0 0x00080C
		23	#define MCF_GPT_GMS1 0x000810
		24	#define MCF_GPT_GCIR1 0x000814
		25	#define MCF_GPT_GPWM1 0x000818
		26	#define MCF_GPT_GSR1 0x00081C
		27	#define MCF_GPT_GMS2 0x000820
		28	#define MCF_GPT_GCIR2 0x000824
		29	#define MCF_GPT_GPWM2 0x000828
		30	#define MCF_GPT_GSR2 0x00082C
		31	#define MCF_GPT_GMS3 0x000830
		32	#define MCF_GPT_GCIR3 0x000834
		33	#define MCF_GPT_GPWM3 0x000838
		34	#define MCF_GPT_GSR3 0x00083C
		35	#define MCF_GPT_GMS(x) (0x000800+((x)*0x010))
		36	#define MCF_GPT_GCIR(x) (0x000804+((x)*0x010))
		37	#define MCF_GPT_GPWM(x) (0x000808+((x)*0x010))
		38	#define MCF_GPT_GSR(x) (0x00080C+((x)*0x010))
		39
		40	/* Bit definitions and macros for MCF_GPT_GMS */
		41	#define MCF_GPT_GMS_TMS(x) (((x)&0x00000007)<<0)
		42	#define MCF_GPT_GMS_GPIO(x) (((x)&0x00000003)<<4)
		43	#define MCF_GPT_GMS_IEN (0x00000100)
		44	#define MCF_GPT_GMS_OD (0x00000200)
		45	#define MCF_GPT_GMS_SC (0x00000400)
		46	#define MCF_GPT_GMS_CE (0x00001000)
		47	#define MCF_GPT_GMS_WDEN (0x00008000)
		48	#define MCF_GPT_GMS_ICT(x) (((x)&0x00000003)<<16)
		49	#define MCF_GPT_GMS_OCT(x) (((x)&0x00000003)<<20)
		50	#define MCF_GPT_GMS_OCPW(x) (((x)&0x000000FF)<<24)
		51	#define MCF_GPT_GMS_OCT_FRCLOW (0x00000000)
		52	#define MCF_GPT_GMS_OCT_PULSEHI (0x00100000)
		53	#define MCF_GPT_GMS_OCT_PULSELO (0x00200000)
		54	#define MCF_GPT_GMS_OCT_TOGGLE (0x00300000)
		55	#define MCF_GPT_GMS_ICT_ANY (0x00000000)
		56	#define MCF_GPT_GMS_ICT_RISE (0x00010000)
		57	#define MCF_GPT_GMS_ICT_FALL (0x00020000)
		58	#define MCF_GPT_GMS_ICT_PULSE (0x00030000)
		59	#define MCF_GPT_GMS_GPIO_INPUT (0x00000000)
		60	#define MCF_GPT_GMS_GPIO_OUTLO (0x00000020)
		61	#define MCF_GPT_GMS_GPIO_OUTHI (0x00000030)
		62	#define MCF_GPT_GMS_TMS_DISABLE (0x00000000)
		63	#define MCF_GPT_GMS_TMS_INCAPT (0x00000001)
		64	#define MCF_GPT_GMS_TMS_OUTCAPT (0x00000002)
		65	#define MCF_GPT_GMS_TMS_PWM (0x00000003)
		66	#define MCF_GPT_GMS_TMS_GPIO (0x00000004)
		67
		68	/* Bit definitions and macros for MCF_GPT_GCIR */
		69	#define MCF_GPT_GCIR_CNT(x) (((x)&0x0000FFFF)<<0)
		70	#define MCF_GPT_GCIR_PRE(x) (((x)&0x0000FFFF)<<16)
		71
		72	/* Bit definitions and macros for MCF_GPT_GPWM */
		73	#define MCF_GPT_GPWM_LOAD (0x00000001)
		74	#define MCF_GPT_GPWM_PWMOP (0x00000100)
		75	#define MCF_GPT_GPWM_WIDTH(x) (((x)&0x0000FFFF)<<16)
		76
		77	/* Bit definitions and macros for MCF_GPT_GSR */
		78	#define MCF_GPT_GSR_CAPT (0x00000001)
		79	#define MCF_GPT_GSR_COMP (0x00000002)
		80	#define MCF_GPT_GSR_PWMP (0x00000004)
		81	#define MCF_GPT_GSR_TEXP (0x00000008)
		82	#define MCF_GPT_GSR_PIN (0x00000100)
		83	#define MCF_GPT_GSR_OVF(x) (((x)&0x00000007)<<12)
		84	#define MCF_GPT_GSR_CAPTURE(x) (((x)&0x0000FFFF)<<16)
		85
		86	/********************************************************************/
		87
		88	#endif /* m548xgpt_h */


diff --git a/arch/m68k/include/asm/m548xsim.h b/arch/m68k/include/asm/m548xsim.h new file mode 100644 index 000000000000..149135ef30d2 --- /dev/null +++ b/arch/m68k/include/asm/m548xsim.h
@@ -0,0 +1,55 @@
		1	/*
		2	* m548xsim.h -- ColdFire 547x/548x System Integration Unit support.
		3	*/
		4
		5	#ifndef m548xsim_h
		6	#define m548xsim_h
		7
		8	#define MCFINT_VECBASE 64
		9
		10	/*
		11	* Interrupt Controller Registers
		12	*/
		13	#define MCFICM_INTC0 0x0700 /* Base for Interrupt Ctrl 0 */
		14	#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
		15	#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
		16	#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
		17	#define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
		18	#define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
		19	#define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
		20	#define MCFINTC_IRLR 0x18 /* */
		21	#define MCFINTC_IACKL 0x19 /* */
		22	#define MCFINTC_ICR0 0x40 /* Base ICR register */
		23
		24	/*
		25	* Define system peripheral IRQ usage.
		26	*/
		27	#define MCF_IRQ_TIMER (64 + 54) /* Slice Timer 0 */
		28	#define MCF_IRQ_PROFILER (64 + 53) /* Slice Timer 1 */
		29
		30	/*
		31	* Generic GPIO support
		32	*/
		33	#define MCFGPIO_PIN_MAX 0 /* I am too lazy to count */
		34	#define MCFGPIO_IRQ_MAX -1
		35	#define MCFGPIO_IRQ_VECBASE -1
		36
		37	/*
		38	* Some PSC related definitions
		39	*/
		40	#define MCF_PAR_PSC(x) (0x000A4F-((x)&0x3))
		41	#define MCF_PAR_SDA (0x0008)
		42	#define MCF_PAR_SCL (0x0004)
		43	#define MCF_PAR_PSC_TXD (0x04)
		44	#define MCF_PAR_PSC_RXD (0x08)
		45	#define MCF_PAR_PSC_RTS(x) (((x)&0x03)<<4)
		46	#define MCF_PAR_PSC_CTS(x) (((x)&0x03)<<6)
		47	#define MCF_PAR_PSC_CTS_GPIO (0x00)
		48	#define MCF_PAR_PSC_CTS_BCLK (0x80)
		49	#define MCF_PAR_PSC_CTS_CTS (0xC0)
		50	#define MCF_PAR_PSC_RTS_GPIO (0x00)
		51	#define MCF_PAR_PSC_RTS_FSYNC (0x20)
		52	#define MCF_PAR_PSC_RTS_RTS (0x30)
		53	#define MCF_PAR_PSC_CANRX (0x40)
		54
		55	#endif /* m548xsim_h */


diff --git a/arch/m68k/include/asm/mcfcache.h b/arch/m68k/include/asm/mcfcache.h index c042634fadaa..f49dfc09f70a 100644 --- a/arch/m68k/include/asm/mcfcache.h +++ b/arch/m68k/include/asm/mcfcache.h
@@ -107,7 +107,7 @@
107	.endm	107	.endm
108	#endif /* CONFIG_M532x */	108	#endif /* CONFIG_M532x */
109		109
110	#if defined(CONFIG_M5407)	110	#if defined(CONFIG_M5407) \|\| defined(CONFIG_M548x)
111	/*	111	/*
112	* Version 4 cores have a true harvard style separate instruction	112	* Version 4 cores have a true harvard style separate instruction
113	* and data cache. Invalidate and enable cache, also enable write	113	* and data cache. Invalidate and enable cache, also enable write


diff --git a/arch/m68k/include/asm/mcfsim.h b/arch/m68k/include/asm/mcfsim.h index 9c70a67bf85f..6901fd68165b 100644 --- a/arch/m68k/include/asm/mcfsim.h +++ b/arch/m68k/include/asm/mcfsim.h
@@ -41,6 +41,8 @@
41	#elif defined(CONFIG_M5407)	41	#elif defined(CONFIG_M5407)
42	#include <asm/m5407sim.h>	42	#include <asm/m5407sim.h>
43	#include <asm/mcfintc.h>	43	#include <asm/mcfintc.h>
		44	#elif defined(CONFIG_M548x)
		45	#include <asm/m548xsim.h>
44	#endif	46	#endif
45		47
46	/****************************************************************************/	48	/****************************************************************************/


diff --git a/arch/m68k/include/asm/mcfslt.h b/arch/m68k/include/asm/mcfslt.h new file mode 100644 index 000000000000..d0d0ecba5333 --- /dev/null +++ b/arch/m68k/include/asm/mcfslt.h
@@ -0,0 +1,44 @@
		1	/****************************************************************************/
		2
		3	/*
		4	* mcfslt.h -- ColdFire internal Slice (SLT) timer support defines.
		5	*
		6	* (C) Copyright 2004, Greg Ungerer (gerg@snapgear.com)
		7	* (C) Copyright 2009, Philippe De Muyter (phdm@macqel.be)
		8	*/
		9
		10	/****************************************************************************/
		11	#ifndef mcfslt_h
		12	#define mcfslt_h
		13	/****************************************************************************/
		14
		15	/*
		16	* Get address specific defines for the 547x.
		17	*/
		18	#define MCFSLT_TIMER0 0x900 /* Base address of TIMER0 */
		19	#define MCFSLT_TIMER1 0x910 /* Base address of TIMER1 */
		20
		21
		22	/*
		23	* Define the SLT timer register set addresses.
		24	*/
		25	#define MCFSLT_STCNT 0x00 /* Terminal count */
		26	#define MCFSLT_SCR 0x04 /* Control */
		27	#define MCFSLT_SCNT 0x08 /* Current count */
		28	#define MCFSLT_SSR 0x0C /* Status */
		29
		30	/*
		31	* Bit definitions for the SCR control register.
		32	*/
		33	#define MCFSLT_SCR_RUN 0x04000000 /* Run mode (continuous) */
		34	#define MCFSLT_SCR_IEN 0x02000000 /* Interrupt enable */
		35	#define MCFSLT_SCR_TEN 0x01000000 /* Timer enable */
		36
		37	/*
		38	* Bit definitions for the SSR status register.
		39	*/
		40	#define MCFSLT_SSR_BE 0x02000000 /* Bus error condition */
		41	#define MCFSLT_SSR_TE 0x01000000 /* Timeout condition */
		42
		43	/****************************************************************************/
		44	#endif /* mcfslt_h */


diff --git a/arch/m68k/include/asm/mcfuart.h b/arch/m68k/include/asm/mcfuart.h index 01a8716c5fc5..db72e2b889ca 100644 --- a/arch/m68k/include/asm/mcfuart.h +++ b/arch/m68k/include/asm/mcfuart.h
@@ -47,6 +47,11 @@
47	#define MCFUART_BASE1 0xfc060000 /* Base address of UART1 */	47	#define MCFUART_BASE1 0xfc060000 /* Base address of UART1 */
48	#define MCFUART_BASE2 0xfc064000 /* Base address of UART2 */	48	#define MCFUART_BASE2 0xfc064000 /* Base address of UART2 */
49	#define MCFUART_BASE3 0xfc068000 /* Base address of UART3 */	49	#define MCFUART_BASE3 0xfc068000 /* Base address of UART3 */
		50	#elif defined(CONFIG_M548x)
		51	#define MCFUART_BASE1 0x8600 /* on M548x */
		52	#define MCFUART_BASE2 0x8700 /* on M548x */
		53	#define MCFUART_BASE3 0x8800 /* on M548x */
		54	#define MCFUART_BASE4 0x8900 /* on M548x */
50	#endif	55	#endif
51		56
52		57
@@ -212,7 +217,9 @@ struct mcf_platform_uart {
212	#define MCFUART_URF_RXS 0xc0 /* Receiver status */	217	#define MCFUART_URF_RXS 0xc0 /* Receiver status */
213	#endif	218	#endif
214		219
215	#if defined(CONFIG_M5272)	220	#if defined(CONFIG_M548x)
		221	#define MCFUART_TXFIFOSIZE 512
		222	#elif defined(CONFIG_M5272)
216	#define MCFUART_TXFIFOSIZE 25	223	#define MCFUART_TXFIFOSIZE 25
217	#else	224	#else
218	#define MCFUART_TXFIFOSIZE 1	225	#define MCFUART_TXFIFOSIZE 1


diff --git a/arch/m68k/kernel/asm-offsets.c b/arch/m68k/kernel/asm-offsets.c index 73e5e581245b..78e59b82ebc3 100644 --- a/arch/m68k/kernel/asm-offsets.c +++ b/arch/m68k/kernel/asm-offsets.c
@@ -22,13 +22,9 @@
22	int main(void)	22	int main(void)
23	{	23	{
24	/* offsets into the task struct */	24	/* offsets into the task struct */
25	DEFINE(TASK_STATE, offsetof(struct task_struct, state));
26	DEFINE(TASK_FLAGS, offsetof(struct task_struct, flags));
27	DEFINE(TASK_PTRACE, offsetof(struct task_struct, ptrace));
28	DEFINE(TASK_THREAD, offsetof(struct task_struct, thread));	25	DEFINE(TASK_THREAD, offsetof(struct task_struct, thread));
29	DEFINE(TASK_INFO, offsetof(struct task_struct, thread.info));	26	DEFINE(TASK_INFO, offsetof(struct task_struct, thread.info));
30	DEFINE(TASK_MM, offsetof(struct task_struct, mm));	27	DEFINE(TASK_MM, offsetof(struct task_struct, mm));
31	DEFINE(TASK_ACTIVE_MM, offsetof(struct task_struct, active_mm));
32	#ifdef CONFIG_MMU	28	#ifdef CONFIG_MMU
33	DEFINE(TASK_TINFO, offsetof(struct task_struct, thread.info));	29	DEFINE(TASK_TINFO, offsetof(struct task_struct, thread.info));
34	#endif	30	#endif
@@ -64,14 +60,6 @@ int main(void)
64	/* bitfields are a bit difficult */	60	/* bitfields are a bit difficult */
65	DEFINE(PT_OFF_FORMATVEC, offsetof(struct pt_regs, pc) + 4);	61	DEFINE(PT_OFF_FORMATVEC, offsetof(struct pt_regs, pc) + 4);
66		62
67	/* offsets into the irq_handler struct */
68	DEFINE(IRQ_HANDLER, offsetof(struct irq_node, handler));
69	DEFINE(IRQ_DEVID, offsetof(struct irq_node, dev_id));
70	DEFINE(IRQ_NEXT, offsetof(struct irq_node, next));
71
72	/* offsets into the kernel_stat struct */
73	DEFINE(STAT_IRQ, offsetof(struct kernel_stat, irqs));
74
75	/* offsets into the irq_cpustat_t struct */	63	/* offsets into the irq_cpustat_t struct */
76	DEFINE(CPUSTAT_SOFTIRQ_PENDING, offsetof(irq_cpustat_t, __softirq_pending));	64	DEFINE(CPUSTAT_SOFTIRQ_PENDING, offsetof(irq_cpustat_t, __softirq_pending));
77		65