28 files changed, 313 insertions, 230 deletions

diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig
index bc9271b85759..a85e251c411f 100644
--- a/arch/m68k/Kconfig
+++ b/arch/m68k/Kconfig
@@ -554,14 +554,6 @@ config MVME147_SCC
           This is the driver for the serial ports on the Motorola MVME147
           boards.  Everyone using one of these boards should say Y here.
 
-config SERIAL167
-        bool "CD2401 support for MVME166/7 serial ports"
-        depends on MVME16x
-        help
-          This is the driver for the serial ports on the Motorola MVME166,
-          167, and 172 boards.  Everyone using one of these boards should say
-          Y here.
-
 config MVME162_SCC
         bool "SCC support for MVME162 serial ports"
         depends on MVME16x && BROKEN
diff --git a/arch/m68k/amiga/config.c b/arch/m68k/amiga/config.c
index b1577f741fa8..82a4bb51d5d8 100644
--- a/arch/m68k/amiga/config.c
+++ b/arch/m68k/amiga/config.c
@@ -610,17 +610,17 @@ static void amiga_mem_console_write(struct console *co, const char *s,
 
 static int __init amiga_savekmsg_setup(char *arg)
 {
-        static struct resource debug_res = { .name = "Debug" };
-
         if (!MACH_IS_AMIGA || strcmp(arg, "mem"))
-                goto done;
+                return 0;
 
-        if (!AMIGAHW_PRESENT(CHIP_RAM)) {
-                printk("Warning: no chipram present for debugging\n");
-                goto done;
+        if (amiga_chip_size < SAVEKMSG_MAXMEM) {
+                pr_err("Not enough chipram for debugging\n");
+                return -ENOMEM;
         }
 
-        savekmsg = amiga_chip_alloc_res(SAVEKMSG_MAXMEM, &debug_res);
+        /* Just steal the block, the chipram allocator isn't functional yet */
+        amiga_chip_size -= SAVEKMSG_MAXMEM;
+        savekmsg = (void *)ZTWO_VADDR(CHIP_PHYSADDR + amiga_chip_size);
         savekmsg->magic1 = SAVEKMSG_MAGIC1;
         savekmsg->magic2 = SAVEKMSG_MAGIC2;
         savekmsg->magicptr = ZTWO_PADDR(savekmsg);
@@ -628,8 +628,6 @@ static int __init amiga_savekmsg_setup(char *arg)
 
         amiga_console_driver.write = amiga_mem_console_write;
         register_console(&amiga_console_driver);
-
-done:
         return 0;
 }
 
diff --git a/arch/m68k/atari/ataints.c b/arch/m68k/atari/ataints.c
index 39478dd08e67..26a804e67bce 100644
--- a/arch/m68k/atari/ataints.c
+++ b/arch/m68k/atari/ataints.c
@@ -388,9 +388,9 @@ void __init atari_init_IRQ(void)
         }
 
         if (ATARIHW_PRESENT(SCC) && !atari_SCC_reset_done) {
-                scc.cha_a_ctrl = 9;
+                atari_scc.cha_a_ctrl = 9;
                 MFPDELAY();
-                scc.cha_a_ctrl = (char) 0xc0; /* hardware reset */
+                atari_scc.cha_a_ctrl = (char) 0xc0; /* hardware reset */
         }
 
         if (ATARIHW_PRESENT(SCU)) {
diff --git a/arch/m68k/atari/config.c b/arch/m68k/atari/config.c
index ae2d96e5d618..4203d101363c 100644
--- a/arch/m68k/atari/config.c
+++ b/arch/m68k/atari/config.c
@@ -315,7 +315,7 @@ void __init config_atari(void)
                 ATARIHW_SET(SCC_DMA);
                 printk("SCC_DMA ");
         }
-        if (scc_test(&scc.cha_a_ctrl)) {
+        if (scc_test(&atari_scc.cha_a_ctrl)) {
                 ATARIHW_SET(SCC);
                 printk("SCC ");
         }
diff --git a/arch/m68k/atari/debug.c b/arch/m68k/atari/debug.c
index 28efdc33c1ae..5a484247e493 100644
--- a/arch/m68k/atari/debug.c
+++ b/arch/m68k/atari/debug.c
@@ -53,9 +53,9 @@ static inline void ata_scc_out(char c)
 {
         do {
                 MFPDELAY();
-        } while (!(scc.cha_b_ctrl & 0x04)); /* wait for tx buf empty */
+        } while (!(atari_scc.cha_b_ctrl & 0x04)); /* wait for tx buf empty */
         MFPDELAY();
-        scc.cha_b_data = c;
+        atari_scc.cha_b_data = c;
 }
 
 static void atari_scc_console_write(struct console *co, const char *str,
@@ -140,9 +140,9 @@ int atari_scc_console_wait_key(struct console *co)
 {
         do {
                 MFPDELAY();
-        } while (!(scc.cha_b_ctrl & 0x01)); /* wait for rx buf filled */
+        } while (!(atari_scc.cha_b_ctrl & 0x01)); /* wait for rx buf filled */
         MFPDELAY();
-        return scc.cha_b_data;
+        return atari_scc.cha_b_data;
 }
 
 int atari_midi_console_wait_key(struct console *co)
@@ -185,9 +185,9 @@ static void __init atari_init_mfp_port(int cflag)
 
 #define SCC_WRITE(reg, val)                             \
         do {                                            \
-                scc.cha_b_ctrl = (reg);                 \
+                atari_scc.cha_b_ctrl = (reg);           \
                 MFPDELAY();                             \
-                scc.cha_b_ctrl = (val);                 \
+                atari_scc.cha_b_ctrl = (val);           \
                 MFPDELAY();                             \
         } while (0)
 
@@ -240,7 +240,7 @@ static void __init atari_init_scc_port(int cflag)
         reg3 = (cflag & CSIZE) == CS8 ? 0xc0 : 0x40;
         reg5 = (cflag & CSIZE) == CS8 ? 0x60 : 0x20 | 0x82 /* assert DTR/RTS */;
 
-        (void)scc.cha_b_ctrl;           /* reset reg pointer */
+        (void)atari_scc.cha_b_ctrl;     /* reset reg pointer */
         SCC_WRITE(9, 0xc0);             /* reset */
         LONG_DELAY();                   /* extra delay after WR9 access */
         SCC_WRITE(4, (cflag & PARENB) ? ((cflag & PARODD) ? 0x01 : 0x03)
diff --git a/arch/m68k/bvme6000/config.c b/arch/m68k/bvme6000/config.c
index 9fe6fefb5e14..1edd95095cb4 100644
--- a/arch/m68k/bvme6000/config.c
+++ b/arch/m68k/bvme6000/config.c
@@ -45,8 +45,8 @@ extern int bvme6000_set_clock_mmss (unsigned long);
 extern void bvme6000_reset (void);
 void bvme6000_set_vectors (void);
 
-/* Save tick handler routine pointer, will point to do_timer() in
- * kernel/sched.c, called via bvme6000_process_int() */
+/* Save tick handler routine pointer, will point to xtime_update() in
+ * kernel/timer/timekeeping.c, called via bvme6000_process_int() */
 
 static irq_handler_t tick_handler;
 
diff --git a/arch/m68k/include/asm/atarihw.h b/arch/m68k/include/asm/atarihw.h
index a714e1aa072a..f51f709bbf30 100644
--- a/arch/m68k/include/asm/atarihw.h
+++ b/arch/m68k/include/asm/atarihw.h
@@ -449,7 +449,7 @@ struct SCC
   u_char char_dummy3;
   u_char cha_b_data;
  };
-# define scc ((*(volatile struct SCC*)SCC_BAS))
+# define atari_scc ((*(volatile struct SCC*)SCC_BAS))
 
 /* The ESCC (Z85230) in an Atari ST. The channels are reversed! */
 # define st_escc ((*(volatile struct SCC*)0xfffffa31))
diff --git a/arch/m68k/include/asm/coldfire.h b/arch/m68k/include/asm/coldfire.h
index 213028cbe110..c94557b91448 100644
--- a/arch/m68k/include/asm/coldfire.h
+++ b/arch/m68k/include/asm/coldfire.h
@@ -14,39 +14,35 @@
 
 
 /*
- *      Define master clock frequency. This is essentially done at config
- *      time now. No point enumerating dozens of possible clock options
- *      here. Also the peripheral clock (bus clock) divide ratio is set
- *      at config time too.
+ *      Define master clock frequency. This is done at config time now.
+ *      No point enumerating dozens of possible clock options here. And
+ *      in any case new boards come along from time to time that have yet
+ *      another different clocking frequency.
  */
 #ifdef CONFIG_CLOCK_SET
 #define MCF_CLK         CONFIG_CLOCK_FREQ
-#define MCF_BUSCLK      (CONFIG_CLOCK_FREQ / CONFIG_CLOCK_DIV)
 #else
 #error "Don't know what your ColdFire CPU clock frequency is??"
 #endif
 
 /*
- *      Define the processor support peripherals base address.
- *      This is generally setup by the boards start up code.
+ *      Define the processor internal peripherals base address.
+ *
+ *      The majority of ColdFire parts use an MBAR register to set
+ *      the base address. Some have an IPSBAR register instead, and it
+ *      has slightly different rules on its size and alignment. Some
+ *      parts have fixed addresses and the internal peripherals cannot
+ *      be relocated in the CPU address space.
+ *
+ *      The value of MBAR or IPSBAR is config time selectable, we no
+ *      longer hard define it here. No MBAR or IPSBAR will be defined if
+ *      this part has a fixed peripheral address map.
  */
-#define MCF_MBAR        0x10000000
-#define MCF_MBAR2       0x80000000
-#if defined(CONFIG_M54xx)
-#define MCF_IPSBAR      MCF_MBAR
-#elif defined(CONFIG_M520x)
-#define MCF_IPSBAR      0xFC000000
-#else
-#define MCF_IPSBAR      0x40000000
+#ifdef CONFIG_MBAR
+#define MCF_MBAR        CONFIG_MBAR
 #endif
-
-#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
-    defined(CONFIG_M520x)
-#undef MCF_MBAR
-#define MCF_MBAR        MCF_IPSBAR
-#elif defined(CONFIG_M532x)
-#undef MCF_MBAR
-#define MCF_MBAR        0x00000000
+#ifdef CONFIG_IPSBAR
+#define MCF_IPSBAR      CONFIG_IPSBAR
 #endif
 
 /****************************************************************************/
diff --git a/arch/m68k/include/asm/m5206sim.h b/arch/m68k/include/asm/m5206sim.h
index 561b03b5ddf8..9015eadd5c00 100644
--- a/arch/m68k/include/asm/m5206sim.h
+++ b/arch/m68k/include/asm/m5206sim.h
@@ -14,6 +14,7 @@
 
 #define CPU_NAME                "COLDFIRE(m5206)"
 #define CPU_INSTR_PER_JIFFY     3
+#define MCF_BUSCLK              MCF_CLK
 
 #include <asm/m52xxacr.h>
 
@@ -48,14 +49,14 @@
 #define MCFSIM_SWIVR            0x42            /* SW Watchdog intr reg (r/w) */
 #define MCFSIM_SWSR             0x43            /* SW Watchdog service (r/w) */
 
-#define MCFSIM_DCRR             0x46            /* DRAM Refresh reg (r/w) */
-#define MCFSIM_DCTR             0x4a            /* DRAM Timing reg (r/w) */
-#define MCFSIM_DAR0             0x4c            /* DRAM 0 Address reg(r/w) */
-#define MCFSIM_DMR0             0x50            /* DRAM 0 Mask reg (r/w) */
-#define MCFSIM_DCR0             0x57            /* DRAM 0 Control reg (r/w) */
-#define MCFSIM_DAR1             0x58            /* DRAM 1 Address reg (r/w) */
-#define MCFSIM_DMR1             0x5c            /* DRAM 1 Mask reg (r/w) */
-#define MCFSIM_DCR1             0x63            /* DRAM 1 Control reg (r/w) */
+#define MCFSIM_DCRR             (MCF_MBAR + 0x46) /* DRAM Refresh reg (r/w) */
+#define MCFSIM_DCTR             (MCF_MBAR + 0x4a) /* DRAM Timing reg (r/w) */
+#define MCFSIM_DAR0             (MCF_MBAR + 0x4c) /* DRAM 0 Address reg(r/w) */
+#define MCFSIM_DMR0             (MCF_MBAR + 0x50) /* DRAM 0 Mask reg (r/w) */
+#define MCFSIM_DCR0             (MCF_MBAR + 0x57) /* DRAM 0 Control reg (r/w) */
+#define MCFSIM_DAR1             (MCF_MBAR + 0x58) /* DRAM 1 Address reg (r/w) */
+#define MCFSIM_DMR1             (MCF_MBAR + 0x5c) /* DRAM 1 Mask reg (r/w) */
+#define MCFSIM_DCR1             (MCF_MBAR + 0x63) /* DRAM 1 Control reg (r/w) */
 
 #define MCFSIM_CSAR0            0x64            /* CS 0 Address 0 reg (r/w) */
 #define MCFSIM_CSMR0            0x68            /* CS 0 Mask 0 reg (r/w) */
@@ -89,9 +90,15 @@
 #define MCFSIM_PAR              0xcb            /* Pin Assignment reg (r/w) */
 #endif
 
+#define MCFTIMER_BASE1          (MCF_MBAR + 0x100)      /* Base of TIMER1 */
+#define MCFTIMER_BASE2          (MCF_MBAR + 0x120)      /* Base of TIMER2 */
+
 #define MCFSIM_PADDR            (MCF_MBAR + 0x1c5)      /* Parallel Direction (r/w) */
 #define MCFSIM_PADAT            (MCF_MBAR + 0x1c9)      /* Parallel Port Value (r/w) */
 
+#define MCFDMA_BASE0            (MCF_MBAR + 0x200)      /* Base address DMA 0 */
+#define MCFDMA_BASE1            (MCF_MBAR + 0x240)      /* Base address DMA 1 */
+
 #if defined(CONFIG_NETtel)
 #define MCFUART_BASE1           0x180           /* Base address of UART1 */
 #define MCFUART_BASE2           0x140           /* Base address of UART2 */
diff --git a/arch/m68k/include/asm/m520xsim.h b/arch/m68k/include/asm/m520xsim.h
index 88ed8239fe4e..55d5a4c5fe0b 100644
--- a/arch/m68k/include/asm/m520xsim.h
+++ b/arch/m68k/include/asm/m520xsim.h
@@ -13,13 +13,14 @@
 
 #define CPU_NAME                "COLDFIRE(m520x)"
 #define CPU_INSTR_PER_JIFFY     3
+#define MCF_BUSCLK              (MCF_CLK / 2)
 
 #include <asm/m52xxacr.h>
 
 /*
  *  Define the 520x SIM register set addresses.
  */
-#define MCFICM_INTC0        0x48000     /* Base for Interrupt Ctrl 0 */
+#define MCFICM_INTC0        0xFC048000  /* Base for Interrupt Ctrl 0 */
 #define MCFINTC_IPRH        0x00        /* Interrupt pending 32-63 */
 #define MCFINTC_IPRL        0x04        /* Interrupt pending 1-31 */
 #define MCFINTC_IMRH        0x08        /* Interrupt mask 32-63 */
@@ -35,9 +36,9 @@
  *  address to the SIMR and CIMR registers (not offsets into IPSBAR).
  *  The 520x family only has a single INTC unit.
  */
-#define MCFINTC0_SIMR       (MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_SIMR)
-#define MCFINTC0_CIMR       (MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_CIMR)
-#define MCFINTC0_ICR0       (MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_ICR0)
+#define MCFINTC0_SIMR       (MCFICM_INTC0 + MCFINTC_SIMR)
+#define MCFINTC0_CIMR       (MCFICM_INTC0 + MCFINTC_CIMR)
+#define MCFINTC0_ICR0       (MCFICM_INTC0 + MCFINTC_ICR0)
 #define MCFINTC1_SIMR       (0)
 #define MCFINTC1_CIMR       (0)
 #define MCFINTC1_ICR0       (0)
@@ -52,19 +53,22 @@
 /*
  *  SDRAM configuration registers.
  */
-#define MCFSIM_SDMR         0x000a8000  /* SDRAM Mode/Extended Mode Register */
-#define MCFSIM_SDCR         0x000a8004  /* SDRAM Control Register */
-#define MCFSIM_SDCFG1       0x000a8008  /* SDRAM Configuration Register 1 */
-#define MCFSIM_SDCFG2       0x000a800c  /* SDRAM Configuration Register 2 */
-#define MCFSIM_SDCS0        0x000a8110  /* SDRAM Chip Select 0 Configuration */
-#define MCFSIM_SDCS1        0x000a8114  /* SDRAM Chip Select 1 Configuration */
+#define MCFSIM_SDMR         0xFC0a8000  /* SDRAM Mode/Extended Mode Register */
+#define MCFSIM_SDCR         0xFC0a8004  /* SDRAM Control Register */
+#define MCFSIM_SDCFG1       0xFC0a8008  /* SDRAM Configuration Register 1 */
+#define MCFSIM_SDCFG2       0xFC0a800c  /* SDRAM Configuration Register 2 */
+#define MCFSIM_SDCS0        0xFC0a8110  /* SDRAM Chip Select 0 Configuration */
+#define MCFSIM_SDCS1        0xFC0a8114  /* SDRAM Chip Select 1 Configuration */
 
 /*
  * EPORT and GPIO registers.
  */
+#define MCFEPORT_EPPAR                  0xFC088000
 #define MCFEPORT_EPDDR                  0xFC088002
+#define MCFEPORT_EPIER                  0xFC088003
 #define MCFEPORT_EPDR                   0xFC088004
 #define MCFEPORT_EPPDR                  0xFC088005
+#define MCFEPORT_EPFR                   0xFC088006
 
 #define MCFGPIO_PODR_BUSCTL             0xFC0A4000
 #define MCFGPIO_PODR_BE                 0xFC0A4001
@@ -119,10 +123,10 @@
 #define MCFGPIO_IRQ_MAX                 8
 #define MCFGPIO_IRQ_VECBASE             MCFINT_VECBASE
 
-#define MCF_GPIO_PAR_UART                   (0xA4036)
-#define MCF_GPIO_PAR_FECI2C                 (0xA4033)
-#define MCF_GPIO_PAR_QSPI                   (0xA4034)
-#define MCF_GPIO_PAR_FEC                    (0xA4038)
+#define MCF_GPIO_PAR_UART               0xFC0A4036
+#define MCF_GPIO_PAR_FECI2C             0xFC0A4033
+#define MCF_GPIO_PAR_QSPI               0xFC0A4034
+#define MCF_GPIO_PAR_FEC                0xFC0A4038
 
 #define MCF_GPIO_PAR_UART_PAR_URXD0         (0x0001)
 #define MCF_GPIO_PAR_UART_PAR_UTXD0         (0x0002)
@@ -134,11 +138,23 @@
 #define MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2   (0x04)
 
 /*
+ *  PIT timer module.
+ */
+#define MCFPIT_BASE1            0xFC080000      /* Base address of TIMER1 */
+#define MCFPIT_BASE2            0xFC084000      /* Base address of TIMER2 */
+
+/*
  *  UART module.
  */
-#define MCFUART_BASE1           0x60000         /* Base address of UART1 */
-#define MCFUART_BASE2           0x64000         /* Base address of UART2 */
-#define MCFUART_BASE3           0x68000         /* Base address of UART2 */
+#define MCFUART_BASE1           0xFC060000      /* Base address of UART1 */
+#define MCFUART_BASE2           0xFC064000      /* Base address of UART2 */
+#define MCFUART_BASE3           0xFC068000      /* Base address of UART2 */
+
+/*
+ *  FEC module.
+ */
+#define MCFFEC_BASE             0xFC030000      /* Base of FEC ethernet */
+#define MCFFEC_SIZE             0x800           /* Register set size */
 
 /*
  *  Reset Controll Unit.
diff --git a/arch/m68k/include/asm/m523xsim.h b/arch/m68k/include/asm/m523xsim.h
index 4ad7a00257a8..8996df62ede4 100644
--- a/arch/m68k/include/asm/m523xsim.h
+++ b/arch/m68k/include/asm/m523xsim.h
@@ -13,14 +13,16 @@
 
 #define CPU_NAME                "COLDFIRE(m523x)"
 #define CPU_INSTR_PER_JIFFY     3
+#define MCF_BUSCLK              (MCF_CLK / 2)
 
 #include <asm/m52xxacr.h>
 
 /*
  *      Define the 523x SIM register set addresses.
  */
-#define MCFICM_INTC0            0x0c00          /* Base for Interrupt Ctrl 0 */
-#define MCFICM_INTC1            0x0d00          /* Base for Interrupt Ctrl 0 */
+#define MCFICM_INTC0            (MCF_IPSBAR + 0x0c00)   /* Base for Interrupt Ctrl 0 */
+#define MCFICM_INTC1            (MCF_IPSBAR + 0x0d00)   /* Base for Interrupt Ctrl 0 */
+
 #define MCFINTC_IPRH            0x00            /* Interrupt pending 32-63 */
 #define MCFINTC_IPRL            0x04            /* Interrupt pending 1-31 */
 #define MCFINTC_IMRH            0x08            /* Interrupt mask 32-63 */
@@ -39,11 +41,11 @@
 /*
  *      SDRAM configuration registers.
  */
-#define MCFSIM_DCR              0x44            /* SDRAM control */
-#define MCFSIM_DACR0            0x48            /* SDRAM base address 0 */
-#define MCFSIM_DMR0             0x4c            /* SDRAM address mask 0 */
-#define MCFSIM_DACR1            0x50            /* SDRAM base address 1 */
-#define MCFSIM_DMR1             0x54            /* SDRAM address mask 1 */
+#define MCFSIM_DCR              (MCF_IPSBAR + 0x44)     /* Control */
+#define MCFSIM_DACR0            (MCF_IPSBAR + 0x48)     /* Base address 0 */
+#define MCFSIM_DMR0             (MCF_IPSBAR + 0x4c)     /* Address mask 0 */
+#define MCFSIM_DACR1            (MCF_IPSBAR + 0x50)     /* Base address 1 */
+#define MCFSIM_DMR1             (MCF_IPSBAR + 0x54)     /* Address mask 1 */
 
 /*
  *  Reset Controll Unit (relative to IPSBAR).
@@ -57,10 +59,19 @@
 /*
  *  UART module.
  */
-#define MCFUART_BASE1           0x200           /* Base address of UART1 */
-#define MCFUART_BASE2           0x240           /* Base address of UART2 */
-#define MCFUART_BASE3           0x280           /* Base address of UART3 */
+#define MCFUART_BASE1           (MCF_IPSBAR + 0x200)
+#define MCFUART_BASE2           (MCF_IPSBAR + 0x240)
+#define MCFUART_BASE3           (MCF_IPSBAR + 0x280)
+
+/*
+ *  FEC ethernet module.
+ */
+#define MCFFEC_BASE             (MCF_IPSBAR + 0x1000)
+#define MCFFEC_SIZE             0x800
 
+/*
+ *  GPIO module.
+ */
 #define MCFGPIO_PODR_ADDR       (MCF_IPSBAR + 0x100000)
 #define MCFGPIO_PODR_DATAH      (MCF_IPSBAR + 0x100001)
 #define MCFGPIO_PODR_DATAL      (MCF_IPSBAR + 0x100002)
@@ -118,12 +129,22 @@
 #define MCFGPIO_PCLRR_ETPU      (MCF_IPSBAR + 0x10003C)
 
 /*
- * EPort
+ * PIT timer base addresses.
  */
+#define MCFPIT_BASE1            (MCF_IPSBAR + 0x150000)
+#define MCFPIT_BASE2            (MCF_IPSBAR + 0x160000)
+#define MCFPIT_BASE3            (MCF_IPSBAR + 0x170000)
+#define MCFPIT_BASE4            (MCF_IPSBAR + 0x180000)
 
+/*
+ * EPort
+ */
+#define MCFEPORT_EPPAR          (MCF_IPSBAR + 0x130000)
 #define MCFEPORT_EPDDR          (MCF_IPSBAR + 0x130002)
+#define MCFEPORT_EPIER          (MCF_IPSBAR + 0x130003)
 #define MCFEPORT_EPDR           (MCF_IPSBAR + 0x130004)
 #define MCFEPORT_EPPDR          (MCF_IPSBAR + 0x130005)
+#define MCFEPORT_EPFR           (MCF_IPSBAR + 0x130006)
 
 /*
  * Generic GPIO support
@@ -143,5 +164,14 @@
 */
 #define MCFGPIO_PAR_QSPI        (MCF_IPSBAR + 0x10004A)
 #define MCFGPIO_PAR_TIMER       (MCF_IPSBAR + 0x10004C)
+
+/*
+ * DMA unit base addresses.
+ */
+#define MCFDMA_BASE0            (MCF_IPSBAR + 0x100)
+#define MCFDMA_BASE1            (MCF_IPSBAR + 0x140)
+#define MCFDMA_BASE2            (MCF_IPSBAR + 0x180)
+#define MCFDMA_BASE3            (MCF_IPSBAR + 0x1C0)
+
 /****************************************************************************/
 #endif  /* m523xsim_h */
diff --git a/arch/m68k/include/asm/m5249sim.h b/arch/m68k/include/asm/m5249sim.h
index 4908b118f2fd..805714ca8d7d 100644
--- a/arch/m68k/include/asm/m5249sim.h
+++ b/arch/m68k/include/asm/m5249sim.h
@@ -13,10 +13,16 @@
 
 #define CPU_NAME                "COLDFIRE(m5249)"
 #define CPU_INSTR_PER_JIFFY     3
+#define MCF_BUSCLK              (MCF_CLK / 2)
 
 #include <asm/m52xxacr.h>
 
 /*
+ *      The 5249 has a second MBAR region, define its address.
+ */
+#define MCF_MBAR2               0x80000000
+
+/*
  *      Define the 5249 SIM register set addresses.
  */
 #define MCFSIM_RSR              0x00            /* Reset Status reg (r/w) */
@@ -55,11 +61,17 @@
 #define MCFSIM_CSMR3            0xa8            /* CS 3 Mask reg (r/w) */
 #define MCFSIM_CSCR3            0xae            /* CS 3 Control reg (r/w) */
 
-#define MCFSIM_DCR              0x100           /* DRAM Control reg (r/w) */
-#define MCFSIM_DACR0            0x108           /* DRAM 0 Addr and Ctrl (r/w) */
-#define MCFSIM_DMR0             0x10c           /* DRAM 0 Mask reg (r/w) */
-#define MCFSIM_DACR1            0x110           /* DRAM 1 Addr and Ctrl (r/w) */
-#define MCFSIM_DMR1             0x114           /* DRAM 1 Mask reg (r/w) */
+#define MCFSIM_DCR              (MCF_MBAR + 0x100)      /* DRAM Control */
+#define MCFSIM_DACR0            (MCF_MBAR + 0x108)      /* DRAM 0 Addr/Ctrl */
+#define MCFSIM_DMR0             (MCF_MBAR + 0x10c)      /* DRAM 0 Mask */
+#define MCFSIM_DACR1            (MCF_MBAR + 0x110)      /* DRAM 1 Addr/Ctrl */
+#define MCFSIM_DMR1             (MCF_MBAR + 0x114)      /* DRAM 1 Mask */
+
+/*
+ *      Timer module.
+ */
+#define MCFTIMER_BASE1          (MCF_MBAR + 0x140)      /* Base of TIMER1 */
+#define MCFTIMER_BASE2          (MCF_MBAR + 0x180)      /* Base of TIMER2 */
 
 /*
  *      UART module.
@@ -68,6 +80,14 @@
 #define MCFUART_BASE2           0x200           /* Base address of UART2 */
 
 /*
+ *      DMA unit base addresses.
+ */
+#define MCFDMA_BASE0            (MCF_MBAR + 0x300)      /* Base address DMA 0 */
+#define MCFDMA_BASE1            (MCF_MBAR + 0x340)      /* Base address DMA 1 */
+#define MCFDMA_BASE2            (MCF_MBAR + 0x380)      /* Base address DMA 2 */
+#define MCFDMA_BASE3            (MCF_MBAR + 0x3C0)      /* Base address DMA 3 */
+
+/*
  *      Some symbol defines for the above...
  */
 #define MCFSIM_SWDICR           MCFSIM_ICR0     /* Watchdog timer ICR */
diff --git a/arch/m68k/include/asm/m5272sim.h b/arch/m68k/include/asm/m5272sim.h
index b7cc50abc831..759c2b07a994 100644
--- a/arch/m68k/include/asm/m5272sim.h
+++ b/arch/m68k/include/asm/m5272sim.h
@@ -14,6 +14,7 @@
 
 #define CPU_NAME                "COLDFIRE(m5272)"
 #define CPU_INSTR_PER_JIFFY     3
+#define MCF_BUSCLK              MCF_CLK
 
 #include <asm/m52xxacr.h>
 
@@ -80,6 +81,13 @@
 #define MCFSIM_PCDAT            (MCF_MBAR + 0x96) /* Port C Data (r/w) */
 #define MCFSIM_PDCNT            (MCF_MBAR + 0x98) /* Port D Control (r/w) */
 
+#define MCFDMA_BASE0            (MCF_MBAR + 0xe0) /* Base address DMA 0 */
+
+#define MCFTIMER_BASE1          (MCF_MBAR + 0x200) /* Base address TIMER1 */
+#define MCFTIMER_BASE2          (MCF_MBAR + 0x220) /* Base address TIMER2 */
+#define MCFTIMER_BASE3          (MCF_MBAR + 0x240) /* Base address TIMER4 */
+#define MCFTIMER_BASE4          (MCF_MBAR + 0x260) /* Base address TIMER3 */
+
 /*
  *      Define system peripheral IRQ usage.
  */
diff --git a/arch/m68k/include/asm/m527xsim.h b/arch/m68k/include/asm/m527xsim.h
index e8042e8bc003..74855a66c050 100644
--- a/arch/m68k/include/asm/m527xsim.h
+++ b/arch/m68k/include/asm/m527xsim.h
@@ -13,14 +13,16 @@
 
 #define CPU_NAME                "COLDFIRE(m527x)"
 #define CPU_INSTR_PER_JIFFY     3
+#define MCF_BUSCLK              (MCF_CLK / 2)
 
 #include <asm/m52xxacr.h>
 
 /*
  *      Define the 5270/5271 SIM register set addresses.
  */
-#define MCFICM_INTC0            0x0c00          /* Base for Interrupt Ctrl 0 */
-#define MCFICM_INTC1            0x0d00          /* Base for Interrupt Ctrl 1 */
+#define MCFICM_INTC0            (MCF_IPSBAR + 0x0c00)   /* Base for Interrupt Ctrl 0 */
+#define MCFICM_INTC1            (MCF_IPSBAR + 0x0d00)   /* Base for Interrupt Ctrl 1 */
+
 #define MCFINTC_IPRH            0x00            /* Interrupt pending 32-63 */
 #define MCFINTC_IPRL            0x04            /* Interrupt pending 1-31 */
 #define MCFINTC_IMRH            0x08            /* Interrupt mask 32-63 */
@@ -42,29 +44,45 @@
  *      SDRAM configuration registers.
  */
 #ifdef CONFIG_M5271
-#define MCFSIM_DCR              0x40            /* SDRAM control */
-#define MCFSIM_DACR0            0x48            /* SDRAM base address 0 */
-#define MCFSIM_DMR0             0x4c            /* SDRAM address mask 0 */
-#define MCFSIM_DACR1            0x50            /* SDRAM base address 1 */
-#define MCFSIM_DMR1             0x54            /* SDRAM address mask 1 */
+#define MCFSIM_DCR              (MCF_IPSBAR + 0x40)     /* Control */
+#define MCFSIM_DACR0            (MCF_IPSBAR + 0x48)     /* Base address 0 */
+#define MCFSIM_DMR0             (MCF_IPSBAR + 0x4c)     /* Address mask 0 */
+#define MCFSIM_DACR1            (MCF_IPSBAR + 0x50)     /* Base address 1 */
+#define MCFSIM_DMR1             (MCF_IPSBAR + 0x54)     /* Address mask 1 */
 #endif
 #ifdef CONFIG_M5275
-#define MCFSIM_DMR              0x40            /* SDRAM mode */
-#define MCFSIM_DCR              0x44            /* SDRAM control */
-#define MCFSIM_DCFG1            0x48            /* SDRAM configuration 1 */
-#define MCFSIM_DCFG2            0x4c            /* SDRAM configuration 2 */
-#define MCFSIM_DBAR0            0x50            /* SDRAM base address 0 */
-#define MCFSIM_DMR0             0x54            /* SDRAM address mask 0 */
-#define MCFSIM_DBAR1            0x58            /* SDRAM base address 1 */
-#define MCFSIM_DMR1             0x5c            /* SDRAM address mask 1 */
+#define MCFSIM_DMR              (MCF_IPSBAR + 0x40)     /* Mode */
+#define MCFSIM_DCR              (MCF_IPSBAR + 0x44)     /* Control */
+#define MCFSIM_DCFG1            (MCF_IPSBAR + 0x48)     /* Configuration 1 */
+#define MCFSIM_DCFG2            (MCF_IPSBAR + 0x4c)     /* Configuration 2 */
+#define MCFSIM_DBAR0            (MCF_IPSBAR + 0x50)     /* Base address 0 */
+#define MCFSIM_DMR0             (MCF_IPSBAR + 0x54)     /* Address mask 0 */
+#define MCFSIM_DBAR1            (MCF_IPSBAR + 0x58)     /* Base address 1 */
+#define MCFSIM_DMR1             (MCF_IPSBAR + 0x5c)     /* Address mask 1 */
 #endif
 
 /*
+ *      DMA unit base addresses.
+ */
+#define MCFDMA_BASE0            (MCF_IPSBAR + 0x100)
+#define MCFDMA_BASE1            (MCF_IPSBAR + 0x140)
+#define MCFDMA_BASE2            (MCF_IPSBAR + 0x180)
+#define MCFDMA_BASE3            (MCF_IPSBAR + 0x1C0)
+
+/*
  *      UART module.
  */
-#define MCFUART_BASE1           0x200           /* Base address of UART1 */
-#define MCFUART_BASE2           0x240           /* Base address of UART2 */
-#define MCFUART_BASE3           0x280           /* Base address of UART3 */
+#define MCFUART_BASE1           (MCF_IPSBAR + 0x200)
+#define MCFUART_BASE2           (MCF_IPSBAR + 0x240)
+#define MCFUART_BASE3           (MCF_IPSBAR + 0x280)
+
+/*
+ *      FEC ethernet module.
+ */
+#define MCFFEC_BASE0            (MCF_IPSBAR + 0x1000)
+#define MCFFEC_SIZE0            0x800
+#define MCFFEC_BASE1            (MCF_IPSBAR + 0x1800)
+#define MCFFEC_SIZE1            0x800
 
 #ifdef CONFIG_M5271
 #define MCFGPIO_PODR_ADDR       (MCF_IPSBAR + 0x100000)
@@ -231,14 +249,22 @@
 #endif
 
 /*
- * EPort
+ * PIT timer base addresses.
  */
+#define MCFPIT_BASE1            (MCF_IPSBAR + 0x150000)
+#define MCFPIT_BASE2            (MCF_IPSBAR + 0x160000)
+#define MCFPIT_BASE3            (MCF_IPSBAR + 0x170000)
+#define MCFPIT_BASE4            (MCF_IPSBAR + 0x180000)
 
+/*
+ * EPort
+ */
+#define MCFEPORT_EPPAR          (MCF_IPSBAR + 0x130000)
 #define MCFEPORT_EPDDR          (MCF_IPSBAR + 0x130002)
+#define MCFEPORT_EPIER          (MCF_IPSBAR + 0x130003)
 #define MCFEPORT_EPDR           (MCF_IPSBAR + 0x130004)
 #define MCFEPORT_EPPDR          (MCF_IPSBAR + 0x130005)
-
-
+#define MCFEPORT_EPFR           (MCF_IPSBAR + 0x130006)
 
 /*
  *      GPIO pins setups to enable the UARTs.
diff --git a/arch/m68k/include/asm/m528xsim.h b/arch/m68k/include/asm/m528xsim.h
index a6d2f4d9aaa0..d798bd5df56c 100644
--- a/arch/m68k/include/asm/m528xsim.h
+++ b/arch/m68k/include/asm/m528xsim.h
@@ -13,14 +13,16 @@
 
 #define CPU_NAME                "COLDFIRE(m528x)"
 #define CPU_INSTR_PER_JIFFY     3
+#define MCF_BUSCLK              MCF_CLK
 
 #include <asm/m52xxacr.h>
 
 /*
  *      Define the 5280/5282 SIM register set addresses.
  */
-#define MCFICM_INTC0            0x0c00          /* Base for Interrupt Ctrl 0 */
-#define MCFICM_INTC1            0x0d00          /* Base for Interrupt Ctrl 0 */
+#define MCFICM_INTC0            (MCF_IPSBAR + 0x0c00)   /* Base for Interrupt Ctrl 0 */
+#define MCFICM_INTC1            (MCF_IPSBAR + 0x0d00)   /* Base for Interrupt Ctrl 0 */
+
 #define MCFINTC_IPRH            0x00            /* Interrupt pending 32-63 */
 #define MCFINTC_IPRL            0x04            /* Interrupt pending 1-31 */
 #define MCFINTC_IMRH            0x08            /* Interrupt mask 32-63 */
@@ -39,18 +41,32 @@
 /*
  *      SDRAM configuration registers.
  */
-#define MCFSIM_DCR              0x44            /* SDRAM control */
-#define MCFSIM_DACR0            0x48            /* SDRAM base address 0 */
-#define MCFSIM_DMR0             0x4c            /* SDRAM address mask 0 */
-#define MCFSIM_DACR1            0x50            /* SDRAM base address 1 */
-#define MCFSIM_DMR1             0x54            /* SDRAM address mask 1 */
+#define MCFSIM_DCR              (MCF_IPSBAR + 0x00000044) /* Control */
+#define MCFSIM_DACR0            (MCF_IPSBAR + 0x00000048) /* Base address 0 */
+#define MCFSIM_DMR0             (MCF_IPSBAR + 0x0000004c) /* Address mask 0 */
+#define MCFSIM_DACR1            (MCF_IPSBAR + 0x00000050) /* Base address 1 */
+#define MCFSIM_DMR1             (MCF_IPSBAR + 0x00000054) /* Address mask 1 */
+
+/*
+ *      DMA unit base addresses.
+ */
+#define MCFDMA_BASE0            (MCF_IPSBAR + 0x00000100)
+#define MCFDMA_BASE1            (MCF_IPSBAR + 0x00000140)
+#define MCFDMA_BASE2            (MCF_IPSBAR + 0x00000180)
+#define MCFDMA_BASE3            (MCF_IPSBAR + 0x000001C0)
 
 /*
  *      UART module.
  */
-#define MCFUART_BASE1           0x200           /* Base address of UART1 */
-#define MCFUART_BASE2           0x240           /* Base address of UART2 */
-#define MCFUART_BASE3           0x280           /* Base address of UART3 */
+#define MCFUART_BASE1           (MCF_IPSBAR + 0x00000200)
+#define MCFUART_BASE2           (MCF_IPSBAR + 0x00000240)
+#define MCFUART_BASE3           (MCF_IPSBAR + 0x00000280)
+
+/*
+ *      FEC ethernet module.
+ */
+#define MCFFEC_BASE             (MCF_IPSBAR + 0x00001000)
+#define MCFFEC_SIZE             0x800
 
 /*
  *      GPIO registers
@@ -163,6 +179,14 @@
 #define MCFGPIO_PUAPAR          (MCF_IPSBAR + 0x0010005C)
 
 /*
+ * PIT timer base addresses.
+ */
+#define MCFPIT_BASE1            (MCF_IPSBAR + 0x00150000)
+#define MCFPIT_BASE2            (MCF_IPSBAR + 0x00160000)
+#define MCFPIT_BASE3            (MCF_IPSBAR + 0x00170000)
+#define MCFPIT_BASE4            (MCF_IPSBAR + 0x00180000)
+
+/*
  *      Edge Port registers
  */
 #define MCFEPORT_EPPAR          (MCF_IPSBAR + 0x00130000)
diff --git a/arch/m68k/include/asm/m5307sim.h b/arch/m68k/include/asm/m5307sim.h
index 0bf57397e7a9..4c94c01f36c4 100644
--- a/arch/m68k/include/asm/m5307sim.h
+++ b/arch/m68k/include/asm/m5307sim.h
@@ -16,6 +16,7 @@
 
 #define CPU_NAME                "COLDFIRE(m5307)"
 #define CPU_INSTR_PER_JIFFY     3
+#define MCF_BUSCLK              (MCF_CLK / 2)
 
 #include <asm/m53xxacr.h>
 
@@ -89,16 +90,30 @@
 #define MCFSIM_CSCR7            0xde            /* CS 7 Control reg (r/w) */
 #endif /* CONFIG_OLDMASK */
 
-#define MCFSIM_DCR              0x100           /* DRAM Control reg (r/w) */
-#define MCFSIM_DACR0            0x108           /* DRAM 0 Addr and Ctrl (r/w) */
-#define MCFSIM_DMR0             0x10c           /* DRAM 0 Mask reg (r/w) */
-#define MCFSIM_DACR1            0x110           /* DRAM 1 Addr and Ctrl (r/w) */
-#define MCFSIM_DMR1             0x114           /* DRAM 1 Mask reg (r/w) */
+#define MCFSIM_DCR              (MCF_MBAR + 0x100)      /* DRAM Control */
+#define MCFSIM_DACR0            (MCF_MBAR + 0x108)      /* DRAM Addr/Ctrl 0 */
+#define MCFSIM_DMR0             (MCF_MBAR + 0x10c)      /* DRAM Mask 0 */
+#define MCFSIM_DACR1            (MCF_MBAR + 0x110)      /* DRAM Addr/Ctrl 1 */
+#define MCFSIM_DMR1             (MCF_MBAR + 0x114)      /* DRAM Mask 1 */
+
+/*
+ *  Timer module.
+ */
+#define MCFTIMER_BASE1          (MCF_MBAR + 0x140)      /* Base of TIMER1 */
+#define MCFTIMER_BASE2          (MCF_MBAR + 0x180)      /* Base of TIMER2 */
 
 #define MCFSIM_PADDR            (MCF_MBAR + 0x244)
 #define MCFSIM_PADAT            (MCF_MBAR + 0x248)
 
 /*
+ *  DMA unit base addresses.
+ */
+#define MCFDMA_BASE0            (MCF_MBAR + 0x300)      /* Base address DMA 0 */
+#define MCFDMA_BASE1            (MCF_MBAR + 0x340)      /* Base address DMA 1 */
+#define MCFDMA_BASE2            (MCF_MBAR + 0x380)      /* Base address DMA 2 */
+#define MCFDMA_BASE3            (MCF_MBAR + 0x3C0)      /* Base address DMA 3 */
+
+/*
  *  UART module.
  */
 #if defined(CONFIG_NETtel) || defined(CONFIG_SECUREEDGEMP3)
diff --git a/arch/m68k/include/asm/m532xsim.h b/arch/m68k/include/asm/m532xsim.h
index e6470f8ca324..ba4cc784f574 100644
--- a/arch/m68k/include/asm/m532xsim.h
+++ b/arch/m68k/include/asm/m532xsim.h
@@ -11,6 +11,7 @@
 
 #define CPU_NAME                "COLDFIRE(m532x)"
 #define CPU_INSTR_PER_JIFFY     3
+#define MCF_BUSCLK              (MCF_CLK / 3)
 
 #include <asm/m53xxacr.h>
 
@@ -85,6 +86,14 @@
 #define MCFUART_BASE2           0xFC064000      /* Base address of UART2 */
 #define MCFUART_BASE3           0xFC068000      /* Base address of UART3 */
 
+/*
+ *  Timer module.
+ */
+#define MCFTIMER_BASE1          0xFC070000      /* Base address of TIMER1 */
+#define MCFTIMER_BASE2          0xFC074000      /* Base address of TIMER2 */
+#define MCFTIMER_BASE3          0xFC078000      /* Base address of TIMER3 */
+#define MCFTIMER_BASE4          0xFC07C000      /* Base address of TIMER4 */
+
 /*********************************************************************
  *
  * Reset Controller Module
diff --git a/arch/m68k/include/asm/m5407sim.h b/arch/m68k/include/asm/m5407sim.h
index 75f5c28a551d..762c58c89050 100644
--- a/arch/m68k/include/asm/m5407sim.h
+++ b/arch/m68k/include/asm/m5407sim.h
@@ -16,6 +16,7 @@
 
 #define CPU_NAME                "COLDFIRE(m5407)"
 #define CPU_INSTR_PER_JIFFY     3
+#define MCF_BUSCLK              (MCF_CLK / 2)
 
 #include <asm/m54xxacr.h>
 
@@ -72,11 +73,17 @@
 #define MCFSIM_CSMR7            0xd8            /* CS 7 Mask reg (r/w) */
 #define MCFSIM_CSCR7            0xde            /* CS 7 Control reg (r/w) */
 
-#define MCFSIM_DCR              0x100           /* DRAM Control reg (r/w) */
-#define MCFSIM_DACR0            0x108           /* DRAM 0 Addr and Ctrl (r/w) */
-#define MCFSIM_DMR0             0x10c           /* DRAM 0 Mask reg (r/w) */
-#define MCFSIM_DACR1            0x110           /* DRAM 1 Addr and Ctrl (r/w) */
-#define MCFSIM_DMR1             0x114           /* DRAM 1 Mask reg (r/w) */
+#define MCFSIM_DCR              (MCF_MBAR + 0x100)      /* DRAM Control */
+#define MCFSIM_DACR0            (MCF_MBAR + 0x108)      /* DRAM 0 Addr/Ctrl */
+#define MCFSIM_DMR0             (MCF_MBAR + 0x10c)      /* DRAM 0 Mask */
+#define MCFSIM_DACR1            (MCF_MBAR + 0x110)      /* DRAM 1 Addr/Ctrl */
+#define MCFSIM_DMR1             (MCF_MBAR + 0x114)      /* DRAM 1 Mask */
+
+/*
+ *      Timer module.
+ */
+#define MCFTIMER_BASE1          (MCF_MBAR + 0x140)      /* Base of TIMER1 */
+#define MCFTIMER_BASE2          (MCF_MBAR + 0x180)      /* Base of TIMER2 */
 
 #define MCFUART_BASE1           0x1c0           /* Base address of UART1 */
 #define MCFUART_BASE2           0x200           /* Base address of UART2 */
@@ -85,6 +92,14 @@
 #define MCFSIM_PADAT            (MCF_MBAR + 0x248)
 
 /*
+ *      DMA unit base addresses.
+ */
+#define MCFDMA_BASE0            (MCF_MBAR + 0x300)      /* Base address DMA 0 */
+#define MCFDMA_BASE1            (MCF_MBAR + 0x340)      /* Base address DMA 1 */
+#define MCFDMA_BASE2            (MCF_MBAR + 0x380)      /* Base address DMA 2 */
+#define MCFDMA_BASE3            (MCF_MBAR + 0x3C0)      /* Base address DMA 3 */
+
+/*
  * Generic GPIO support
  */
 #define MCFGPIO_PIN_MAX                 16
diff --git a/arch/m68k/include/asm/m54xxsim.h b/arch/m68k/include/asm/m54xxsim.h
index 462ae5328441..1ed8bfb02772 100644
--- a/arch/m68k/include/asm/m54xxsim.h
+++ b/arch/m68k/include/asm/m54xxsim.h
@@ -7,6 +7,7 @@
 
 #define CPU_NAME                "COLDFIRE(m54xx)"
 #define CPU_INSTR_PER_JIFFY     2
+#define MCF_BUSCLK              (MCF_CLK / 2)
 
 #include <asm/m54xxacr.h>
 
@@ -15,7 +16,8 @@
 /*
  *      Interrupt Controller Registers
  */
-#define MCFICM_INTC0            0x0700          /* Base for Interrupt Ctrl 0 */
+#define MCFICM_INTC0            (MCF_MBAR + 0x700)      /* Base for Interrupt Ctrl 0 */
+
 #define MCFINTC_IPRH            0x00            /* Interrupt pending 32-63 */
 #define MCFINTC_IPRL            0x04            /* Interrupt pending 1-31 */
 #define MCFINTC_IMRH            0x08            /* Interrupt mask 32-63 */
@@ -48,6 +50,16 @@
 #define MCFGPIO_IRQ_VECBASE     -1
 
 /*
+ *      EDGE Port support.
+ */
+#define MCFEPORT_EPPAR          (MCF_MBAR + 0xf00)      /* Pin assignment */
+#define MCFEPORT_EPDDR          (MCF_MBAR + 0xf04)      /* Data direction */
+#define MCFEPORT_EPIER          (MCF_MBAR + 0xf05)      /* Interrupt enable */
+#define MCFEPORT_EPDR           (MCF_MBAR + 0xf08)      /* Port data (w) */
+#define MCFEPORT_EPPDR          (MCF_MBAR + 0xf09)      /* Port data (r) */
+#define MCFEPORT_EPFR           (MCF_MBAR + 0xf0c)      /* Flags */
+
+/*
  *      Some PSC related definitions
  */
 #define MCF_PAR_PSC(x)          (0x000A4F-((x)&0x3))
diff --git a/arch/m68k/include/asm/mcfdma.h b/arch/m68k/include/asm/mcfdma.h
index 705c52c79cd8..10bc7e391c14 100644
--- a/arch/m68k/include/asm/mcfdma.h
+++ b/arch/m68k/include/asm/mcfdma.h
@@ -11,29 +11,6 @@
 #define mcfdma_h
 /****************************************************************************/
 
-
-/*
- *      Get address specific defines for this Coldfire member.
- */
-#if defined(CONFIG_M5206) || defined(CONFIG_M5206e)
-#define MCFDMA_BASE0            0x200           /* Base address of DMA 0 */
-#define MCFDMA_BASE1            0x240           /* Base address of DMA 1 */
-#elif defined(CONFIG_M5272)
-#define MCFDMA_BASE0            0x0e0           /* Base address of DMA 0 */
-#elif defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x)
-/* These are relative to the IPSBAR, not MBAR */
-#define MCFDMA_BASE0            0x100           /* Base address of DMA 0 */
-#define MCFDMA_BASE1            0x140           /* Base address of DMA 1 */
-#define MCFDMA_BASE2            0x180           /* Base address of DMA 2 */
-#define MCFDMA_BASE3            0x1C0           /* Base address of DMA 3 */
-#elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407)
-#define MCFDMA_BASE0            0x300           /* Base address of DMA 0 */
-#define MCFDMA_BASE1            0x340           /* Base address of DMA 1 */
-#define MCFDMA_BASE2            0x380           /* Base address of DMA 2 */
-#define MCFDMA_BASE3            0x3C0           /* Base address of DMA 3 */
-#endif
-
-
 #if !defined(CONFIG_M5272)
 
 /*
diff --git a/arch/m68k/include/asm/mcfpit.h b/arch/m68k/include/asm/mcfpit.h
index f570cf64fd29..9fd321ca0725 100644
--- a/arch/m68k/include/asm/mcfpit.h
+++ b/arch/m68k/include/asm/mcfpit.h
@@ -11,22 +11,8 @@
 #define mcfpit_h
 /****************************************************************************/
 
-
-/*
- *      Get address specific defines for the 5270/5271, 5280/5282, and 5208.
- */
-#if defined(CONFIG_M520x)
-#define MCFPIT_BASE1            0x00080000      /* Base address of TIMER1 */
-#define MCFPIT_BASE2            0x00084000      /* Base address of TIMER2 */
-#else
-#define MCFPIT_BASE1            0x00150000      /* Base address of TIMER1 */
-#define MCFPIT_BASE2            0x00160000      /* Base address of TIMER2 */
-#define MCFPIT_BASE3            0x00170000      /* Base address of TIMER3 */
-#define MCFPIT_BASE4            0x00180000      /* Base address of TIMER4 */
-#endif
-
 /*
- *      Define the PIT timer register set addresses.
+ *      Define the PIT timer register address offsets.
  */
 #define MCFPIT_PCSR             0x0             /* PIT control register */
 #define MCFPIT_PMR              0x2             /* PIT modulus register */
diff --git a/arch/m68k/include/asm/mcftimer.h b/arch/m68k/include/asm/mcftimer.h
index 0f90f6d2227a..92b276fe8240 100644
--- a/arch/m68k/include/asm/mcftimer.h
+++ b/arch/m68k/include/asm/mcftimer.h
@@ -12,29 +12,6 @@
 #define mcftimer_h
 /****************************************************************************/
 
-
-/*
- *      Get address specific defines for this ColdFire member.
- */
-#if defined(CONFIG_M5206) || defined(CONFIG_M5206e)
-#define MCFTIMER_BASE1          0x100           /* Base address of TIMER1 */
-#define MCFTIMER_BASE2          0x120           /* Base address of TIMER2 */
-#elif defined(CONFIG_M5272)
-#define MCFTIMER_BASE1          0x200           /* Base address of TIMER1 */
-#define MCFTIMER_BASE2          0x220           /* Base address of TIMER2 */
-#define MCFTIMER_BASE3          0x240           /* Base address of TIMER4 */
-#define MCFTIMER_BASE4          0x260           /* Base address of TIMER3 */
-#elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407)
-#define MCFTIMER_BASE1          0x140           /* Base address of TIMER1 */
-#define MCFTIMER_BASE2          0x180           /* Base address of TIMER2 */
-#elif defined(CONFIG_M532x)
-#define MCFTIMER_BASE1          0xfc070000      /* Base address of TIMER1 */
-#define MCFTIMER_BASE2          0xfc074000      /* Base address of TIMER2 */
-#define MCFTIMER_BASE3          0xfc078000      /* Base address of TIMER3 */
-#define MCFTIMER_BASE4          0xfc07c000      /* Base address of TIMER4 */
-#endif
-
-
 /*
  *      Define the TIMER register set addresses.
  */
diff --git a/arch/m68k/include/asm/string.h b/arch/m68k/include/asm/string.h
index 2936dda938d7..32198454da70 100644
--- a/arch/m68k/include/asm/string.h
+++ b/arch/m68k/include/asm/string.h
@@ -81,18 +81,6 @@ static inline char *strncpy(char *dest, const char *src, size_t n)
         strcpy(__d + strlen(__d), (s));         \
 })
 
-#define __HAVE_ARCH_STRCHR
-static inline char *strchr(const char *s, int c)
-{
-        char sc, ch = c;
-
-        for (; (sc = *s++) != ch; ) {
-                if (!sc)
-                        return NULL;
-        }
-        return (char *)s - 1;
-}
-
 #ifndef CONFIG_COLDFIRE
 #define __HAVE_ARCH_STRCMP
 static inline int strcmp(const char *cs, const char *ct)
@@ -111,14 +99,12 @@ static inline int strcmp(const char *cs, const char *ct)
                 : "+a" (cs), "+a" (ct), "=d" (res));
         return res;
 }
+#endif /* CONFIG_COLDFIRE */
 
 #define __HAVE_ARCH_MEMMOVE
 extern void *memmove(void *, const void *, __kernel_size_t);
 
-#define __HAVE_ARCH_MEMCMP
-extern int memcmp(const void *, const void *, __kernel_size_t);
 #define memcmp(d, s, n) __builtin_memcmp(d, s, n)
-#endif /* CONFIG_COLDFIRE */
 
 #define __HAVE_ARCH_MEMSET
 extern void *memset(void *, int, __kernel_size_t);
diff --git a/arch/m68k/kernel/time.c b/arch/m68k/kernel/time.c
index 06438dac08ff..18b34ee5db3b 100644
--- a/arch/m68k/kernel/time.c
+++ b/arch/m68k/kernel/time.c
@@ -37,11 +37,11 @@ static inline int set_rtc_mmss(unsigned long nowtime)
 
 /*
  * timer_interrupt() needs to keep up the real-time clock,
- * as well as call the "do_timer()" routine every clocktick
+ * as well as call the "xtime_update()" routine every clocktick
  */
 static irqreturn_t timer_interrupt(int irq, void *dummy)
 {
-        do_timer(1);
+        xtime_update(1);
         update_process_times(user_mode(get_irq_regs()));
         profile_tick(CPU_PROFILING);
 
diff --git a/arch/m68k/lib/string.c b/arch/m68k/lib/string.c
index 4253f870e54f..d399c5f25636 100644
--- a/arch/m68k/lib/string.c
+++ b/arch/m68k/lib/string.c
@@ -243,14 +243,3 @@ void *memmove(void *dest, const void *src, size_t n)
         return xdest;
 }
 EXPORT_SYMBOL(memmove);
-
-int memcmp(const void *cs, const void *ct, size_t count)
-{
-        const unsigned char *su1, *su2;
-
-        for (su1 = cs, su2 = ct; count > 0; ++su1, ++su2, count--)
-                if (*su1 != *su2)
-                        return *su1 < *su2 ? -1 : +1;
-        return 0;
-}
-EXPORT_SYMBOL(memcmp);
diff --git a/arch/m68k/mvme147/config.c b/arch/m68k/mvme147/config.c
index 100baaa692a1..6cb9c3a9b6c9 100644
--- a/arch/m68k/mvme147/config.c
+++ b/arch/m68k/mvme147/config.c
@@ -46,8 +46,8 @@ extern void mvme147_reset (void);
 
 static int bcd2int (unsigned char b);
 
-/* Save tick handler routine pointer, will point to do_timer() in
- * kernel/sched.c, called via mvme147_process_int() */
+/* Save tick handler routine pointer, will point to xtime_update() in
+ * kernel/time/timekeeping.c, called via mvme147_process_int() */
 
 irq_handler_t tick_handler;
 
diff --git a/arch/m68k/mvme16x/config.c b/arch/m68k/mvme16x/config.c
index 11edf61cc2c4..0b28e2621653 100644
--- a/arch/m68k/mvme16x/config.c
+++ b/arch/m68k/mvme16x/config.c
@@ -51,8 +51,8 @@ extern void mvme16x_reset (void);
 
 int bcd2int (unsigned char b);
 
-/* Save tick handler routine pointer, will point to do_timer() in
- * kernel/sched.c, called via mvme16x_process_int() */
+/* Save tick handler routine pointer, will point to xtime_update() in
+ * kernel/time/timekeeping.c, called via mvme16x_process_int() */
 
 static irq_handler_t tick_handler;
 
diff --git a/arch/m68k/sun3/sun3ints.c b/arch/m68k/sun3/sun3ints.c
index 2d9e21bd313a..6464ad3ae3e6 100644
--- a/arch/m68k/sun3/sun3ints.c
+++ b/arch/m68k/sun3/sun3ints.c
@@ -66,7 +66,7 @@ static irqreturn_t sun3_int5(int irq, void *dev_id)
 #ifdef CONFIG_SUN3
         intersil_clear();
 #endif
-        do_timer(1);
+        xtime_update(1);
         update_process_times(user_mode(get_irq_regs()));
         if (!(kstat_cpu(0).irqs[irq] % 20))
                 sun3_leds(led_pattern[(kstat_cpu(0).irqs[irq] % 160) / 20]);