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-rw-r--r--arch/m68k/Kconfig1
-rw-r--r--arch/m68k/Kconfig.bus7
-rw-r--r--arch/m68k/Kconfig.cpu18
-rw-r--r--arch/m68k/Makefile2
-rw-r--r--arch/m68k/include/asm/cacheflush_mm.h41
-rw-r--r--arch/m68k/include/asm/dma.h8
-rw-r--r--arch/m68k/include/asm/gpio.h179
-rw-r--r--arch/m68k/include/asm/io_mm.h50
-rw-r--r--arch/m68k/include/asm/m520xsim.h14
-rw-r--r--arch/m68k/include/asm/m523xsim.h1
-rw-r--r--arch/m68k/include/asm/m525xsim.h194
-rw-r--r--arch/m68k/include/asm/m527xsim.h1
-rw-r--r--arch/m68k/include/asm/m528xsim.h2
-rw-r--r--arch/m68k/include/asm/m532xsim.h17
-rw-r--r--arch/m68k/include/asm/m5441xsim.h276
-rw-r--r--arch/m68k/include/asm/m54xxacr.h4
-rw-r--r--arch/m68k/include/asm/m54xxpci.h138
-rw-r--r--arch/m68k/include/asm/m54xxsim.h3
-rw-r--r--arch/m68k/include/asm/mcf8390.h (renamed from arch/m68k/include/asm/mcfne.h)137
-rw-r--r--arch/m68k/include/asm/mcfclk.h43
-rw-r--r--arch/m68k/include/asm/mcfgpio.h343
-rw-r--r--arch/m68k/include/asm/mcfsim.h5
-rw-r--r--arch/m68k/include/asm/mcftimer.h2
-rw-r--r--arch/m68k/include/asm/mcfuart.h4
-rw-r--r--arch/m68k/include/asm/pci.h6
-rw-r--r--arch/m68k/include/asm/pinmux.h30
-rw-r--r--arch/m68k/include/asm/unistd.h1
-rw-r--r--arch/m68k/kernel/Makefile1
-rw-r--r--arch/m68k/kernel/dma.c5
-rw-r--r--arch/m68k/kernel/entry.S452
-rw-r--r--arch/m68k/kernel/entry_mm.S419
-rw-r--r--arch/m68k/kernel/entry_no.S130
-rw-r--r--arch/m68k/kernel/module.c4
-rw-r--r--arch/m68k/kernel/pcibios.c109
-rw-r--r--arch/m68k/mm/memory.c2
-rw-r--r--arch/m68k/platform/coldfire/Makefile7
-rw-r--r--arch/m68k/platform/coldfire/clk.c111
-rw-r--r--arch/m68k/platform/coldfire/device.c57
-rw-r--r--arch/m68k/platform/coldfire/gpio.c172
-rw-r--r--arch/m68k/platform/coldfire/head.S6
-rw-r--r--arch/m68k/platform/coldfire/intc-525x.c91
-rw-r--r--arch/m68k/platform/coldfire/intc-simr.c26
-rw-r--r--arch/m68k/platform/coldfire/m5206.c9
-rw-r--r--arch/m68k/platform/coldfire/m520x.c103
-rw-r--r--arch/m68k/platform/coldfire/m523x.c22
-rw-r--r--arch/m68k/platform/coldfire/m5249.c10
-rw-r--r--arch/m68k/platform/coldfire/m525x.c66
-rw-r--r--arch/m68k/platform/coldfire/m5272.c11
-rw-r--r--arch/m68k/platform/coldfire/m527x.c43
-rw-r--r--arch/m68k/platform/coldfire/m528x.c33
-rw-r--r--arch/m68k/platform/coldfire/m5307.c9
-rw-r--r--arch/m68k/platform/coldfire/m532x.c154
-rw-r--r--arch/m68k/platform/coldfire/m5407.c9
-rw-r--r--arch/m68k/platform/coldfire/m5441x.c261
-rw-r--r--arch/m68k/platform/coldfire/m54xx.c7
-rw-r--r--arch/m68k/platform/coldfire/mcf8390.c38
-rw-r--r--arch/m68k/platform/coldfire/pci.c327
-rw-r--r--arch/m68k/platform/coldfire/pinmux.c28
-rw-r--r--arch/m68k/platform/coldfire/pit.c4
-rw-r--r--arch/m68k/platform/coldfire/timers.c2
60 files changed, 3005 insertions, 1250 deletions
diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig
index 147120128260..0b0f8b8c4a26 100644
--- a/arch/m68k/Kconfig
+++ b/arch/m68k/Kconfig
@@ -10,6 +10,7 @@ config M68K
10 select GENERIC_STRNCPY_FROM_USER if MMU 10 select GENERIC_STRNCPY_FROM_USER if MMU
11 select GENERIC_STRNLEN_USER if MMU 11 select GENERIC_STRNLEN_USER if MMU
12 select FPU if MMU 12 select FPU if MMU
13 select ARCH_WANT_IPC_PARSE_VERSION
13 select ARCH_USES_GETTIMEOFFSET if MMU && !COLDFIRE 14 select ARCH_USES_GETTIMEOFFSET if MMU && !COLDFIRE
14 15
15config RWSEM_GENERIC_SPINLOCK 16config RWSEM_GENERIC_SPINLOCK
diff --git a/arch/m68k/Kconfig.bus b/arch/m68k/Kconfig.bus
index 3adb499584fb..ffc0601a2a19 100644
--- a/arch/m68k/Kconfig.bus
+++ b/arch/m68k/Kconfig.bus
@@ -48,6 +48,13 @@ config ISA
48config GENERIC_ISA_DMA 48config GENERIC_ISA_DMA
49 def_bool ISA 49 def_bool ISA
50 50
51config PCI
52 bool "PCI support"
53 depends on M54xx
54 help
55 Enable the PCI bus. Support for the PCI bus hardware built into the
56 ColdFire 547x and 548x processors.
57
51source "drivers/pci/Kconfig" 58source "drivers/pci/Kconfig"
52 59
53source "drivers/zorro/Kconfig" 60source "drivers/zorro/Kconfig"
diff --git a/arch/m68k/Kconfig.cpu b/arch/m68k/Kconfig.cpu
index 2b53254ad994..43a9f8f1b8eb 100644
--- a/arch/m68k/Kconfig.cpu
+++ b/arch/m68k/Kconfig.cpu
@@ -23,7 +23,7 @@ config M68KCLASSIC
23config COLDFIRE 23config COLDFIRE
24 bool "Coldfire CPU family support" 24 bool "Coldfire CPU family support"
25 select GENERIC_GPIO 25 select GENERIC_GPIO
26 select ARCH_REQUIRE_GPIOLIB 26 select ARCH_WANT_OPTIONAL_GPIOLIB
27 select ARCH_HAVE_CUSTOM_GPIO_H 27 select ARCH_HAVE_CUSTOM_GPIO_H
28 select CPU_HAS_NO_BITFIELDS 28 select CPU_HAS_NO_BITFIELDS
29 select CPU_HAS_NO_MULDIV64 29 select CPU_HAS_NO_MULDIV64
@@ -167,6 +167,14 @@ config M5249
167 help 167 help
168 Motorola ColdFire 5249 processor support. 168 Motorola ColdFire 5249 processor support.
169 169
170config M525x
171 bool "MCF525x"
172 depends on !MMU
173 select COLDFIRE_SW_A7
174 select HAVE_MBAR
175 help
176 Freescale (Motorola) Coldfire 5251/5253 processor support.
177
170config M527x 178config M527x
171 bool 179 bool
172 180
@@ -253,6 +261,14 @@ config M548x
253 help 261 help
254 Freescale ColdFire 5480/5481/5482/5483/5484/5485 processor support. 262 Freescale ColdFire 5480/5481/5482/5483/5484/5485 processor support.
255 263
264config M5441x
265 bool "MCF5441x"
266 depends on !MMU
267 select GENERIC_CLOCKEVENTS
268 select HAVE_CACHE_CB
269 help
270 Freescale Coldfire 54410/54415/54416/54417/54418 processor support.
271
256endif # COLDFIRE 272endif # COLDFIRE
257 273
258 274
diff --git a/arch/m68k/Makefile b/arch/m68k/Makefile
index b7f2e2d5cd2e..7636751f2f87 100644
--- a/arch/m68k/Makefile
+++ b/arch/m68k/Makefile
@@ -41,6 +41,7 @@ cpuflags-$(CONFIG_M68030) :=
41cpuflags-$(CONFIG_M68020) := 41cpuflags-$(CONFIG_M68020) :=
42cpuflags-$(CONFIG_M68360) := -m68332 42cpuflags-$(CONFIG_M68360) := -m68332
43cpuflags-$(CONFIG_M68000) := -m68000 43cpuflags-$(CONFIG_M68000) := -m68000
44cpuflags-$(CONFIG_M5441x) := $(call cc-option,-mcpu=54455,-mcfv4e)
44cpuflags-$(CONFIG_M54xx) := $(call cc-option,-mcpu=5475,-m5200) 45cpuflags-$(CONFIG_M54xx) := $(call cc-option,-mcpu=5475,-m5200)
45cpuflags-$(CONFIG_M5407) := $(call cc-option,-mcpu=5407,-m5200) 46cpuflags-$(CONFIG_M5407) := $(call cc-option,-mcpu=5407,-m5200)
46cpuflags-$(CONFIG_M532x) := $(call cc-option,-mcpu=532x,-m5307) 47cpuflags-$(CONFIG_M532x) := $(call cc-option,-mcpu=532x,-m5307)
@@ -50,6 +51,7 @@ cpuflags-$(CONFIG_M5275) := $(call cc-option,-mcpu=5275,-m5307)
50cpuflags-$(CONFIG_M5272) := $(call cc-option,-mcpu=5272,-m5307) 51cpuflags-$(CONFIG_M5272) := $(call cc-option,-mcpu=5272,-m5307)
51cpuflags-$(CONFIG_M5271) := $(call cc-option,-mcpu=5271,-m5307) 52cpuflags-$(CONFIG_M5271) := $(call cc-option,-mcpu=5271,-m5307)
52cpuflags-$(CONFIG_M523x) := $(call cc-option,-mcpu=523x,-m5307) 53cpuflags-$(CONFIG_M523x) := $(call cc-option,-mcpu=523x,-m5307)
54cpuflags-$(CONFIG_M525x) := $(call cc-option,-mcpu=5253,-m5200)
53cpuflags-$(CONFIG_M5249) := $(call cc-option,-mcpu=5249,-m5200) 55cpuflags-$(CONFIG_M5249) := $(call cc-option,-mcpu=5249,-m5200)
54cpuflags-$(CONFIG_M520x) := $(call cc-option,-mcpu=5208,-m5200) 56cpuflags-$(CONFIG_M520x) := $(call cc-option,-mcpu=5208,-m5200)
55cpuflags-$(CONFIG_M5206e) := $(call cc-option,-mcpu=5206e,-m5200) 57cpuflags-$(CONFIG_M5206e) := $(call cc-option,-mcpu=5206e,-m5200)
diff --git a/arch/m68k/include/asm/cacheflush_mm.h b/arch/m68k/include/asm/cacheflush_mm.h
index 8104bd874649..fa2c3d681d84 100644
--- a/arch/m68k/include/asm/cacheflush_mm.h
+++ b/arch/m68k/include/asm/cacheflush_mm.h
@@ -16,7 +16,48 @@
16#define DCACHE_MAX_ADDR 0 16#define DCACHE_MAX_ADDR 0
17#define DCACHE_SETMASK 0 17#define DCACHE_SETMASK 0
18#endif 18#endif
19#ifndef CACHE_MODE
20#define CACHE_MODE 0
21#define CACR_ICINVA 0
22#define CACR_DCINVA 0
23#define CACR_BCINVA 0
24#endif
25
26/*
27 * ColdFire architecture has no way to clear individual cache lines, so we
28 * are stuck invalidating all the cache entries when we want a clear operation.
29 */
30static inline void clear_cf_icache(unsigned long start, unsigned long end)
31{
32 __asm__ __volatile__ (
33 "movec %0,%%cacr\n\t"
34 "nop"
35 :
36 : "r" (CACHE_MODE | CACR_ICINVA | CACR_BCINVA));
37}
38
39static inline void clear_cf_dcache(unsigned long start, unsigned long end)
40{
41 __asm__ __volatile__ (
42 "movec %0,%%cacr\n\t"
43 "nop"
44 :
45 : "r" (CACHE_MODE | CACR_DCINVA));
46}
19 47
48static inline void clear_cf_bcache(unsigned long start, unsigned long end)
49{
50 __asm__ __volatile__ (
51 "movec %0,%%cacr\n\t"
52 "nop"
53 :
54 : "r" (CACHE_MODE | CACR_ICINVA | CACR_BCINVA | CACR_DCINVA));
55}
56
57/*
58 * Use the ColdFire cpushl instruction to push (and invalidate) cache lines.
59 * The start and end addresses are cache line numbers not memory addresses.
60 */
20static inline void flush_cf_icache(unsigned long start, unsigned long end) 61static inline void flush_cf_icache(unsigned long start, unsigned long end)
21{ 62{
22 unsigned long set; 63 unsigned long set;
diff --git a/arch/m68k/include/asm/dma.h b/arch/m68k/include/asm/dma.h
index 6fbdfe895104..0ff3fc6a6d9a 100644
--- a/arch/m68k/include/asm/dma.h
+++ b/arch/m68k/include/asm/dma.h
@@ -33,7 +33,9 @@
33 * Set number of channels of DMA on ColdFire for different implementations. 33 * Set number of channels of DMA on ColdFire for different implementations.
34 */ 34 */
35#if defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407) || \ 35#if defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407) || \
36 defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) 36 defined(CONFIG_M523x) || defined(CONFIG_M527x) || \
37 defined(CONFIG_M528x) || defined(CONFIG_M525x)
38
37#define MAX_M68K_DMA_CHANNELS 4 39#define MAX_M68K_DMA_CHANNELS 4
38#elif defined(CONFIG_M5272) 40#elif defined(CONFIG_M5272)
39#define MAX_M68K_DMA_CHANNELS 1 41#define MAX_M68K_DMA_CHANNELS 1
@@ -486,6 +488,10 @@ static __inline__ int get_dma_residue(unsigned int dmanr)
486extern int request_dma(unsigned int dmanr, const char * device_id); /* reserve a DMA channel */ 488extern int request_dma(unsigned int dmanr, const char * device_id); /* reserve a DMA channel */
487extern void free_dma(unsigned int dmanr); /* release it again */ 489extern void free_dma(unsigned int dmanr); /* release it again */
488 490
491#ifdef CONFIG_PCI
492extern int isa_dma_bridge_buggy;
493#else
489#define isa_dma_bridge_buggy (0) 494#define isa_dma_bridge_buggy (0)
495#endif
490 496
491#endif /* _M68K_DMA_H */ 497#endif /* _M68K_DMA_H */
diff --git a/arch/m68k/include/asm/gpio.h b/arch/m68k/include/asm/gpio.h
index 00d0071de4c3..4395ffc51fdb 100644
--- a/arch/m68k/include/asm/gpio.h
+++ b/arch/m68k/include/asm/gpio.h
@@ -17,170 +17,9 @@
17#define coldfire_gpio_h 17#define coldfire_gpio_h
18 18
19#include <linux/io.h> 19#include <linux/io.h>
20#include <asm-generic/gpio.h>
21#include <asm/coldfire.h> 20#include <asm/coldfire.h>
22#include <asm/mcfsim.h> 21#include <asm/mcfsim.h>
23 22#include <asm/mcfgpio.h>
24/*
25 * The Freescale Coldfire family is quite varied in how they implement GPIO.
26 * Some parts have 8 bit ports, some have 16bit and some have 32bit; some have
27 * only one port, others have multiple ports; some have a single data latch
28 * for both input and output, others have a separate pin data register to read
29 * input; some require a read-modify-write access to change an output, others
30 * have set and clear registers for some of the outputs; Some have all the
31 * GPIOs in a single control area, others have some GPIOs implemented in
32 * different modules.
33 *
34 * This implementation attempts accommodate the differences while presenting
35 * a generic interface that will optimize to as few instructions as possible.
36 */
37#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
38 defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
39 defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
40 defined(CONFIG_M532x) || defined(CONFIG_M54xx)
41
42/* These parts have GPIO organized by 8 bit ports */
43
44#define MCFGPIO_PORTTYPE u8
45#define MCFGPIO_PORTSIZE 8
46#define mcfgpio_read(port) __raw_readb(port)
47#define mcfgpio_write(data, port) __raw_writeb(data, port)
48
49#elif defined(CONFIG_M5307) || defined(CONFIG_M5407) || defined(CONFIG_M5272)
50
51/* These parts have GPIO organized by 16 bit ports */
52
53#define MCFGPIO_PORTTYPE u16
54#define MCFGPIO_PORTSIZE 16
55#define mcfgpio_read(port) __raw_readw(port)
56#define mcfgpio_write(data, port) __raw_writew(data, port)
57
58#elif defined(CONFIG_M5249)
59
60/* These parts have GPIO organized by 32 bit ports */
61
62#define MCFGPIO_PORTTYPE u32
63#define MCFGPIO_PORTSIZE 32
64#define mcfgpio_read(port) __raw_readl(port)
65#define mcfgpio_write(data, port) __raw_writel(data, port)
66
67#endif
68
69#define mcfgpio_bit(gpio) (1 << ((gpio) % MCFGPIO_PORTSIZE))
70#define mcfgpio_port(gpio) ((gpio) / MCFGPIO_PORTSIZE)
71
72#if defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
73 defined(CONFIG_M527x) || defined(CONFIG_M528x) || defined(CONFIG_M532x)
74/*
75 * These parts have an 'Edge' Port module (external interrupt/GPIO) which uses
76 * read-modify-write to change an output and a GPIO module which has separate
77 * set/clr registers to directly change outputs with a single write access.
78 */
79#if defined(CONFIG_M528x)
80/*
81 * The 528x also has GPIOs in other modules (GPT, QADC) which use
82 * read-modify-write as well as those controlled by the EPORT and GPIO modules.
83 */
84#define MCFGPIO_SCR_START 40
85#else
86#define MCFGPIO_SCR_START 8
87#endif
88
89#define MCFGPIO_SETR_PORT(gpio) (MCFGPIO_SETR + \
90 mcfgpio_port(gpio - MCFGPIO_SCR_START))
91
92#define MCFGPIO_CLRR_PORT(gpio) (MCFGPIO_CLRR + \
93 mcfgpio_port(gpio - MCFGPIO_SCR_START))
94#else
95
96#define MCFGPIO_SCR_START MCFGPIO_PIN_MAX
97/* with MCFGPIO_SCR == MCFGPIO_PIN_MAX, these will be optimized away */
98#define MCFGPIO_SETR_PORT(gpio) 0
99#define MCFGPIO_CLRR_PORT(gpio) 0
100
101#endif
102/*
103 * Coldfire specific helper functions
104 */
105
106/* return the port pin data register for a gpio */
107static inline u32 __mcf_gpio_ppdr(unsigned gpio)
108{
109#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
110 defined(CONFIG_M5307) || defined(CONFIG_M5407)
111 return MCFSIM_PADAT;
112#elif defined(CONFIG_M5272)
113 if (gpio < 16)
114 return MCFSIM_PADAT;
115 else if (gpio < 32)
116 return MCFSIM_PBDAT;
117 else
118 return MCFSIM_PCDAT;
119#elif defined(CONFIG_M5249)
120 if (gpio < 32)
121 return MCFSIM2_GPIOREAD;
122 else
123 return MCFSIM2_GPIO1READ;
124#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
125 defined(CONFIG_M527x) || defined(CONFIG_M528x) || defined(CONFIG_M532x)
126 if (gpio < 8)
127 return MCFEPORT_EPPDR;
128#if defined(CONFIG_M528x)
129 else if (gpio < 16)
130 return MCFGPTA_GPTPORT;
131 else if (gpio < 24)
132 return MCFGPTB_GPTPORT;
133 else if (gpio < 32)
134 return MCFQADC_PORTQA;
135 else if (gpio < 40)
136 return MCFQADC_PORTQB;
137#endif
138 else
139 return MCFGPIO_PPDR + mcfgpio_port(gpio - MCFGPIO_SCR_START);
140#else
141 return 0;
142#endif
143}
144
145/* return the port output data register for a gpio */
146static inline u32 __mcf_gpio_podr(unsigned gpio)
147{
148#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
149 defined(CONFIG_M5307) || defined(CONFIG_M5407)
150 return MCFSIM_PADAT;
151#elif defined(CONFIG_M5272)
152 if (gpio < 16)
153 return MCFSIM_PADAT;
154 else if (gpio < 32)
155 return MCFSIM_PBDAT;
156 else
157 return MCFSIM_PCDAT;
158#elif defined(CONFIG_M5249)
159 if (gpio < 32)
160 return MCFSIM2_GPIOWRITE;
161 else
162 return MCFSIM2_GPIO1WRITE;
163#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
164 defined(CONFIG_M527x) || defined(CONFIG_M528x) || defined(CONFIG_M532x)
165 if (gpio < 8)
166 return MCFEPORT_EPDR;
167#if defined(CONFIG_M528x)
168 else if (gpio < 16)
169 return MCFGPTA_GPTPORT;
170 else if (gpio < 24)
171 return MCFGPTB_GPTPORT;
172 else if (gpio < 32)
173 return MCFQADC_PORTQA;
174 else if (gpio < 40)
175 return MCFQADC_PORTQB;
176#endif
177 else
178 return MCFGPIO_PODR + mcfgpio_port(gpio - MCFGPIO_SCR_START);
179#else
180 return 0;
181#endif
182}
183
184/* 23/*
185 * The Generic GPIO functions 24 * The Generic GPIO functions
186 * 25 *
@@ -191,7 +30,7 @@ static inline u32 __mcf_gpio_podr(unsigned gpio)
191static inline int gpio_get_value(unsigned gpio) 30static inline int gpio_get_value(unsigned gpio)
192{ 31{
193 if (__builtin_constant_p(gpio) && gpio < MCFGPIO_PIN_MAX) 32 if (__builtin_constant_p(gpio) && gpio < MCFGPIO_PIN_MAX)
194 return mcfgpio_read(__mcf_gpio_ppdr(gpio)) & mcfgpio_bit(gpio); 33 return mcfgpio_read(__mcfgpio_ppdr(gpio)) & mcfgpio_bit(gpio);
195 else 34 else
196 return __gpio_get_value(gpio); 35 return __gpio_get_value(gpio);
197} 36}
@@ -204,12 +43,12 @@ static inline void gpio_set_value(unsigned gpio, int value)
204 MCFGPIO_PORTTYPE data; 43 MCFGPIO_PORTTYPE data;
205 44
206 local_irq_save(flags); 45 local_irq_save(flags);
207 data = mcfgpio_read(__mcf_gpio_podr(gpio)); 46 data = mcfgpio_read(__mcfgpio_podr(gpio));
208 if (value) 47 if (value)
209 data |= mcfgpio_bit(gpio); 48 data |= mcfgpio_bit(gpio);
210 else 49 else
211 data &= ~mcfgpio_bit(gpio); 50 data &= ~mcfgpio_bit(gpio);
212 mcfgpio_write(data, __mcf_gpio_podr(gpio)); 51 mcfgpio_write(data, __mcfgpio_podr(gpio));
213 local_irq_restore(flags); 52 local_irq_restore(flags);
214 } else { 53 } else {
215 if (value) 54 if (value)
@@ -225,8 +64,14 @@ static inline void gpio_set_value(unsigned gpio, int value)
225 64
226static inline int gpio_to_irq(unsigned gpio) 65static inline int gpio_to_irq(unsigned gpio)
227{ 66{
228 return (gpio < MCFGPIO_IRQ_MAX) ? gpio + MCFGPIO_IRQ_VECBASE 67#if defined(MCFGPIO_IRQ_MIN)
229 : __gpio_to_irq(gpio); 68 if ((gpio >= MCFGPIO_IRQ_MIN) && (gpio < MCFGPIO_IRQ_MAX))
69#else
70 if (gpio < MCFGPIO_IRQ_MAX)
71#endif
72 return gpio + MCFGPIO_IRQ_VECBASE;
73 else
74 return __gpio_to_irq(gpio);
230} 75}
231 76
232static inline int irq_to_gpio(unsigned irq) 77static inline int irq_to_gpio(unsigned irq)
diff --git a/arch/m68k/include/asm/io_mm.h b/arch/m68k/include/asm/io_mm.h
index fa4324bcf566..a6686d26fe17 100644
--- a/arch/m68k/include/asm/io_mm.h
+++ b/arch/m68k/include/asm/io_mm.h
@@ -65,7 +65,53 @@
65 65
66 66
67 67
68#ifdef CONFIG_ISA 68#if defined(CONFIG_PCI) && defined(CONFIG_COLDFIRE)
69
70#define HAVE_ARCH_PIO_SIZE
71#define PIO_OFFSET 0
72#define PIO_MASK 0xffff
73#define PIO_RESERVED 0x10000
74
75u8 mcf_pci_inb(u32 addr);
76u16 mcf_pci_inw(u32 addr);
77u32 mcf_pci_inl(u32 addr);
78void mcf_pci_insb(u32 addr, u8 *buf, u32 len);
79void mcf_pci_insw(u32 addr, u16 *buf, u32 len);
80void mcf_pci_insl(u32 addr, u32 *buf, u32 len);
81
82void mcf_pci_outb(u8 v, u32 addr);
83void mcf_pci_outw(u16 v, u32 addr);
84void mcf_pci_outl(u32 v, u32 addr);
85void mcf_pci_outsb(u32 addr, const u8 *buf, u32 len);
86void mcf_pci_outsw(u32 addr, const u16 *buf, u32 len);
87void mcf_pci_outsl(u32 addr, const u32 *buf, u32 len);
88
89#define inb mcf_pci_inb
90#define inb_p mcf_pci_inb
91#define inw mcf_pci_inw
92#define inw_p mcf_pci_inw
93#define inl mcf_pci_inl
94#define inl_p mcf_pci_inl
95#define insb mcf_pci_insb
96#define insw mcf_pci_insw
97#define insl mcf_pci_insl
98
99#define outb mcf_pci_outb
100#define outb_p mcf_pci_outb
101#define outw mcf_pci_outw
102#define outw_p mcf_pci_outw
103#define outl mcf_pci_outl
104#define outl_p mcf_pci_outl
105#define outsb mcf_pci_outsb
106#define outsw mcf_pci_outsw
107#define outsl mcf_pci_outsl
108
109#define readb(addr) in_8(addr)
110#define writeb(v, addr) out_8((addr), (v))
111#define readw(addr) in_le16(addr)
112#define writew(v, addr) out_le16((addr), (v))
113
114#elif defined(CONFIG_ISA)
69 115
70#if MULTI_ISA == 0 116#if MULTI_ISA == 0
71#undef MULTI_ISA 117#undef MULTI_ISA
@@ -340,4 +386,6 @@ static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int
340 */ 386 */
341#define xlate_dev_kmem_ptr(p) p 387#define xlate_dev_kmem_ptr(p) p
342 388
389#define ioport_map(port, nr) ((void __iomem *)(port))
390
343#endif /* _IO_H */ 391#endif /* _IO_H */
diff --git a/arch/m68k/include/asm/m520xsim.h b/arch/m68k/include/asm/m520xsim.h
index 17f2aab9cf97..db3f8ee4a6c6 100644
--- a/arch/m68k/include/asm/m520xsim.h
+++ b/arch/m68k/include/asm/m520xsim.h
@@ -42,6 +42,9 @@
42#define MCFINTC1_SIMR (0) 42#define MCFINTC1_SIMR (0)
43#define MCFINTC1_CIMR (0) 43#define MCFINTC1_CIMR (0)
44#define MCFINTC1_ICR0 (0) 44#define MCFINTC1_ICR0 (0)
45#define MCFINTC2_SIMR (0)
46#define MCFINTC2_CIMR (0)
47#define MCFINTC2_ICR0 (0)
45 48
46#define MCFINT_VECBASE 64 49#define MCFINT_VECBASE 64
47#define MCFINT_UART0 26 /* Interrupt number for UART0 */ 50#define MCFINT_UART0 26 /* Interrupt number for UART0 */
@@ -62,6 +65,7 @@
62#define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0) 65#define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0)
63 66
64#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI) 67#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
68#define MCF_IRQ_PIT1 (MCFINT_VECBASE + MCFINT_PIT1)
65 69
66/* 70/*
67 * SDRAM configuration registers. 71 * SDRAM configuration registers.
@@ -186,5 +190,15 @@
186#define MCF_RCR_SWRESET 0x80 /* Software reset bit */ 190#define MCF_RCR_SWRESET 0x80 /* Software reset bit */
187#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */ 191#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */
188 192
193/*
194 * Power Management.
195 */
196#define MCFPM_WCR 0xfc040013
197#define MCFPM_PPMSR0 0xfc04002c
198#define MCFPM_PPMCR0 0xfc04002d
199#define MCFPM_PPMHR0 0xfc040030
200#define MCFPM_PPMLR0 0xfc040034
201#define MCFPM_LPCR 0xfc0a0007
202
189/****************************************************************************/ 203/****************************************************************************/
190#endif /* m520xsim_h */ 204#endif /* m520xsim_h */
diff --git a/arch/m68k/include/asm/m523xsim.h b/arch/m68k/include/asm/m523xsim.h
index 075062d4eecd..91d3abc3f2a5 100644
--- a/arch/m68k/include/asm/m523xsim.h
+++ b/arch/m68k/include/asm/m523xsim.h
@@ -52,6 +52,7 @@
52#define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0) 52#define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0)
53 53
54#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI) 54#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
55#define MCF_IRQ_PIT1 (MCFINT_VECBASE + MCFINT_PIT1)
55 56
56/* 57/*
57 * SDRAM configuration registers. 58 * SDRAM configuration registers.
diff --git a/arch/m68k/include/asm/m525xsim.h b/arch/m68k/include/asm/m525xsim.h
new file mode 100644
index 000000000000..6da24f653902
--- /dev/null
+++ b/arch/m68k/include/asm/m525xsim.h
@@ -0,0 +1,194 @@
1/****************************************************************************/
2
3/*
4 * m525xsim.h -- ColdFire 525x System Integration Module support.
5 *
6 * (C) Copyright 2012, Steven king <sfking@fdwdc.com>
7 * (C) Copyright 2002, Greg Ungerer (gerg@snapgear.com)
8 */
9
10/****************************************************************************/
11#ifndef m525xsim_h
12#define m525xsim_h
13/****************************************************************************/
14
15#define CPU_NAME "COLDFIRE(m525x)"
16#define CPU_INSTR_PER_JIFFY 3
17#define MCF_BUSCLK (MCF_CLK / 2)
18
19#include <asm/m52xxacr.h>
20
21/*
22 * The 525x has a second MBAR region, define its address.
23 */
24#define MCF_MBAR2 0x80000000
25
26/*
27 * Define the 525x SIM register set addresses.
28 */
29#define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */
30#define MCFSIM_SYPCR 0x01 /* System Protection reg (r/w)*/
31#define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */
32#define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */
33#define MCFSIM_MPARK 0x0C /* BUS Master Control Reg*/
34#define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */
35#define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */
36#define MCFSIM_ICR0 0x4c /* Intr Ctrl reg 0 (r/w) */
37#define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */
38#define MCFSIM_ICR2 0x4e /* Intr Ctrl reg 2 (r/w) */
39#define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */
40#define MCFSIM_ICR4 0x50 /* Intr Ctrl reg 4 (r/w) */
41#define MCFSIM_ICR5 0x51 /* Intr Ctrl reg 5 (r/w) */
42#define MCFSIM_ICR6 0x52 /* Intr Ctrl reg 6 (r/w) */
43#define MCFSIM_ICR7 0x53 /* Intr Ctrl reg 7 (r/w) */
44#define MCFSIM_ICR8 0x54 /* Intr Ctrl reg 8 (r/w) */
45#define MCFSIM_ICR9 0x55 /* Intr Ctrl reg 9 (r/w) */
46#define MCFSIM_ICR10 0x56 /* Intr Ctrl reg 10 (r/w) */
47#define MCFSIM_ICR11 0x57 /* Intr Ctrl reg 11 (r/w) */
48
49#define MCFSIM_CSAR0 0x80 /* CS 0 Address 0 reg (r/w) */
50#define MCFSIM_CSMR0 0x84 /* CS 0 Mask 0 reg (r/w) */
51#define MCFSIM_CSCR0 0x8a /* CS 0 Control reg (r/w) */
52#define MCFSIM_CSAR1 0x8c /* CS 1 Address reg (r/w) */
53#define MCFSIM_CSMR1 0x90 /* CS 1 Mask reg (r/w) */
54#define MCFSIM_CSCR1 0x96 /* CS 1 Control reg (r/w) */
55#define MCFSIM_CSAR2 0x98 /* CS 2 Address reg (r/w) */
56#define MCFSIM_CSMR2 0x9c /* CS 2 Mask reg (r/w) */
57#define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */
58#define MCFSIM_CSAR3 0xa4 /* CS 3 Address reg (r/w) */
59#define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */
60#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */
61#define MCFSIM_CSAR4 0xb0 /* CS 4 Address reg (r/w) */
62#define MCFSIM_CSMR4 0xb4 /* CS 4 Mask reg (r/w) */
63#define MCFSIM_CSCR4 0xba /* CS 4 Control reg (r/w) */
64
65#define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */
66#define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM 0 Addr/Ctrl */
67#define MCFSIM_DMR0 (MCF_MBAR + 0x10c) /* DRAM 0 Mask */
68
69/*
70 * Secondary Interrupt Controller (in MBAR2)
71*/
72#define MCFINTC2_INTBASE (MCF_MBAR2 + 0x168) /* Base Vector Reg */
73#define MCFINTC2_INTPRI1 (MCF_MBAR2 + 0x140) /* 0-7 priority */
74#define MCFINTC2_INTPRI2 (MCF_MBAR2 + 0x144) /* 8-15 priority */
75#define MCFINTC2_INTPRI3 (MCF_MBAR2 + 0x148) /* 16-23 priority */
76#define MCFINTC2_INTPRI4 (MCF_MBAR2 + 0x14c) /* 24-31 priority */
77#define MCFINTC2_INTPRI5 (MCF_MBAR2 + 0x150) /* 32-39 priority */
78#define MCFINTC2_INTPRI6 (MCF_MBAR2 + 0x154) /* 40-47 priority */
79#define MCFINTC2_INTPRI7 (MCF_MBAR2 + 0x158) /* 48-55 priority */
80#define MCFINTC2_INTPRI8 (MCF_MBAR2 + 0x15c) /* 56-63 priority */
81
82#define MCFINTC2_INTPRI_REG(i) (MCFINTC2_INTPRI1 + \
83 ((((i) - MCFINTC2_VECBASE) / 8) * 4))
84#define MCFINTC2_INTPRI_BITS(b, i) ((b) << (((i) % 8) * 4))
85
86/*
87 * Timer module.
88 */
89#define MCFTIMER_BASE1 (MCF_MBAR + 0x140) /* Base of TIMER1 */
90#define MCFTIMER_BASE2 (MCF_MBAR + 0x180) /* Base of TIMER2 */
91
92/*
93 * UART module.
94 */
95#define MCFUART_BASE0 (MCF_MBAR + 0x1c0) /* Base address UART0 */
96#define MCFUART_BASE1 (MCF_MBAR + 0x200) /* Base address UART1 */
97
98/*
99 * QSPI module.
100 */
101#define MCFQSPI_BASE (MCF_MBAR + 0x300) /* Base address QSPI */
102#define MCFQSPI_SIZE 0x40 /* Register set size */
103
104
105#define MCFQSPI_CS0 15
106#define MCFQSPI_CS1 16
107#define MCFQSPI_CS2 24
108#define MCFQSPI_CS3 28
109
110/*
111 * I2C module.
112 */
113#define MCFI2C_BASE0 (MCF_MBAR + 0x280) /* Base addreess I2C0 */
114#define MCFI2C_SIZE0 0x20 /* Register set size */
115
116#define MCFI2C_BASE1 (MCF_MBAR2 + 0x440) /* Base addreess I2C1 */
117#define MCFI2C_SIZE1 0x20 /* Register set size */
118/*
119 * DMA unit base addresses.
120 */
121#define MCFDMA_BASE0 (MCF_MBAR + 0x300) /* Base address DMA 0 */
122#define MCFDMA_BASE1 (MCF_MBAR + 0x340) /* Base address DMA 1 */
123#define MCFDMA_BASE2 (MCF_MBAR + 0x380) /* Base address DMA 2 */
124#define MCFDMA_BASE3 (MCF_MBAR + 0x3C0) /* Base address DMA 3 */
125
126/*
127 * Some symbol defines for the above...
128 */
129#define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */
130#define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */
131#define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */
132#define MCFSIM_I2CICR MCFSIM_ICR3 /* I2C ICR */
133#define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */
134#define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */
135#define MCFSIM_DMA0ICR MCFSIM_ICR6 /* DMA 0 ICR */
136#define MCFSIM_DMA1ICR MCFSIM_ICR7 /* DMA 1 ICR */
137#define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */
138#define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */
139#define MCFSIM_QSPIICR MCFSIM_ICR10 /* QSPI ICR */
140
141/*
142 * Define system peripheral IRQ usage.
143 */
144#define MCF_IRQ_QSPI 28 /* QSPI, Level 4 */
145#define MCF_IRQ_I2C0 29
146#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */
147#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */
148
149#define MCF_IRQ_UART0 73 /* UART0 */
150#define MCF_IRQ_UART1 74 /* UART1 */
151
152/*
153 * Define the base interrupt for the second interrupt controller.
154 * We set it to 128, out of the way of the base interrupts, and plenty
155 * of room for its 64 interrupts.
156 */
157#define MCFINTC2_VECBASE 128
158
159#define MCF_IRQ_GPIO0 (MCFINTC2_VECBASE + 32)
160#define MCF_IRQ_GPIO1 (MCFINTC2_VECBASE + 33)
161#define MCF_IRQ_GPIO2 (MCFINTC2_VECBASE + 34)
162#define MCF_IRQ_GPIO3 (MCFINTC2_VECBASE + 35)
163#define MCF_IRQ_GPIO4 (MCFINTC2_VECBASE + 36)
164#define MCF_IRQ_GPIO5 (MCFINTC2_VECBASE + 37)
165#define MCF_IRQ_GPIO6 (MCFINTC2_VECBASE + 38)
166
167#define MCF_IRQ_USBWUP (MCFINTC2_VECBASE + 40)
168#define MCF_IRQ_I2C1 (MCFINTC2_VECBASE + 62)
169
170/*
171 * General purpose IO registers (in MBAR2).
172 */
173#define MCFSIM2_GPIOREAD (MCF_MBAR2 + 0x000) /* GPIO read values */
174#define MCFSIM2_GPIOWRITE (MCF_MBAR2 + 0x004) /* GPIO write values */
175#define MCFSIM2_GPIOENABLE (MCF_MBAR2 + 0x008) /* GPIO enabled */
176#define MCFSIM2_GPIOFUNC (MCF_MBAR2 + 0x00C) /* GPIO function */
177#define MCFSIM2_GPIO1READ (MCF_MBAR2 + 0x0B0) /* GPIO1 read values */
178#define MCFSIM2_GPIO1WRITE (MCF_MBAR2 + 0x0B4) /* GPIO1 write values */
179#define MCFSIM2_GPIO1ENABLE (MCF_MBAR2 + 0x0B8) /* GPIO1 enabled */
180#define MCFSIM2_GPIO1FUNC (MCF_MBAR2 + 0x0BC) /* GPIO1 function */
181
182#define MCFSIM2_GPIOINTSTAT (MCF_MBAR2 + 0xc0) /* GPIO intr status */
183#define MCFSIM2_GPIOINTCLEAR (MCF_MBAR2 + 0xc0) /* GPIO intr clear */
184#define MCFSIM2_GPIOINTENABLE (MCF_MBAR2 + 0xc4) /* GPIO intr enable */
185
186/*
187 * Generic GPIO support
188 */
189#define MCFGPIO_PIN_MAX 64
190#define MCFGPIO_IRQ_MAX 7
191#define MCFGPIO_IRQ_VECBASE MCF_IRQ_GPIO0
192
193/****************************************************************************/
194#endif /* m525xsim_h */
diff --git a/arch/m68k/include/asm/m527xsim.h b/arch/m68k/include/asm/m527xsim.h
index 83db8106f50a..71aa5104d3d6 100644
--- a/arch/m68k/include/asm/m527xsim.h
+++ b/arch/m68k/include/asm/m527xsim.h
@@ -60,6 +60,7 @@
60#define MCF_IRQ_FECENTC1 (MCFINT2_VECBASE + MCFINT2_FECENTC1) 60#define MCF_IRQ_FECENTC1 (MCFINT2_VECBASE + MCFINT2_FECENTC1)
61 61
62#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI) 62#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
63#define MCF_IRQ_PIT1 (MCFINT_VECBASE + MCFINT_PIT1)
63 64
64/* 65/*
65 * SDRAM configuration registers. 66 * SDRAM configuration registers.
diff --git a/arch/m68k/include/asm/m528xsim.h b/arch/m68k/include/asm/m528xsim.h
index 497c31c803ff..4acb3c0a642e 100644
--- a/arch/m68k/include/asm/m528xsim.h
+++ b/arch/m68k/include/asm/m528xsim.h
@@ -52,7 +52,7 @@
52#define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0) 52#define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0)
53 53
54#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI) 54#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
55 55#define MCF_IRQ_PIT1 (MCFINT_VECBASE + MCFINT_PIT1)
56/* 56/*
57 * SDRAM configuration registers. 57 * SDRAM configuration registers.
58 */ 58 */
diff --git a/arch/m68k/include/asm/m532xsim.h b/arch/m68k/include/asm/m532xsim.h
index 29b66e21413a..5ca7b298c6eb 100644
--- a/arch/m68k/include/asm/m532xsim.h
+++ b/arch/m68k/include/asm/m532xsim.h
@@ -82,6 +82,9 @@
82#define MCFINTC1_SIMR 0xFC04C01C 82#define MCFINTC1_SIMR 0xFC04C01C
83#define MCFINTC1_CIMR 0xFC04C01D 83#define MCFINTC1_CIMR 0xFC04C01D
84#define MCFINTC1_ICR0 0xFC04C040 84#define MCFINTC1_ICR0 0xFC04C040
85#define MCFINTC2_SIMR (0)
86#define MCFINTC2_CIMR (0)
87#define MCFINTC2_ICR0 (0)
85 88
86#define MCFSIM_ICR_TIMER1 (0xFC048040+32) 89#define MCFSIM_ICR_TIMER1 (0xFC048040+32)
87#define MCFSIM_ICR_TIMER2 (0xFC048040+33) 90#define MCFSIM_ICR_TIMER2 (0xFC048040+33)
@@ -135,6 +138,20 @@
135#define MCF_RCR_SWRESET 0x80 /* Software reset bit */ 138#define MCF_RCR_SWRESET 0x80 /* Software reset bit */
136#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */ 139#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */
137 140
141
142/*
143 * Power Management
144 */
145#define MCFPM_WCR 0xfc040013
146#define MCFPM_PPMSR0 0xfc04002c
147#define MCFPM_PPMCR0 0xfc04002d
148#define MCFPM_PPMSR1 0xfc04002e
149#define MCFPM_PPMCR1 0xfc04002f
150#define MCFPM_PPMHR0 0xfc040030
151#define MCFPM_PPMLR0 0xfc040034
152#define MCFPM_PPMHR1 0xfc040038
153#define MCFPM_LPCR 0xec090007
154
138/********************************************************************* 155/*********************************************************************
139 * 156 *
140 * Inter-IC (I2C) Module 157 * Inter-IC (I2C) Module
diff --git a/arch/m68k/include/asm/m5441xsim.h b/arch/m68k/include/asm/m5441xsim.h
new file mode 100644
index 000000000000..cc798ab9524b
--- /dev/null
+++ b/arch/m68k/include/asm/m5441xsim.h
@@ -0,0 +1,276 @@
1/*
2 * m5441xsim.h -- Coldfire 5441x register definitions
3 *
4 * (C) Copyright 2012, Steven King <sfking@fdwdc.com>
5*/
6
7#ifndef m5441xsim_h
8#define m5441xsim_h
9
10#define CPU_NAME "COLDFIRE(m5441x)"
11#define CPU_INSTR_PER_JIFFY 2
12#define MCF_BUSCLK (MCF_CLK / 2)
13
14#include <asm/m54xxacr.h>
15
16/*
17 * Reset Controller Module.
18 */
19
20#define MCF_RCR 0xec090000
21#define MCF_RSR 0xec090001
22
23#define MCF_RCR_SWRESET 0x80 /* Software reset bit */
24#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */
25
26/*
27 * Interrupt Controller Modules.
28 */
29/* the 5441x have 3 interrupt controllers, each control 64 interrupts */
30#define MCFINT_VECBASE 64
31#define MCFINT0_VECBASE MCFINT_VECBASE
32#define MCFINT1_VECBASE (MCFINT0_VECBASE + 64)
33#define MCFINT2_VECBASE (MCFINT1_VECBASE + 64)
34
35/* interrupt controller 0 */
36#define MCFINTC0_SIMR 0xfc04801c
37#define MCFINTC0_CIMR 0xfc04801d
38#define MCFINTC0_ICR0 0xfc048040
39/* interrupt controller 1 */
40#define MCFINTC1_SIMR 0xfc04c01c
41#define MCFINTC1_CIMR 0xfc04c01d
42#define MCFINTC1_ICR0 0xfc04c040
43/* interrupt controller 2 */
44#define MCFINTC2_SIMR 0xfc05001c
45#define MCFINTC2_CIMR 0xfc05001d
46#define MCFINTC2_ICR0 0xfc050040
47
48/* on interrupt controller 0 */
49#define MCFINT0_EPORT0 1
50#define MCFINT0_UART0 26
51#define MCFINT0_UART1 27
52#define MCFINT0_UART2 28
53#define MCFINT0_UART3 29
54#define MCFINT0_I2C0 30
55#define MCFINT0_DSPI0 31
56
57#define MCFINT0_TIMER0 32
58#define MCFINT0_TIMER1 33
59#define MCFINT0_TIMER2 34
60#define MCFINT0_TIMER3 35
61
62#define MCFINT0_FECRX0 36
63#define MCFINT0_FECTX0 40
64#define MCFINT0_FECENTC0 42
65
66#define MCFINT0_FECRX1 49
67#define MCFINT0_FECTX1 53
68#define MCFINT0_FECENTC1 55
69
70/* on interrupt controller 1 */
71#define MCFINT1_UART4 48
72#define MCFINT1_UART5 49
73#define MCFINT1_UART6 50
74#define MCFINT1_UART7 51
75#define MCFINT1_UART8 52
76#define MCFINT1_UART9 53
77#define MCFINT1_DSPI1 54
78#define MCFINT1_DSPI2 55
79#define MCFINT1_DSPI3 56
80#define MCFINT1_I2C1 57
81#define MCFINT1_I2C2 58
82#define MCFINT1_I2C3 59
83#define MCFINT1_I2C4 60
84#define MCFINT1_I2C5 61
85
86/* on interrupt controller 2 */
87#define MCFINT2_PIT0 13
88#define MCFINT2_PIT1 14
89#define MCFINT2_PIT2 15
90#define MCFINT2_PIT3 16
91#define MCFINT2_RTC 26
92
93/*
94 * PIT timer module.
95 */
96#define MCFPIT_BASE0 0xFC080000 /* Base address of TIMER0 */
97#define MCFPIT_BASE1 0xFC084000 /* Base address of TIMER1 */
98#define MCFPIT_BASE2 0xFC088000 /* Base address of TIMER2 */
99#define MCFPIT_BASE3 0xFC08C000 /* Base address of TIMER3 */
100
101
102#define MCF_IRQ_PIT1 (MCFINT2_VECBASE + MCFINT2_PIT1)
103
104/*
105 * Power Management
106 */
107#define MCFPM_WCR 0xfc040013
108#define MCFPM_PPMSR0 0xfc04002c
109#define MCFPM_PPMCR0 0xfc04002d
110#define MCFPM_PPMSR1 0xfc04002e
111#define MCFPM_PPMCR1 0xfc04002f
112#define MCFPM_PPMHR0 0xfc040030
113#define MCFPM_PPMLR0 0xfc040034
114#define MCFPM_PPMHR1 0xfc040038
115#define MCFPM_PPMLR1 0xfc04003c
116#define MCFPM_LPCR 0xec090007
117/*
118 * UART module.
119 */
120#define MCFUART_BASE0 0xfc060000 /* Base address of UART0 */
121#define MCFUART_BASE1 0xfc064000 /* Base address of UART1 */
122#define MCFUART_BASE2 0xfc068000 /* Base address of UART2 */
123#define MCFUART_BASE3 0xfc06c000 /* Base address of UART3 */
124#define MCFUART_BASE4 0xec060000 /* Base address of UART4 */
125#define MCFUART_BASE5 0xec064000 /* Base address of UART5 */
126#define MCFUART_BASE6 0xec068000 /* Base address of UART6 */
127#define MCFUART_BASE7 0xec06c000 /* Base address of UART7 */
128#define MCFUART_BASE8 0xec070000 /* Base address of UART8 */
129#define MCFUART_BASE9 0xec074000 /* Base address of UART9 */
130
131#define MCF_IRQ_UART0 (MCFINT0_VECBASE + MCFINT0_UART0)
132#define MCF_IRQ_UART1 (MCFINT0_VECBASE + MCFINT0_UART1)
133#define MCF_IRQ_UART2 (MCFINT0_VECBASE + MCFINT0_UART2)
134#define MCF_IRQ_UART3 (MCFINT0_VECBASE + MCFINT0_UART3)
135#define MCF_IRQ_UART4 (MCFINT1_VECBASE + MCFINT1_UART4)
136#define MCF_IRQ_UART5 (MCFINT1_VECBASE + MCFINT1_UART5)
137#define MCF_IRQ_UART6 (MCFINT1_VECBASE + MCFINT1_UART6)
138#define MCF_IRQ_UART7 (MCFINT1_VECBASE + MCFINT1_UART7)
139#define MCF_IRQ_UART8 (MCFINT1_VECBASE + MCFINT1_UART8)
140#define MCF_IRQ_UART9 (MCFINT1_VECBASE + MCFINT1_UART9)
141/*
142 * FEC modules.
143 */
144#define MCFFEC_BASE0 0xfc0d4000
145#define MCFFEC_SIZE0 0x800
146#define MCF_IRQ_FECRX0 (MCFINT0_VECBASE + MCFINT0_FECRX0)
147#define MCF_IRQ_FECTX0 (MCFINT0_VECBASE + MCFINT0_FECTX0)
148#define MCF_IRQ_FECENTC0 (MCFINT0_VECBASE + MCFINT0_FECENTC0)
149
150#define MCFFEC_BASE1 0xfc0d8000
151#define MCFFEC_SIZE1 0x800
152#define MCF_IRQ_FECRX1 (MCFINT0_VECBASE + MCFINT0_FECRX1)
153#define MCF_IRQ_FECTX1 (MCFINT0_VECBASE + MCFINT0_FECTX1)
154#define MCF_IRQ_FECENTC1 (MCFINT0_VECBASE + MCFINT0_FECENTC1)
155/*
156 * I2C modules.
157 */
158#define MCFI2C_BASE0 0xfc058000
159#define MCFI2C_SIZE0 0x20
160#define MCFI2C_BASE1 0xfc038000
161#define MCFI2C_SIZE1 0x20
162#define MCFI2C_BASE2 0xec010000
163#define MCFI2C_SIZE2 0x20
164#define MCFI2C_BASE3 0xec014000
165#define MCFI2C_SIZE3 0x20
166#define MCFI2C_BASE4 0xec018000
167#define MCFI2C_SIZE4 0x20
168#define MCFI2C_BASE5 0xec01c000
169#define MCFI2C_SIZE5 0x20
170
171#define MCF_IRQ_I2C0 (MCFINT0_VECBASE + MCFINT0_I2C0)
172#define MCF_IRQ_I2C1 (MCFINT1_VECBASE + MCFINT1_I2C1)
173#define MCF_IRQ_I2C2 (MCFINT1_VECBASE + MCFINT1_I2C2)
174#define MCF_IRQ_I2C3 (MCFINT1_VECBASE + MCFINT1_I2C3)
175#define MCF_IRQ_I2C4 (MCFINT1_VECBASE + MCFINT1_I2C4)
176#define MCF_IRQ_I2C5 (MCFINT1_VECBASE + MCFINT1_I2C5)
177/*
178 * EPORT Module.
179 */
180#define MCFEPORT_EPPAR 0xfc090000
181#define MCFEPORT_EPIER 0xfc090003
182#define MCFEPORT_EPFR 0xfc090006
183/*
184 * RTC Module.
185 */
186#define MCFRTC_BASE 0xfc0a8000
187#define MCFRTC_SIZE (0xfc0a8840 - 0xfc0a8000)
188#define MCF_IRQ_RTC (MCFINT2_VECBASE + MCFINT2_RTC)
189
190/*
191 * GPIO Module.
192 */
193#define MCFGPIO_PODR_A 0xec094000
194#define MCFGPIO_PODR_B 0xec094001
195#define MCFGPIO_PODR_C 0xec094002
196#define MCFGPIO_PODR_D 0xec094003
197#define MCFGPIO_PODR_E 0xec094004
198#define MCFGPIO_PODR_F 0xec094005
199#define MCFGPIO_PODR_G 0xec094006
200#define MCFGPIO_PODR_H 0xec094007
201#define MCFGPIO_PODR_I 0xec094008
202#define MCFGPIO_PODR_J 0xec094009
203#define MCFGPIO_PODR_K 0xec09400a
204
205#define MCFGPIO_PDDR_A 0xec09400c
206#define MCFGPIO_PDDR_B 0xec09400d
207#define MCFGPIO_PDDR_C 0xec09400e
208#define MCFGPIO_PDDR_D 0xec09400f
209#define MCFGPIO_PDDR_E 0xec094010
210#define MCFGPIO_PDDR_F 0xec094011
211#define MCFGPIO_PDDR_G 0xec094012
212#define MCFGPIO_PDDR_H 0xec094013
213#define MCFGPIO_PDDR_I 0xec094014
214#define MCFGPIO_PDDR_J 0xec094015
215#define MCFGPIO_PDDR_K 0xec094016
216
217#define MCFGPIO_PPDSDR_A 0xec094018
218#define MCFGPIO_PPDSDR_B 0xec094019
219#define MCFGPIO_PPDSDR_C 0xec09401a
220#define MCFGPIO_PPDSDR_D 0xec09401b
221#define MCFGPIO_PPDSDR_E 0xec09401c
222#define MCFGPIO_PPDSDR_F 0xec09401d
223#define MCFGPIO_PPDSDR_G 0xec09401e
224#define MCFGPIO_PPDSDR_H 0xec09401f
225#define MCFGPIO_PPDSDR_I 0xec094020
226#define MCFGPIO_PPDSDR_J 0xec094021
227#define MCFGPIO_PPDSDR_K 0xec094022
228
229#define MCFGPIO_PCLRR_A 0xec094024
230#define MCFGPIO_PCLRR_B 0xec094025
231#define MCFGPIO_PCLRR_C 0xec094026
232#define MCFGPIO_PCLRR_D 0xec094027
233#define MCFGPIO_PCLRR_E 0xec094028
234#define MCFGPIO_PCLRR_F 0xec094029
235#define MCFGPIO_PCLRR_G 0xec09402a
236#define MCFGPIO_PCLRR_H 0xec09402b
237#define MCFGPIO_PCLRR_I 0xec09402c
238#define MCFGPIO_PCLRR_J 0xec09402d
239#define MCFGPIO_PCLRR_K 0xec09402e
240
241#define MCFGPIO_PAR_FBCTL 0xec094048
242#define MCFGPIO_PAR_BE 0xec094049
243#define MCFGPIO_PAR_CS 0xec09404a
244#define MCFGPIO_PAR_CANI2C 0xec09404b
245#define MCFGPIO_PAR_IRQ0H 0xec09404c
246#define MCFGPIO_PAR_IRQ0L 0xec09404d
247#define MCFGPIO_PAR_DSPIOWH 0xec09404e
248#define MCFGPIO_PAR_DSPIOWL 0xec09404f
249#define MCFGPIO_PAR_TIMER 0xec094050
250#define MCFGPIO_PAR_UART2 0xec094051
251#define MCFGPIO_PAR_UART1 0xec094052
252#define MCFGPIO_PAR_UART0 0xec094053
253#define MCFGPIO_PAR_SDHCH 0xec094054
254#define MCFGPIO_PAR_SDHCL 0xec094055
255#define MCFGPIO_PAR_SIMP0H 0xec094056
256#define MCFGPIO_PAR_SIMP0L 0xec094057
257#define MCFGPIO_PAR_SSI0H 0xec094058
258#define MCFGPIO_PAR_SSI0L 0xec094059
259#define MCFGPIO_PAR_DEBUGH1 0xec09405a
260#define MCFGPIO_PAR_DEBUGH0 0xec09405b
261#define MCFGPIO_PAR_DEBUGl 0xec09405c
262#define MCFGPIO_PAR_FEC 0xec09405e
263
264/* generalization for generic gpio support */
265#define MCFGPIO_PODR MCFGPIO_PODR_A
266#define MCFGPIO_PDDR MCFGPIO_PDDR_A
267#define MCFGPIO_PPDR MCFGPIO_PPDSDR_A
268#define MCFGPIO_SETR MCFGPIO_PPDSDR_A
269#define MCFGPIO_CLRR MCFGPIO_PCLRR_A
270
271#define MCFGPIO_IRQ_MIN 17
272#define MCFGPIO_IRQ_MAX 24
273#define MCFGPIO_IRQ_VECBASE (MCFINT_VECBASE - MCFGPIO_IRQ_MIN)
274#define MCFGPIO_PIN_MAX 87
275
276#endif /* m5441xsim_h */
diff --git a/arch/m68k/include/asm/m54xxacr.h b/arch/m68k/include/asm/m54xxacr.h
index 47906aafbf67..192bbfeabf70 100644
--- a/arch/m68k/include/asm/m54xxacr.h
+++ b/arch/m68k/include/asm/m54xxacr.h
@@ -55,6 +55,10 @@
55#define ICACHE_SIZE 0x8000 /* instruction - 32k */ 55#define ICACHE_SIZE 0x8000 /* instruction - 32k */
56#define DCACHE_SIZE 0x8000 /* data - 32k */ 56#define DCACHE_SIZE 0x8000 /* data - 32k */
57 57
58#elif defined(CONFIG_M5441x)
59
60#define ICACHE_SIZE 0x2000 /* instruction - 8k */
61#define DCACHE_SIZE 0x2000 /* data - 8k */
58#endif 62#endif
59 63
60#define CACHE_LINE_SIZE 0x0010 /* 16 bytes */ 64#define CACHE_LINE_SIZE 0x0010 /* 16 bytes */
diff --git a/arch/m68k/include/asm/m54xxpci.h b/arch/m68k/include/asm/m54xxpci.h
new file mode 100644
index 000000000000..6fbf54f72f2e
--- /dev/null
+++ b/arch/m68k/include/asm/m54xxpci.h
@@ -0,0 +1,138 @@
1/****************************************************************************/
2
3/*
4 * m54xxpci.h -- ColdFire 547x and 548x PCI bus support
5 *
6 * (C) Copyright 2011, Greg Ungerer <gerg@uclinux.org>
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file COPYING in the main directory of this archive
10 * for more details.
11 */
12
13/****************************************************************************/
14#ifndef M54XXPCI_H
15#define M54XXPCI_H
16/****************************************************************************/
17
18/*
19 * The core set of PCI support registers are mapped into the MBAR region.
20 */
21#define PCIIDR (CONFIG_MBAR + 0xb00) /* PCI device/vendor ID */
22#define PCISCR (CONFIG_MBAR + 0xb04) /* PCI status/command */
23#define PCICCRIR (CONFIG_MBAR + 0xb08) /* PCI class/revision */
24#define PCICR1 (CONFIG_MBAR + 0xb0c) /* PCI configuration 1 */
25#define PCIBAR0 (CONFIG_MBAR + 0xb10) /* PCI base address 0 */
26#define PCIBAR1 (CONFIG_MBAR + 0xb14) /* PCI base address 1 */
27#define PCICCPR (CONFIG_MBAR + 0xb28) /* PCI cardbus CIS pointer */
28#define PCISID (CONFIG_MBAR + 0xb2c) /* PCI subsystem IDs */
29#define PCIERBAR (CONFIG_MBAR + 0xb30) /* PCI expansion ROM */
30#define PCICPR (CONFIG_MBAR + 0xb34) /* PCI capabilities pointer */
31#define PCICR2 (CONFIG_MBAR + 0xb3c) /* PCI configuration 2 */
32
33#define PCIGSCR (CONFIG_MBAR + 0xb60) /* Global status/control */
34#define PCITBATR0 (CONFIG_MBAR + 0xb64) /* Target base translation 0 */
35#define PCITBATR1 (CONFIG_MBAR + 0xb68) /* Target base translation 1 */
36#define PCITCR (CONFIG_MBAR + 0xb6c) /* Target control */
37#define PCIIW0BTAR (CONFIG_MBAR + 0xb70) /* Initiator window 0 */
38#define PCIIW1BTAR (CONFIG_MBAR + 0xb74) /* Initiator window 1 */
39#define PCIIW2BTAR (CONFIG_MBAR + 0xb78) /* Initiator window 2 */
40#define PCIIWCR (CONFIG_MBAR + 0xb80) /* Initiator window config */
41#define PCIICR (CONFIG_MBAR + 0xb84) /* Initiator control */
42#define PCIISR (CONFIG_MBAR + 0xb88) /* Initiator status */
43#define PCICAR (CONFIG_MBAR + 0xbf8) /* Configuration address */
44
45#define PCITPSR (CONFIG_MBAR + 0x8400) /* TX packet size */
46#define PCITSAR (CONFIG_MBAR + 0x8404) /* TX start address */
47#define PCITTCR (CONFIG_MBAR + 0x8408) /* TX transaction control */
48#define PCITER (CONFIG_MBAR + 0x840c) /* TX enables */
49#define PCITNAR (CONFIG_MBAR + 0x8410) /* TX next address */
50#define PCITLWR (CONFIG_MBAR + 0x8414) /* TX last word */
51#define PCITDCR (CONFIG_MBAR + 0x8418) /* TX done counts */
52#define PCITSR (CONFIG_MBAR + 0x841c) /* TX status */
53#define PCITFDR (CONFIG_MBAR + 0x8440) /* TX FIFO data */
54#define PCITFSR (CONFIG_MBAR + 0x8444) /* TX FIFO status */
55#define PCITFCR (CONFIG_MBAR + 0x8448) /* TX FIFO control */
56#define PCITFAR (CONFIG_MBAR + 0x844c) /* TX FIFO alarm */
57#define PCITFRPR (CONFIG_MBAR + 0x8450) /* TX FIFO read pointer */
58#define PCITFWPR (CONFIG_MBAR + 0x8454) /* TX FIFO write pointer */
59
60#define PCIRPSR (CONFIG_MBAR + 0x8480) /* RX packet size */
61#define PCIRSAR (CONFIG_MBAR + 0x8484) /* RX start address */
62#define PCIRTCR (CONFIG_MBAR + 0x8488) /* RX transaction control */
63#define PCIRER (CONFIG_MBAR + 0x848c) /* RX enables */
64#define PCIRNAR (CONFIG_MBAR + 0x8490) /* RX next address */
65#define PCIRDCR (CONFIG_MBAR + 0x8498) /* RX done counts */
66#define PCIRSR (CONFIG_MBAR + 0x849c) /* RX status */
67#define PCIRFDR (CONFIG_MBAR + 0x84c0) /* RX FIFO data */
68#define PCIRFSR (CONFIG_MBAR + 0x84c4) /* RX FIFO status */
69#define PCIRFCR (CONFIG_MBAR + 0x84c8) /* RX FIFO control */
70#define PCIRFAR (CONFIG_MBAR + 0x84cc) /* RX FIFO alarm */
71#define PCIRFRPR (CONFIG_MBAR + 0x84d0) /* RX FIFO read pointer */
72#define PCIRFWPR (CONFIG_MBAR + 0x84d4) /* RX FIFO write pointer */
73
74#define PACR (CONFIG_MBAR + 0xc00) /* PCI arbiter control */
75#define PASR (COFNIG_MBAR + 0xc04) /* PCI arbiter status */
76
77/*
78 * Definitions for the Global status and control register.
79 */
80#define PCIGSCR_PE 0x20000000 /* Parity error detected */
81#define PCIGSCR_SE 0x10000000 /* System error detected */
82#define PCIGSCR_XCLKBIN 0x07000000 /* XLB2CLKIN mask */
83#define PCIGSCR_PEE 0x00002000 /* Parity error intr enable */
84#define PCIGSCR_SEE 0x00001000 /* System error intr enable */
85#define PCIGSCR_RESET 0x00000001 /* Reset bit */
86
87/*
88 * Bit definitions for the PCICAR configuration address register.
89 */
90#define PCICAR_E 0x80000000 /* Enable config space */
91#define PCICAR_BUSN 16 /* Move bus bits */
92#define PCICAR_DEVFNN 8 /* Move devfn bits */
93#define PCICAR_DWORDN 0 /* Move dword bits */
94
95/*
96 * The initiator windows hold the memory and IO mapping information.
97 * This macro creates the register values from the desired addresses.
98 */
99#define WXBTAR(hostaddr, pciaddr, size) \
100 (((hostaddr) & 0xff000000) | \
101 ((((size) - 1) & 0xff000000) >> 8) | \
102 (((pciaddr) & 0xff000000) >> 16))
103
104#define PCIIWCR_W0_MEM 0x00000000 /* Window 0 is memory */
105#define PCIIWCR_W0_IO 0x08000000 /* Window 0 is IO */
106#define PCIIWCR_W0_MRD 0x00000000 /* Window 0 memory read */
107#define PCIIWCR_W0_MRDL 0x02000000 /* Window 0 memory read line */
108#define PCIIWCR_W0_MRDM 0x04000000 /* Window 0 memory read mult */
109#define PCIIWCR_W0_E 0x01000000 /* Window 0 enable */
110
111#define PCIIWCR_W1_MEM 0x00000000 /* Window 0 is memory */
112#define PCIIWCR_W1_IO 0x00080000 /* Window 0 is IO */
113#define PCIIWCR_W1_MRD 0x00000000 /* Window 0 memory read */
114#define PCIIWCR_W1_MRDL 0x00020000 /* Window 0 memory read line */
115#define PCIIWCR_W1_MRDM 0x00040000 /* Window 0 memory read mult */
116#define PCIIWCR_W1_E 0x00010000 /* Window 0 enable */
117
118/*
119 * Bit definitions for the PCIBATR registers.
120 */
121#define PCITBATR0_E 0x00000001 /* Enable window 0 */
122#define PCITBATR1_E 0x00000001 /* Enable window 1 */
123
124/*
125 * PCI arbiter support definitions and macros.
126 */
127#define PACR_INTMPRI 0x00000001
128#define PACR_EXTMPRI(x) (((x) & 0x1f) << 1)
129#define PACR_INTMINTE 0x00010000
130#define PACR_EXTMINTE(x) (((x) & 0x1f) << 17)
131#define PACR_PKMD 0x40000000
132#define PACR_DS 0x80000000
133
134#define PCICR1_CL(x) ((x) & 0xf) /* Cacheline size field */
135#define PCICR1_LT(x) (((x) & 0xff) << 8) /* Latency timer field */
136
137/****************************************************************************/
138#endif /* M54XXPCI_H */
diff --git a/arch/m68k/include/asm/m54xxsim.h b/arch/m68k/include/asm/m54xxsim.h
index ae56b8848a9d..d3c5e0dbdadf 100644
--- a/arch/m68k/include/asm/m54xxsim.h
+++ b/arch/m68k/include/asm/m54xxsim.h
@@ -81,4 +81,7 @@
81#define MCF_PAR_PSC_RTS_RTS (0x30) 81#define MCF_PAR_PSC_RTS_RTS (0x30)
82#define MCF_PAR_PSC_CANRX (0x40) 82#define MCF_PAR_PSC_CANRX (0x40)
83 83
84#define MCF_PAR_PCIBG (CONFIG_MBAR + 0xa48) /* PCI bus grant */
85#define MCF_PAR_PCIBR (CONFIG_MBAR + 0xa4a) /* PCI */
86
84#endif /* m54xxsim_h */ 87#endif /* m54xxsim_h */
diff --git a/arch/m68k/include/asm/mcfne.h b/arch/m68k/include/asm/mcf8390.h
index bf638be0958c..a72a20819a54 100644
--- a/arch/m68k/include/asm/mcfne.h
+++ b/arch/m68k/include/asm/mcf8390.h
@@ -1,7 +1,7 @@
1/****************************************************************************/ 1/****************************************************************************/
2 2
3/* 3/*
4 * mcfne.h -- NE2000 in ColdFire eval boards. 4 * mcf8390.h -- NS8390 support for ColdFire eval boards.
5 * 5 *
6 * (C) Copyright 1999-2000, Greg Ungerer (gerg@snapgear.com) 6 * (C) Copyright 1999-2000, Greg Ungerer (gerg@snapgear.com)
7 * (C) Copyright 2000, Lineo (www.lineo.com) 7 * (C) Copyright 2000, Lineo (www.lineo.com)
@@ -14,8 +14,8 @@
14 */ 14 */
15 15
16/****************************************************************************/ 16/****************************************************************************/
17#ifndef mcfne_h 17#ifndef mcf8390_h
18#define mcfne_h 18#define mcf8390_h
19/****************************************************************************/ 19/****************************************************************************/
20 20
21 21
@@ -37,6 +37,7 @@
37#if defined(CONFIG_ARN5206) 37#if defined(CONFIG_ARN5206)
38#define NE2000_ADDR 0x40000300 38#define NE2000_ADDR 0x40000300
39#define NE2000_ODDOFFSET 0x00010000 39#define NE2000_ODDOFFSET 0x00010000
40#define NE2000_ADDRSIZE 0x00020000
40#define NE2000_IRQ_VECTOR 0xf0 41#define NE2000_IRQ_VECTOR 0xf0
41#define NE2000_IRQ_PRIORITY 2 42#define NE2000_IRQ_PRIORITY 2
42#define NE2000_IRQ_LEVEL 4 43#define NE2000_IRQ_LEVEL 4
@@ -46,6 +47,7 @@
46#if defined(CONFIG_M5206eC3) 47#if defined(CONFIG_M5206eC3)
47#define NE2000_ADDR 0x40000300 48#define NE2000_ADDR 0x40000300
48#define NE2000_ODDOFFSET 0x00010000 49#define NE2000_ODDOFFSET 0x00010000
50#define NE2000_ADDRSIZE 0x00020000
49#define NE2000_IRQ_VECTOR 0x1c 51#define NE2000_IRQ_VECTOR 0x1c
50#define NE2000_IRQ_PRIORITY 2 52#define NE2000_IRQ_PRIORITY 2
51#define NE2000_IRQ_LEVEL 4 53#define NE2000_IRQ_LEVEL 4
@@ -54,6 +56,7 @@
54 56
55#if defined(CONFIG_M5206e) && defined(CONFIG_NETtel) 57#if defined(CONFIG_M5206e) && defined(CONFIG_NETtel)
56#define NE2000_ADDR 0x30000300 58#define NE2000_ADDR 0x30000300
59#define NE2000_ADDRSIZE 0x00001000
57#define NE2000_IRQ_VECTOR 25 60#define NE2000_IRQ_VECTOR 25
58#define NE2000_IRQ_PRIORITY 1 61#define NE2000_IRQ_PRIORITY 1
59#define NE2000_IRQ_LEVEL 3 62#define NE2000_IRQ_LEVEL 3
@@ -63,6 +66,7 @@
63#if defined(CONFIG_M5307C3) 66#if defined(CONFIG_M5307C3)
64#define NE2000_ADDR 0x40000300 67#define NE2000_ADDR 0x40000300
65#define NE2000_ODDOFFSET 0x00010000 68#define NE2000_ODDOFFSET 0x00010000
69#define NE2000_ADDRSIZE 0x00020000
66#define NE2000_IRQ_VECTOR 0x1b 70#define NE2000_IRQ_VECTOR 0x1b
67#define NE2000_BYTE volatile unsigned short 71#define NE2000_BYTE volatile unsigned short
68#endif 72#endif
@@ -70,6 +74,7 @@
70#if defined(CONFIG_M5272) && defined(CONFIG_NETtel) 74#if defined(CONFIG_M5272) && defined(CONFIG_NETtel)
71#define NE2000_ADDR 0x30600300 75#define NE2000_ADDR 0x30600300
72#define NE2000_ODDOFFSET 0x00008000 76#define NE2000_ODDOFFSET 0x00008000
77#define NE2000_ADDRSIZE 0x00010000
73#define NE2000_IRQ_VECTOR 67 78#define NE2000_IRQ_VECTOR 67
74#undef BSWAP 79#undef BSWAP
75#define BSWAP(w) (w) 80#define BSWAP(w) (w)
@@ -82,6 +87,7 @@
82#define NE2000_ADDR0 0x30600300 87#define NE2000_ADDR0 0x30600300
83#define NE2000_ADDR1 0x30800300 88#define NE2000_ADDR1 0x30800300
84#define NE2000_ODDOFFSET 0x00008000 89#define NE2000_ODDOFFSET 0x00008000
90#define NE2000_ADDRSIZE 0x00010000
85#define NE2000_IRQ_VECTOR0 27 91#define NE2000_IRQ_VECTOR0 27
86#define NE2000_IRQ_VECTOR1 29 92#define NE2000_IRQ_VECTOR1 29
87#undef BSWAP 93#undef BSWAP
@@ -94,6 +100,7 @@
94#if defined(CONFIG_M5307) && defined(CONFIG_SECUREEDGEMP3) 100#if defined(CONFIG_M5307) && defined(CONFIG_SECUREEDGEMP3)
95#define NE2000_ADDR 0x30600300 101#define NE2000_ADDR 0x30600300
96#define NE2000_ODDOFFSET 0x00008000 102#define NE2000_ODDOFFSET 0x00008000
103#define NE2000_ADDRSIZE 0x00010000
97#define NE2000_IRQ_VECTOR 27 104#define NE2000_IRQ_VECTOR 27
98#undef BSWAP 105#undef BSWAP
99#define BSWAP(w) (w) 106#define BSWAP(w) (w)
@@ -105,6 +112,7 @@
105#if defined(CONFIG_ARN5307) 112#if defined(CONFIG_ARN5307)
106#define NE2000_ADDR 0xfe600300 113#define NE2000_ADDR 0xfe600300
107#define NE2000_ODDOFFSET 0x00010000 114#define NE2000_ODDOFFSET 0x00010000
115#define NE2000_ADDRSIZE 0x00020000
108#define NE2000_IRQ_VECTOR 0x1b 116#define NE2000_IRQ_VECTOR 0x1b
109#define NE2000_IRQ_PRIORITY 2 117#define NE2000_IRQ_PRIORITY 2
110#define NE2000_IRQ_LEVEL 3 118#define NE2000_IRQ_LEVEL 3
@@ -114,129 +122,10 @@
114#if defined(CONFIG_M5407C3) 122#if defined(CONFIG_M5407C3)
115#define NE2000_ADDR 0x40000300 123#define NE2000_ADDR 0x40000300
116#define NE2000_ODDOFFSET 0x00010000 124#define NE2000_ODDOFFSET 0x00010000
125#define NE2000_ADDRSIZE 0x00020000
117#define NE2000_IRQ_VECTOR 0x1b 126#define NE2000_IRQ_VECTOR 0x1b
118#define NE2000_BYTE volatile unsigned short 127#define NE2000_BYTE volatile unsigned short
119#endif 128#endif
120 129
121/****************************************************************************/ 130/****************************************************************************/
122 131#endif /* mcf8390_h */
123/*
124 * Side-band address space for odd address requires re-mapping
125 * many of the standard ISA access functions.
126 */
127#ifdef NE2000_ODDOFFSET
128
129#undef outb
130#undef outb_p
131#undef inb
132#undef inb_p
133#undef outsb
134#undef outsw
135#undef insb
136#undef insw
137
138#define outb ne2000_outb
139#define inb ne2000_inb
140#define outb_p ne2000_outb
141#define inb_p ne2000_inb
142#define outsb ne2000_outsb
143#define outsw ne2000_outsw
144#define insb ne2000_insb
145#define insw ne2000_insw
146
147
148#ifndef COLDFIRE_NE2000_FUNCS
149
150void ne2000_outb(unsigned int val, unsigned int addr);
151int ne2000_inb(unsigned int addr);
152void ne2000_insb(unsigned int addr, void *vbuf, int unsigned long len);
153void ne2000_insw(unsigned int addr, void *vbuf, unsigned long len);
154void ne2000_outsb(unsigned int addr, void *vbuf, unsigned long len);
155void ne2000_outsw(unsigned int addr, void *vbuf, unsigned long len);
156
157#else
158
159/*
160 * This macro converts a conventional register address into the
161 * real memory pointer of the mapped NE2000 device.
162 * On most NE2000 implementations on ColdFire boards the chip is
163 * mapped in kinda funny, due to its ISA heritage.
164 */
165#define NE2000_PTR(addr) ((addr&0x1)?(NE2000_ODDOFFSET+addr-1):(addr))
166#define NE2000_DATA_PTR(addr) (addr)
167
168
169void ne2000_outb(unsigned int val, unsigned int addr)
170{
171 NE2000_BYTE *rp;
172
173 rp = (NE2000_BYTE *) NE2000_PTR(addr);
174 *rp = RSWAP(val);
175}
176
177int ne2000_inb(unsigned int addr)
178{
179 NE2000_BYTE *rp, val;
180
181 rp = (NE2000_BYTE *) NE2000_PTR(addr);
182 val = *rp;
183 return((int) ((NE2000_BYTE) RSWAP(val)));
184}
185
186void ne2000_insb(unsigned int addr, void *vbuf, int unsigned long len)
187{
188 NE2000_BYTE *rp, val;
189 unsigned char *buf;
190
191 buf = (unsigned char *) vbuf;
192 rp = (NE2000_BYTE *) NE2000_DATA_PTR(addr);
193 for (; (len > 0); len--) {
194 val = *rp;
195 *buf++ = RSWAP(val);
196 }
197}
198
199void ne2000_insw(unsigned int addr, void *vbuf, unsigned long len)
200{
201 volatile unsigned short *rp;
202 unsigned short w, *buf;
203
204 buf = (unsigned short *) vbuf;
205 rp = (volatile unsigned short *) NE2000_DATA_PTR(addr);
206 for (; (len > 0); len--) {
207 w = *rp;
208 *buf++ = BSWAP(w);
209 }
210}
211
212void ne2000_outsb(unsigned int addr, const void *vbuf, unsigned long len)
213{
214 NE2000_BYTE *rp, val;
215 unsigned char *buf;
216
217 buf = (unsigned char *) vbuf;
218 rp = (NE2000_BYTE *) NE2000_DATA_PTR(addr);
219 for (; (len > 0); len--) {
220 val = *buf++;
221 *rp = RSWAP(val);
222 }
223}
224
225void ne2000_outsw(unsigned int addr, const void *vbuf, unsigned long len)
226{
227 volatile unsigned short *rp;
228 unsigned short w, *buf;
229
230 buf = (unsigned short *) vbuf;
231 rp = (volatile unsigned short *) NE2000_DATA_PTR(addr);
232 for (; (len > 0); len--) {
233 w = *buf++;
234 *rp = BSWAP(w);
235 }
236}
237
238#endif /* COLDFIRE_NE2000_FUNCS */
239#endif /* NE2000_OFFOFFSET */
240
241/****************************************************************************/
242#endif /* mcfne_h */
diff --git a/arch/m68k/include/asm/mcfclk.h b/arch/m68k/include/asm/mcfclk.h
new file mode 100644
index 000000000000..b676a02bb392
--- /dev/null
+++ b/arch/m68k/include/asm/mcfclk.h
@@ -0,0 +1,43 @@
1/*
2 * mcfclk.h -- coldfire specific clock structure
3 */
4
5
6#ifndef mcfclk_h
7#define mcfclk_h
8
9struct clk;
10
11#ifdef MCFPM_PPMCR0
12struct clk_ops {
13 void (*enable)(struct clk *);
14 void (*disable)(struct clk *);
15};
16
17struct clk {
18 const char *name;
19 struct clk_ops *clk_ops;
20 unsigned long rate;
21 unsigned long enabled;
22 u8 slot;
23};
24
25extern struct clk *mcf_clks[];
26extern struct clk_ops clk_ops0;
27#ifdef MCFPM_PPMCR1
28extern struct clk_ops clk_ops1;
29#endif /* MCFPM_PPMCR1 */
30
31#define DEFINE_CLK(clk_bank, clk_name, clk_slot, clk_rate) \
32static struct clk __clk_##clk_bank##_##clk_slot = { \
33 .name = clk_name, \
34 .clk_ops = &clk_ops##clk_bank, \
35 .rate = clk_rate, \
36 .slot = clk_slot, \
37}
38
39void __clk_init_enabled(struct clk *);
40void __clk_init_disabled(struct clk *);
41#endif /* MCFPM_PPMCR0 */
42
43#endif /* mcfclk_h */
diff --git a/arch/m68k/include/asm/mcfgpio.h b/arch/m68k/include/asm/mcfgpio.h
index fe468eaa51e0..fa1059f50dfc 100644
--- a/arch/m68k/include/asm/mcfgpio.h
+++ b/arch/m68k/include/asm/mcfgpio.h
@@ -16,82 +16,289 @@
16#ifndef mcfgpio_h 16#ifndef mcfgpio_h
17#define mcfgpio_h 17#define mcfgpio_h
18 18
19#include <linux/io.h> 19#ifdef CONFIG_GPIOLIB
20#include <asm-generic/gpio.h> 20#include <asm-generic/gpio.h>
21#else
22
23int __mcfgpio_get_value(unsigned gpio);
24void __mcfgpio_set_value(unsigned gpio, int value);
25int __mcfgpio_direction_input(unsigned gpio);
26int __mcfgpio_direction_output(unsigned gpio, int value);
27int __mcfgpio_request(unsigned gpio);
28void __mcfgpio_free(unsigned gpio);
29
30/* our alternate 'gpiolib' functions */
31static inline int __gpio_get_value(unsigned gpio)
32{
33 if (gpio < MCFGPIO_PIN_MAX)
34 return __mcfgpio_get_value(gpio);
35 else
36 return -EINVAL;
37}
38
39static inline void __gpio_set_value(unsigned gpio, int value)
40{
41 if (gpio < MCFGPIO_PIN_MAX)
42 __mcfgpio_set_value(gpio, value);
43}
44
45static inline int __gpio_cansleep(unsigned gpio)
46{
47 if (gpio < MCFGPIO_PIN_MAX)
48 return 0;
49 else
50 return -EINVAL;
51}
52
53static inline int __gpio_to_irq(unsigned gpio)
54{
55 return -EINVAL;
56}
57
58static inline int gpio_direction_input(unsigned gpio)
59{
60 if (gpio < MCFGPIO_PIN_MAX)
61 return __mcfgpio_direction_input(gpio);
62 else
63 return -EINVAL;
64}
65
66static inline int gpio_direction_output(unsigned gpio, int value)
67{
68 if (gpio < MCFGPIO_PIN_MAX)
69 return __mcfgpio_direction_output(gpio, value);
70 else
71 return -EINVAL;
72}
73
74static inline int gpio_request(unsigned gpio, const char *label)
75{
76 if (gpio < MCFGPIO_PIN_MAX)
77 return __mcfgpio_request(gpio);
78 else
79 return -EINVAL;
80}
81
82static inline void gpio_free(unsigned gpio)
83{
84 if (gpio < MCFGPIO_PIN_MAX)
85 __mcfgpio_free(gpio);
86}
87
88#endif /* CONFIG_GPIOLIB */
21 89
22struct mcf_gpio_chip {
23 struct gpio_chip gpio_chip;
24 void __iomem *pddr;
25 void __iomem *podr;
26 void __iomem *ppdr;
27 void __iomem *setr;
28 void __iomem *clrr;
29 const u8 *gpio_to_pinmux;
30};
31
32extern struct mcf_gpio_chip mcf_gpio_chips[];
33extern unsigned int mcf_gpio_chips_size;
34
35int mcf_gpio_direction_input(struct gpio_chip *, unsigned);
36int mcf_gpio_get_value(struct gpio_chip *, unsigned);
37int mcf_gpio_direction_output(struct gpio_chip *, unsigned, int);
38void mcf_gpio_set_value(struct gpio_chip *, unsigned, int);
39void mcf_gpio_set_value_fast(struct gpio_chip *, unsigned, int);
40int mcf_gpio_request(struct gpio_chip *, unsigned);
41void mcf_gpio_free(struct gpio_chip *, unsigned);
42 90
43/* 91/*
44 * Define macros to ease the pain of setting up the GPIO tables. There 92 * The Freescale Coldfire family is quite varied in how they implement GPIO.
45 * are two cases we need to deal with here, they cover all currently 93 * Some parts have 8 bit ports, some have 16bit and some have 32bit; some have
46 * available ColdFire GPIO hardware. There are of course minor differences 94 * only one port, others have multiple ports; some have a single data latch
47 * in the layout and number of bits in each ColdFire part, but the macros 95 * for both input and output, others have a separate pin data register to read
48 * take all that in. 96 * input; some require a read-modify-write access to change an output, others
97 * have set and clear registers for some of the outputs; Some have all the
98 * GPIOs in a single control area, others have some GPIOs implemented in
99 * different modules.
49 * 100 *
50 * Firstly is the conventional GPIO registers where we toggle individual 101 * This implementation attempts accommodate the differences while presenting
51 * bits in a register, preserving the other bits in the register. For 102 * a generic interface that will optimize to as few instructions as possible.
52 * lack of a better term I have called this the slow method. 103 */
104#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
105 defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
106 defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
107 defined(CONFIG_M532x) || defined(CONFIG_M54xx) || \
108 defined(CONFIG_M5441x)
109
110/* These parts have GPIO organized by 8 bit ports */
111
112#define MCFGPIO_PORTTYPE u8
113#define MCFGPIO_PORTSIZE 8
114#define mcfgpio_read(port) __raw_readb(port)
115#define mcfgpio_write(data, port) __raw_writeb(data, port)
116
117#elif defined(CONFIG_M5307) || defined(CONFIG_M5407) || defined(CONFIG_M5272)
118
119/* These parts have GPIO organized by 16 bit ports */
120
121#define MCFGPIO_PORTTYPE u16
122#define MCFGPIO_PORTSIZE 16
123#define mcfgpio_read(port) __raw_readw(port)
124#define mcfgpio_write(data, port) __raw_writew(data, port)
125
126#elif defined(CONFIG_M5249) || defined(CONFIG_M525x)
127
128/* These parts have GPIO organized by 32 bit ports */
129
130#define MCFGPIO_PORTTYPE u32
131#define MCFGPIO_PORTSIZE 32
132#define mcfgpio_read(port) __raw_readl(port)
133#define mcfgpio_write(data, port) __raw_writel(data, port)
134
135#endif
136
137#define mcfgpio_bit(gpio) (1 << ((gpio) % MCFGPIO_PORTSIZE))
138#define mcfgpio_port(gpio) ((gpio) / MCFGPIO_PORTSIZE)
139
140#if defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
141 defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
142 defined(CONFIG_M532x) || defined(CONFIG_M5441x)
143/*
144 * These parts have an 'Edge' Port module (external interrupt/GPIO) which uses
145 * read-modify-write to change an output and a GPIO module which has separate
146 * set/clr registers to directly change outputs with a single write access.
147 */
148#if defined(CONFIG_M528x)
149/*
150 * The 528x also has GPIOs in other modules (GPT, QADC) which use
151 * read-modify-write as well as those controlled by the EPORT and GPIO modules.
53 */ 152 */
54#define MCFGPS(mlabel, mbase, mngpio, mpddr, mpodr, mppdr) \ 153#define MCFGPIO_SCR_START 40
55 { \ 154#elif defined(CONFIGM5441x)
56 .gpio_chip = { \ 155/* The m5441x EPORT doesn't have its own GPIO port, uses PORT C */
57 .label = #mlabel, \ 156#define MCFGPIO_SCR_START 0
58 .request = mcf_gpio_request, \ 157#else
59 .free = mcf_gpio_free, \ 158#define MCFGPIO_SCR_START 8
60 .direction_input = mcf_gpio_direction_input, \ 159#endif
61 .direction_output = mcf_gpio_direction_output,\
62 .get = mcf_gpio_get_value, \
63 .set = mcf_gpio_set_value, \
64 .base = mbase, \
65 .ngpio = mngpio, \
66 }, \
67 .pddr = (void __iomem *) mpddr, \
68 .podr = (void __iomem *) mpodr, \
69 .ppdr = (void __iomem *) mppdr, \
70 }
71 160
161#define MCFGPIO_SETR_PORT(gpio) (MCFGPIO_SETR + \
162 mcfgpio_port(gpio - MCFGPIO_SCR_START))
163
164#define MCFGPIO_CLRR_PORT(gpio) (MCFGPIO_CLRR + \
165 mcfgpio_port(gpio - MCFGPIO_SCR_START))
166#else
167
168#define MCFGPIO_SCR_START MCFGPIO_PIN_MAX
169/* with MCFGPIO_SCR == MCFGPIO_PIN_MAX, these will be optimized away */
170#define MCFGPIO_SETR_PORT(gpio) 0
171#define MCFGPIO_CLRR_PORT(gpio) 0
172
173#endif
72/* 174/*
73 * Secondly is the faster case, where we have set and clear registers 175 * Coldfire specific helper functions
74 * that allow us to set or clear a bit with a single write, not having
75 * to worry about preserving other bits.
76 */ 176 */
77#define MCFGPF(mlabel, mbase, mngpio) \
78 { \
79 .gpio_chip = { \
80 .label = #mlabel, \
81 .request = mcf_gpio_request, \
82 .free = mcf_gpio_free, \
83 .direction_input = mcf_gpio_direction_input, \
84 .direction_output = mcf_gpio_direction_output,\
85 .get = mcf_gpio_get_value, \
86 .set = mcf_gpio_set_value_fast, \
87 .base = mbase, \
88 .ngpio = mngpio, \
89 }, \
90 .pddr = (void __iomem *) MCFGPIO_PDDR_##mlabel, \
91 .podr = (void __iomem *) MCFGPIO_PODR_##mlabel, \
92 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_##mlabel, \
93 .setr = (void __iomem *) MCFGPIO_PPDSDR_##mlabel, \
94 .clrr = (void __iomem *) MCFGPIO_PCLRR_##mlabel, \
95 }
96 177
178/* return the port pin data register for a gpio */
179static inline u32 __mcfgpio_ppdr(unsigned gpio)
180{
181#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
182 defined(CONFIG_M5307) || defined(CONFIG_M5407)
183 return MCFSIM_PADAT;
184#elif defined(CONFIG_M5272)
185 if (gpio < 16)
186 return MCFSIM_PADAT;
187 else if (gpio < 32)
188 return MCFSIM_PBDAT;
189 else
190 return MCFSIM_PCDAT;
191#elif defined(CONFIG_M5249) || defined(CONFIG_M525x)
192 if (gpio < 32)
193 return MCFSIM2_GPIOREAD;
194 else
195 return MCFSIM2_GPIO1READ;
196#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
197 defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
198 defined(CONFIG_M532x) || defined(CONFIG_M5441x)
199#if !defined(CONFIG_M5441x)
200 if (gpio < 8)
201 return MCFEPORT_EPPDR;
202#if defined(CONFIG_M528x)
203 else if (gpio < 16)
204 return MCFGPTA_GPTPORT;
205 else if (gpio < 24)
206 return MCFGPTB_GPTPORT;
207 else if (gpio < 32)
208 return MCFQADC_PORTQA;
209 else if (gpio < 40)
210 return MCFQADC_PORTQB;
211#endif /* defined(CONFIG_M528x) */
212 else
213#endif /* !defined(CONFIG_M5441x) */
214 return MCFGPIO_PPDR + mcfgpio_port(gpio - MCFGPIO_SCR_START);
215#else
216 return 0;
97#endif 217#endif
218}
219
220/* return the port output data register for a gpio */
221static inline u32 __mcfgpio_podr(unsigned gpio)
222{
223#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
224 defined(CONFIG_M5307) || defined(CONFIG_M5407)
225 return MCFSIM_PADAT;
226#elif defined(CONFIG_M5272)
227 if (gpio < 16)
228 return MCFSIM_PADAT;
229 else if (gpio < 32)
230 return MCFSIM_PBDAT;
231 else
232 return MCFSIM_PCDAT;
233#elif defined(CONFIG_M5249) || defined(CONFIG_M525x)
234 if (gpio < 32)
235 return MCFSIM2_GPIOWRITE;
236 else
237 return MCFSIM2_GPIO1WRITE;
238#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
239 defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
240 defined(CONFIG_M532x) || defined(CONFIG_M5441x)
241#if !defined(CONFIG_M5441x)
242 if (gpio < 8)
243 return MCFEPORT_EPDR;
244#if defined(CONFIG_M528x)
245 else if (gpio < 16)
246 return MCFGPTA_GPTPORT;
247 else if (gpio < 24)
248 return MCFGPTB_GPTPORT;
249 else if (gpio < 32)
250 return MCFQADC_PORTQA;
251 else if (gpio < 40)
252 return MCFQADC_PORTQB;
253#endif /* defined(CONFIG_M528x) */
254 else
255#endif /* !defined(CONFIG_M5441x) */
256 return MCFGPIO_PODR + mcfgpio_port(gpio - MCFGPIO_SCR_START);
257#else
258 return 0;
259#endif
260}
261
262/* return the port direction data register for a gpio */
263static inline u32 __mcfgpio_pddr(unsigned gpio)
264{
265#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
266 defined(CONFIG_M5307) || defined(CONFIG_M5407)
267 return MCFSIM_PADDR;
268#elif defined(CONFIG_M5272)
269 if (gpio < 16)
270 return MCFSIM_PADDR;
271 else if (gpio < 32)
272 return MCFSIM_PBDDR;
273 else
274 return MCFSIM_PCDDR;
275#elif defined(CONFIG_M5249) || defined(CONFIG_M525x)
276 if (gpio < 32)
277 return MCFSIM2_GPIOENABLE;
278 else
279 return MCFSIM2_GPIO1ENABLE;
280#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
281 defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
282 defined(CONFIG_M532x) || defined(CONFIG_M5441x)
283#if !defined(CONFIG_M5441x)
284 if (gpio < 8)
285 return MCFEPORT_EPDDR;
286#if defined(CONFIG_M528x)
287 else if (gpio < 16)
288 return MCFGPTA_GPTDDR;
289 else if (gpio < 24)
290 return MCFGPTB_GPTDDR;
291 else if (gpio < 32)
292 return MCFQADC_DDRQA;
293 else if (gpio < 40)
294 return MCFQADC_DDRQB;
295#endif /* defined(CONFIG_M528x) */
296 else
297#endif /* !defined(CONFIG_M5441x) */
298 return MCFGPIO_PDDR + mcfgpio_port(gpio - MCFGPIO_SCR_START);
299#else
300 return 0;
301#endif
302}
303
304#endif /* mcfgpio_h */
diff --git a/arch/m68k/include/asm/mcfsim.h b/arch/m68k/include/asm/mcfsim.h
index ebd0304054ad..7a83e619e73b 100644
--- a/arch/m68k/include/asm/mcfsim.h
+++ b/arch/m68k/include/asm/mcfsim.h
@@ -27,6 +27,9 @@
27#elif defined(CONFIG_M5249) 27#elif defined(CONFIG_M5249)
28#include <asm/m5249sim.h> 28#include <asm/m5249sim.h>
29#include <asm/mcfintc.h> 29#include <asm/mcfintc.h>
30#elif defined(CONFIG_M525x)
31#include <asm/m525xsim.h>
32#include <asm/mcfintc.h>
30#elif defined(CONFIG_M527x) 33#elif defined(CONFIG_M527x)
31#include <asm/m527xsim.h> 34#include <asm/m527xsim.h>
32#elif defined(CONFIG_M5272) 35#elif defined(CONFIG_M5272)
@@ -43,6 +46,8 @@
43#include <asm/mcfintc.h> 46#include <asm/mcfintc.h>
44#elif defined(CONFIG_M54xx) 47#elif defined(CONFIG_M54xx)
45#include <asm/m54xxsim.h> 48#include <asm/m54xxsim.h>
49#elif defined(CONFIG_M5441x)
50#include <asm/m5441xsim.h>
46#endif 51#endif
47 52
48/****************************************************************************/ 53/****************************************************************************/
diff --git a/arch/m68k/include/asm/mcftimer.h b/arch/m68k/include/asm/mcftimer.h
index 351c27237874..da2fa43c2e45 100644
--- a/arch/m68k/include/asm/mcftimer.h
+++ b/arch/m68k/include/asm/mcftimer.h
@@ -19,7 +19,7 @@
19#define MCFTIMER_TRR 0x04 /* Timer Reference (r/w) */ 19#define MCFTIMER_TRR 0x04 /* Timer Reference (r/w) */
20#define MCFTIMER_TCR 0x08 /* Timer Capture reg (r/w) */ 20#define MCFTIMER_TCR 0x08 /* Timer Capture reg (r/w) */
21#define MCFTIMER_TCN 0x0C /* Timer Counter reg (r/w) */ 21#define MCFTIMER_TCN 0x0C /* Timer Counter reg (r/w) */
22#if defined(CONFIG_M532x) 22#if defined(CONFIG_M532x) || defined(CONFIG_M5441x)
23#define MCFTIMER_TER 0x03 /* Timer Event reg (r/w) */ 23#define MCFTIMER_TER 0x03 /* Timer Event reg (r/w) */
24#else 24#else
25#define MCFTIMER_TER 0x11 /* Timer Event reg (r/w) */ 25#define MCFTIMER_TER 0x11 /* Timer Event reg (r/w) */
diff --git a/arch/m68k/include/asm/mcfuart.h b/arch/m68k/include/asm/mcfuart.h
index 2d3bc774b3c5..b40c20f66647 100644
--- a/arch/m68k/include/asm/mcfuart.h
+++ b/arch/m68k/include/asm/mcfuart.h
@@ -43,8 +43,8 @@ struct mcf_platform_uart {
43#define MCFUART_UFPD 0x30 /* Frac Prec. Divider (r/w) */ 43#define MCFUART_UFPD 0x30 /* Frac Prec. Divider (r/w) */
44#endif 44#endif
45#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \ 45#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
46 defined(CONFIG_M5249) || defined(CONFIG_M5307) || \ 46 defined(CONFIG_M5249) || defined(CONFIG_M525x) || \
47 defined(CONFIG_M5407) 47 defined(CONFIG_M5307) || defined(CONFIG_M5407)
48#define MCFUART_UIVR 0x30 /* Interrupt Vector (r/w) */ 48#define MCFUART_UIVR 0x30 /* Interrupt Vector (r/w) */
49#endif 49#endif
50#define MCFUART_UIPR 0x34 /* Input Port (r) */ 50#define MCFUART_UIPR 0x34 /* Input Port (r) */
diff --git a/arch/m68k/include/asm/pci.h b/arch/m68k/include/asm/pci.h
index 4ad0aea48ab4..848c3dfaad50 100644
--- a/arch/m68k/include/asm/pci.h
+++ b/arch/m68k/include/asm/pci.h
@@ -2,6 +2,7 @@
2#define _ASM_M68K_PCI_H 2#define _ASM_M68K_PCI_H
3 3
4#include <asm-generic/pci-dma-compat.h> 4#include <asm-generic/pci-dma-compat.h>
5#include <asm-generic/pci.h>
5 6
6/* The PCI address space does equal the physical memory 7/* The PCI address space does equal the physical memory
7 * address space. The networking and block device layers use 8 * address space. The networking and block device layers use
@@ -9,4 +10,9 @@
9 */ 10 */
10#define PCI_DMA_BUS_IS_PHYS (1) 11#define PCI_DMA_BUS_IS_PHYS (1)
11 12
13#define pcibios_assign_all_busses() 1
14
15#define PCIBIOS_MIN_IO 0x00000100
16#define PCIBIOS_MIN_MEM 0x02000000
17
12#endif /* _ASM_M68K_PCI_H */ 18#endif /* _ASM_M68K_PCI_H */
diff --git a/arch/m68k/include/asm/pinmux.h b/arch/m68k/include/asm/pinmux.h
deleted file mode 100644
index 119ee686dbd1..000000000000
--- a/arch/m68k/include/asm/pinmux.h
+++ /dev/null
@@ -1,30 +0,0 @@
1/*
2 * Coldfire generic GPIO pinmux support.
3 *
4 * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#ifndef pinmux_h
17#define pinmux_h
18
19#define MCFPINMUX_NONE -1
20
21extern int mcf_pinmux_request(unsigned, unsigned);
22extern void mcf_pinmux_release(unsigned, unsigned);
23
24static inline int mcf_pinmux_is_valid(unsigned pinmux)
25{
26 return pinmux != MCFPINMUX_NONE;
27}
28
29#endif
30
diff --git a/arch/m68k/include/asm/unistd.h b/arch/m68k/include/asm/unistd.h
index ea0b502f845e..045cfd6a9e31 100644
--- a/arch/m68k/include/asm/unistd.h
+++ b/arch/m68k/include/asm/unistd.h
@@ -357,7 +357,6 @@
357 357
358#define NR_syscalls 347 358#define NR_syscalls 347
359 359
360#define __ARCH_WANT_IPC_PARSE_VERSION
361#define __ARCH_WANT_OLD_READDIR 360#define __ARCH_WANT_OLD_READDIR
362#define __ARCH_WANT_OLD_STAT 361#define __ARCH_WANT_OLD_STAT
363#define __ARCH_WANT_STAT64 362#define __ARCH_WANT_STAT64
diff --git a/arch/m68k/kernel/Makefile b/arch/m68k/kernel/Makefile
index 5c7070e21eb7..068ad49210d6 100644
--- a/arch/m68k/kernel/Makefile
+++ b/arch/m68k/kernel/Makefile
@@ -18,6 +18,7 @@ obj-y += setup.o signal.o sys_m68k.o syscalltable.o time.o traps.o
18 18
19obj-$(CONFIG_MMU_MOTOROLA) += ints.o vectors.o 19obj-$(CONFIG_MMU_MOTOROLA) += ints.o vectors.o
20obj-$(CONFIG_MMU_SUN3) += ints.o vectors.o 20obj-$(CONFIG_MMU_SUN3) += ints.o vectors.o
21obj-$(CONFIG_PCI) += pcibios.o
21 22
22ifndef CONFIG_MMU_SUN3 23ifndef CONFIG_MMU_SUN3
23obj-y += dma.o 24obj-y += dma.o
diff --git a/arch/m68k/kernel/dma.c b/arch/m68k/kernel/dma.c
index f6daf6e15d2e..e546a5534dd4 100644
--- a/arch/m68k/kernel/dma.c
+++ b/arch/m68k/kernel/dma.c
@@ -16,7 +16,7 @@
16 16
17#include <asm/pgalloc.h> 17#include <asm/pgalloc.h>
18 18
19#ifdef CONFIG_MMU 19#if defined(CONFIG_MMU) && !defined(CONFIG_COLDFIRE)
20 20
21void *dma_alloc_coherent(struct device *dev, size_t size, 21void *dma_alloc_coherent(struct device *dev, size_t size,
22 dma_addr_t *handle, gfp_t flag) 22 dma_addr_t *handle, gfp_t flag)
@@ -96,7 +96,7 @@ void dma_free_coherent(struct device *dev, size_t size,
96 free_pages((unsigned long)vaddr, get_order(size)); 96 free_pages((unsigned long)vaddr, get_order(size));
97} 97}
98 98
99#endif /* CONFIG_MMU */ 99#endif /* CONFIG_MMU && !CONFIG_COLDFIRE */
100 100
101EXPORT_SYMBOL(dma_alloc_coherent); 101EXPORT_SYMBOL(dma_alloc_coherent);
102EXPORT_SYMBOL(dma_free_coherent); 102EXPORT_SYMBOL(dma_free_coherent);
@@ -105,6 +105,7 @@ void dma_sync_single_for_device(struct device *dev, dma_addr_t handle,
105 size_t size, enum dma_data_direction dir) 105 size_t size, enum dma_data_direction dir)
106{ 106{
107 switch (dir) { 107 switch (dir) {
108 case DMA_BIDIRECTIONAL:
108 case DMA_TO_DEVICE: 109 case DMA_TO_DEVICE:
109 cache_push(handle, size); 110 cache_push(handle, size);
110 break; 111 break;
diff --git a/arch/m68k/kernel/entry.S b/arch/m68k/kernel/entry.S
index b8daf64e347d..165ee9f9d5c9 100644
--- a/arch/m68k/kernel/entry.S
+++ b/arch/m68k/kernel/entry.S
@@ -1,5 +1,451 @@
1#if defined(CONFIG_MMU) && !defined(CONFIG_COLDFIRE) 1/* -*- mode: asm -*-
2#include "entry_mm.S" 2 *
3 * linux/arch/m68k/kernel/entry.S
4 *
5 * Copyright (C) 1991, 1992 Linus Torvalds
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file README.legal in the main directory of this archive
9 * for more details.
10 *
11 * Linux/m68k support by Hamish Macdonald
12 *
13 * 68060 fixes by Jesper Skov
14 *
15 */
16
17/*
18 * entry.S contains the system-call and fault low-level handling routines.
19 * This also contains the timer-interrupt handler, as well as all interrupts
20 * and faults that can result in a task-switch.
21 *
22 * NOTE: This code handles signal-recognition, which happens every time
23 * after a timer-interrupt and after each system call.
24 *
25 */
26
27/*
28 * 12/03/96 Jes: Currently we only support m68k single-cpu systems, so
29 * all pointers that used to be 'current' are now entry
30 * number 0 in the 'current_set' list.
31 *
32 * 6/05/00 RZ: addedd writeback completion after return from sighandler
33 * for 68040
34 */
35
36#include <linux/linkage.h>
37#include <asm/errno.h>
38#include <asm/setup.h>
39#include <asm/segment.h>
40#include <asm/traps.h>
41#include <asm/unistd.h>
42#include <asm/asm-offsets.h>
43#include <asm/entry.h>
44
45.globl system_call, buserr, trap, resume
46.globl sys_call_table
47.globl sys_fork, sys_clone, sys_vfork
48.globl ret_from_interrupt, bad_interrupt
49.globl auto_irqhandler_fixup
50.globl user_irqvec_fixup
51
52.text
53ENTRY(sys_fork)
54 SAVE_SWITCH_STACK
55 pea %sp@(SWITCH_STACK_SIZE)
56 jbsr m68k_fork
57 addql #4,%sp
58 RESTORE_SWITCH_STACK
59 rts
60
61ENTRY(sys_clone)
62 SAVE_SWITCH_STACK
63 pea %sp@(SWITCH_STACK_SIZE)
64 jbsr m68k_clone
65 addql #4,%sp
66 RESTORE_SWITCH_STACK
67 rts
68
69ENTRY(sys_vfork)
70 SAVE_SWITCH_STACK
71 pea %sp@(SWITCH_STACK_SIZE)
72 jbsr m68k_vfork
73 addql #4,%sp
74 RESTORE_SWITCH_STACK
75 rts
76
77ENTRY(sys_sigreturn)
78 SAVE_SWITCH_STACK
79 jbsr do_sigreturn
80 RESTORE_SWITCH_STACK
81 rts
82
83ENTRY(sys_rt_sigreturn)
84 SAVE_SWITCH_STACK
85 jbsr do_rt_sigreturn
86 RESTORE_SWITCH_STACK
87 rts
88
89ENTRY(buserr)
90 SAVE_ALL_INT
91 GET_CURRENT(%d0)
92 movel %sp,%sp@- | stack frame pointer argument
93 jbsr buserr_c
94 addql #4,%sp
95 jra ret_from_exception
96
97ENTRY(trap)
98 SAVE_ALL_INT
99 GET_CURRENT(%d0)
100 movel %sp,%sp@- | stack frame pointer argument
101 jbsr trap_c
102 addql #4,%sp
103 jra ret_from_exception
104
105 | After a fork we jump here directly from resume,
106 | so that %d1 contains the previous task
107 | schedule_tail now used regardless of CONFIG_SMP
108ENTRY(ret_from_fork)
109 movel %d1,%sp@-
110 jsr schedule_tail
111 addql #4,%sp
112 jra ret_from_exception
113
114#if defined(CONFIG_COLDFIRE) || !defined(CONFIG_MMU)
115
116#ifdef TRAP_DBG_INTERRUPT
117
118.globl dbginterrupt
119ENTRY(dbginterrupt)
120 SAVE_ALL_INT
121 GET_CURRENT(%d0)
122 movel %sp,%sp@- /* stack frame pointer argument */
123 jsr dbginterrupt_c
124 addql #4,%sp
125 jra ret_from_exception
126#endif
127
128ENTRY(reschedule)
129 /* save top of frame */
130 pea %sp@
131 jbsr set_esp0
132 addql #4,%sp
133 pea ret_from_exception
134 jmp schedule
135
136ENTRY(ret_from_user_signal)
137 moveq #__NR_sigreturn,%d0
138 trap #0
139
140ENTRY(ret_from_user_rt_signal)
141 movel #__NR_rt_sigreturn,%d0
142 trap #0
143
3#else 144#else
4#include "entry_no.S" 145
146do_trace_entry:
147 movel #-ENOSYS,%sp@(PT_OFF_D0)| needed for strace
148 subql #4,%sp
149 SAVE_SWITCH_STACK
150 jbsr syscall_trace
151 RESTORE_SWITCH_STACK
152 addql #4,%sp
153 movel %sp@(PT_OFF_ORIG_D0),%d0
154 cmpl #NR_syscalls,%d0
155 jcs syscall
156badsys:
157 movel #-ENOSYS,%sp@(PT_OFF_D0)
158 jra ret_from_syscall
159
160do_trace_exit:
161 subql #4,%sp
162 SAVE_SWITCH_STACK
163 jbsr syscall_trace
164 RESTORE_SWITCH_STACK
165 addql #4,%sp
166 jra .Lret_from_exception
167
168ENTRY(ret_from_signal)
169 movel %curptr@(TASK_STACK),%a1
170 tstb %a1@(TINFO_FLAGS+2)
171 jge 1f
172 jbsr syscall_trace
1731: RESTORE_SWITCH_STACK
174 addql #4,%sp
175/* on 68040 complete pending writebacks if any */
176#ifdef CONFIG_M68040
177 bfextu %sp@(PT_OFF_FORMATVEC){#0,#4},%d0
178 subql #7,%d0 | bus error frame ?
179 jbne 1f
180 movel %sp,%sp@-
181 jbsr berr_040cleanup
182 addql #4,%sp
1831:
184#endif
185 jra .Lret_from_exception
186
187ENTRY(system_call)
188 SAVE_ALL_SYS
189
190 GET_CURRENT(%d1)
191 movel %d1,%a1
192
193 | save top of frame
194 movel %sp,%curptr@(TASK_THREAD+THREAD_ESP0)
195
196 | syscall trace?
197 tstb %a1@(TINFO_FLAGS+2)
198 jmi do_trace_entry
199 cmpl #NR_syscalls,%d0
200 jcc badsys
201syscall:
202 jbsr @(sys_call_table,%d0:l:4)@(0)
203 movel %d0,%sp@(PT_OFF_D0) | save the return value
204ret_from_syscall:
205 |oriw #0x0700,%sr
206 movel %curptr@(TASK_STACK),%a1
207 movew %a1@(TINFO_FLAGS+2),%d0
208 jne syscall_exit_work
2091: RESTORE_ALL
210
211syscall_exit_work:
212 btst #5,%sp@(PT_OFF_SR) | check if returning to kernel
213 bnes 1b | if so, skip resched, signals
214 lslw #1,%d0
215 jcs do_trace_exit
216 jmi do_delayed_trace
217 lslw #8,%d0
218 jne do_signal_return
219 pea resume_userspace
220 jra schedule
221
222
223ENTRY(ret_from_exception)
224.Lret_from_exception:
225 btst #5,%sp@(PT_OFF_SR) | check if returning to kernel
226 bnes 1f | if so, skip resched, signals
227 | only allow interrupts when we are really the last one on the
228 | kernel stack, otherwise stack overflow can occur during
229 | heavy interrupt load
230 andw #ALLOWINT,%sr
231
232resume_userspace:
233 movel %curptr@(TASK_STACK),%a1
234 moveb %a1@(TINFO_FLAGS+3),%d0
235 jne exit_work
2361: RESTORE_ALL
237
238exit_work:
239 | save top of frame
240 movel %sp,%curptr@(TASK_THREAD+THREAD_ESP0)
241 lslb #1,%d0
242 jne do_signal_return
243 pea resume_userspace
244 jra schedule
245
246
247do_signal_return:
248 |andw #ALLOWINT,%sr
249 subql #4,%sp | dummy return address
250 SAVE_SWITCH_STACK
251 pea %sp@(SWITCH_STACK_SIZE)
252 bsrl do_notify_resume
253 addql #4,%sp
254 RESTORE_SWITCH_STACK
255 addql #4,%sp
256 jbra resume_userspace
257
258do_delayed_trace:
259 bclr #7,%sp@(PT_OFF_SR) | clear trace bit in SR
260 pea 1 | send SIGTRAP
261 movel %curptr,%sp@-
262 pea LSIGTRAP
263 jbsr send_sig
264 addql #8,%sp
265 addql #4,%sp
266 jbra resume_userspace
267
268
269/* This is the main interrupt handler for autovector interrupts */
270
271ENTRY(auto_inthandler)
272 SAVE_ALL_INT
273 GET_CURRENT(%d0)
274 movel %d0,%a1
275 addqb #1,%a1@(TINFO_PREEMPT+1)
276 | put exception # in d0
277 bfextu %sp@(PT_OFF_FORMATVEC){#4,#10},%d0
278 subw #VEC_SPUR,%d0
279
280 movel %sp,%sp@-
281 movel %d0,%sp@- | put vector # on stack
282auto_irqhandler_fixup = . + 2
283 jsr do_IRQ | process the IRQ
284 addql #8,%sp | pop parameters off stack
285
286ret_from_interrupt:
287 movel %curptr@(TASK_STACK),%a1
288 subqb #1,%a1@(TINFO_PREEMPT+1)
289 jeq ret_from_last_interrupt
2902: RESTORE_ALL
291
292 ALIGN
293ret_from_last_interrupt:
294 moveq #(~ALLOWINT>>8)&0xff,%d0
295 andb %sp@(PT_OFF_SR),%d0
296 jne 2b
297
298 /* check if we need to do software interrupts */
299 tstl irq_stat+CPUSTAT_SOFTIRQ_PENDING
300 jeq .Lret_from_exception
301 pea ret_from_exception
302 jra do_softirq
303
304/* Handler for user defined interrupt vectors */
305
306ENTRY(user_inthandler)
307 SAVE_ALL_INT
308 GET_CURRENT(%d0)
309 movel %d0,%a1
310 addqb #1,%a1@(TINFO_PREEMPT+1)
311 | put exception # in d0
312 bfextu %sp@(PT_OFF_FORMATVEC){#4,#10},%d0
313user_irqvec_fixup = . + 2
314 subw #VEC_USER,%d0
315
316 movel %sp,%sp@-
317 movel %d0,%sp@- | put vector # on stack
318 jsr do_IRQ | process the IRQ
319 addql #8,%sp | pop parameters off stack
320
321 movel %curptr@(TASK_STACK),%a1
322 subqb #1,%a1@(TINFO_PREEMPT+1)
323 jeq ret_from_last_interrupt
324 RESTORE_ALL
325
326/* Handler for uninitialized and spurious interrupts */
327
328ENTRY(bad_inthandler)
329 SAVE_ALL_INT
330 GET_CURRENT(%d0)
331 movel %d0,%a1
332 addqb #1,%a1@(TINFO_PREEMPT+1)
333
334 movel %sp,%sp@-
335 jsr handle_badint
336 addql #4,%sp
337
338 movel %curptr@(TASK_STACK),%a1
339 subqb #1,%a1@(TINFO_PREEMPT+1)
340 jeq ret_from_last_interrupt
341 RESTORE_ALL
342
343
344resume:
345 /*
346 * Beware - when entering resume, prev (the current task) is
347 * in a0, next (the new task) is in a1,so don't change these
348 * registers until their contents are no longer needed.
349 */
350
351 /* save sr */
352 movew %sr,%a0@(TASK_THREAD+THREAD_SR)
353
354 /* save fs (sfc,%dfc) (may be pointing to kernel memory) */
355 movec %sfc,%d0
356 movew %d0,%a0@(TASK_THREAD+THREAD_FS)
357
358 /* save usp */
359 /* it is better to use a movel here instead of a movew 8*) */
360 movec %usp,%d0
361 movel %d0,%a0@(TASK_THREAD+THREAD_USP)
362
363 /* save non-scratch registers on stack */
364 SAVE_SWITCH_STACK
365
366 /* save current kernel stack pointer */
367 movel %sp,%a0@(TASK_THREAD+THREAD_KSP)
368
369 /* save floating point context */
370#ifndef CONFIG_M68KFPU_EMU_ONLY
371#ifdef CONFIG_M68KFPU_EMU
372 tstl m68k_fputype
373 jeq 3f
374#endif
375 fsave %a0@(TASK_THREAD+THREAD_FPSTATE)
376
377#if defined(CONFIG_M68060)
378#if !defined(CPU_M68060_ONLY)
379 btst #3,m68k_cputype+3
380 beqs 1f
381#endif
382 /* The 060 FPU keeps status in bits 15-8 of the first longword */
383 tstb %a0@(TASK_THREAD+THREAD_FPSTATE+2)
384 jeq 3f
385#if !defined(CPU_M68060_ONLY)
386 jra 2f
387#endif
388#endif /* CONFIG_M68060 */
389#if !defined(CPU_M68060_ONLY)
3901: tstb %a0@(TASK_THREAD+THREAD_FPSTATE)
391 jeq 3f
392#endif
3932: fmovemx %fp0-%fp7,%a0@(TASK_THREAD+THREAD_FPREG)
394 fmoveml %fpcr/%fpsr/%fpiar,%a0@(TASK_THREAD+THREAD_FPCNTL)
3953:
396#endif /* CONFIG_M68KFPU_EMU_ONLY */
397 /* Return previous task in %d1 */
398 movel %curptr,%d1
399
400 /* switch to new task (a1 contains new task) */
401 movel %a1,%curptr
402
403 /* restore floating point context */
404#ifndef CONFIG_M68KFPU_EMU_ONLY
405#ifdef CONFIG_M68KFPU_EMU
406 tstl m68k_fputype
407 jeq 4f
408#endif
409#if defined(CONFIG_M68060)
410#if !defined(CPU_M68060_ONLY)
411 btst #3,m68k_cputype+3
412 beqs 1f
413#endif
414 /* The 060 FPU keeps status in bits 15-8 of the first longword */
415 tstb %a1@(TASK_THREAD+THREAD_FPSTATE+2)
416 jeq 3f
417#if !defined(CPU_M68060_ONLY)
418 jra 2f
419#endif
420#endif /* CONFIG_M68060 */
421#if !defined(CPU_M68060_ONLY)
4221: tstb %a1@(TASK_THREAD+THREAD_FPSTATE)
423 jeq 3f
5#endif 424#endif
4252: fmovemx %a1@(TASK_THREAD+THREAD_FPREG),%fp0-%fp7
426 fmoveml %a1@(TASK_THREAD+THREAD_FPCNTL),%fpcr/%fpsr/%fpiar
4273: frestore %a1@(TASK_THREAD+THREAD_FPSTATE)
4284:
429#endif /* CONFIG_M68KFPU_EMU_ONLY */
430
431 /* restore the kernel stack pointer */
432 movel %a1@(TASK_THREAD+THREAD_KSP),%sp
433
434 /* restore non-scratch registers */
435 RESTORE_SWITCH_STACK
436
437 /* restore user stack pointer */
438 movel %a1@(TASK_THREAD+THREAD_USP),%a0
439 movel %a0,%usp
440
441 /* restore fs (sfc,%dfc) */
442 movew %a1@(TASK_THREAD+THREAD_FS),%a0
443 movec %a0,%sfc
444 movec %a0,%dfc
445
446 /* restore status register */
447 movew %a1@(TASK_THREAD+THREAD_SR),%sr
448
449 rts
450
451#endif /* CONFIG_MMU && !CONFIG_COLDFIRE */
diff --git a/arch/m68k/kernel/entry_mm.S b/arch/m68k/kernel/entry_mm.S
deleted file mode 100644
index f29e73ca9dbb..000000000000
--- a/arch/m68k/kernel/entry_mm.S
+++ /dev/null
@@ -1,419 +0,0 @@
1/* -*- mode: asm -*-
2 *
3 * linux/arch/m68k/kernel/entry.S
4 *
5 * Copyright (C) 1991, 1992 Linus Torvalds
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file README.legal in the main directory of this archive
9 * for more details.
10 *
11 * Linux/m68k support by Hamish Macdonald
12 *
13 * 68060 fixes by Jesper Skov
14 *
15 */
16
17/*
18 * entry.S contains the system-call and fault low-level handling routines.
19 * This also contains the timer-interrupt handler, as well as all interrupts
20 * and faults that can result in a task-switch.
21 *
22 * NOTE: This code handles signal-recognition, which happens every time
23 * after a timer-interrupt and after each system call.
24 *
25 */
26
27/*
28 * 12/03/96 Jes: Currently we only support m68k single-cpu systems, so
29 * all pointers that used to be 'current' are now entry
30 * number 0 in the 'current_set' list.
31 *
32 * 6/05/00 RZ: addedd writeback completion after return from sighandler
33 * for 68040
34 */
35
36#include <linux/linkage.h>
37#include <asm/entry.h>
38#include <asm/errno.h>
39#include <asm/setup.h>
40#include <asm/segment.h>
41#include <asm/traps.h>
42#include <asm/unistd.h>
43
44#include <asm/asm-offsets.h>
45
46.globl system_call, buserr, trap, resume
47.globl sys_call_table
48.globl sys_fork, sys_clone, sys_vfork
49.globl ret_from_interrupt, bad_interrupt
50.globl auto_irqhandler_fixup
51.globl user_irqvec_fixup
52
53.text
54ENTRY(buserr)
55 SAVE_ALL_INT
56 GET_CURRENT(%d0)
57 movel %sp,%sp@- | stack frame pointer argument
58 bsrl buserr_c
59 addql #4,%sp
60 jra .Lret_from_exception
61
62ENTRY(trap)
63 SAVE_ALL_INT
64 GET_CURRENT(%d0)
65 movel %sp,%sp@- | stack frame pointer argument
66 bsrl trap_c
67 addql #4,%sp
68 jra .Lret_from_exception
69
70 | After a fork we jump here directly from resume,
71 | so that %d1 contains the previous task
72 | schedule_tail now used regardless of CONFIG_SMP
73ENTRY(ret_from_fork)
74 movel %d1,%sp@-
75 jsr schedule_tail
76 addql #4,%sp
77 jra .Lret_from_exception
78
79do_trace_entry:
80 movel #-ENOSYS,%sp@(PT_OFF_D0)| needed for strace
81 subql #4,%sp
82 SAVE_SWITCH_STACK
83 jbsr syscall_trace
84 RESTORE_SWITCH_STACK
85 addql #4,%sp
86 movel %sp@(PT_OFF_ORIG_D0),%d0
87 cmpl #NR_syscalls,%d0
88 jcs syscall
89badsys:
90 movel #-ENOSYS,%sp@(PT_OFF_D0)
91 jra ret_from_syscall
92
93do_trace_exit:
94 subql #4,%sp
95 SAVE_SWITCH_STACK
96 jbsr syscall_trace
97 RESTORE_SWITCH_STACK
98 addql #4,%sp
99 jra .Lret_from_exception
100
101ENTRY(ret_from_signal)
102 movel %curptr@(TASK_STACK),%a1
103 tstb %a1@(TINFO_FLAGS+2)
104 jge 1f
105 jbsr syscall_trace
1061: RESTORE_SWITCH_STACK
107 addql #4,%sp
108/* on 68040 complete pending writebacks if any */
109#ifdef CONFIG_M68040
110 bfextu %sp@(PT_OFF_FORMATVEC){#0,#4},%d0
111 subql #7,%d0 | bus error frame ?
112 jbne 1f
113 movel %sp,%sp@-
114 jbsr berr_040cleanup
115 addql #4,%sp
1161:
117#endif
118 jra .Lret_from_exception
119
120ENTRY(system_call)
121 SAVE_ALL_SYS
122
123 GET_CURRENT(%d1)
124 movel %d1,%a1
125
126 | save top of frame
127 movel %sp,%curptr@(TASK_THREAD+THREAD_ESP0)
128
129 | syscall trace?
130 tstb %a1@(TINFO_FLAGS+2)
131 jmi do_trace_entry
132 cmpl #NR_syscalls,%d0
133 jcc badsys
134syscall:
135 jbsr @(sys_call_table,%d0:l:4)@(0)
136 movel %d0,%sp@(PT_OFF_D0) | save the return value
137ret_from_syscall:
138 |oriw #0x0700,%sr
139 movel %curptr@(TASK_STACK),%a1
140 movew %a1@(TINFO_FLAGS+2),%d0
141 jne syscall_exit_work
1421: RESTORE_ALL
143
144syscall_exit_work:
145 btst #5,%sp@(PT_OFF_SR) | check if returning to kernel
146 bnes 1b | if so, skip resched, signals
147 lslw #1,%d0
148 jcs do_trace_exit
149 jmi do_delayed_trace
150 lslw #8,%d0
151 jne do_signal_return
152 pea resume_userspace
153 jra schedule
154
155
156ENTRY(ret_from_exception)
157.Lret_from_exception:
158 btst #5,%sp@(PT_OFF_SR) | check if returning to kernel
159 bnes 1f | if so, skip resched, signals
160 | only allow interrupts when we are really the last one on the
161 | kernel stack, otherwise stack overflow can occur during
162 | heavy interrupt load
163 andw #ALLOWINT,%sr
164
165resume_userspace:
166 movel %curptr@(TASK_STACK),%a1
167 moveb %a1@(TINFO_FLAGS+3),%d0
168 jne exit_work
1691: RESTORE_ALL
170
171exit_work:
172 | save top of frame
173 movel %sp,%curptr@(TASK_THREAD+THREAD_ESP0)
174 lslb #1,%d0
175 jne do_signal_return
176 pea resume_userspace
177 jra schedule
178
179
180do_signal_return:
181 |andw #ALLOWINT,%sr
182 subql #4,%sp | dummy return address
183 SAVE_SWITCH_STACK
184 pea %sp@(SWITCH_STACK_SIZE)
185 bsrl do_notify_resume
186 addql #4,%sp
187 RESTORE_SWITCH_STACK
188 addql #4,%sp
189 jbra resume_userspace
190
191do_delayed_trace:
192 bclr #7,%sp@(PT_OFF_SR) | clear trace bit in SR
193 pea 1 | send SIGTRAP
194 movel %curptr,%sp@-
195 pea LSIGTRAP
196 jbsr send_sig
197 addql #8,%sp
198 addql #4,%sp
199 jbra resume_userspace
200
201
202/* This is the main interrupt handler for autovector interrupts */
203
204ENTRY(auto_inthandler)
205 SAVE_ALL_INT
206 GET_CURRENT(%d0)
207 movel %d0,%a1
208 addqb #1,%a1@(TINFO_PREEMPT+1)
209 | put exception # in d0
210 bfextu %sp@(PT_OFF_FORMATVEC){#4,#10},%d0
211 subw #VEC_SPUR,%d0
212
213 movel %sp,%sp@-
214 movel %d0,%sp@- | put vector # on stack
215auto_irqhandler_fixup = . + 2
216 jsr do_IRQ | process the IRQ
217 addql #8,%sp | pop parameters off stack
218
219ret_from_interrupt:
220 movel %curptr@(TASK_STACK),%a1
221 subqb #1,%a1@(TINFO_PREEMPT+1)
222 jeq ret_from_last_interrupt
2232: RESTORE_ALL
224
225 ALIGN
226ret_from_last_interrupt:
227 moveq #(~ALLOWINT>>8)&0xff,%d0
228 andb %sp@(PT_OFF_SR),%d0
229 jne 2b
230
231 /* check if we need to do software interrupts */
232 tstl irq_stat+CPUSTAT_SOFTIRQ_PENDING
233 jeq .Lret_from_exception
234 pea ret_from_exception
235 jra do_softirq
236
237/* Handler for user defined interrupt vectors */
238
239ENTRY(user_inthandler)
240 SAVE_ALL_INT
241 GET_CURRENT(%d0)
242 movel %d0,%a1
243 addqb #1,%a1@(TINFO_PREEMPT+1)
244 | put exception # in d0
245 bfextu %sp@(PT_OFF_FORMATVEC){#4,#10},%d0
246user_irqvec_fixup = . + 2
247 subw #VEC_USER,%d0
248
249 movel %sp,%sp@-
250 movel %d0,%sp@- | put vector # on stack
251 jsr do_IRQ | process the IRQ
252 addql #8,%sp | pop parameters off stack
253
254 movel %curptr@(TASK_STACK),%a1
255 subqb #1,%a1@(TINFO_PREEMPT+1)
256 jeq ret_from_last_interrupt
257 RESTORE_ALL
258
259/* Handler for uninitialized and spurious interrupts */
260
261ENTRY(bad_inthandler)
262 SAVE_ALL_INT
263 GET_CURRENT(%d0)
264 movel %d0,%a1
265 addqb #1,%a1@(TINFO_PREEMPT+1)
266
267 movel %sp,%sp@-
268 jsr handle_badint
269 addql #4,%sp
270
271 movel %curptr@(TASK_STACK),%a1
272 subqb #1,%a1@(TINFO_PREEMPT+1)
273 jeq ret_from_last_interrupt
274 RESTORE_ALL
275
276
277ENTRY(sys_fork)
278 SAVE_SWITCH_STACK
279 pea %sp@(SWITCH_STACK_SIZE)
280 jbsr m68k_fork
281 addql #4,%sp
282 RESTORE_SWITCH_STACK
283 rts
284
285ENTRY(sys_clone)
286 SAVE_SWITCH_STACK
287 pea %sp@(SWITCH_STACK_SIZE)
288 jbsr m68k_clone
289 addql #4,%sp
290 RESTORE_SWITCH_STACK
291 rts
292
293ENTRY(sys_vfork)
294 SAVE_SWITCH_STACK
295 pea %sp@(SWITCH_STACK_SIZE)
296 jbsr m68k_vfork
297 addql #4,%sp
298 RESTORE_SWITCH_STACK
299 rts
300
301ENTRY(sys_sigreturn)
302 SAVE_SWITCH_STACK
303 jbsr do_sigreturn
304 RESTORE_SWITCH_STACK
305 rts
306
307ENTRY(sys_rt_sigreturn)
308 SAVE_SWITCH_STACK
309 jbsr do_rt_sigreturn
310 RESTORE_SWITCH_STACK
311 rts
312
313resume:
314 /*
315 * Beware - when entering resume, prev (the current task) is
316 * in a0, next (the new task) is in a1,so don't change these
317 * registers until their contents are no longer needed.
318 */
319
320 /* save sr */
321 movew %sr,%a0@(TASK_THREAD+THREAD_SR)
322
323 /* save fs (sfc,%dfc) (may be pointing to kernel memory) */
324 movec %sfc,%d0
325 movew %d0,%a0@(TASK_THREAD+THREAD_FS)
326
327 /* save usp */
328 /* it is better to use a movel here instead of a movew 8*) */
329 movec %usp,%d0
330 movel %d0,%a0@(TASK_THREAD+THREAD_USP)
331
332 /* save non-scratch registers on stack */
333 SAVE_SWITCH_STACK
334
335 /* save current kernel stack pointer */
336 movel %sp,%a0@(TASK_THREAD+THREAD_KSP)
337
338 /* save floating point context */
339#ifndef CONFIG_M68KFPU_EMU_ONLY
340#ifdef CONFIG_M68KFPU_EMU
341 tstl m68k_fputype
342 jeq 3f
343#endif
344 fsave %a0@(TASK_THREAD+THREAD_FPSTATE)
345
346#if defined(CONFIG_M68060)
347#if !defined(CPU_M68060_ONLY)
348 btst #3,m68k_cputype+3
349 beqs 1f
350#endif
351 /* The 060 FPU keeps status in bits 15-8 of the first longword */
352 tstb %a0@(TASK_THREAD+THREAD_FPSTATE+2)
353 jeq 3f
354#if !defined(CPU_M68060_ONLY)
355 jra 2f
356#endif
357#endif /* CONFIG_M68060 */
358#if !defined(CPU_M68060_ONLY)
3591: tstb %a0@(TASK_THREAD+THREAD_FPSTATE)
360 jeq 3f
361#endif
3622: fmovemx %fp0-%fp7,%a0@(TASK_THREAD+THREAD_FPREG)
363 fmoveml %fpcr/%fpsr/%fpiar,%a0@(TASK_THREAD+THREAD_FPCNTL)
3643:
365#endif /* CONFIG_M68KFPU_EMU_ONLY */
366 /* Return previous task in %d1 */
367 movel %curptr,%d1
368
369 /* switch to new task (a1 contains new task) */
370 movel %a1,%curptr
371
372 /* restore floating point context */
373#ifndef CONFIG_M68KFPU_EMU_ONLY
374#ifdef CONFIG_M68KFPU_EMU
375 tstl m68k_fputype
376 jeq 4f
377#endif
378#if defined(CONFIG_M68060)
379#if !defined(CPU_M68060_ONLY)
380 btst #3,m68k_cputype+3
381 beqs 1f
382#endif
383 /* The 060 FPU keeps status in bits 15-8 of the first longword */
384 tstb %a1@(TASK_THREAD+THREAD_FPSTATE+2)
385 jeq 3f
386#if !defined(CPU_M68060_ONLY)
387 jra 2f
388#endif
389#endif /* CONFIG_M68060 */
390#if !defined(CPU_M68060_ONLY)
3911: tstb %a1@(TASK_THREAD+THREAD_FPSTATE)
392 jeq 3f
393#endif
3942: fmovemx %a1@(TASK_THREAD+THREAD_FPREG),%fp0-%fp7
395 fmoveml %a1@(TASK_THREAD+THREAD_FPCNTL),%fpcr/%fpsr/%fpiar
3963: frestore %a1@(TASK_THREAD+THREAD_FPSTATE)
3974:
398#endif /* CONFIG_M68KFPU_EMU_ONLY */
399
400 /* restore the kernel stack pointer */
401 movel %a1@(TASK_THREAD+THREAD_KSP),%sp
402
403 /* restore non-scratch registers */
404 RESTORE_SWITCH_STACK
405
406 /* restore user stack pointer */
407 movel %a1@(TASK_THREAD+THREAD_USP),%a0
408 movel %a0,%usp
409
410 /* restore fs (sfc,%dfc) */
411 movew %a1@(TASK_THREAD+THREAD_FS),%a0
412 movec %a0,%sfc
413 movec %a0,%dfc
414
415 /* restore status register */
416 movew %a1@(TASK_THREAD+THREAD_SR),%sr
417
418 rts
419
diff --git a/arch/m68k/kernel/entry_no.S b/arch/m68k/kernel/entry_no.S
deleted file mode 100644
index d80cba45589f..000000000000
--- a/arch/m68k/kernel/entry_no.S
+++ /dev/null
@@ -1,130 +0,0 @@
1/*
2 * linux/arch/m68knommu/kernel/entry.S
3 *
4 * Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com)
5 * Copyright (C) 1998 D. Jeff Dionne <jeff@lineo.ca>,
6 * Kenneth Albanowski <kjahds@kjahds.com>,
7 * Copyright (C) 2000 Lineo Inc. (www.lineo.com)
8 *
9 * Based on:
10 *
11 * linux/arch/m68k/kernel/entry.S
12 *
13 * Copyright (C) 1991, 1992 Linus Torvalds
14 *
15 * This file is subject to the terms and conditions of the GNU General Public
16 * License. See the file README.legal in the main directory of this archive
17 * for more details.
18 *
19 * Linux/m68k support by Hamish Macdonald
20 *
21 * 68060 fixes by Jesper Skov
22 * ColdFire support by Greg Ungerer (gerg@snapgear.com)
23 * 5307 fixes by David W. Miller
24 * linux 2.4 support David McCullough <davidm@snapgear.com>
25 */
26
27#include <linux/linkage.h>
28#include <asm/errno.h>
29#include <asm/setup.h>
30#include <asm/segment.h>
31#include <asm/asm-offsets.h>
32#include <asm/entry.h>
33#include <asm/unistd.h>
34
35.text
36
37.globl buserr
38.globl trap
39.globl ret_from_exception
40.globl ret_from_signal
41.globl sys_fork
42.globl sys_clone
43.globl sys_vfork
44
45ENTRY(buserr)
46 SAVE_ALL_INT
47 GET_CURRENT(%d0)
48 movel %sp,%sp@- /* stack frame pointer argument */
49 jsr buserr_c
50 addql #4,%sp
51 jra ret_from_exception
52
53ENTRY(trap)
54 SAVE_ALL_INT
55 GET_CURRENT(%d0)
56 movel %sp,%sp@- /* stack frame pointer argument */
57 jsr trap_c
58 addql #4,%sp
59 jra ret_from_exception
60
61#ifdef TRAP_DBG_INTERRUPT
62
63.globl dbginterrupt
64ENTRY(dbginterrupt)
65 SAVE_ALL_INT
66 GET_CURRENT(%d0)
67 movel %sp,%sp@- /* stack frame pointer argument */
68 jsr dbginterrupt_c
69 addql #4,%sp
70 jra ret_from_exception
71#endif
72
73ENTRY(reschedule)
74 /* save top of frame */
75 pea %sp@
76 jbsr set_esp0
77 addql #4,%sp
78 pea ret_from_exception
79 jmp schedule
80
81ENTRY(ret_from_fork)
82 movel %d1,%sp@-
83 jsr schedule_tail
84 addql #4,%sp
85 jra ret_from_exception
86
87ENTRY(sys_fork)
88 SAVE_SWITCH_STACK
89 pea %sp@(SWITCH_STACK_SIZE)
90 jbsr m68k_fork
91 addql #4,%sp
92 RESTORE_SWITCH_STACK
93 rts
94
95ENTRY(sys_vfork)
96 SAVE_SWITCH_STACK
97 pea %sp@(SWITCH_STACK_SIZE)
98 jbsr m68k_vfork
99 addql #4,%sp
100 RESTORE_SWITCH_STACK
101 rts
102
103ENTRY(sys_clone)
104 SAVE_SWITCH_STACK
105 pea %sp@(SWITCH_STACK_SIZE)
106 jbsr m68k_clone
107 addql #4,%sp
108 RESTORE_SWITCH_STACK
109 rts
110
111ENTRY(sys_sigreturn)
112 SAVE_SWITCH_STACK
113 jbsr do_sigreturn
114 RESTORE_SWITCH_STACK
115 rts
116
117ENTRY(sys_rt_sigreturn)
118 SAVE_SWITCH_STACK
119 jbsr do_rt_sigreturn
120 RESTORE_SWITCH_STACK
121 rts
122
123ENTRY(ret_from_user_signal)
124 moveq #__NR_sigreturn,%d0
125 trap #0
126
127ENTRY(ret_from_user_rt_signal)
128 movel #__NR_rt_sigreturn,%d0
129 trap #0
130
diff --git a/arch/m68k/kernel/module.c b/arch/m68k/kernel/module.c
index 34849c4c6e3d..eb46fd6038ca 100644
--- a/arch/m68k/kernel/module.c
+++ b/arch/m68k/kernel/module.c
@@ -47,7 +47,7 @@ int apply_relocate(Elf32_Shdr *sechdrs,
47 *location += sym->st_value; 47 *location += sym->st_value;
48 break; 48 break;
49 case R_68K_PC32: 49 case R_68K_PC32:
50 /* Add the value, subtract its postition */ 50 /* Add the value, subtract its position */
51 *location += sym->st_value - (uint32_t)location; 51 *location += sym->st_value - (uint32_t)location;
52 break; 52 break;
53 default: 53 default:
@@ -87,7 +87,7 @@ int apply_relocate_add(Elf32_Shdr *sechdrs,
87 *location = rel[i].r_addend + sym->st_value; 87 *location = rel[i].r_addend + sym->st_value;
88 break; 88 break;
89 case R_68K_PC32: 89 case R_68K_PC32:
90 /* Add the value, subtract its postition */ 90 /* Add the value, subtract its position */
91 *location = rel[i].r_addend + sym->st_value - (uint32_t)location; 91 *location = rel[i].r_addend + sym->st_value - (uint32_t)location;
92 break; 92 break;
93 default: 93 default:
diff --git a/arch/m68k/kernel/pcibios.c b/arch/m68k/kernel/pcibios.c
new file mode 100644
index 000000000000..b2988aa1840b
--- /dev/null
+++ b/arch/m68k/kernel/pcibios.c
@@ -0,0 +1,109 @@
1/*
2 * pci.c -- basic PCI support code
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 *
9 * (C) Copyright 2011, Greg Ungerer <gerg@uclinux.org>
10 */
11
12#include <linux/kernel.h>
13#include <linux/types.h>
14#include <linux/mm.h>
15#include <linux/init.h>
16#include <linux/pci.h>
17
18/*
19 * From arch/i386/kernel/pci-i386.c:
20 *
21 * We need to avoid collisions with `mirrored' VGA ports
22 * and other strange ISA hardware, so we always want the
23 * addresses to be allocated in the 0x000-0x0ff region
24 * modulo 0x400.
25 *
26 * Why? Because some silly external IO cards only decode
27 * the low 10 bits of the IO address. The 0x00-0xff region
28 * is reserved for motherboard devices that decode all 16
29 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
30 * but we want to try to avoid allocating at 0x2900-0x2bff
31 * which might be mirrored at 0x0100-0x03ff..
32 */
33resource_size_t pcibios_align_resource(void *data, const struct resource *res,
34 resource_size_t size, resource_size_t align)
35{
36 resource_size_t start = res->start;
37
38 if ((res->flags & IORESOURCE_IO) && (start & 0x300))
39 start = (start + 0x3ff) & ~0x3ff;
40
41 start = (start + align - 1) & ~(align - 1);
42
43 return start;
44}
45
46/*
47 * This is taken from the ARM code for this.
48 */
49int pcibios_enable_device(struct pci_dev *dev, int mask)
50{
51 struct resource *r;
52 u16 cmd, newcmd;
53 int idx;
54
55 pci_read_config_word(dev, PCI_COMMAND, &cmd);
56 newcmd = cmd;
57
58 for (idx = 0; idx < 6; idx++) {
59 /* Only set up the requested stuff */
60 if (!(mask & (1 << idx)))
61 continue;
62
63 r = dev->resource + idx;
64 if (!r->start && r->end) {
65 pr_err(KERN_ERR "PCI: Device %s not available because of resource collisions\n",
66 pci_name(dev));
67 return -EINVAL;
68 }
69 if (r->flags & IORESOURCE_IO)
70 newcmd |= PCI_COMMAND_IO;
71 if (r->flags & IORESOURCE_MEM)
72 newcmd |= PCI_COMMAND_MEMORY;
73 }
74
75 /*
76 * Bridges (eg, cardbus bridges) need to be fully enabled
77 */
78 if ((dev->class >> 16) == PCI_BASE_CLASS_BRIDGE)
79 newcmd |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
80
81
82 if (newcmd != cmd) {
83 pr_info("PCI: enabling device %s (0x%04x -> 0x%04x)\n",
84 pci_name(dev), cmd, newcmd);
85 pci_write_config_word(dev, PCI_COMMAND, newcmd);
86 }
87 return 0;
88}
89
90void pcibios_update_irq(struct pci_dev *dev, int irq)
91{
92 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
93}
94
95void __devinit pcibios_fixup_bus(struct pci_bus *bus)
96{
97 struct pci_dev *dev;
98
99 list_for_each_entry(dev, &bus->devices, bus_list) {
100 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8);
101 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 32);
102 }
103}
104
105char __devinit *pcibios_setup(char *str)
106{
107 return str;
108}
109
diff --git a/arch/m68k/mm/memory.c b/arch/m68k/mm/memory.c
index 250b8b786f4f..51bc9d258ede 100644
--- a/arch/m68k/mm/memory.c
+++ b/arch/m68k/mm/memory.c
@@ -203,7 +203,7 @@ static inline void pushcl040(unsigned long paddr)
203void cache_clear (unsigned long paddr, int len) 203void cache_clear (unsigned long paddr, int len)
204{ 204{
205 if (CPU_IS_COLDFIRE) { 205 if (CPU_IS_COLDFIRE) {
206 flush_cf_bcache(0, DCACHE_MAX_ADDR); 206 clear_cf_bcache(0, DCACHE_MAX_ADDR);
207 } else if (CPU_IS_040_OR_060) { 207 } else if (CPU_IS_040_OR_060) {
208 int tmp; 208 int tmp;
209 209
diff --git a/arch/m68k/platform/coldfire/Makefile b/arch/m68k/platform/coldfire/Makefile
index 76d389d9a84e..02591a109f8c 100644
--- a/arch/m68k/platform/coldfire/Makefile
+++ b/arch/m68k/platform/coldfire/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_M5206e) += m5206.o timers.o intc.o reset.o
20obj-$(CONFIG_M520x) += m520x.o pit.o intc-simr.o reset.o 20obj-$(CONFIG_M520x) += m520x.o pit.o intc-simr.o reset.o
21obj-$(CONFIG_M523x) += m523x.o pit.o dma_timer.o intc-2.o reset.o 21obj-$(CONFIG_M523x) += m523x.o pit.o dma_timer.o intc-2.o reset.o
22obj-$(CONFIG_M5249) += m5249.o timers.o intc.o intc-5249.o reset.o 22obj-$(CONFIG_M5249) += m5249.o timers.o intc.o intc-5249.o reset.o
23obj-$(CONFIG_M525x) += m525x.o timers.o intc.o intc-525x.o reset.o
23obj-$(CONFIG_M527x) += m527x.o pit.o intc-2.o reset.o 24obj-$(CONFIG_M527x) += m527x.o pit.o intc-2.o reset.o
24obj-$(CONFIG_M5272) += m5272.o intc-5272.o timers.o 25obj-$(CONFIG_M5272) += m5272.o intc-5272.o timers.o
25obj-$(CONFIG_M528x) += m528x.o pit.o intc-2.o reset.o 26obj-$(CONFIG_M528x) += m528x.o pit.o intc-2.o reset.o
@@ -27,10 +28,14 @@ obj-$(CONFIG_M5307) += m5307.o timers.o intc.o reset.o
27obj-$(CONFIG_M532x) += m532x.o timers.o intc-simr.o reset.o 28obj-$(CONFIG_M532x) += m532x.o timers.o intc-simr.o reset.o
28obj-$(CONFIG_M5407) += m5407.o timers.o intc.o reset.o 29obj-$(CONFIG_M5407) += m5407.o timers.o intc.o reset.o
29obj-$(CONFIG_M54xx) += m54xx.o sltimers.o intc-2.o 30obj-$(CONFIG_M54xx) += m54xx.o sltimers.o intc-2.o
31obj-$(CONFIG_M5441x) += m5441x.o pit.o intc-simr.o reset.o
30 32
31obj-$(CONFIG_NETtel) += nettel.o 33obj-$(CONFIG_NETtel) += nettel.o
32obj-$(CONFIG_CLEOPATRA) += nettel.o 34obj-$(CONFIG_CLEOPATRA) += nettel.o
33obj-$(CONFIG_FIREBEE) += firebee.o 35obj-$(CONFIG_FIREBEE) += firebee.o
36obj-$(CONFIG_MCF8390) += mcf8390.o
34 37
35obj-y += pinmux.o gpio.o 38obj-$(CONFIG_PCI) += pci.o
39
40obj-y += gpio.o
36extra-y := head.o 41extra-y := head.o
diff --git a/arch/m68k/platform/coldfire/clk.c b/arch/m68k/platform/coldfire/clk.c
index 9f1260c5e2ad..75f9ee967ea7 100644
--- a/arch/m68k/platform/coldfire/clk.c
+++ b/arch/m68k/platform/coldfire/clk.c
@@ -10,11 +10,17 @@
10 10
11#include <linux/kernel.h> 11#include <linux/kernel.h>
12#include <linux/module.h> 12#include <linux/module.h>
13#include <linux/platform_device.h>
14#include <linux/mutex.h>
13#include <linux/clk.h> 15#include <linux/clk.h>
16#include <linux/io.h>
17#include <linux/err.h>
14#include <asm/coldfire.h> 18#include <asm/coldfire.h>
19#include <asm/mcfsim.h>
20#include <asm/mcfclk.h>
15 21
16/***************************************************************************/ 22/***************************************************************************/
17 23#ifndef MCFPM_PPMCR0
18struct clk *clk_get(struct device *dev, const char *id) 24struct clk *clk_get(struct device *dev, const char *id)
19{ 25{
20 return NULL; 26 return NULL;
@@ -42,4 +48,107 @@ unsigned long clk_get_rate(struct clk *clk)
42 return MCF_CLK; 48 return MCF_CLK;
43} 49}
44EXPORT_SYMBOL(clk_get_rate); 50EXPORT_SYMBOL(clk_get_rate);
51#else
52static DEFINE_SPINLOCK(clk_lock);
53
54struct clk *clk_get(struct device *dev, const char *id)
55{
56 const char *clk_name = dev ? dev_name(dev) : id ? id : NULL;
57 struct clk *clk;
58 unsigned i;
59
60 for (i = 0; (clk = mcf_clks[i]) != NULL; ++i)
61 if (!strcmp(clk->name, clk_name))
62 return clk;
63 pr_warn("clk_get: didn't find clock %s\n", clk_name);
64 return ERR_PTR(-ENOENT);
65}
66EXPORT_SYMBOL(clk_get);
67
68int clk_enable(struct clk *clk)
69{
70 unsigned long flags;
71 spin_lock_irqsave(&clk_lock, flags);
72 if ((clk->enabled++ == 0) && clk->clk_ops)
73 clk->clk_ops->enable(clk);
74 spin_unlock_irqrestore(&clk_lock, flags);
75
76 return 0;
77}
78EXPORT_SYMBOL(clk_enable);
79
80void clk_disable(struct clk *clk)
81{
82 unsigned long flags;
83 spin_lock_irqsave(&clk_lock, flags);
84 if ((--clk->enabled == 0) && clk->clk_ops)
85 clk->clk_ops->disable(clk);
86 spin_unlock_irqrestore(&clk_lock, flags);
87}
88EXPORT_SYMBOL(clk_disable);
89
90void clk_put(struct clk *clk)
91{
92 if (clk->enabled != 0)
93 pr_warn("clk_put %s still enabled\n", clk->name);
94}
95EXPORT_SYMBOL(clk_put);
96
97unsigned long clk_get_rate(struct clk *clk)
98{
99 return clk->rate;
100}
101EXPORT_SYMBOL(clk_get_rate);
102
45/***************************************************************************/ 103/***************************************************************************/
104
105void __clk_init_enabled(struct clk *clk)
106{
107 clk->enabled = 1;
108 clk->clk_ops->enable(clk);
109}
110
111void __clk_init_disabled(struct clk *clk)
112{
113 clk->enabled = 0;
114 clk->clk_ops->disable(clk);
115}
116
117static void __clk_enable0(struct clk *clk)
118{
119 __raw_writeb(clk->slot, MCFPM_PPMCR0);
120}
121
122static void __clk_disable0(struct clk *clk)
123{
124 __raw_writeb(clk->slot, MCFPM_PPMSR0);
125}
126
127struct clk_ops clk_ops0 = {
128 .enable = __clk_enable0,
129 .disable = __clk_disable0,
130};
131
132#ifdef MCFPM_PPMCR1
133static void __clk_enable1(struct clk *clk)
134{
135 __raw_writeb(clk->slot, MCFPM_PPMCR1);
136}
137
138static void __clk_disable1(struct clk *clk)
139{
140 __raw_writeb(clk->slot, MCFPM_PPMSR1);
141}
142
143struct clk_ops clk_ops1 = {
144 .enable = __clk_enable1,
145 .disable = __clk_disable1,
146};
147#endif /* MCFPM_PPMCR1 */
148#endif /* MCFPM_PPMCR0 */
149
150struct clk *devm_clk_get(struct device *dev, const char *id)
151{
152 return NULL;
153}
154EXPORT_SYMBOL(devm_clk_get);
diff --git a/arch/m68k/platform/coldfire/device.c b/arch/m68k/platform/coldfire/device.c
index 3aa77ddea89d..81f0fb5e51cf 100644
--- a/arch/m68k/platform/coldfire/device.c
+++ b/arch/m68k/platform/coldfire/device.c
@@ -13,6 +13,7 @@
13#include <linux/io.h> 13#include <linux/io.h>
14#include <linux/spi/spi.h> 14#include <linux/spi/spi.h>
15#include <linux/gpio.h> 15#include <linux/gpio.h>
16#include <linux/fec.h>
16#include <asm/traps.h> 17#include <asm/traps.h>
17#include <asm/coldfire.h> 18#include <asm/coldfire.h>
18#include <asm/mcfsim.h> 19#include <asm/mcfsim.h>
@@ -20,7 +21,7 @@
20#include <asm/mcfqspi.h> 21#include <asm/mcfqspi.h>
21 22
22/* 23/*
23 * All current ColdFire parts contain from 2, 3 or 4 UARTS. 24 * All current ColdFire parts contain from 2, 3, 4 or 10 UARTS.
24 */ 25 */
25static struct mcf_platform_uart mcf_uart_platform_data[] = { 26static struct mcf_platform_uart mcf_uart_platform_data[] = {
26 { 27 {
@@ -43,6 +44,42 @@ static struct mcf_platform_uart mcf_uart_platform_data[] = {
43 .irq = MCF_IRQ_UART3, 44 .irq = MCF_IRQ_UART3,
44 }, 45 },
45#endif 46#endif
47#ifdef MCFUART_BASE4
48 {
49 .mapbase = MCFUART_BASE4,
50 .irq = MCF_IRQ_UART4,
51 },
52#endif
53#ifdef MCFUART_BASE5
54 {
55 .mapbase = MCFUART_BASE5,
56 .irq = MCF_IRQ_UART5,
57 },
58#endif
59#ifdef MCFUART_BASE6
60 {
61 .mapbase = MCFUART_BASE6,
62 .irq = MCF_IRQ_UART6,
63 },
64#endif
65#ifdef MCFUART_BASE7
66 {
67 .mapbase = MCFUART_BASE7,
68 .irq = MCF_IRQ_UART7,
69 },
70#endif
71#ifdef MCFUART_BASE8
72 {
73 .mapbase = MCFUART_BASE8,
74 .irq = MCF_IRQ_UART8,
75 },
76#endif
77#ifdef MCFUART_BASE9
78 {
79 .mapbase = MCFUART_BASE9,
80 .irq = MCF_IRQ_UART9,
81 },
82#endif
46 { }, 83 { },
47}; 84};
48 85
@@ -53,6 +90,18 @@ static struct platform_device mcf_uart = {
53}; 90};
54 91
55#ifdef CONFIG_FEC 92#ifdef CONFIG_FEC
93
94#ifdef CONFIG_M5441x
95#define FEC_NAME "enet-fec"
96static struct fec_platform_data fec_pdata = {
97 .phy = PHY_INTERFACE_MODE_RMII,
98};
99#define FEC_PDATA (&fec_pdata)
100#else
101#define FEC_NAME "fec"
102#define FEC_PDATA NULL
103#endif
104
56/* 105/*
57 * Some ColdFire cores contain the Fast Ethernet Controller (FEC) 106 * Some ColdFire cores contain the Fast Ethernet Controller (FEC)
58 * block. It is Freescale's own hardware block. Some ColdFires 107 * block. It is Freescale's own hardware block. Some ColdFires
@@ -82,10 +131,11 @@ static struct resource mcf_fec0_resources[] = {
82}; 131};
83 132
84static struct platform_device mcf_fec0 = { 133static struct platform_device mcf_fec0 = {
85 .name = "fec", 134 .name = FEC_NAME,
86 .id = 0, 135 .id = 0,
87 .num_resources = ARRAY_SIZE(mcf_fec0_resources), 136 .num_resources = ARRAY_SIZE(mcf_fec0_resources),
88 .resource = mcf_fec0_resources, 137 .resource = mcf_fec0_resources,
138 .dev.platform_data = FEC_PDATA,
89}; 139};
90 140
91#ifdef MCFFEC_BASE1 141#ifdef MCFFEC_BASE1
@@ -113,10 +163,11 @@ static struct resource mcf_fec1_resources[] = {
113}; 163};
114 164
115static struct platform_device mcf_fec1 = { 165static struct platform_device mcf_fec1 = {
116 .name = "fec", 166 .name = FEC_NAME,
117 .id = 1, 167 .id = 1,
118 .num_resources = ARRAY_SIZE(mcf_fec1_resources), 168 .num_resources = ARRAY_SIZE(mcf_fec1_resources),
119 .resource = mcf_fec1_resources, 169 .resource = mcf_fec1_resources,
170 .dev.platform_data = FEC_PDATA,
120}; 171};
121#endif /* MCFFEC_BASE1 */ 172#endif /* MCFFEC_BASE1 */
122#endif /* CONFIG_FEC */ 173#endif /* CONFIG_FEC */
diff --git a/arch/m68k/platform/coldfire/gpio.c b/arch/m68k/platform/coldfire/gpio.c
index 4c8c42450a4e..9cd2b5c70519 100644
--- a/arch/m68k/platform/coldfire/gpio.c
+++ b/arch/m68k/platform/coldfire/gpio.c
@@ -14,119 +14,161 @@
14 */ 14 */
15 15
16#include <linux/kernel.h> 16#include <linux/kernel.h>
17#include <linux/module.h>
17#include <linux/init.h> 18#include <linux/init.h>
18#include <linux/device.h> 19#include <linux/device.h>
19 20
20#include <asm/gpio.h> 21#include <linux/io.h>
21#include <asm/pinmux.h> 22#include <asm/coldfire.h>
23#include <asm/mcfsim.h>
22#include <asm/mcfgpio.h> 24#include <asm/mcfgpio.h>
23 25
24#define MCF_CHIP(chip) container_of(chip, struct mcf_gpio_chip, gpio_chip) 26int __mcfgpio_get_value(unsigned gpio)
27{
28 return mcfgpio_read(__mcfgpio_ppdr(gpio)) & mcfgpio_bit(gpio);
29}
30EXPORT_SYMBOL(__mcfgpio_get_value);
31
32void __mcfgpio_set_value(unsigned gpio, int value)
33{
34 if (gpio < MCFGPIO_SCR_START) {
35 unsigned long flags;
36 MCFGPIO_PORTTYPE data;
37
38 local_irq_save(flags);
39 data = mcfgpio_read(__mcfgpio_podr(gpio));
40 if (value)
41 data |= mcfgpio_bit(gpio);
42 else
43 data &= ~mcfgpio_bit(gpio);
44 mcfgpio_write(data, __mcfgpio_podr(gpio));
45 local_irq_restore(flags);
46 } else {
47 if (value)
48 mcfgpio_write(mcfgpio_bit(gpio),
49 MCFGPIO_SETR_PORT(gpio));
50 else
51 mcfgpio_write(~mcfgpio_bit(gpio),
52 MCFGPIO_CLRR_PORT(gpio));
53 }
54}
55EXPORT_SYMBOL(__mcfgpio_set_value);
25 56
26int mcf_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 57int __mcfgpio_direction_input(unsigned gpio)
27{ 58{
28 unsigned long flags; 59 unsigned long flags;
29 MCFGPIO_PORTTYPE dir; 60 MCFGPIO_PORTTYPE dir;
30 struct mcf_gpio_chip *mcf_chip = MCF_CHIP(chip);
31 61
32 local_irq_save(flags); 62 local_irq_save(flags);
33 dir = mcfgpio_read(mcf_chip->pddr); 63 dir = mcfgpio_read(__mcfgpio_pddr(gpio));
34 dir &= ~mcfgpio_bit(chip->base + offset); 64 dir &= ~mcfgpio_bit(gpio);
35 mcfgpio_write(dir, mcf_chip->pddr); 65 mcfgpio_write(dir, __mcfgpio_pddr(gpio));
36 local_irq_restore(flags); 66 local_irq_restore(flags);
37 67
38 return 0; 68 return 0;
39} 69}
70EXPORT_SYMBOL(__mcfgpio_direction_input);
40 71
41int mcf_gpio_get_value(struct gpio_chip *chip, unsigned offset) 72int __mcfgpio_direction_output(unsigned gpio, int value)
42{
43 struct mcf_gpio_chip *mcf_chip = MCF_CHIP(chip);
44
45 return mcfgpio_read(mcf_chip->ppdr) & mcfgpio_bit(chip->base + offset);
46}
47
48int mcf_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
49 int value)
50{ 73{
51 unsigned long flags; 74 unsigned long flags;
52 MCFGPIO_PORTTYPE data; 75 MCFGPIO_PORTTYPE data;
53 struct mcf_gpio_chip *mcf_chip = MCF_CHIP(chip);
54 76
55 local_irq_save(flags); 77 local_irq_save(flags);
56 /* write the value to the output latch */ 78 data = mcfgpio_read(__mcfgpio_pddr(gpio));
57 data = mcfgpio_read(mcf_chip->podr);
58 if (value) 79 if (value)
59 data |= mcfgpio_bit(chip->base + offset); 80 data |= mcfgpio_bit(gpio);
60 else 81 else
61 data &= ~mcfgpio_bit(chip->base + offset); 82 data &= mcfgpio_bit(gpio);
62 mcfgpio_write(data, mcf_chip->podr); 83 mcfgpio_write(data, __mcfgpio_pddr(gpio));
63 84
64 /* now set the direction to output */ 85 /* now set the data to output */
65 data = mcfgpio_read(mcf_chip->pddr); 86 if (gpio < MCFGPIO_SCR_START) {
66 data |= mcfgpio_bit(chip->base + offset); 87 data = mcfgpio_read(__mcfgpio_podr(gpio));
67 mcfgpio_write(data, mcf_chip->pddr); 88 if (value)
89 data |= mcfgpio_bit(gpio);
90 else
91 data &= ~mcfgpio_bit(gpio);
92 mcfgpio_write(data, __mcfgpio_podr(gpio));
93 } else {
94 if (value)
95 mcfgpio_write(mcfgpio_bit(gpio),
96 MCFGPIO_SETR_PORT(gpio));
97 else
98 mcfgpio_write(~mcfgpio_bit(gpio),
99 MCFGPIO_CLRR_PORT(gpio));
100 }
68 local_irq_restore(flags); 101 local_irq_restore(flags);
102 return 0;
103}
104EXPORT_SYMBOL(__mcfgpio_direction_output);
69 105
106int __mcfgpio_request(unsigned gpio)
107{
70 return 0; 108 return 0;
71} 109}
110EXPORT_SYMBOL(__mcfgpio_request);
72 111
73void mcf_gpio_set_value(struct gpio_chip *chip, unsigned offset, int value) 112void __mcfgpio_free(unsigned gpio)
74{ 113{
75 struct mcf_gpio_chip *mcf_chip = MCF_CHIP(chip); 114 __mcfgpio_direction_input(gpio);
115}
116EXPORT_SYMBOL(__mcfgpio_free);
76 117
77 unsigned long flags; 118#ifdef CONFIG_GPIOLIB
78 MCFGPIO_PORTTYPE data;
79 119
80 local_irq_save(flags); 120int mcfgpio_direction_input(struct gpio_chip *chip, unsigned offset)
81 data = mcfgpio_read(mcf_chip->podr); 121{
82 if (value) 122 return __mcfgpio_direction_input(offset);
83 data |= mcfgpio_bit(chip->base + offset);
84 else
85 data &= ~mcfgpio_bit(chip->base + offset);
86 mcfgpio_write(data, mcf_chip->podr);
87 local_irq_restore(flags);
88} 123}
89 124
90void mcf_gpio_set_value_fast(struct gpio_chip *chip, unsigned offset, int value) 125int mcfgpio_get_value(struct gpio_chip *chip, unsigned offset)
91{ 126{
92 struct mcf_gpio_chip *mcf_chip = MCF_CHIP(chip); 127 return __mcfgpio_get_value(offset);
93
94 if (value)
95 mcfgpio_write(mcfgpio_bit(chip->base + offset), mcf_chip->setr);
96 else
97 mcfgpio_write(~mcfgpio_bit(chip->base + offset), mcf_chip->clrr);
98} 128}
99 129
100int mcf_gpio_request(struct gpio_chip *chip, unsigned offset) 130int mcfgpio_direction_output(struct gpio_chip *chip, unsigned offset, int value)
101{ 131{
102 struct mcf_gpio_chip *mcf_chip = MCF_CHIP(chip); 132 return __mcfgpio_direction_output(offset, value);
103
104 return mcf_chip->gpio_to_pinmux ?
105 mcf_pinmux_request(mcf_chip->gpio_to_pinmux[offset], 0) : 0;
106} 133}
107 134
108void mcf_gpio_free(struct gpio_chip *chip, unsigned offset) 135void mcfgpio_set_value(struct gpio_chip *chip, unsigned offset, int value)
109{ 136{
110 struct mcf_gpio_chip *mcf_chip = MCF_CHIP(chip); 137 __mcfgpio_set_value(offset, value);
138}
111 139
112 mcf_gpio_direction_input(chip, offset); 140int mcfgpio_request(struct gpio_chip *chip, unsigned offset)
141{
142 return __mcfgpio_request(offset);
143}
113 144
114 if (mcf_chip->gpio_to_pinmux) 145void mcfgpio_free(struct gpio_chip *chip, unsigned offset)
115 mcf_pinmux_release(mcf_chip->gpio_to_pinmux[offset], 0); 146{
147 __mcfgpio_free(offset);
116} 148}
117 149
118struct bus_type mcf_gpio_subsys = { 150struct bus_type mcfgpio_subsys = {
119 .name = "gpio", 151 .name = "gpio",
120 .dev_name = "gpio", 152 .dev_name = "gpio",
121}; 153};
122 154
123static int __init mcf_gpio_sysinit(void) 155static struct gpio_chip mcfgpio_chip = {
124{ 156 .label = "mcfgpio",
125 unsigned int i = 0; 157 .request = mcfgpio_request,
158 .free = mcfgpio_free,
159 .direction_input = mcfgpio_direction_input,
160 .direction_output = mcfgpio_direction_output,
161 .get = mcfgpio_get_value,
162 .set = mcfgpio_set_value,
163 .base = 0,
164 .ngpio = MCFGPIO_PIN_MAX,
165};
126 166
127 while (i < mcf_gpio_chips_size) 167static int __init mcfgpio_sysinit(void)
128 gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]); 168{
129 return subsys_system_register(&mcf_gpio_subsys, NULL); 169 gpiochip_add(&mcfgpio_chip);
170 return subsys_system_register(&mcfgpio_subsys, NULL);
130} 171}
131 172
132core_initcall(mcf_gpio_sysinit); 173core_initcall(mcfgpio_sysinit);
174#endif
diff --git a/arch/m68k/platform/coldfire/head.S b/arch/m68k/platform/coldfire/head.S
index c3db70ed33b3..4e0c9eb3bd1f 100644
--- a/arch/m68k/platform/coldfire/head.S
+++ b/arch/m68k/platform/coldfire/head.S
@@ -31,9 +31,9 @@
31.endm 31.endm
32 32
33#elif defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \ 33#elif defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
34 defined(CONFIG_M5249) || defined(CONFIG_M527x) || \ 34 defined(CONFIG_M5249) || defined(CONFIG_M525x) || \
35 defined(CONFIG_M528x) || defined(CONFIG_M5307) || \ 35 defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
36 defined(CONFIG_M5407) 36 defined(CONFIG_M5307) || defined(CONFIG_M5407)
37/* 37/*
38 * Not all these devices have exactly the same DRAM controller, 38 * Not all these devices have exactly the same DRAM controller,
39 * but the DCMR register is virtually identical - give or take 39 * but the DCMR register is virtually identical - give or take
diff --git a/arch/m68k/platform/coldfire/intc-525x.c b/arch/m68k/platform/coldfire/intc-525x.c
new file mode 100644
index 000000000000..b23204d059ac
--- /dev/null
+++ b/arch/m68k/platform/coldfire/intc-525x.c
@@ -0,0 +1,91 @@
1/*
2 * intc2.c -- support for the 2nd INTC controller of the 525x
3 *
4 * (C) Copyright 2012, Steven King <sfking@fdwdc.com>
5 * (C) Copyright 2009, Greg Ungerer <gerg@snapgear.com>
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file COPYING in the main directory of this archive
9 * for more details.
10 */
11
12#include <linux/types.h>
13#include <linux/init.h>
14#include <linux/kernel.h>
15#include <linux/interrupt.h>
16#include <linux/irq.h>
17#include <linux/io.h>
18#include <asm/coldfire.h>
19#include <asm/mcfsim.h>
20
21static void intc2_irq_gpio_mask(struct irq_data *d)
22{
23 u32 imr = readl(MCFSIM2_GPIOINTENABLE);
24 u32 type = irqd_get_trigger_type(d);
25 int irq = d->irq - MCF_IRQ_GPIO0;
26
27 if (type & IRQ_TYPE_EDGE_RISING)
28 imr &= ~(0x001 << irq);
29 if (type & IRQ_TYPE_EDGE_FALLING)
30 imr &= ~(0x100 << irq);
31 writel(imr, MCFSIM2_GPIOINTENABLE);
32}
33
34static void intc2_irq_gpio_unmask(struct irq_data *d)
35{
36 u32 imr = readl(MCFSIM2_GPIOINTENABLE);
37 u32 type = irqd_get_trigger_type(d);
38 int irq = d->irq - MCF_IRQ_GPIO0;
39
40 if (type & IRQ_TYPE_EDGE_RISING)
41 imr |= (0x001 << irq);
42 if (type & IRQ_TYPE_EDGE_FALLING)
43 imr |= (0x100 << irq);
44 writel(imr, MCFSIM2_GPIOINTENABLE);
45}
46
47static void intc2_irq_gpio_ack(struct irq_data *d)
48{
49 u32 imr = 0;
50 u32 type = irqd_get_trigger_type(d);
51 int irq = d->irq - MCF_IRQ_GPIO0;
52
53 if (type & IRQ_TYPE_EDGE_RISING)
54 imr |= (0x001 << irq);
55 if (type & IRQ_TYPE_EDGE_FALLING)
56 imr |= (0x100 << irq);
57 writel(imr, MCFSIM2_GPIOINTCLEAR);
58}
59
60static int intc2_irq_gpio_set_type(struct irq_data *d, unsigned int f)
61{
62 if (f & ~IRQ_TYPE_EDGE_BOTH)
63 return -EINVAL;
64 return 0;
65}
66
67static struct irq_chip intc2_irq_gpio_chip = {
68 .name = "CF-INTC2",
69 .irq_mask = intc2_irq_gpio_mask,
70 .irq_unmask = intc2_irq_gpio_unmask,
71 .irq_ack = intc2_irq_gpio_ack,
72 .irq_set_type = intc2_irq_gpio_set_type,
73};
74
75static int __init mcf_intc2_init(void)
76{
77 int irq;
78
79 /* set the interrupt base for the second interrupt controller */
80 writel(MCFINTC2_VECBASE, MCFINTC2_INTBASE);
81
82 /* GPIO interrupt sources */
83 for (irq = MCF_IRQ_GPIO0; (irq <= MCF_IRQ_GPIO6); irq++) {
84 irq_set_chip(irq, &intc2_irq_gpio_chip);
85 irq_set_handler(irq, handle_edge_irq);
86 }
87
88 return 0;
89}
90
91arch_initcall(mcf_intc2_init);
diff --git a/arch/m68k/platform/coldfire/intc-simr.c b/arch/m68k/platform/coldfire/intc-simr.c
index 650d52e2927e..7cf2c156f72d 100644
--- a/arch/m68k/platform/coldfire/intc-simr.c
+++ b/arch/m68k/platform/coldfire/intc-simr.c
@@ -59,16 +59,18 @@ static unsigned int inline irq2ebit(unsigned int irq)
59#endif 59#endif
60 60
61/* 61/*
62 * There maybe one or two interrupt control units, each has 64 62 * There maybe one, two or three interrupt control units, each has 64
63 * interrupts. If there is no second unit then MCFINTC1_* defines 63 * interrupts. If there is no second or third unit then MCFINTC1_* or
64 * will be 0 (and code for them optimized away). 64 * MCFINTC2_* defines will be 0 (and code for them optimized away).
65 */ 65 */
66 66
67static void intc_irq_mask(struct irq_data *d) 67static void intc_irq_mask(struct irq_data *d)
68{ 68{
69 unsigned int irq = d->irq - MCFINT_VECBASE; 69 unsigned int irq = d->irq - MCFINT_VECBASE;
70 70
71 if (MCFINTC1_SIMR && (irq > 64)) 71 if (MCFINTC2_SIMR && (irq > 128))
72 __raw_writeb(irq - 128, MCFINTC2_SIMR);
73 else if (MCFINTC1_SIMR && (irq > 64))
72 __raw_writeb(irq - 64, MCFINTC1_SIMR); 74 __raw_writeb(irq - 64, MCFINTC1_SIMR);
73 else 75 else
74 __raw_writeb(irq, MCFINTC0_SIMR); 76 __raw_writeb(irq, MCFINTC0_SIMR);
@@ -78,7 +80,9 @@ static void intc_irq_unmask(struct irq_data *d)
78{ 80{
79 unsigned int irq = d->irq - MCFINT_VECBASE; 81 unsigned int irq = d->irq - MCFINT_VECBASE;
80 82
81 if (MCFINTC1_CIMR && (irq > 64)) 83 if (MCFINTC2_CIMR && (irq > 128))
84 __raw_writeb(irq - 128, MCFINTC2_CIMR);
85 else if (MCFINTC1_CIMR && (irq > 64))
82 __raw_writeb(irq - 64, MCFINTC1_CIMR); 86 __raw_writeb(irq - 64, MCFINTC1_CIMR);
83 else 87 else
84 __raw_writeb(irq, MCFINTC0_CIMR); 88 __raw_writeb(irq, MCFINTC0_CIMR);
@@ -99,9 +103,11 @@ static unsigned int intc_irq_startup(struct irq_data *d)
99 unsigned int ebit = irq2ebit(irq); 103 unsigned int ebit = irq2ebit(irq);
100 u8 v; 104 u8 v;
101 105
106#if defined(MCFEPORT_EPDDR)
102 /* Set EPORT line as input */ 107 /* Set EPORT line as input */
103 v = __raw_readb(MCFEPORT_EPDDR); 108 v = __raw_readb(MCFEPORT_EPDDR);
104 __raw_writeb(v & ~(0x1 << ebit), MCFEPORT_EPDDR); 109 __raw_writeb(v & ~(0x1 << ebit), MCFEPORT_EPDDR);
110#endif
105 111
106 /* Set EPORT line as interrupt source */ 112 /* Set EPORT line as interrupt source */
107 v = __raw_readb(MCFEPORT_EPIER); 113 v = __raw_readb(MCFEPORT_EPIER);
@@ -109,12 +115,13 @@ static unsigned int intc_irq_startup(struct irq_data *d)
109 } 115 }
110 116
111 irq -= MCFINT_VECBASE; 117 irq -= MCFINT_VECBASE;
112 if (MCFINTC1_ICR0 && (irq > 64)) 118 if (MCFINTC2_ICR0 && (irq > 128))
119 __raw_writeb(5, MCFINTC2_ICR0 + irq - 128);
120 else if (MCFINTC1_ICR0 && (irq > 64))
113 __raw_writeb(5, MCFINTC1_ICR0 + irq - 64); 121 __raw_writeb(5, MCFINTC1_ICR0 + irq - 64);
114 else 122 else
115 __raw_writeb(5, MCFINTC0_ICR0 + irq); 123 __raw_writeb(5, MCFINTC0_ICR0 + irq);
116 124
117
118 intc_irq_unmask(d); 125 intc_irq_unmask(d);
119 return 0; 126 return 0;
120} 127}
@@ -175,8 +182,11 @@ void __init init_IRQ(void)
175 __raw_writeb(0xff, MCFINTC0_SIMR); 182 __raw_writeb(0xff, MCFINTC0_SIMR);
176 if (MCFINTC1_SIMR) 183 if (MCFINTC1_SIMR)
177 __raw_writeb(0xff, MCFINTC1_SIMR); 184 __raw_writeb(0xff, MCFINTC1_SIMR);
185 if (MCFINTC2_SIMR)
186 __raw_writeb(0xff, MCFINTC2_SIMR);
178 187
179 eirq = MCFINT_VECBASE + 64 + (MCFINTC1_ICR0 ? 64 : 0); 188 eirq = MCFINT_VECBASE + 64 + (MCFINTC1_ICR0 ? 64 : 0) +
189 (MCFINTC2_ICR0 ? 64 : 0);
180 for (irq = MCFINT_VECBASE; (irq < eirq); irq++) { 190 for (irq = MCFINT_VECBASE; (irq < eirq); irq++) {
181 if ((irq >= EINT1) && (irq <= EINT7)) 191 if ((irq >= EINT1) && (irq <= EINT7))
182 irq_set_chip(irq, &intc_irq_chip_edge_port); 192 irq_set_chip(irq, &intc_irq_chip_edge_port);
diff --git a/arch/m68k/platform/coldfire/m5206.c b/arch/m68k/platform/coldfire/m5206.c
index a8b81df653f0..6bfbeebd231b 100644
--- a/arch/m68k/platform/coldfire/m5206.c
+++ b/arch/m68k/platform/coldfire/m5206.c
@@ -16,15 +16,6 @@
16#include <asm/machdep.h> 16#include <asm/machdep.h>
17#include <asm/coldfire.h> 17#include <asm/coldfire.h>
18#include <asm/mcfsim.h> 18#include <asm/mcfsim.h>
19#include <asm/mcfgpio.h>
20
21/***************************************************************************/
22
23struct mcf_gpio_chip mcf_gpio_chips[] = {
24 MCFGPS(PP, 0, 8, MCFSIM_PADDR, MCFSIM_PADAT, MCFSIM_PADAT),
25};
26
27unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips);
28 19
29/***************************************************************************/ 20/***************************************************************************/
30 21
diff --git a/arch/m68k/platform/coldfire/m520x.c b/arch/m68k/platform/coldfire/m520x.c
index 3264b8883d5f..ea1be0e98ad6 100644
--- a/arch/m68k/platform/coldfire/m520x.c
+++ b/arch/m68k/platform/coldfire/m520x.c
@@ -19,22 +19,102 @@
19#include <asm/coldfire.h> 19#include <asm/coldfire.h>
20#include <asm/mcfsim.h> 20#include <asm/mcfsim.h>
21#include <asm/mcfuart.h> 21#include <asm/mcfuart.h>
22#include <asm/mcfgpio.h> 22#include <asm/mcfclk.h>
23 23
24/***************************************************************************/ 24/***************************************************************************/
25 25
26struct mcf_gpio_chip mcf_gpio_chips[] = { 26DEFINE_CLK(0, "flexbus", 2, MCF_CLK);
27 MCFGPS(PIRQ, 0, 8, MCFEPORT_EPDDR, MCFEPORT_EPDR, MCFEPORT_EPPDR), 27DEFINE_CLK(0, "fec.0", 12, MCF_CLK);
28 MCFGPF(CS, 9, 3), 28DEFINE_CLK(0, "edma", 17, MCF_CLK);
29 MCFGPF(FECI2C, 16, 4), 29DEFINE_CLK(0, "intc.0", 18, MCF_CLK);
30 MCFGPF(QSPI, 24, 4), 30DEFINE_CLK(0, "iack.0", 21, MCF_CLK);
31 MCFGPF(TIMER, 32, 4), 31DEFINE_CLK(0, "mcfi2c.0", 22, MCF_CLK);
32 MCFGPF(UART, 40, 8), 32DEFINE_CLK(0, "mcfqspi.0", 23, MCF_CLK);
33 MCFGPF(FECH, 48, 8), 33DEFINE_CLK(0, "mcfuart.0", 24, MCF_BUSCLK);
34 MCFGPF(FECL, 56, 8), 34DEFINE_CLK(0, "mcfuart.1", 25, MCF_BUSCLK);
35DEFINE_CLK(0, "mcfuart.2", 26, MCF_BUSCLK);
36DEFINE_CLK(0, "mcftmr.0", 28, MCF_CLK);
37DEFINE_CLK(0, "mcftmr.1", 29, MCF_CLK);
38DEFINE_CLK(0, "mcftmr.2", 30, MCF_CLK);
39DEFINE_CLK(0, "mcftmr.3", 31, MCF_CLK);
40
41DEFINE_CLK(0, "mcfpit.0", 32, MCF_CLK);
42DEFINE_CLK(0, "mcfpit.1", 33, MCF_CLK);
43DEFINE_CLK(0, "mcfeport.0", 34, MCF_CLK);
44DEFINE_CLK(0, "mcfwdt.0", 35, MCF_CLK);
45DEFINE_CLK(0, "pll.0", 36, MCF_CLK);
46DEFINE_CLK(0, "sys.0", 40, MCF_BUSCLK);
47DEFINE_CLK(0, "gpio.0", 41, MCF_BUSCLK);
48DEFINE_CLK(0, "sdram.0", 42, MCF_CLK);
49
50struct clk *mcf_clks[] = {
51 &__clk_0_2, /* flexbus */
52 &__clk_0_12, /* fec.0 */
53 &__clk_0_17, /* edma */
54 &__clk_0_18, /* intc.0 */
55 &__clk_0_21, /* iack.0 */
56 &__clk_0_22, /* mcfi2c.0 */
57 &__clk_0_23, /* mcfqspi.0 */
58 &__clk_0_24, /* mcfuart.0 */
59 &__clk_0_25, /* mcfuart.1 */
60 &__clk_0_26, /* mcfuart.2 */
61 &__clk_0_28, /* mcftmr.0 */
62 &__clk_0_29, /* mcftmr.1 */
63 &__clk_0_30, /* mcftmr.2 */
64 &__clk_0_31, /* mcftmr.3 */
65
66 &__clk_0_32, /* mcfpit.0 */
67 &__clk_0_33, /* mcfpit.1 */
68 &__clk_0_34, /* mcfeport.0 */
69 &__clk_0_35, /* mcfwdt.0 */
70 &__clk_0_36, /* pll.0 */
71 &__clk_0_40, /* sys.0 */
72 &__clk_0_41, /* gpio.0 */
73 &__clk_0_42, /* sdram.0 */
74NULL,
35}; 75};
36 76
37unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips); 77static struct clk * const enable_clks[] __initconst = {
78 &__clk_0_2, /* flexbus */
79 &__clk_0_18, /* intc.0 */
80 &__clk_0_21, /* iack.0 */
81 &__clk_0_24, /* mcfuart.0 */
82 &__clk_0_25, /* mcfuart.1 */
83 &__clk_0_26, /* mcfuart.2 */
84
85 &__clk_0_32, /* mcfpit.0 */
86 &__clk_0_33, /* mcfpit.1 */
87 &__clk_0_34, /* mcfeport.0 */
88 &__clk_0_36, /* pll.0 */
89 &__clk_0_40, /* sys.0 */
90 &__clk_0_41, /* gpio.0 */
91 &__clk_0_42, /* sdram.0 */
92};
93
94static struct clk * const disable_clks[] __initconst = {
95 &__clk_0_12, /* fec.0 */
96 &__clk_0_17, /* edma */
97 &__clk_0_22, /* mcfi2c.0 */
98 &__clk_0_23, /* mcfqspi.0 */
99 &__clk_0_28, /* mcftmr.0 */
100 &__clk_0_29, /* mcftmr.1 */
101 &__clk_0_30, /* mcftmr.2 */
102 &__clk_0_31, /* mcftmr.3 */
103 &__clk_0_35, /* mcfwdt.0 */
104};
105
106
107static void __init m520x_clk_init(void)
108{
109 unsigned i;
110
111 /* make sure these clocks are enabled */
112 for (i = 0; i < ARRAY_SIZE(enable_clks); ++i)
113 __clk_init_enabled(enable_clks[i]);
114 /* make sure these clocks are disabled */
115 for (i = 0; i < ARRAY_SIZE(disable_clks); ++i)
116 __clk_init_disabled(disable_clks[i]);
117}
38 118
39/***************************************************************************/ 119/***************************************************************************/
40 120
@@ -93,6 +173,7 @@ static void __init m520x_fec_init(void)
93void __init config_BSP(char *commandp, int size) 173void __init config_BSP(char *commandp, int size)
94{ 174{
95 mach_sched_init = hw_timer_init; 175 mach_sched_init = hw_timer_init;
176 m520x_clk_init();
96 m520x_uarts_init(); 177 m520x_uarts_init();
97 m520x_fec_init(); 178 m520x_fec_init();
98#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) 179#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
diff --git a/arch/m68k/platform/coldfire/m523x.c b/arch/m68k/platform/coldfire/m523x.c
index 5d57a4249412..d47dfd8f50a2 100644
--- a/arch/m68k/platform/coldfire/m523x.c
+++ b/arch/m68k/platform/coldfire/m523x.c
@@ -19,28 +19,6 @@
19#include <asm/machdep.h> 19#include <asm/machdep.h>
20#include <asm/coldfire.h> 20#include <asm/coldfire.h>
21#include <asm/mcfsim.h> 21#include <asm/mcfsim.h>
22#include <asm/mcfgpio.h>
23
24/***************************************************************************/
25
26struct mcf_gpio_chip mcf_gpio_chips[] = {
27 MCFGPS(PIRQ, 1, 7, MCFEPORT_EPDDR, MCFEPORT_EPDR, MCFEPORT_EPPDR),
28 MCFGPF(ADDR, 13, 3),
29 MCFGPF(DATAH, 16, 8),
30 MCFGPF(DATAL, 24, 8),
31 MCFGPF(BUSCTL, 32, 8),
32 MCFGPF(BS, 40, 4),
33 MCFGPF(CS, 49, 7),
34 MCFGPF(SDRAM, 56, 6),
35 MCFGPF(FECI2C, 64, 4),
36 MCFGPF(UARTH, 72, 2),
37 MCFGPF(UARTL, 80, 8),
38 MCFGPF(QSPI, 88, 5),
39 MCFGPF(TIMER, 96, 8),
40 MCFGPF(ETPU, 104, 3),
41};
42
43unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips);
44 22
45/***************************************************************************/ 23/***************************************************************************/
46 24
diff --git a/arch/m68k/platform/coldfire/m5249.c b/arch/m68k/platform/coldfire/m5249.c
index fdfa1edfd1ac..300e729a58d0 100644
--- a/arch/m68k/platform/coldfire/m5249.c
+++ b/arch/m68k/platform/coldfire/m5249.c
@@ -16,16 +16,6 @@
16#include <asm/machdep.h> 16#include <asm/machdep.h>
17#include <asm/coldfire.h> 17#include <asm/coldfire.h>
18#include <asm/mcfsim.h> 18#include <asm/mcfsim.h>
19#include <asm/mcfgpio.h>
20
21/***************************************************************************/
22
23struct mcf_gpio_chip mcf_gpio_chips[] = {
24 MCFGPS(GPIO0, 0, 32, MCFSIM2_GPIOENABLE, MCFSIM2_GPIOWRITE, MCFSIM2_GPIOREAD),
25 MCFGPS(GPIO1, 32, 32, MCFSIM2_GPIO1ENABLE, MCFSIM2_GPIO1WRITE, MCFSIM2_GPIO1READ),
26};
27
28unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips);
29 19
30/***************************************************************************/ 20/***************************************************************************/
31 21
diff --git a/arch/m68k/platform/coldfire/m525x.c b/arch/m68k/platform/coldfire/m525x.c
new file mode 100644
index 000000000000..8ce905f9b84f
--- /dev/null
+++ b/arch/m68k/platform/coldfire/m525x.c
@@ -0,0 +1,66 @@
1/***************************************************************************/
2
3/*
4 * 525x.c
5 *
6 * Copyright (C) 2012, Steven King <sfking@fdwdc.com>
7 */
8
9/***************************************************************************/
10
11#include <linux/kernel.h>
12#include <linux/param.h>
13#include <linux/init.h>
14#include <linux/io.h>
15#include <linux/platform_device.h>
16#include <asm/machdep.h>
17#include <asm/coldfire.h>
18#include <asm/mcfsim.h>
19
20/***************************************************************************/
21
22static void __init m525x_qspi_init(void)
23{
24#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
25 /* set the GPIO function for the qspi cs gpios */
26 /* FIXME: replace with pinmux/pinctl support */
27 u32 f = readl(MCFSIM2_GPIOFUNC);
28 f |= (1 << MCFQSPI_CS2) | (1 << MCFQSPI_CS1) | (1 << MCFQSPI_CS0);
29 writel(f, MCFSIM2_GPIOFUNC);
30
31 /* QSPI irq setup */
32 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL4 | MCFSIM_ICR_PRI0,
33 MCF_MBAR + MCFSIM_QSPIICR);
34 mcf_mapirq2imr(MCF_IRQ_QSPI, MCFINTC_QSPI);
35#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
36}
37
38static void __init m525x_i2c_init(void)
39{
40#if IS_ENABLED(CONFIG_I2C_COLDFIRE)
41 u32 r;
42
43 /* first I2C controller uses regular irq setup */
44 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI0,
45 MCF_MBAR + MCFSIM_I2CICR);
46 mcf_mapirq2imr(MCF_IRQ_I2C0, MCFINTC_I2C);
47
48 /* second I2C controller is completely different */
49 r = readl(MCFINTC2_INTPRI_REG(MCF_IRQ_I2C1));
50 r &= ~MCFINTC2_INTPRI_BITS(0xf, MCF_IRQ_I2C1);
51 r |= MCFINTC2_INTPRI_BITS(0x5, MCF_IRQ_I2C1);
52 writel(r, MCFINTC2_INTPRI_REG(MCF_IRQ_I2C1));
53#endif /* IS_ENABLED(CONFIG_I2C_COLDFIRE) */
54}
55
56/***************************************************************************/
57
58void __init config_BSP(char *commandp, int size)
59{
60 mach_sched_init = hw_timer_init;
61
62 m525x_qspi_init();
63 m525x_i2c_init();
64}
65
66/***************************************************************************/
diff --git a/arch/m68k/platform/coldfire/m5272.c b/arch/m68k/platform/coldfire/m5272.c
index 43e36060da18..e68bc7a148eb 100644
--- a/arch/m68k/platform/coldfire/m5272.c
+++ b/arch/m68k/platform/coldfire/m5272.c
@@ -19,7 +19,6 @@
19#include <asm/coldfire.h> 19#include <asm/coldfire.h>
20#include <asm/mcfsim.h> 20#include <asm/mcfsim.h>
21#include <asm/mcfuart.h> 21#include <asm/mcfuart.h>
22#include <asm/mcfgpio.h>
23 22
24/***************************************************************************/ 23/***************************************************************************/
25 24
@@ -31,16 +30,6 @@ unsigned char ledbank = 0xff;
31 30
32/***************************************************************************/ 31/***************************************************************************/
33 32
34struct mcf_gpio_chip mcf_gpio_chips[] = {
35 MCFGPS(PA, 0, 16, MCFSIM_PADDR, MCFSIM_PADAT, MCFSIM_PADAT),
36 MCFGPS(PB, 16, 16, MCFSIM_PBDDR, MCFSIM_PBDAT, MCFSIM_PBDAT),
37 MCFGPS(Pc, 32, 16, MCFSIM_PCDDR, MCFSIM_PCDAT, MCFSIM_PCDAT),
38};
39
40unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips);
41
42/***************************************************************************/
43
44static void __init m5272_uarts_init(void) 33static void __init m5272_uarts_init(void)
45{ 34{
46 u32 v; 35 u32 v;
diff --git a/arch/m68k/platform/coldfire/m527x.c b/arch/m68k/platform/coldfire/m527x.c
index 9b0b66aabd1b..b3cb378c5e94 100644
--- a/arch/m68k/platform/coldfire/m527x.c
+++ b/arch/m68k/platform/coldfire/m527x.c
@@ -20,49 +20,6 @@
20#include <asm/coldfire.h> 20#include <asm/coldfire.h>
21#include <asm/mcfsim.h> 21#include <asm/mcfsim.h>
22#include <asm/mcfuart.h> 22#include <asm/mcfuart.h>
23#include <asm/mcfgpio.h>
24
25/***************************************************************************/
26
27struct mcf_gpio_chip mcf_gpio_chips[] = {
28#if defined(CONFIG_M5271)
29 MCFGPS(PIRQ, 1, 7, MCFEPORT_EPDDR, MCFEPORT_EPDR, MCFEPORT_EPPDR),
30 MCFGPF(ADDR, 13, 3),
31 MCFGPF(DATAH, 16, 8),
32 MCFGPF(DATAL, 24, 8),
33 MCFGPF(BUSCTL, 32, 8),
34 MCFGPF(BS, 40, 4),
35 MCFGPF(CS, 49, 7),
36 MCFGPF(SDRAM, 56, 6),
37 MCFGPF(FECI2C, 64, 4),
38 MCFGPF(UARTH, 72, 2),
39 MCFGPF(UARTL, 80, 8),
40 MCFGPF(QSPI, 88, 5),
41 MCFGPF(TIMER, 96, 8),
42#elif defined(CONFIG_M5275)
43 MCFGPS(PIRQ, 1, 7, MCFEPORT_EPDDR, MCFEPORT_EPDR, MCFEPORT_EPPDR),
44 MCFGPF(BUSCTL, 8, 8),
45 MCFGPF(ADDR, 21, 3),
46 MCFGPF(CS, 25, 7),
47 MCFGPF(FEC0H, 32, 8),
48 MCFGPF(FEC0L, 40, 8),
49 MCFGPF(FECI2C, 48, 6),
50 MCFGPF(QSPI, 56, 7),
51 MCFGPF(SDRAM, 64, 8),
52 MCFGPF(TIMERH, 72, 4),
53 MCFGPF(TIMERL, 80, 4),
54 MCFGPF(UARTL, 88, 8),
55 MCFGPF(FEC1H, 96, 8),
56 MCFGPF(FEC1L, 104, 8),
57 MCFGPF(BS, 114, 2),
58 MCFGPF(IRQ, 121, 7),
59 MCFGPF(USBH, 128, 1),
60 MCFGPF(USBL, 136, 8),
61 MCFGPF(UARTH, 144, 4),
62#endif
63};
64
65unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips);
66 23
67/***************************************************************************/ 24/***************************************************************************/
68 25
diff --git a/arch/m68k/platform/coldfire/m528x.c b/arch/m68k/platform/coldfire/m528x.c
index 7ed1276b29dc..f1319e5d2546 100644
--- a/arch/m68k/platform/coldfire/m528x.c
+++ b/arch/m68k/platform/coldfire/m528x.c
@@ -21,37 +21,6 @@
21#include <asm/coldfire.h> 21#include <asm/coldfire.h>
22#include <asm/mcfsim.h> 22#include <asm/mcfsim.h>
23#include <asm/mcfuart.h> 23#include <asm/mcfuart.h>
24#include <asm/mcfgpio.h>
25
26/***************************************************************************/
27
28struct mcf_gpio_chip mcf_gpio_chips[] = {
29 MCFGPS(NQ, 1, 7, MCFEPORT_EPDDR, MCFEPORT_EPDR, MCFEPORT_EPPDR),
30 MCFGPS(TA, 8, 4, MCFGPTA_GPTDDR, MCFGPTA_GPTPORT, MCFGPTB_GPTPORT),
31 MCFGPS(TB, 16, 4, MCFGPTB_GPTDDR, MCFGPTB_GPTPORT, MCFGPTB_GPTPORT),
32 MCFGPS(QA, 24, 4, MCFQADC_DDRQA, MCFQADC_PORTQA, MCFQADC_PORTQA),
33 MCFGPS(QB, 32, 4, MCFQADC_DDRQB, MCFQADC_PORTQB, MCFQADC_PORTQB),
34 MCFGPF(A, 40, 8),
35 MCFGPF(B, 48, 8),
36 MCFGPF(C, 56, 8),
37 MCFGPF(D, 64, 8),
38 MCFGPF(E, 72, 8),
39 MCFGPF(F, 80, 8),
40 MCFGPF(G, 88, 8),
41 MCFGPF(H, 96, 8),
42 MCFGPF(J, 104, 8),
43 MCFGPF(DD, 112, 8),
44 MCFGPF(EH, 120, 8),
45 MCFGPF(EL, 128, 8),
46 MCFGPF(AS, 136, 6),
47 MCFGPF(QS, 144, 7),
48 MCFGPF(SD, 152, 6),
49 MCFGPF(TC, 160, 4),
50 MCFGPF(TD, 168, 4),
51 MCFGPF(UA, 176, 4),
52};
53
54unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips);
55 24
56/***************************************************************************/ 25/***************************************************************************/
57 26
@@ -74,7 +43,7 @@ static void __init m528x_uarts_init(void)
74 /* make sure PUAPAR is set for UART0 and UART1 */ 43 /* make sure PUAPAR is set for UART0 and UART1 */
75 port = readb(MCF5282_GPIO_PUAPAR); 44 port = readb(MCF5282_GPIO_PUAPAR);
76 port |= 0x03 | (0x03 << 2); 45 port |= 0x03 | (0x03 << 2);
77 writeb(port, MCF5282_GPIO_PUAPAR); 46 writeb(port, MCFGPIO_PUAPAR);
78} 47}
79 48
80/***************************************************************************/ 49/***************************************************************************/
diff --git a/arch/m68k/platform/coldfire/m5307.c b/arch/m68k/platform/coldfire/m5307.c
index 93b484976ab3..a568d2870d15 100644
--- a/arch/m68k/platform/coldfire/m5307.c
+++ b/arch/m68k/platform/coldfire/m5307.c
@@ -16,7 +16,6 @@
16#include <asm/machdep.h> 16#include <asm/machdep.h>
17#include <asm/coldfire.h> 17#include <asm/coldfire.h>
18#include <asm/mcfsim.h> 18#include <asm/mcfsim.h>
19#include <asm/mcfgpio.h>
20#include <asm/mcfwdebug.h> 19#include <asm/mcfwdebug.h>
21 20
22/***************************************************************************/ 21/***************************************************************************/
@@ -29,14 +28,6 @@ unsigned char ledbank = 0xff;
29 28
30/***************************************************************************/ 29/***************************************************************************/
31 30
32struct mcf_gpio_chip mcf_gpio_chips[] = {
33 MCFGPS(PP, 0, 16, MCFSIM_PADDR, MCFSIM_PADAT, MCFSIM_PADAT),
34};
35
36unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips);
37
38/***************************************************************************/
39
40void __init config_BSP(char *commandp, int size) 31void __init config_BSP(char *commandp, int size)
41{ 32{
42#if defined(CONFIG_NETtel) || \ 33#if defined(CONFIG_NETtel) || \
diff --git a/arch/m68k/platform/coldfire/m532x.c b/arch/m68k/platform/coldfire/m532x.c
index 5394223639f8..4819a44991ed 100644
--- a/arch/m68k/platform/coldfire/m532x.c
+++ b/arch/m68k/platform/coldfire/m532x.c
@@ -26,32 +26,144 @@
26#include <asm/mcfsim.h> 26#include <asm/mcfsim.h>
27#include <asm/mcfuart.h> 27#include <asm/mcfuart.h>
28#include <asm/mcfdma.h> 28#include <asm/mcfdma.h>
29#include <asm/mcfgpio.h>
30#include <asm/mcfwdebug.h> 29#include <asm/mcfwdebug.h>
30#include <asm/mcfclk.h>
31 31
32/***************************************************************************/ 32/***************************************************************************/
33 33
34struct mcf_gpio_chip mcf_gpio_chips[] = { 34DEFINE_CLK(0, "flexbus", 2, MCF_CLK);
35 MCFGPS(PIRQ, 0, 8, MCFEPORT_EPDDR, MCFEPORT_EPDR, MCFEPORT_EPPDR), 35DEFINE_CLK(0, "mcfcan.0", 8, MCF_CLK);
36 MCFGPF(FECH, 8, 8), 36DEFINE_CLK(0, "fec.0", 12, MCF_CLK);
37 MCFGPF(FECL, 16, 8), 37DEFINE_CLK(0, "edma", 17, MCF_CLK);
38 MCFGPF(SSI, 24, 5), 38DEFINE_CLK(0, "intc.0", 18, MCF_CLK);
39 MCFGPF(BUSCTL, 32, 4), 39DEFINE_CLK(0, "intc.1", 19, MCF_CLK);
40 MCFGPF(BE, 40, 4), 40DEFINE_CLK(0, "iack.0", 21, MCF_CLK);
41 MCFGPF(CS, 49, 5), 41DEFINE_CLK(0, "mcfi2c.0", 22, MCF_CLK);
42 MCFGPF(PWM, 58, 4), 42DEFINE_CLK(0, "mcfqspi.0", 23, MCF_CLK);
43 MCFGPF(FECI2C, 64, 4), 43DEFINE_CLK(0, "mcfuart.0", 24, MCF_BUSCLK);
44 MCFGPF(UART, 72, 8), 44DEFINE_CLK(0, "mcfuart.1", 25, MCF_BUSCLK);
45 MCFGPF(QSPI, 80, 6), 45DEFINE_CLK(0, "mcfuart.2", 26, MCF_BUSCLK);
46 MCFGPF(TIMER, 88, 4), 46DEFINE_CLK(0, "mcftmr.0", 28, MCF_CLK);
47 MCFGPF(LCDDATAH, 96, 2), 47DEFINE_CLK(0, "mcftmr.1", 29, MCF_CLK);
48 MCFGPF(LCDDATAM, 104, 8), 48DEFINE_CLK(0, "mcftmr.2", 30, MCF_CLK);
49 MCFGPF(LCDDATAL, 112, 8), 49DEFINE_CLK(0, "mcftmr.3", 31, MCF_CLK);
50 MCFGPF(LCDCTLH, 120, 1), 50
51 MCFGPF(LCDCTLL, 128, 8), 51DEFINE_CLK(0, "mcfpit.0", 32, MCF_CLK);
52DEFINE_CLK(0, "mcfpit.1", 33, MCF_CLK);
53DEFINE_CLK(0, "mcfpit.2", 34, MCF_CLK);
54DEFINE_CLK(0, "mcfpit.3", 35, MCF_CLK);
55DEFINE_CLK(0, "mcfpwm.0", 36, MCF_CLK);
56DEFINE_CLK(0, "mcfeport.0", 37, MCF_CLK);
57DEFINE_CLK(0, "mcfwdt.0", 38, MCF_CLK);
58DEFINE_CLK(0, "sys.0", 40, MCF_BUSCLK);
59DEFINE_CLK(0, "gpio.0", 41, MCF_BUSCLK);
60DEFINE_CLK(0, "mcfrtc.0", 42, MCF_CLK);
61DEFINE_CLK(0, "mcflcd.0", 43, MCF_CLK);
62DEFINE_CLK(0, "mcfusb-otg.0", 44, MCF_CLK);
63DEFINE_CLK(0, "mcfusb-host.0", 45, MCF_CLK);
64DEFINE_CLK(0, "sdram.0", 46, MCF_CLK);
65DEFINE_CLK(0, "ssi.0", 47, MCF_CLK);
66DEFINE_CLK(0, "pll.0", 48, MCF_CLK);
67
68DEFINE_CLK(1, "mdha.0", 32, MCF_CLK);
69DEFINE_CLK(1, "skha.0", 33, MCF_CLK);
70DEFINE_CLK(1, "rng.0", 34, MCF_CLK);
71
72struct clk *mcf_clks[] = {
73 &__clk_0_2, /* flexbus */
74 &__clk_0_8, /* mcfcan.0 */
75 &__clk_0_12, /* fec.0 */
76 &__clk_0_17, /* edma */
77 &__clk_0_18, /* intc.0 */
78 &__clk_0_19, /* intc.1 */
79 &__clk_0_21, /* iack.0 */
80 &__clk_0_22, /* mcfi2c.0 */
81 &__clk_0_23, /* mcfqspi.0 */
82 &__clk_0_24, /* mcfuart.0 */
83 &__clk_0_25, /* mcfuart.1 */
84 &__clk_0_26, /* mcfuart.2 */
85 &__clk_0_28, /* mcftmr.0 */
86 &__clk_0_29, /* mcftmr.1 */
87 &__clk_0_30, /* mcftmr.2 */
88 &__clk_0_31, /* mcftmr.3 */
89
90 &__clk_0_32, /* mcfpit.0 */
91 &__clk_0_33, /* mcfpit.1 */
92 &__clk_0_34, /* mcfpit.2 */
93 &__clk_0_35, /* mcfpit.3 */
94 &__clk_0_36, /* mcfpwm.0 */
95 &__clk_0_37, /* mcfeport.0 */
96 &__clk_0_38, /* mcfwdt.0 */
97 &__clk_0_40, /* sys.0 */
98 &__clk_0_41, /* gpio.0 */
99 &__clk_0_42, /* mcfrtc.0 */
100 &__clk_0_43, /* mcflcd.0 */
101 &__clk_0_44, /* mcfusb-otg.0 */
102 &__clk_0_45, /* mcfusb-host.0 */
103 &__clk_0_46, /* sdram.0 */
104 &__clk_0_47, /* ssi.0 */
105 &__clk_0_48, /* pll.0 */
106
107 &__clk_1_32, /* mdha.0 */
108 &__clk_1_33, /* skha.0 */
109 &__clk_1_34, /* rng.0 */
110 NULL,
111};
112
113static struct clk * const enable_clks[] __initconst = {
114 &__clk_0_2, /* flexbus */
115 &__clk_0_18, /* intc.0 */
116 &__clk_0_19, /* intc.1 */
117 &__clk_0_21, /* iack.0 */
118 &__clk_0_24, /* mcfuart.0 */
119 &__clk_0_25, /* mcfuart.1 */
120 &__clk_0_26, /* mcfuart.2 */
121
122 &__clk_0_32, /* mcfpit.0 */
123 &__clk_0_33, /* mcfpit.1 */
124 &__clk_0_37, /* mcfeport.0 */
125 &__clk_0_40, /* sys.0 */
126 &__clk_0_41, /* gpio.0 */
127 &__clk_0_46, /* sdram.0 */
128 &__clk_0_48, /* pll.0 */
129};
130
131static struct clk * const disable_clks[] __initconst = {
132 &__clk_0_8, /* mcfcan.0 */
133 &__clk_0_12, /* fec.0 */
134 &__clk_0_17, /* edma */
135 &__clk_0_22, /* mcfi2c.0 */
136 &__clk_0_23, /* mcfqspi.0 */
137 &__clk_0_28, /* mcftmr.0 */
138 &__clk_0_29, /* mcftmr.1 */
139 &__clk_0_30, /* mcftmr.2 */
140 &__clk_0_31, /* mcftmr.3 */
141 &__clk_0_34, /* mcfpit.2 */
142 &__clk_0_35, /* mcfpit.3 */
143 &__clk_0_36, /* mcfpwm.0 */
144 &__clk_0_38, /* mcfwdt.0 */
145 &__clk_0_42, /* mcfrtc.0 */
146 &__clk_0_43, /* mcflcd.0 */
147 &__clk_0_44, /* mcfusb-otg.0 */
148 &__clk_0_45, /* mcfusb-host.0 */
149 &__clk_0_47, /* ssi.0 */
150 &__clk_1_32, /* mdha.0 */
151 &__clk_1_33, /* skha.0 */
152 &__clk_1_34, /* rng.0 */
52}; 153};
53 154
54unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips); 155
156static void __init m532x_clk_init(void)
157{
158 unsigned i;
159
160 /* make sure these clocks are enabled */
161 for (i = 0; i < ARRAY_SIZE(enable_clks); ++i)
162 __clk_init_enabled(enable_clks[i]);
163 /* make sure these clocks are disabled */
164 for (i = 0; i < ARRAY_SIZE(disable_clks); ++i)
165 __clk_init_disabled(disable_clks[i]);
166}
55 167
56/***************************************************************************/ 168/***************************************************************************/
57 169
@@ -98,8 +210,8 @@ void __init config_BSP(char *commandp, int size)
98 memset(commandp, 0, size); 210 memset(commandp, 0, size);
99 } 211 }
100#endif 212#endif
101
102 mach_sched_init = hw_timer_init; 213 mach_sched_init = hw_timer_init;
214 m532x_clk_init();
103 m532x_uarts_init(); 215 m532x_uarts_init();
104 m532x_fec_init(); 216 m532x_fec_init();
105#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) 217#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
diff --git a/arch/m68k/platform/coldfire/m5407.c b/arch/m68k/platform/coldfire/m5407.c
index faa6680b3404..bb6c746ae819 100644
--- a/arch/m68k/platform/coldfire/m5407.c
+++ b/arch/m68k/platform/coldfire/m5407.c
@@ -16,15 +16,6 @@
16#include <asm/machdep.h> 16#include <asm/machdep.h>
17#include <asm/coldfire.h> 17#include <asm/coldfire.h>
18#include <asm/mcfsim.h> 18#include <asm/mcfsim.h>
19#include <asm/mcfgpio.h>
20
21/***************************************************************************/
22
23struct mcf_gpio_chip mcf_gpio_chips[] = {
24 MCFGPS(PP, 0, 16, MCFSIM_PADDR, MCFSIM_PADAT, MCFSIM_PADAT),
25};
26
27unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips);
28 19
29/***************************************************************************/ 20/***************************************************************************/
30 21
diff --git a/arch/m68k/platform/coldfire/m5441x.c b/arch/m68k/platform/coldfire/m5441x.c
new file mode 100644
index 000000000000..98a13cce93d8
--- /dev/null
+++ b/arch/m68k/platform/coldfire/m5441x.c
@@ -0,0 +1,261 @@
1/*
2 * m5441x.c -- support for Coldfire m5441x processors
3 *
4 * (C) Copyright Steven King <sfking@fdwdc.com>
5 */
6
7#include <linux/kernel.h>
8#include <linux/param.h>
9#include <linux/init.h>
10#include <linux/io.h>
11#include <linux/clk.h>
12#include <asm/machdep.h>
13#include <asm/coldfire.h>
14#include <asm/mcfsim.h>
15#include <asm/mcfuart.h>
16#include <asm/mcfdma.h>
17#include <asm/mcfclk.h>
18
19DEFINE_CLK(0, "flexbus", 2, MCF_CLK);
20DEFINE_CLK(0, "mcfcan.0", 8, MCF_CLK);
21DEFINE_CLK(0, "mcfcan.1", 9, MCF_CLK);
22DEFINE_CLK(0, "mcfi2c.1", 14, MCF_CLK);
23DEFINE_CLK(0, "mcfdspi.1", 15, MCF_CLK);
24DEFINE_CLK(0, "edma", 17, MCF_CLK);
25DEFINE_CLK(0, "intc.0", 18, MCF_CLK);
26DEFINE_CLK(0, "intc.1", 19, MCF_CLK);
27DEFINE_CLK(0, "intc.2", 20, MCF_CLK);
28DEFINE_CLK(0, "mcfi2c.0", 22, MCF_CLK);
29DEFINE_CLK(0, "mcfdspi.0", 23, MCF_CLK);
30DEFINE_CLK(0, "mcfuart.0", 24, MCF_BUSCLK);
31DEFINE_CLK(0, "mcfuart.1", 25, MCF_BUSCLK);
32DEFINE_CLK(0, "mcfuart.2", 26, MCF_BUSCLK);
33DEFINE_CLK(0, "mcfuart.3", 27, MCF_BUSCLK);
34DEFINE_CLK(0, "mcftmr.0", 28, MCF_CLK);
35DEFINE_CLK(0, "mcftmr.1", 29, MCF_CLK);
36DEFINE_CLK(0, "mcftmr.2", 30, MCF_CLK);
37DEFINE_CLK(0, "mcftmr.3", 31, MCF_CLK);
38DEFINE_CLK(0, "mcfpit.0", 32, MCF_CLK);
39DEFINE_CLK(0, "mcfpit.1", 33, MCF_CLK);
40DEFINE_CLK(0, "mcfpit.2", 34, MCF_CLK);
41DEFINE_CLK(0, "mcfpit.3", 35, MCF_CLK);
42DEFINE_CLK(0, "mcfeport.0", 37, MCF_CLK);
43DEFINE_CLK(0, "mcfadc.0", 38, MCF_CLK);
44DEFINE_CLK(0, "mcfdac.0", 39, MCF_CLK);
45DEFINE_CLK(0, "mcfrtc.0", 42, MCF_CLK);
46DEFINE_CLK(0, "mcfsim.0", 43, MCF_CLK);
47DEFINE_CLK(0, "mcfusb-otg.0", 44, MCF_CLK);
48DEFINE_CLK(0, "mcfusb-host.0", 45, MCF_CLK);
49DEFINE_CLK(0, "mcfddr-sram.0", 46, MCF_CLK);
50DEFINE_CLK(0, "mcfssi.0", 47, MCF_CLK);
51DEFINE_CLK(0, "pll.0", 48, MCF_CLK);
52DEFINE_CLK(0, "mcfrng.0", 49, MCF_CLK);
53DEFINE_CLK(0, "mcfssi.1", 50, MCF_CLK);
54DEFINE_CLK(0, "mcfsdhc.0", 51, MCF_CLK);
55DEFINE_CLK(0, "enet-fec.0", 53, MCF_CLK);
56DEFINE_CLK(0, "enet-fec.1", 54, MCF_CLK);
57DEFINE_CLK(0, "switch.0", 55, MCF_CLK);
58DEFINE_CLK(0, "switch.1", 56, MCF_CLK);
59DEFINE_CLK(0, "nand.0", 63, MCF_CLK);
60
61DEFINE_CLK(1, "mcfow.0", 2, MCF_CLK);
62DEFINE_CLK(1, "mcfi2c.2", 4, MCF_CLK);
63DEFINE_CLK(1, "mcfi2c.3", 5, MCF_CLK);
64DEFINE_CLK(1, "mcfi2c.4", 6, MCF_CLK);
65DEFINE_CLK(1, "mcfi2c.5", 7, MCF_CLK);
66DEFINE_CLK(1, "mcfuart.4", 24, MCF_BUSCLK);
67DEFINE_CLK(1, "mcfuart.5", 25, MCF_BUSCLK);
68DEFINE_CLK(1, "mcfuart.6", 26, MCF_BUSCLK);
69DEFINE_CLK(1, "mcfuart.7", 27, MCF_BUSCLK);
70DEFINE_CLK(1, "mcfuart.8", 28, MCF_BUSCLK);
71DEFINE_CLK(1, "mcfuart.9", 29, MCF_BUSCLK);
72DEFINE_CLK(1, "mcfpwm.0", 34, MCF_BUSCLK);
73DEFINE_CLK(1, "sys.0", 36, MCF_BUSCLK);
74DEFINE_CLK(1, "gpio.0", 37, MCF_BUSCLK);
75
76struct clk *mcf_clks[] = {
77 &__clk_0_2,
78 &__clk_0_8,
79 &__clk_0_9,
80 &__clk_0_14,
81 &__clk_0_15,
82 &__clk_0_17,
83 &__clk_0_18,
84 &__clk_0_19,
85 &__clk_0_20,
86 &__clk_0_22,
87 &__clk_0_23,
88 &__clk_0_24,
89 &__clk_0_25,
90 &__clk_0_26,
91 &__clk_0_27,
92 &__clk_0_28,
93 &__clk_0_29,
94 &__clk_0_30,
95 &__clk_0_31,
96 &__clk_0_32,
97 &__clk_0_33,
98 &__clk_0_34,
99 &__clk_0_35,
100 &__clk_0_37,
101 &__clk_0_38,
102 &__clk_0_39,
103 &__clk_0_42,
104 &__clk_0_43,
105 &__clk_0_44,
106 &__clk_0_45,
107 &__clk_0_46,
108 &__clk_0_47,
109 &__clk_0_48,
110 &__clk_0_49,
111 &__clk_0_50,
112 &__clk_0_51,
113 &__clk_0_53,
114 &__clk_0_54,
115 &__clk_0_55,
116 &__clk_0_56,
117 &__clk_0_63,
118
119 &__clk_1_2,
120 &__clk_1_4,
121 &__clk_1_5,
122 &__clk_1_6,
123 &__clk_1_7,
124 &__clk_1_24,
125 &__clk_1_25,
126 &__clk_1_26,
127 &__clk_1_27,
128 &__clk_1_28,
129 &__clk_1_29,
130 &__clk_1_34,
131 &__clk_1_36,
132 &__clk_1_37,
133 NULL,
134};
135
136
137static struct clk * const enable_clks[] __initconst = {
138 /* make sure these clocks are enabled */
139 &__clk_0_18, /* intc0 */
140 &__clk_0_19, /* intc0 */
141 &__clk_0_20, /* intc0 */
142 &__clk_0_24, /* uart0 */
143 &__clk_0_25, /* uart1 */
144 &__clk_0_26, /* uart2 */
145 &__clk_0_27, /* uart3 */
146
147 &__clk_0_33, /* pit.1 */
148 &__clk_0_37, /* eport */
149 &__clk_0_48, /* pll */
150
151 &__clk_1_36, /* CCM/reset module/Power management */
152 &__clk_1_37, /* gpio */
153};
154static struct clk * const disable_clks[] __initconst = {
155 &__clk_0_8, /* can.0 */
156 &__clk_0_9, /* can.1 */
157 &__clk_0_14, /* i2c.1 */
158 &__clk_0_15, /* dspi.1 */
159 &__clk_0_17, /* eDMA */
160 &__clk_0_22, /* i2c.0 */
161 &__clk_0_23, /* dspi.0 */
162 &__clk_0_28, /* tmr.1 */
163 &__clk_0_29, /* tmr.2 */
164 &__clk_0_30, /* tmr.2 */
165 &__clk_0_31, /* tmr.3 */
166 &__clk_0_32, /* pit.0 */
167 &__clk_0_34, /* pit.2 */
168 &__clk_0_35, /* pit.3 */
169 &__clk_0_38, /* adc */
170 &__clk_0_39, /* dac */
171 &__clk_0_44, /* usb otg */
172 &__clk_0_45, /* usb host */
173 &__clk_0_47, /* ssi.0 */
174 &__clk_0_49, /* rng */
175 &__clk_0_50, /* ssi.1 */
176 &__clk_0_51, /* eSDHC */
177 &__clk_0_53, /* enet-fec */
178 &__clk_0_54, /* enet-fec */
179 &__clk_0_55, /* switch.0 */
180 &__clk_0_56, /* switch.1 */
181
182 &__clk_1_2, /* 1-wire */
183 &__clk_1_4, /* i2c.2 */
184 &__clk_1_5, /* i2c.3 */
185 &__clk_1_6, /* i2c.4 */
186 &__clk_1_7, /* i2c.5 */
187 &__clk_1_24, /* uart 4 */
188 &__clk_1_25, /* uart 5 */
189 &__clk_1_26, /* uart 6 */
190 &__clk_1_27, /* uart 7 */
191 &__clk_1_28, /* uart 8 */
192 &__clk_1_29, /* uart 9 */
193};
194
195static void __init m5441x_clk_init(void)
196{
197 unsigned i;
198
199 for (i = 0; i < ARRAY_SIZE(enable_clks); ++i)
200 __clk_init_enabled(enable_clks[i]);
201 /* make sure these clocks are disabled */
202 for (i = 0; i < ARRAY_SIZE(disable_clks); ++i)
203 __clk_init_disabled(disable_clks[i]);
204}
205
206static void __init m5441x_uarts_init(void)
207{
208 __raw_writeb(0x0f, MCFGPIO_PAR_UART0);
209 __raw_writeb(0x00, MCFGPIO_PAR_UART1);
210 __raw_writeb(0x00, MCFGPIO_PAR_UART2);
211}
212
213static void __init m5441x_fec_init(void)
214{
215 __raw_writeb(0x03, MCFGPIO_PAR_FEC);
216}
217
218void __init config_BSP(char *commandp, int size)
219{
220 m5441x_clk_init();
221 mach_sched_init = hw_timer_init;
222 m5441x_uarts_init();
223 m5441x_fec_init();
224}
225
226
227#if IS_ENABLED(CONFIG_RTC_DRV_M5441x)
228static struct resource m5441x_rtc_resources[] = {
229 {
230 .start = MCFRTC_BASE,
231 .end = MCFRTC_BASE + MCFRTC_SIZE - 1,
232 .flags = IORESOURCE_MEM,
233 },
234 {
235 .start = MCF_IRQ_RTC,
236 .end = MCF_IRQ_RTC,
237 .flags = IORESOURCE_IRQ,
238 },
239};
240
241static struct platform_device m5441x_rtc = {
242 .name = "mcfrtc",
243 .id = 0,
244 .resource = m5441x_rtc_resources,
245 .num_resources = ARRAY_SIZE(m5441x_rtc_resources),
246};
247#endif
248
249static struct platform_device *m5441x_devices[] __initdata = {
250#if IS_ENABLED(CONFIG_RTC_DRV_M5441x)
251 &m5441x_rtc,
252#endif
253};
254
255static int __init init_BSP(void)
256{
257 platform_add_devices(m5441x_devices, ARRAY_SIZE(m5441x_devices));
258 return 0;
259}
260
261arch_initcall(init_BSP);
diff --git a/arch/m68k/platform/coldfire/m54xx.c b/arch/m68k/platform/coldfire/m54xx.c
index 20672dadb252..2081c6cbb3de 100644
--- a/arch/m68k/platform/coldfire/m54xx.c
+++ b/arch/m68k/platform/coldfire/m54xx.c
@@ -21,19 +21,12 @@
21#include <asm/m54xxsim.h> 21#include <asm/m54xxsim.h>
22#include <asm/mcfuart.h> 22#include <asm/mcfuart.h>
23#include <asm/m54xxgpt.h> 23#include <asm/m54xxgpt.h>
24#include <asm/mcfgpio.h>
25#ifdef CONFIG_MMU 24#ifdef CONFIG_MMU
26#include <asm/mmu_context.h> 25#include <asm/mmu_context.h>
27#endif 26#endif
28 27
29/***************************************************************************/ 28/***************************************************************************/
30 29
31struct mcf_gpio_chip mcf_gpio_chips[] = { };
32
33unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips);
34
35/***************************************************************************/
36
37static void __init m54xx_uarts_init(void) 30static void __init m54xx_uarts_init(void)
38{ 31{
39 /* enable io pins */ 32 /* enable io pins */
diff --git a/arch/m68k/platform/coldfire/mcf8390.c b/arch/m68k/platform/coldfire/mcf8390.c
new file mode 100644
index 000000000000..23a6874a3248
--- /dev/null
+++ b/arch/m68k/platform/coldfire/mcf8390.c
@@ -0,0 +1,38 @@
1/*
2 * mcf8390.c -- platform support for 8390 ethernet on many boards
3 *
4 * (C) Copyright 2012, Greg Ungerer <gerg@uclinux.org>
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file COPYING in the main directory of this archive
8 * for more details.
9 */
10
11#include <linux/kernel.h>
12#include <linux/module.h>
13#include <linux/init.h>
14#include <linux/resource.h>
15#include <linux/platform_device.h>
16#include <asm/mcf8390.h>
17
18static struct resource mcf8390_resources[] = {
19 {
20 .start = NE2000_ADDR,
21 .end = NE2000_ADDR + NE2000_ADDRSIZE - 1,
22 .flags = IORESOURCE_MEM,
23 },
24 {
25 .start = NE2000_IRQ_VECTOR,
26 .end = NE2000_IRQ_VECTOR,
27 .flags = IORESOURCE_IRQ,
28 },
29};
30
31static int __init mcf8390_platform_init(void)
32{
33 platform_device_register_simple("mcf8390", -1, mcf8390_resources,
34 ARRAY_SIZE(mcf8390_resources));
35 return 0;
36}
37
38arch_initcall(mcf8390_platform_init);
diff --git a/arch/m68k/platform/coldfire/pci.c b/arch/m68k/platform/coldfire/pci.c
new file mode 100644
index 000000000000..553210d3d4c1
--- /dev/null
+++ b/arch/m68k/platform/coldfire/pci.c
@@ -0,0 +1,327 @@
1/*
2 * pci.c -- PCI bus support for ColdFire processors
3 *
4 * (C) Copyright 2012, Greg Ungerer <gerg@uclinux.com>
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file COPYING in the main directory of this archive
8 * for more details.
9 */
10
11#include <linux/types.h>
12#include <linux/module.h>
13#include <linux/init.h>
14#include <linux/kernel.h>
15#include <linux/interrupt.h>
16#include <linux/irq.h>
17#include <linux/io.h>
18#include <linux/pci.h>
19#include <linux/delay.h>
20#include <asm/coldfire.h>
21#include <asm/mcfsim.h>
22#include <asm/m54xxpci.h>
23
24/*
25 * Memory and IO mappings. We use a 1:1 mapping for local host memory to
26 * PCI bus memory (no reason not to really). IO space doesn't matter, we
27 * always use access functions for that. The device configuration space is
28 * mapped over the IO map space when we enable it in the PCICAR register.
29 */
30#define PCI_MEM_PA 0xf0000000 /* Host physical address */
31#define PCI_MEM_BA 0xf0000000 /* Bus physical address */
32#define PCI_MEM_SIZE 0x08000000 /* 128 MB */
33#define PCI_MEM_MASK (PCI_MEM_SIZE - 1)
34
35#define PCI_IO_PA 0xf8000000 /* Host physical address */
36#define PCI_IO_BA 0x00000000 /* Bus physical address */
37#define PCI_IO_SIZE 0x00010000 /* 64k */
38#define PCI_IO_MASK (PCI_IO_SIZE - 1)
39
40static struct pci_bus *rootbus;
41static unsigned long iospace;
42
43/*
44 * We need to be carefull probing on bus 0 (directly connected to host
45 * bridge). We should only acccess the well defined possible devices in
46 * use, ignore aliases and the like.
47 */
48static unsigned char mcf_host_slot2sid[32] = {
49 0, 0, 0, 0, 0, 0, 0, 0,
50 0, 0, 0, 0, 0, 0, 0, 0,
51 0, 1, 2, 0, 3, 4, 0, 0,
52 0, 0, 0, 0, 0, 0, 0, 0,
53};
54
55static unsigned char mcf_host_irq[] = {
56 0, 69, 69, 71, 71,
57};
58
59
60static inline void syncio(void)
61{
62 /* The ColdFire "nop" instruction waits for all bus IO to complete */
63 __asm__ __volatile__ ("nop");
64}
65
66/*
67 * Configuration space access functions. Configuration space access is
68 * through the IO mapping window, enabling it via the PCICAR register.
69 */
70static unsigned long mcf_mk_pcicar(int bus, unsigned int devfn, int where)
71{
72 return (bus << PCICAR_BUSN) | (devfn << PCICAR_DEVFNN) | (where & 0xfc);
73}
74
75static int mcf_pci_readconfig(struct pci_bus *bus, unsigned int devfn,
76 int where, int size, u32 *value)
77{
78 unsigned long addr;
79
80 *value = 0xffffffff;
81
82 if (bus->number == 0) {
83 if (mcf_host_slot2sid[PCI_SLOT(devfn)] == 0)
84 return PCIBIOS_SUCCESSFUL;
85 }
86
87 syncio();
88 addr = mcf_mk_pcicar(bus->number, devfn, where);
89 __raw_writel(PCICAR_E | addr, PCICAR);
90 addr = iospace + (where & 0x3);
91
92 switch (size) {
93 case 1:
94 *value = __raw_readb(addr);
95 break;
96 case 2:
97 *value = le16_to_cpu(__raw_readw(addr));
98 break;
99 default:
100 *value = le32_to_cpu(__raw_readl(addr));
101 break;
102 }
103
104 syncio();
105 __raw_writel(0, PCICAR);
106 return PCIBIOS_SUCCESSFUL;
107}
108
109static int mcf_pci_writeconfig(struct pci_bus *bus, unsigned int devfn,
110 int where, int size, u32 value)
111{
112 unsigned long addr;
113
114 if (bus->number == 0) {
115 if (mcf_host_slot2sid[PCI_SLOT(devfn)] == 0)
116 return PCIBIOS_SUCCESSFUL;
117 }
118
119 syncio();
120 addr = mcf_mk_pcicar(bus->number, devfn, where);
121 __raw_writel(PCICAR_E | addr, PCICAR);
122 addr = iospace + (where & 0x3);
123
124 switch (size) {
125 case 1:
126 __raw_writeb(value, addr);
127 break;
128 case 2:
129 __raw_writew(cpu_to_le16(value), addr);
130 break;
131 default:
132 __raw_writel(cpu_to_le32(value), addr);
133 break;
134 }
135
136 syncio();
137 __raw_writel(0, PCICAR);
138 return PCIBIOS_SUCCESSFUL;
139}
140
141static struct pci_ops mcf_pci_ops = {
142 .read = mcf_pci_readconfig,
143 .write = mcf_pci_writeconfig,
144};
145
146/*
147 * IO address space access functions. Pretty strait forward, these are
148 * directly mapped in to the IO mapping window. And that is mapped into
149 * virtual address space.
150 */
151u8 mcf_pci_inb(u32 addr)
152{
153 return __raw_readb(iospace + (addr & PCI_IO_MASK));
154}
155EXPORT_SYMBOL(mcf_pci_inb);
156
157u16 mcf_pci_inw(u32 addr)
158{
159 return le16_to_cpu(__raw_readw(iospace + (addr & PCI_IO_MASK)));
160}
161EXPORT_SYMBOL(mcf_pci_inw);
162
163u32 mcf_pci_inl(u32 addr)
164{
165 return le32_to_cpu(__raw_readl(iospace + (addr & PCI_IO_MASK)));
166}
167EXPORT_SYMBOL(mcf_pci_inl);
168
169void mcf_pci_insb(u32 addr, u8 *buf, u32 len)
170{
171 for (; len; len--)
172 *buf++ = mcf_pci_inb(addr);
173}
174EXPORT_SYMBOL(mcf_pci_insb);
175
176void mcf_pci_insw(u32 addr, u16 *buf, u32 len)
177{
178 for (; len; len--)
179 *buf++ = mcf_pci_inw(addr);
180}
181EXPORT_SYMBOL(mcf_pci_insw);
182
183void mcf_pci_insl(u32 addr, u32 *buf, u32 len)
184{
185 for (; len; len--)
186 *buf++ = mcf_pci_inl(addr);
187}
188EXPORT_SYMBOL(mcf_pci_insl);
189
190void mcf_pci_outb(u8 v, u32 addr)
191{
192 __raw_writeb(v, iospace + (addr & PCI_IO_MASK));
193}
194EXPORT_SYMBOL(mcf_pci_outb);
195
196void mcf_pci_outw(u16 v, u32 addr)
197{
198 __raw_writew(cpu_to_le16(v), iospace + (addr & PCI_IO_MASK));
199}
200EXPORT_SYMBOL(mcf_pci_outw);
201
202void mcf_pci_outl(u32 v, u32 addr)
203{
204 __raw_writel(cpu_to_le32(v), iospace + (addr & PCI_IO_MASK));
205}
206EXPORT_SYMBOL(mcf_pci_outl);
207
208void mcf_pci_outsb(u32 addr, const u8 *buf, u32 len)
209{
210 for (; len; len--)
211 mcf_pci_outb(*buf++, addr);
212}
213EXPORT_SYMBOL(mcf_pci_outsb);
214
215void mcf_pci_outsw(u32 addr, const u16 *buf, u32 len)
216{
217 for (; len; len--)
218 mcf_pci_outw(*buf++, addr);
219}
220EXPORT_SYMBOL(mcf_pci_outsw);
221
222void mcf_pci_outsl(u32 addr, const u32 *buf, u32 len)
223{
224 for (; len; len--)
225 mcf_pci_outl(*buf++, addr);
226}
227EXPORT_SYMBOL(mcf_pci_outsl);
228
229/*
230 * Initialize the PCI bus registers, and scan the bus.
231 */
232static struct resource mcf_pci_mem = {
233 .name = "PCI Memory space",
234 .start = PCI_MEM_PA,
235 .end = PCI_MEM_PA + PCI_MEM_SIZE - 1,
236 .flags = IORESOURCE_MEM,
237};
238
239static struct resource mcf_pci_io = {
240 .name = "PCI IO space",
241 .start = 0x400,
242 .end = 0x10000 - 1,
243 .flags = IORESOURCE_IO,
244};
245
246/*
247 * Interrupt mapping and setting.
248 */
249static int mcf_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
250{
251 int sid;
252
253 sid = mcf_host_slot2sid[slot];
254 if (sid)
255 return mcf_host_irq[sid];
256 return 0;
257}
258
259static int __init mcf_pci_init(void)
260{
261 pr_info("ColdFire: PCI bus initialization...\n");
262
263 /* Reset the external PCI bus */
264 __raw_writel(PCIGSCR_RESET, PCIGSCR);
265 __raw_writel(0, PCITCR);
266
267 request_resource(&iomem_resource, &mcf_pci_mem);
268 request_resource(&iomem_resource, &mcf_pci_io);
269
270 /* Configure PCI arbiter */
271 __raw_writel(PACR_INTMPRI | PACR_INTMINTE | PACR_EXTMPRI(0x1f) |
272 PACR_EXTMINTE(0x1f), PACR);
273
274 /* Set required multi-function pins for PCI bus use */
275 __raw_writew(0x3ff, MCF_PAR_PCIBG);
276 __raw_writew(0x3ff, MCF_PAR_PCIBR);
277
278 /* Set up config space for local host bus controller */
279 __raw_writel(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
280 PCI_COMMAND_INVALIDATE, PCISCR);
281 __raw_writel(PCICR1_LT(32) | PCICR1_CL(8), PCICR1);
282 __raw_writel(0, PCICR2);
283
284 /*
285 * Set up the initiator windows for memory and IO mapping.
286 * These give the CPU bus access onto the PCI bus. One for each of
287 * PCI memory and IO address spaces.
288 */
289 __raw_writel(WXBTAR(PCI_MEM_PA, PCI_MEM_BA, PCI_MEM_SIZE),
290 PCIIW0BTAR);
291 __raw_writel(WXBTAR(PCI_IO_PA, PCI_IO_BA, PCI_IO_SIZE),
292 PCIIW1BTAR);
293 __raw_writel(PCIIWCR_W0_MEM /*| PCIIWCR_W0_MRDL*/ | PCIIWCR_W0_E |
294 PCIIWCR_W1_IO | PCIIWCR_W1_E, PCIIWCR);
295
296 /*
297 * Set up the target windows for access from the PCI bus back to the
298 * CPU bus. All we need is access to system RAM (for mastering).
299 */
300 __raw_writel(CONFIG_RAMBASE, PCIBAR1);
301 __raw_writel(CONFIG_RAMBASE | PCITBATR1_E, PCITBATR1);
302
303 /* Keep a virtual mapping to IO/config space active */
304 iospace = (unsigned long) ioremap(PCI_IO_PA, PCI_IO_SIZE);
305 if (iospace == 0)
306 return -ENODEV;
307 pr_info("Coldfire: PCI IO/config window mapped to 0x%x\n",
308 (u32) iospace);
309
310 /* Turn of PCI reset, and wait for devices to settle */
311 __raw_writel(0, PCIGSCR);
312 set_current_state(TASK_UNINTERRUPTIBLE);
313 schedule_timeout(msecs_to_jiffies(200));
314
315 rootbus = pci_scan_bus(0, &mcf_pci_ops, NULL);
316 rootbus->resource[0] = &mcf_pci_io;
317 rootbus->resource[1] = &mcf_pci_mem;
318
319 pci_fixup_irqs(pci_common_swizzle, mcf_pci_map_irq);
320 pci_bus_size_bridges(rootbus);
321 pci_bus_assign_resources(rootbus);
322 pci_enable_bridges(rootbus);
323 pci_bus_add_devices(rootbus);
324 return 0;
325}
326
327subsys_initcall(mcf_pci_init);
diff --git a/arch/m68k/platform/coldfire/pinmux.c b/arch/m68k/platform/coldfire/pinmux.c
deleted file mode 100644
index 8c62b825939f..000000000000
--- a/arch/m68k/platform/coldfire/pinmux.c
+++ /dev/null
@@ -1,28 +0,0 @@
1/*
2 * Coldfire generic GPIO pinmux support.
3 *
4 * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#include <linux/kernel.h>
18
19#include <asm/pinmux.h>
20
21int mcf_pinmux_request(unsigned pinmux, unsigned func)
22{
23 return 0;
24}
25
26void mcf_pinmux_release(unsigned pinmux, unsigned func)
27{
28}
diff --git a/arch/m68k/platform/coldfire/pit.c b/arch/m68k/platform/coldfire/pit.c
index e62dbbcb10f6..e8f3b97b0f77 100644
--- a/arch/m68k/platform/coldfire/pit.c
+++ b/arch/m68k/platform/coldfire/pit.c
@@ -93,7 +93,7 @@ struct clock_event_device cf_pit_clockevent = {
93 .set_mode = init_cf_pit_timer, 93 .set_mode = init_cf_pit_timer,
94 .set_next_event = cf_pit_next_event, 94 .set_next_event = cf_pit_next_event,
95 .shift = 32, 95 .shift = 32,
96 .irq = MCFINT_VECBASE + MCFINT_PIT1, 96 .irq = MCF_IRQ_PIT1,
97}; 97};
98 98
99 99
@@ -159,7 +159,7 @@ void hw_timer_init(irq_handler_t handler)
159 clockevent_delta2ns(0x3f, &cf_pit_clockevent); 159 clockevent_delta2ns(0x3f, &cf_pit_clockevent);
160 clockevents_register_device(&cf_pit_clockevent); 160 clockevents_register_device(&cf_pit_clockevent);
161 161
162 setup_irq(MCFINT_VECBASE + MCFINT_PIT1, &pit_irq); 162 setup_irq(MCF_IRQ_PIT1, &pit_irq);
163 163
164 clocksource_register_hz(&pit_clk, FREQ); 164 clocksource_register_hz(&pit_clk, FREQ);
165} 165}
diff --git a/arch/m68k/platform/coldfire/timers.c b/arch/m68k/platform/coldfire/timers.c
index ed96ce50d79f..0a273e75408c 100644
--- a/arch/m68k/platform/coldfire/timers.c
+++ b/arch/m68k/platform/coldfire/timers.c
@@ -36,7 +36,7 @@
36 */ 36 */
37void coldfire_profile_init(void); 37void coldfire_profile_init(void);
38 38
39#if defined(CONFIG_M532x) 39#if defined(CONFIG_M532x) || defined(CONFIG_M5441x)
40#define __raw_readtrr __raw_readl 40#define __raw_readtrr __raw_readl
41#define __raw_writetrr __raw_writel 41#define __raw_writetrr __raw_writel
42#else 42#else
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-27 15:32:24 -0500