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-rw-r--r--arch/m68k/include/asm/m5249sim.h23
1 files changed, 14 insertions, 9 deletions
diff --git a/arch/m68k/include/asm/m5249sim.h b/arch/m68k/include/asm/m5249sim.h
index 366eb8602d2f..2c23a83512a4 100644
--- a/arch/m68k/include/asm/m5249sim.h
+++ b/arch/m68k/include/asm/m5249sim.h
@@ -73,14 +73,14 @@
73/* 73/*
74 * General purpose IO registers (in MBAR2). 74 * General purpose IO registers (in MBAR2).
75 */ 75 */
76#define MCFSIM2_GPIOREAD 0x0 /* GPIO read values */ 76#define MCFSIM2_GPIOREAD (MCF_MBAR2 + 0x000) /* GPIO read values */
77#define MCFSIM2_GPIOWRITE 0x4 /* GPIO write values */ 77#define MCFSIM2_GPIOWRITE (MCF_MBAR2 + 0x004) /* GPIO write values */
78#define MCFSIM2_GPIOENABLE 0x8 /* GPIO enabled */ 78#define MCFSIM2_GPIOENABLE (MCF_MBAR2 + 0x008) /* GPIO enabled */
79#define MCFSIM2_GPIOFUNC 0xc /* GPIO function */ 79#define MCFSIM2_GPIOFUNC (MCF_MBAR2 + 0x00C) /* GPIO function */
80#define MCFSIM2_GPIO1READ 0xb0 /* GPIO1 read values */ 80#define MCFSIM2_GPIO1READ (MCF_MBAR2 + 0x0B0) /* GPIO1 read values */
81#define MCFSIM2_GPIO1WRITE 0xb4 /* GPIO1 write values */ 81#define MCFSIM2_GPIO1WRITE (MCF_MBAR2 + 0x0B4) /* GPIO1 write values */
82#define MCFSIM2_GPIO1ENABLE 0xb8 /* GPIO1 enabled */ 82#define MCFSIM2_GPIO1ENABLE (MCF_MBAR2 + 0x0B8) /* GPIO1 enabled */
83#define MCFSIM2_GPIO1FUNC 0xbc /* GPIO1 function */ 83#define MCFSIM2_GPIO1FUNC (MCF_MBAR2 + 0x0BC) /* GPIO1 function */
84 84
85#define MCFSIM2_GPIOINTSTAT 0xc0 /* GPIO interrupt status */ 85#define MCFSIM2_GPIOINTSTAT 0xc0 /* GPIO interrupt status */
86#define MCFSIM2_GPIOINTCLEAR 0xc0 /* GPIO interrupt clear */ 86#define MCFSIM2_GPIOINTCLEAR 0xc0 /* GPIO interrupt clear */
@@ -100,7 +100,12 @@
100#define MCFSIM2_IDECONFIG1 0x18c /* IDEconfig1 */ 100#define MCFSIM2_IDECONFIG1 0x18c /* IDEconfig1 */
101#define MCFSIM2_IDECONFIG2 0x190 /* IDEconfig2 */ 101#define MCFSIM2_IDECONFIG2 0x190 /* IDEconfig2 */
102 102
103 103/*
104 * Generic GPIO support
105 */
106#define MCFGPIO_PIN_MAX 64
107#define MCFGPIO_IRQ_MAX -1
108#define MCFGPIO_IRQ_VECBASE -1
104/* 109/*
105 * Macro to set IMR register. It is 32 bits on the 5249. 110 * Macro to set IMR register. It is 32 bits on the 5249.
106 */ 111 */