diff options
Diffstat (limited to 'arch/m68k')
| -rw-r--r-- | arch/m68k/include/asm/m5407sim.h | 34 | ||||
| -rw-r--r-- | arch/m68k/include/asm/m54xxacr.h | 43 |
2 files changed, 43 insertions, 34 deletions
diff --git a/arch/m68k/include/asm/m5407sim.h b/arch/m68k/include/asm/m5407sim.h index c399abbf953c..2099435e10c7 100644 --- a/arch/m68k/include/asm/m5407sim.h +++ b/arch/m68k/include/asm/m5407sim.h | |||
| @@ -117,39 +117,5 @@ | |||
| 117 | #define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */ | 117 | #define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */ |
| 118 | #define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */ | 118 | #define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */ |
| 119 | 119 | ||
| 120 | /* | ||
| 121 | * Define the Cache register flags. | ||
| 122 | */ | ||
| 123 | #define CACR_DEC 0x80000000 /* Enable data cache */ | ||
| 124 | #define CACR_DWP 0x40000000 /* Data write protection */ | ||
| 125 | #define CACR_DESB 0x20000000 /* Enable data store buffer */ | ||
| 126 | #define CACR_DDPI 0x10000000 /* Disable CPUSHL */ | ||
| 127 | #define CACR_DHCLK 0x08000000 /* Half data cache lock mode */ | ||
| 128 | #define CACR_DDCM_WT 0x00000000 /* Write through cache*/ | ||
| 129 | #define CACR_DDCM_CP 0x02000000 /* Copyback cache */ | ||
| 130 | #define CACR_DDCM_P 0x04000000 /* No cache, precise */ | ||
| 131 | #define CACR_DDCM_IMP 0x06000000 /* No cache, imprecise */ | ||
| 132 | #define CACR_DCINVA 0x01000000 /* Invalidate data cache */ | ||
| 133 | #define CACR_BEC 0x00080000 /* Enable branch cache */ | ||
| 134 | #define CACR_BCINVA 0x00040000 /* Invalidate branch cache */ | ||
| 135 | #define CACR_IEC 0x00008000 /* Enable instruction cache */ | ||
| 136 | #define CACR_DNFB 0x00002000 /* Inhibited fill buffer */ | ||
| 137 | #define CACR_IDPI 0x00001000 /* Disable CPUSHL */ | ||
| 138 | #define CACR_IHLCK 0x00000800 /* Intruction cache half lock */ | ||
| 139 | #define CACR_IDCM 0x00000400 /* Intruction cache inhibit */ | ||
| 140 | #define CACR_ICINVA 0x00000100 /* Invalidate instr cache */ | ||
| 141 | |||
| 142 | #define ACR_BASE_POS 24 /* Address Base */ | ||
| 143 | #define ACR_MASK_POS 16 /* Address Mask */ | ||
| 144 | #define ACR_ENABLE 0x00008000 /* Enable address */ | ||
| 145 | #define ACR_USER 0x00000000 /* User mode access only */ | ||
| 146 | #define ACR_SUPER 0x00002000 /* Supervisor mode only */ | ||
| 147 | #define ACR_ANY 0x00004000 /* Match any access mode */ | ||
| 148 | #define ACR_CM_WT 0x00000000 /* Write through mode */ | ||
| 149 | #define ACR_CM_CP 0x00000020 /* Copyback mode */ | ||
| 150 | #define ACR_CM_OFF_PRE 0x00000040 /* No cache, precise */ | ||
| 151 | #define ACR_CM_OFF_IMP 0x00000060 /* No cache, imprecise */ | ||
| 152 | #define ACR_WPROTECT 0x00000004 /* Write protect */ | ||
| 153 | |||
| 154 | /****************************************************************************/ | 120 | /****************************************************************************/ |
| 155 | #endif /* m5407sim_h */ | 121 | #endif /* m5407sim_h */ |
diff --git a/arch/m68k/include/asm/m54xxacr.h b/arch/m68k/include/asm/m54xxacr.h new file mode 100644 index 000000000000..424d4a677e43 --- /dev/null +++ b/arch/m68k/include/asm/m54xxacr.h | |||
| @@ -0,0 +1,43 @@ | |||
| 1 | /* | ||
| 2 | * Bit definitions for the MCF54xx ACR and CACR registers. | ||
| 3 | */ | ||
| 4 | |||
| 5 | #ifndef m54xxacr_h | ||
| 6 | #define m54xxacr_h | ||
| 7 | |||
| 8 | /* | ||
| 9 | * Define the Cache register flags. | ||
| 10 | */ | ||
| 11 | #define CACR_DEC 0x80000000 /* Enable data cache */ | ||
| 12 | #define CACR_DWP 0x40000000 /* Data write protection */ | ||
| 13 | #define CACR_DESB 0x20000000 /* Enable data store buffer */ | ||
| 14 | #define CACR_DDPI 0x10000000 /* Disable invalidation by CPUSHL */ | ||
| 15 | #define CACR_DHCLK 0x08000000 /* Half data cache lock mode */ | ||
| 16 | #define CACR_DDCM_WT 0x00000000 /* Write through cache*/ | ||
| 17 | #define CACR_DDCM_CP 0x02000000 /* Copyback cache */ | ||
| 18 | #define CACR_DDCM_P 0x04000000 /* No cache, precise */ | ||
| 19 | #define CACR_DDCM_IMP 0x06000000 /* No cache, imprecise */ | ||
| 20 | #define CACR_DCINVA 0x01000000 /* Invalidate data cache */ | ||
| 21 | #define CACR_BEC 0x00080000 /* Enable branch cache */ | ||
| 22 | #define CACR_BCINVA 0x00040000 /* Invalidate branch cache */ | ||
| 23 | #define CACR_IEC 0x00008000 /* Enable instruction cache */ | ||
| 24 | #define CACR_DNFB 0x00002000 /* Inhibited fill buffer */ | ||
| 25 | #define CACR_IDPI 0x00001000 /* Disable CPUSHL */ | ||
| 26 | #define CACR_IHLCK 0x00000800 /* Intruction cache half lock */ | ||
| 27 | #define CACR_IDCM 0x00000400 /* Intruction cache inhibit */ | ||
| 28 | #define CACR_ICINVA 0x00000100 /* Invalidate instr cache */ | ||
| 29 | |||
| 30 | #define ACR_BASE_POS 24 /* Address Base */ | ||
| 31 | #define ACR_MASK_POS 16 /* Address Mask */ | ||
| 32 | #define ACR_ENABLE 0x00008000 /* Enable address */ | ||
| 33 | #define ACR_USER 0x00000000 /* User mode access only */ | ||
| 34 | #define ACR_SUPER 0x00002000 /* Supervisor mode only */ | ||
| 35 | #define ACR_ANY 0x00004000 /* Match any access mode */ | ||
| 36 | #define ACR_CM_WT 0x00000000 /* Write through mode */ | ||
| 37 | #define ACR_CM_CP 0x00000020 /* Copyback mode */ | ||
| 38 | #define ACR_CM_OFF_PRE 0x00000040 /* No cache, precise */ | ||
| 39 | #define ACR_CM_OFF_IMP 0x00000060 /* No cache, imprecise */ | ||
| 40 | #define ACR_CM 0x00000060 /* Cache mode mask */ | ||
| 41 | #define ACR_WPROTECT 0x00000004 /* Write protect */ | ||
| 42 | |||
| 43 | #endif /* m54xxacr_h */ | ||