aboutsummaryrefslogtreecommitdiffstats
path: root/arch/m68k
diff options
context:
space:
mode:
Diffstat (limited to 'arch/m68k')
-rw-r--r--arch/m68k/Kconfig4
-rw-r--r--arch/m68k/kernel/Makefile1
-rw-r--r--arch/m68k/kernel/bios32.c516
3 files changed, 0 insertions, 521 deletions
diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig
index 2ec21f7fcb52..677c93a490f6 100644
--- a/arch/m68k/Kconfig
+++ b/arch/m68k/Kconfig
@@ -122,10 +122,6 @@ config ATARI
122 this kernel on an Atari, say Y here and browse the material 122 this kernel on an Atari, say Y here and browse the material
123 available in <file:Documentation/m68k>; otherwise say N. 123 available in <file:Documentation/m68k>; otherwise say N.
124 124
125config PCI
126 bool
127 help
128
129config MAC 125config MAC
130 bool "Macintosh support" 126 bool "Macintosh support"
131 select MMU_MOTOROLA if MMU 127 select MMU_MOTOROLA if MMU
diff --git a/arch/m68k/kernel/Makefile b/arch/m68k/kernel/Makefile
index 3a7f62225504..55d5d6b680a2 100644
--- a/arch/m68k/kernel/Makefile
+++ b/arch/m68k/kernel/Makefile
@@ -14,5 +14,4 @@ obj-y := entry.o process.o traps.o ints.o signal.o ptrace.o module.o \
14 14
15devres-y = ../../../kernel/irq/devres.o 15devres-y = ../../../kernel/irq/devres.o
16 16
17obj-$(CONFIG_PCI) += bios32.o
18obj-y$(CONFIG_MMU_SUN3) += dma.o # no, it's not a typo 17obj-y$(CONFIG_MMU_SUN3) += dma.o # no, it's not a typo
diff --git a/arch/m68k/kernel/bios32.c b/arch/m68k/kernel/bios32.c
deleted file mode 100644
index 1c3b752f5608..000000000000
--- a/arch/m68k/kernel/bios32.c
+++ /dev/null
@@ -1,516 +0,0 @@
1/*
2 * bios32.c - PCI BIOS functions for m68k systems.
3 *
4 * Written by Wout Klaren.
5 *
6 * Based on the DEC Alpha bios32.c by Dave Rusling and David Mosberger.
7 */
8
9#include <linux/init.h>
10#include <linux/kernel.h>
11
12#if 0
13# define DBG_DEVS(args) printk args
14#else
15# define DBG_DEVS(args)
16#endif
17
18#ifdef CONFIG_PCI
19
20/*
21 * PCI support for Linux/m68k. Currently only the Hades is supported.
22 *
23 * The support for PCI bridges in the DEC Alpha version has
24 * been removed in this version.
25 */
26
27#include <linux/pci.h>
28#include <linux/slab.h>
29#include <linux/mm.h>
30
31#include <asm/io.h>
32#include <asm/pci.h>
33#include <asm/uaccess.h>
34
35#define KB 1024
36#define MB (1024*KB)
37#define GB (1024*MB)
38
39#define MAJOR_REV 0
40#define MINOR_REV 5
41
42/*
43 * Align VAL to ALIGN, which must be a power of two.
44 */
45
46#define ALIGN(val,align) (((val) + ((align) - 1)) & ~((align) - 1))
47
48/*
49 * Offsets relative to the I/O and memory base addresses from where resources
50 * are allocated.
51 */
52
53#define IO_ALLOC_OFFSET 0x00004000
54#define MEM_ALLOC_OFFSET 0x04000000
55
56/*
57 * Declarations of hardware specific initialisation functions.
58 */
59
60extern struct pci_bus_info *init_hades_pci(void);
61
62/*
63 * Bus info structure of the PCI bus. A pointer to this structure is
64 * put in the sysdata member of the pci_bus structure.
65 */
66
67static struct pci_bus_info *bus_info;
68
69static int pci_modify = 1; /* If set, layout the PCI bus ourself. */
70static int skip_vga; /* If set do not modify base addresses
71 of vga cards.*/
72static int disable_pci_burst; /* If set do not allow PCI bursts. */
73
74static unsigned int io_base;
75static unsigned int mem_base;
76
77/*
78 * static void disable_dev(struct pci_dev *dev)
79 *
80 * Disable PCI device DEV so that it does not respond to I/O or memory
81 * accesses.
82 *
83 * Parameters:
84 *
85 * dev - device to disable.
86 */
87
88static void __init disable_dev(struct pci_dev *dev)
89{
90 unsigned short cmd;
91
92 if (((dev->class >> 8 == PCI_CLASS_NOT_DEFINED_VGA) ||
93 (dev->class >> 8 == PCI_CLASS_DISPLAY_VGA) ||
94 (dev->class >> 8 == PCI_CLASS_DISPLAY_XGA)) && skip_vga)
95 return;
96
97 pci_read_config_word(dev, PCI_COMMAND, &cmd);
98
99 cmd &= (~PCI_COMMAND_IO & ~PCI_COMMAND_MEMORY & ~PCI_COMMAND_MASTER);
100 pci_write_config_word(dev, PCI_COMMAND, cmd);
101}
102
103/*
104 * static void layout_dev(struct pci_dev *dev)
105 *
106 * Layout memory and I/O for a device.
107 *
108 * Parameters:
109 *
110 * device - device to layout memory and I/O for.
111 */
112
113static void __init layout_dev(struct pci_dev *dev)
114{
115 unsigned short cmd;
116 unsigned int base, mask, size, reg;
117 unsigned int alignto;
118 int i;
119
120 /*
121 * Skip video cards if requested.
122 */
123
124 if (((dev->class >> 8 == PCI_CLASS_NOT_DEFINED_VGA) ||
125 (dev->class >> 8 == PCI_CLASS_DISPLAY_VGA) ||
126 (dev->class >> 8 == PCI_CLASS_DISPLAY_XGA)) && skip_vga)
127 return;
128
129 pci_read_config_word(dev, PCI_COMMAND, &cmd);
130
131 for (reg = PCI_BASE_ADDRESS_0, i = 0; reg <= PCI_BASE_ADDRESS_5; reg += 4, i++)
132 {
133 /*
134 * Figure out how much space and of what type this
135 * device wants.
136 */
137
138 pci_write_config_dword(dev, reg, 0xffffffff);
139 pci_read_config_dword(dev, reg, &base);
140
141 if (!base)
142 {
143 /* this base-address register is unused */
144 dev->resource[i].start = 0;
145 dev->resource[i].end = 0;
146 dev->resource[i].flags = 0;
147 continue;
148 }
149
150 /*
151 * We've read the base address register back after
152 * writing all ones and so now we must decode it.
153 */
154
155 if (base & PCI_BASE_ADDRESS_SPACE_IO)
156 {
157 /*
158 * I/O space base address register.
159 */
160
161 cmd |= PCI_COMMAND_IO;
162
163 base &= PCI_BASE_ADDRESS_IO_MASK;
164 mask = (~base << 1) | 0x1;
165 size = (mask & base) & 0xffffffff;
166
167 /*
168 * Align to multiple of size of minimum base.
169 */
170
171 alignto = max_t(unsigned int, 0x040, size);
172 base = ALIGN(io_base, alignto);
173 io_base = base + size;
174 pci_write_config_dword(dev, reg, base | PCI_BASE_ADDRESS_SPACE_IO);
175
176 dev->resource[i].start = base;
177 dev->resource[i].end = dev->resource[i].start + size - 1;
178 dev->resource[i].flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO;
179
180 DBG_DEVS(("layout_dev: IO address: %lX\n", base));
181 }
182 else
183 {
184 unsigned int type;
185
186 /*
187 * Memory space base address register.
188 */
189
190 cmd |= PCI_COMMAND_MEMORY;
191 type = base & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
192 base &= PCI_BASE_ADDRESS_MEM_MASK;
193 mask = (~base << 1) | 0x1;
194 size = (mask & base) & 0xffffffff;
195 switch (type)
196 {
197 case PCI_BASE_ADDRESS_MEM_TYPE_32:
198 case PCI_BASE_ADDRESS_MEM_TYPE_64:
199 break;
200
201 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
202 printk("bios32 WARNING: slot %d, function %d "
203 "requests memory below 1MB---don't "
204 "know how to do that.\n",
205 PCI_SLOT(dev->devfn),
206 PCI_FUNC(dev->devfn));
207 continue;
208 }
209
210 /*
211 * Align to multiple of size of minimum base.
212 */
213
214 alignto = max_t(unsigned int, 0x1000, size);
215 base = ALIGN(mem_base, alignto);
216 mem_base = base + size;
217 pci_write_config_dword(dev, reg, base);
218
219 dev->resource[i].start = base;
220 dev->resource[i].end = dev->resource[i].start + size - 1;
221 dev->resource[i].flags = IORESOURCE_MEM;
222
223 if (type == PCI_BASE_ADDRESS_MEM_TYPE_64)
224 {
225 /*
226 * 64-bit address, set the highest 32 bits
227 * to zero.
228 */
229
230 reg += 4;
231 pci_write_config_dword(dev, reg, 0);
232
233 i++;
234 dev->resource[i].start = 0;
235 dev->resource[i].end = 0;
236 dev->resource[i].flags = 0;
237 }
238 }
239 }
240
241 /*
242 * Enable device:
243 */
244
245 if (dev->class >> 8 == PCI_CLASS_NOT_DEFINED ||
246 dev->class >> 8 == PCI_CLASS_NOT_DEFINED_VGA ||
247 dev->class >> 8 == PCI_CLASS_DISPLAY_VGA ||
248 dev->class >> 8 == PCI_CLASS_DISPLAY_XGA)
249 {
250 /*
251 * All of these (may) have I/O scattered all around
252 * and may not use i/o-base address registers at all.
253 * So we just have to always enable I/O to these
254 * devices.
255 */
256 cmd |= PCI_COMMAND_IO;
257 }
258
259 pci_write_config_word(dev, PCI_COMMAND, cmd | PCI_COMMAND_MASTER);
260
261 pci_write_config_byte(dev, PCI_LATENCY_TIMER, (disable_pci_burst) ? 0 : 32);
262
263 if (bus_info != NULL)
264 bus_info->conf_device(dev); /* Machine dependent configuration. */
265
266 DBG_DEVS(("layout_dev: bus %d slot 0x%x VID 0x%x DID 0x%x class 0x%x\n",
267 dev->bus->number, PCI_SLOT(dev->devfn), dev->vendor, dev->device, dev->class));
268}
269
270/*
271 * static void layout_bus(struct pci_bus *bus)
272 *
273 * Layout memory and I/O for all devices on the given bus.
274 *
275 * Parameters:
276 *
277 * bus - bus.
278 */
279
280static void __init layout_bus(struct pci_bus *bus)
281{
282 unsigned int bio, bmem;
283 struct pci_dev *dev;
284
285 DBG_DEVS(("layout_bus: starting bus %d\n", bus->number));
286
287 if (!bus->devices && !bus->children)
288 return;
289
290 /*
291 * Align the current bases on appropriate boundaries (4K for
292 * IO and 1MB for memory).
293 */
294
295 bio = io_base = ALIGN(io_base, 4*KB);
296 bmem = mem_base = ALIGN(mem_base, 1*MB);
297
298 /*
299 * PCI devices might have been setup by a PCI BIOS emulation
300 * running under TOS. In these cases there is a
301 * window during which two devices may have an overlapping
302 * address range. To avoid this causing trouble, we first
303 * turn off the I/O and memory address decoders for all PCI
304 * devices. They'll be re-enabled only once all address
305 * decoders are programmed consistently.
306 */
307
308 DBG_DEVS(("layout_bus: disable_dev for bus %d\n", bus->number));
309
310 for (dev = bus->devices; dev; dev = dev->sibling)
311 {
312 if ((dev->class >> 16 != PCI_BASE_CLASS_BRIDGE) ||
313 (dev->class >> 8 == PCI_CLASS_BRIDGE_PCMCIA))
314 disable_dev(dev);
315 }
316
317 /*
318 * Allocate space to each device:
319 */
320
321 DBG_DEVS(("layout_bus: starting bus %d devices\n", bus->number));
322
323 for (dev = bus->devices; dev; dev = dev->sibling)
324 {
325 if ((dev->class >> 16 != PCI_BASE_CLASS_BRIDGE) ||
326 (dev->class >> 8 == PCI_CLASS_BRIDGE_PCMCIA))
327 layout_dev(dev);
328 }
329
330 DBG_DEVS(("layout_bus: bus %d finished\n", bus->number));
331}
332
333/*
334 * static void pcibios_fixup(void)
335 *
336 * Layout memory and I/O of all devices on the PCI bus if 'pci_modify' is
337 * true. This might be necessary because not every m68k machine with a PCI
338 * bus has a PCI BIOS. This function should be called right after
339 * pci_scan_bus() in pcibios_init().
340 */
341
342static void __init pcibios_fixup(void)
343{
344 if (pci_modify)
345 {
346 /*
347 * Set base addresses for allocation of I/O and memory space.
348 */
349
350 io_base = bus_info->io_space.start + IO_ALLOC_OFFSET;
351 mem_base = bus_info->mem_space.start + MEM_ALLOC_OFFSET;
352
353 /*
354 * Scan the tree, allocating PCI memory and I/O space.
355 */
356
357 layout_bus(pci_bus_b(pci_root.next));
358 }
359
360 /*
361 * Fix interrupt assignments, etc.
362 */
363
364 bus_info->fixup(pci_modify);
365}
366
367/*
368 * static void pcibios_claim_resources(struct pci_bus *bus)
369 *
370 * Claim all resources that are assigned to devices on the given bus.
371 *
372 * Parameters:
373 *
374 * bus - bus.
375 */
376
377static void __init pcibios_claim_resources(struct pci_bus *bus)
378{
379 struct pci_dev *dev;
380 int i;
381
382 while (bus)
383 {
384 for (dev = bus->devices; (dev != NULL); dev = dev->sibling)
385 {
386 for (i = 0; i < PCI_NUM_RESOURCES; i++)
387 {
388 struct resource *r = &dev->resource[i];
389 struct resource *pr;
390 struct pci_bus_info *bus_info = (struct pci_bus_info *) dev->sysdata;
391
392 if ((r->start == 0) || (r->parent != NULL))
393 continue;
394#if 1
395 if (r->flags & IORESOURCE_IO)
396 pr = &bus_info->io_space;
397 else
398 pr = &bus_info->mem_space;
399#else
400 if (r->flags & IORESOURCE_IO)
401 pr = &ioport_resource;
402 else
403 pr = &iomem_resource;
404#endif
405 if (request_resource(pr, r) < 0)
406 {
407 printk(KERN_ERR "PCI: Address space collision on region %d of device %s\n", i, dev->name);
408 }
409 }
410 }
411
412 if (bus->children)
413 pcibios_claim_resources(bus->children);
414
415 bus = bus->next;
416 }
417}
418
419/*
420 * int pcibios_assign_resource(struct pci_dev *dev, int i)
421 *
422 * Assign a new address to a PCI resource.
423 *
424 * Parameters:
425 *
426 * dev - device.
427 * i - resource.
428 *
429 * Result: 0 if successful.
430 */
431
432int __init pcibios_assign_resource(struct pci_dev *dev, int i)
433{
434 struct resource *r = &dev->resource[i];
435 struct resource *pr = pci_find_parent_resource(dev, r);
436 unsigned long size = r->end + 1;
437
438 if (!pr)
439 return -EINVAL;
440
441 if (r->flags & IORESOURCE_IO)
442 {
443 if (size > 0x100)
444 return -EFBIG;
445
446 if (allocate_resource(pr, r, size, bus_info->io_space.start +
447 IO_ALLOC_OFFSET, bus_info->io_space.end, 1024))
448 return -EBUSY;
449 }
450 else
451 {
452 if (allocate_resource(pr, r, size, bus_info->mem_space.start +
453 MEM_ALLOC_OFFSET, bus_info->mem_space.end, size))
454 return -EBUSY;
455 }
456
457 if (i < 6)
458 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + 4 * i, r->start);
459
460 return 0;
461}
462
463void __init pcibios_fixup_bus(struct pci_bus *bus)
464{
465 struct pci_dev *dev;
466 void *sysdata;
467
468 sysdata = (bus->parent) ? bus->parent->sysdata : bus->sysdata;
469
470 for (dev = bus->devices; (dev != NULL); dev = dev->sibling)
471 dev->sysdata = sysdata;
472}
473
474void __init pcibios_init(void)
475{
476 printk("Linux/m68k PCI BIOS32 revision %x.%02x\n", MAJOR_REV, MINOR_REV);
477
478 bus_info = NULL;
479
480/* Hades code was:
481 if (MACH_IS_HADES)
482 bus_info = init_hades_pci();
483*/
484
485 if (bus_info != NULL)
486 {
487 printk("PCI: Probing PCI hardware\n");
488 pci_scan_bus(0, bus_info->m68k_pci_ops, bus_info);
489 pcibios_fixup();
490 pcibios_claim_resources(pci_root);
491 }
492 else
493 printk("PCI: No PCI bus detected\n");
494}
495
496char * __init pcibios_setup(char *str)
497{
498 if (!strcmp(str, "nomodify"))
499 {
500 pci_modify = 0;
501 return NULL;
502 }
503 else if (!strcmp(str, "skipvga"))
504 {
505 skip_vga = 1;
506 return NULL;
507 }
508 else if (!strcmp(str, "noburst"))
509 {
510 disable_pci_burst = 1;
511 return NULL;
512 }
513
514 return str;
515}
516#endif /* CONFIG_PCI */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-15 20:47:46 -0500