19 files changed, 192 insertions, 204 deletions

diff --git a/arch/m68k/platform/coldfire/clk.c b/arch/m68k/platform/coldfire/clk.c
index 75f9ee967ea7..9cd13b4ce42b 100644
--- a/arch/m68k/platform/coldfire/clk.c
+++ b/arch/m68k/platform/coldfire/clk.c
@@ -146,9 +146,3 @@ struct clk_ops clk_ops1 = {
 };
 #endif /* MCFPM_PPMCR1 */
 #endif /* MCFPM_PPMCR0 */
-
-struct clk *devm_clk_get(struct device *dev, const char *id)
-{
-        return NULL;
-}
-EXPORT_SYMBOL(devm_clk_get);
diff --git a/arch/m68k/platform/coldfire/device.c b/arch/m68k/platform/coldfire/device.c
index 81f0fb5e51cf..71ea4c02795d 100644
--- a/arch/m68k/platform/coldfire/device.c
+++ b/arch/m68k/platform/coldfire/device.c
@@ -347,12 +347,12 @@ static void __init mcf_uart_set_irq(void)
 {
 #ifdef MCFUART_UIVR
         /* UART0 interrupt setup */
-        writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR);
+        writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCFSIM_UART1ICR);
         writeb(MCF_IRQ_UART0, MCFUART_BASE0 + MCFUART_UIVR);
         mcf_mapirq2imr(MCF_IRQ_UART0, MCFINTC_UART0);
 
         /* UART1 interrupt setup */
-        writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR);
+        writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCFSIM_UART2ICR);
         writeb(MCF_IRQ_UART1, MCFUART_BASE1 + MCFUART_UIVR);
         mcf_mapirq2imr(MCF_IRQ_UART1, MCFINTC_UART1);
 #endif
diff --git a/arch/m68k/platform/coldfire/head.S b/arch/m68k/platform/coldfire/head.S
index b88f5716f357..fa31be297b85 100644
--- a/arch/m68k/platform/coldfire/head.S
+++ b/arch/m68k/platform/coldfire/head.S
@@ -60,7 +60,7 @@
 
 #elif defined(CONFIG_M5272)
 .macro GET_MEM_SIZE
-        movel   MCF_MBAR+MCFSIM_CSOR7,%d0 /* get SDRAM address mask */
+        movel   MCFSIM_CSOR7,%d0        /* get SDRAM address mask */
         andil   #0xfffff000,%d0         /* mask out chip select options */
         negl    %d0                     /* negate bits */
 .endm
diff --git a/arch/m68k/platform/coldfire/intc-5249.c b/arch/m68k/platform/coldfire/intc-5249.c
index f343bf7bf5b0..0864b836699a 100644
--- a/arch/m68k/platform/coldfire/intc-5249.c
+++ b/arch/m68k/platform/coldfire/intc-5249.c
@@ -20,22 +20,22 @@
 static void intc2_irq_gpio_mask(struct irq_data *d)
 {
         u32 imr;
-        imr = readl(MCF_MBAR2 + MCFSIM2_GPIOINTENABLE);
+        imr = readl(MCFSIM2_GPIOINTENABLE);
         imr &= ~(0x1 << (d->irq - MCFINTC2_GPIOIRQ0));
-        writel(imr, MCF_MBAR2 + MCFSIM2_GPIOINTENABLE);
+        writel(imr, MCFSIM2_GPIOINTENABLE);
 }
 
 static void intc2_irq_gpio_unmask(struct irq_data *d)
 {
         u32 imr;
-        imr = readl(MCF_MBAR2 + MCFSIM2_GPIOINTENABLE);
+        imr = readl(MCFSIM2_GPIOINTENABLE);
         imr |= (0x1 << (d->irq - MCFINTC2_GPIOIRQ0));
-        writel(imr, MCF_MBAR2 + MCFSIM2_GPIOINTENABLE);
+        writel(imr, MCFSIM2_GPIOINTENABLE);
 }
 
 static void intc2_irq_gpio_ack(struct irq_data *d)
 {
-        writel(0x1 << (d->irq - MCFINTC2_GPIOIRQ0), MCF_MBAR2 + MCFSIM2_GPIOINTCLEAR);
+        writel(0x1 << (d->irq - MCFINTC2_GPIOIRQ0), MCFSIM2_GPIOINTCLEAR);
 }
 
 static struct irq_chip intc2_irq_gpio_chip = {
diff --git a/arch/m68k/platform/coldfire/intc-5272.c b/arch/m68k/platform/coldfire/intc-5272.c
index 7160e618b0a9..d7b695629a7e 100644
--- a/arch/m68k/platform/coldfire/intc-5272.c
+++ b/arch/m68k/platform/coldfire/intc-5272.c
@@ -86,7 +86,7 @@ static void intc_irq_mask(struct irq_data *d)
                 u32 v;
                 irq -= MCFINT_VECBASE;
                 v = 0x8 << intc_irqmap[irq].index;
-                writel(v, MCF_MBAR + intc_irqmap[irq].icr);
+                writel(v, intc_irqmap[irq].icr);
         }
 }
 
@@ -98,7 +98,7 @@ static void intc_irq_unmask(struct irq_data *d)
                 u32 v;
                 irq -= MCFINT_VECBASE;
                 v = 0xd << intc_irqmap[irq].index;
-                writel(v, MCF_MBAR + intc_irqmap[irq].icr);
+                writel(v, intc_irqmap[irq].icr);
         }
 }
 
@@ -111,10 +111,10 @@ static void intc_irq_ack(struct irq_data *d)
                 irq -= MCFINT_VECBASE;
                 if (intc_irqmap[irq].ack) {
                         u32 v;
-                        v = readl(MCF_MBAR + intc_irqmap[irq].icr);
+                        v = readl(intc_irqmap[irq].icr);
                         v &= (0x7 << intc_irqmap[irq].index);
                         v |= (0x8 << intc_irqmap[irq].index);
-                        writel(v, MCF_MBAR + intc_irqmap[irq].icr);
+                        writel(v, intc_irqmap[irq].icr);
                 }
         }
 }
@@ -127,12 +127,12 @@ static int intc_irq_set_type(struct irq_data *d, unsigned int type)
                 irq -= MCFINT_VECBASE;
                 if (intc_irqmap[irq].ack) {
                         u32 v;
-                        v = readl(MCF_MBAR + MCFSIM_PITR);
+                        v = readl(MCFSIM_PITR);
                         if (type == IRQ_TYPE_EDGE_FALLING)
                                 v &= ~(0x1 << (32 - irq));
                         else
                                 v |= (0x1 << (32 - irq));
-                        writel(v, MCF_MBAR + MCFSIM_PITR);
+                        writel(v, MCFSIM_PITR);
                 }
         }
         return 0;
@@ -163,10 +163,10 @@ void __init init_IRQ(void)
         int irq, edge;
 
         /* Mask all interrupt sources */
-        writel(0x88888888, MCF_MBAR + MCFSIM_ICR1);
-        writel(0x88888888, MCF_MBAR + MCFSIM_ICR2);
-        writel(0x88888888, MCF_MBAR + MCFSIM_ICR3);
-        writel(0x88888888, MCF_MBAR + MCFSIM_ICR4);
+        writel(0x88888888, MCFSIM_ICR1);
+        writel(0x88888888, MCFSIM_ICR2);
+        writel(0x88888888, MCFSIM_ICR3);
+        writel(0x88888888, MCFSIM_ICR4);
 
         for (irq = 0; (irq < NR_IRQS); irq++) {
                 irq_set_chip(irq, &intc_irq_chip);
diff --git a/arch/m68k/platform/coldfire/intc.c b/arch/m68k/platform/coldfire/intc.c
index 5c0c150b4067..cce257420388 100644
--- a/arch/m68k/platform/coldfire/intc.c
+++ b/arch/m68k/platform/coldfire/intc.c
@@ -45,23 +45,23 @@ unsigned char mcf_irq2imr[NR_IRQS];
 void mcf_setimr(int index)
 {
         u16 imr;
-        imr = __raw_readw(MCF_MBAR + MCFSIM_IMR);
-        __raw_writew(imr | (0x1 << index), MCF_MBAR + MCFSIM_IMR);
+        imr = __raw_readw(MCFSIM_IMR);
+        __raw_writew(imr | (0x1 << index), MCFSIM_IMR);
 }
 
 void mcf_clrimr(int index)
 {
         u16 imr;
-        imr = __raw_readw(MCF_MBAR + MCFSIM_IMR);
-        __raw_writew(imr & ~(0x1 << index), MCF_MBAR + MCFSIM_IMR);
+        imr = __raw_readw(MCFSIM_IMR);
+        __raw_writew(imr & ~(0x1 << index), MCFSIM_IMR);
 }
 
 void mcf_maskimr(unsigned int mask)
 {
         u16 imr;
-        imr = __raw_readw(MCF_MBAR + MCFSIM_IMR);
+        imr = __raw_readw(MCFSIM_IMR);
         imr |= mask;
-        __raw_writew(imr, MCF_MBAR + MCFSIM_IMR);
+        __raw_writew(imr, MCFSIM_IMR);
 }
 
 #else
@@ -69,23 +69,23 @@ void mcf_maskimr(unsigned int mask)
 void mcf_setimr(int index)
 {
         u32 imr;
-        imr = __raw_readl(MCF_MBAR + MCFSIM_IMR);
-        __raw_writel(imr | (0x1 << index), MCF_MBAR + MCFSIM_IMR);
+        imr = __raw_readl(MCFSIM_IMR);
+        __raw_writel(imr | (0x1 << index), MCFSIM_IMR);
 }
 
 void mcf_clrimr(int index)
 {
         u32 imr;
-        imr = __raw_readl(MCF_MBAR + MCFSIM_IMR);
-        __raw_writel(imr & ~(0x1 << index), MCF_MBAR + MCFSIM_IMR);
+        imr = __raw_readl(MCFSIM_IMR);
+        __raw_writel(imr & ~(0x1 << index), MCFSIM_IMR);
 }
 
 void mcf_maskimr(unsigned int mask)
 {
         u32 imr;
-        imr = __raw_readl(MCF_MBAR + MCFSIM_IMR);
+        imr = __raw_readl(MCFSIM_IMR);
         imr |= mask;
-        __raw_writel(imr, MCF_MBAR + MCFSIM_IMR);
+        __raw_writel(imr, MCFSIM_IMR);
 }
 
 #endif
@@ -104,9 +104,9 @@ void mcf_autovector(int irq)
 #ifdef MCFSIM_AVR
         if ((irq >= EIRQ1) && (irq <= EIRQ7)) {
                 u8 avec;
-                avec = __raw_readb(MCF_MBAR + MCFSIM_AVR);
+                avec = __raw_readb(MCFSIM_AVR);
                 avec |= (0x1 << (irq - EIRQ1 + 1));
-                __raw_writeb(avec, MCF_MBAR + MCFSIM_AVR);
+                __raw_writeb(avec, MCFSIM_AVR);
         }
 #endif
 }
diff --git a/arch/m68k/platform/coldfire/m523x.c b/arch/m68k/platform/coldfire/m523x.c
index d47dfd8f50a2..ff37fe9553ea 100644
--- a/arch/m68k/platform/coldfire/m523x.c
+++ b/arch/m68k/platform/coldfire/m523x.c
@@ -42,14 +42,8 @@ static void __init m523x_qspi_init(void)
 
 static void __init m523x_fec_init(void)
 {
-        u16 par;
-        u8 v;
-
         /* Set multi-function pins to ethernet use */
-        par = readw(MCF_IPSBAR + 0x100082);
-        writew(par | 0xf00, MCF_IPSBAR + 0x100082);
-        v = readb(MCF_IPSBAR + 0x100078);
-        writeb(v | 0xc0, MCF_IPSBAR + 0x100078);
+        writeb(readb(MCFGPIO_PAR_FECI2C) | 0xf0, MCFGPIO_PAR_FECI2C);
 }
 
 /***************************************************************************/
diff --git a/arch/m68k/platform/coldfire/m5249.c b/arch/m68k/platform/coldfire/m5249.c
index 300e729a58d0..23b19cb7ab50 100644
--- a/arch/m68k/platform/coldfire/m5249.c
+++ b/arch/m68k/platform/coldfire/m5249.c
@@ -57,7 +57,7 @@ static void __init m5249_qspi_init(void)
 {
         /* QSPI irq setup */
         writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL4 | MCFSIM_ICR_PRI0,
-               MCF_MBAR + MCFSIM_QSPIICR);
+               MCFSIM_QSPIICR);
         mcf_mapirq2imr(MCF_IRQ_QSPI, MCFINTC_QSPI);
 }
 
@@ -72,11 +72,11 @@ static void __init m5249_smc91x_init(void)
         u32  gpio;
 
         /* Set the GPIO line as interrupt source for smc91x device */
-        gpio = readl(MCF_MBAR2 + MCFSIM2_GPIOINTENABLE);
-        writel(gpio | 0x40, MCF_MBAR2 + MCFSIM2_GPIOINTENABLE);
+        gpio = readl(MCFSIM2_GPIOINTENABLE);
+        writel(gpio | 0x40, MCFSIM2_GPIOINTENABLE);
 
-        gpio = readl(MCF_MBAR2 + MCFSIM2_INTLEVEL5);
-        writel(gpio | 0x04000000, MCF_MBAR2 + MCFSIM2_INTLEVEL5);
+        gpio = readl(MCFSIM2_INTLEVEL5);
+        writel(gpio | 0x04000000, MCFSIM2_INTLEVEL5);
 }
 
 #endif /* CONFIG_M5249C3 */
diff --git a/arch/m68k/platform/coldfire/m525x.c b/arch/m68k/platform/coldfire/m525x.c
index 8ce905f9b84f..fce8f8a45bf0 100644
--- a/arch/m68k/platform/coldfire/m525x.c
+++ b/arch/m68k/platform/coldfire/m525x.c
@@ -30,7 +30,7 @@ static void __init m525x_qspi_init(void)
 
         /* QSPI irq setup */
         writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL4 | MCFSIM_ICR_PRI0,
-               MCF_MBAR + MCFSIM_QSPIICR);
+               MCFSIM_QSPIICR);
         mcf_mapirq2imr(MCF_IRQ_QSPI, MCFINTC_QSPI);
 #endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
 }
@@ -42,7 +42,7 @@ static void __init m525x_i2c_init(void)
 
         /* first I2C controller uses regular irq setup */
         writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI0,
-                        MCF_MBAR + MCFSIM_I2CICR);
+                MCFSIM_I2CICR);
         mcf_mapirq2imr(MCF_IRQ_I2C0, MCFINTC_I2C);
 
         /* second I2C controller is completely different */
diff --git a/arch/m68k/platform/coldfire/m5272.c b/arch/m68k/platform/coldfire/m5272.c
index e68bc7a148eb..45b246d052ef 100644
--- a/arch/m68k/platform/coldfire/m5272.c
+++ b/arch/m68k/platform/coldfire/m5272.c
@@ -35,13 +35,13 @@ static void __init m5272_uarts_init(void)
         u32 v;
 
         /* Enable the output lines for the serial ports */
-        v = readl(MCF_MBAR + MCFSIM_PBCNT);
+        v = readl(MCFSIM_PBCNT);
         v = (v & ~0x000000ff) | 0x00000055;
-        writel(v, MCF_MBAR + MCFSIM_PBCNT);
+        writel(v, MCFSIM_PBCNT);
 
-        v = readl(MCF_MBAR + MCFSIM_PDCNT);
+        v = readl(MCFSIM_PDCNT);
         v = (v & ~0x000003fc) | 0x000002a8;
-        writel(v, MCF_MBAR + MCFSIM_PDCNT);
+        writel(v, MCFSIM_PDCNT);
 }
 
 /***************************************************************************/
@@ -50,9 +50,9 @@ static void m5272_cpu_reset(void)
 {
         local_irq_disable();
         /* Set watchdog to reset, and enabled */
-        __raw_writew(0, MCF_MBAR + MCFSIM_WIRR);
-        __raw_writew(1, MCF_MBAR + MCFSIM_WRRR);
-        __raw_writew(0, MCF_MBAR + MCFSIM_WCR);
+        __raw_writew(0, MCFSIM_WIRR);
+        __raw_writew(1, MCFSIM_WRRR);
+        __raw_writew(0, MCFSIM_WCR);
         for (;;)
                 /* wait for watchdog to timeout */;
 }
@@ -62,11 +62,8 @@ static void m5272_cpu_reset(void)
 void __init config_BSP(char *commandp, int size)
 {
 #if defined (CONFIG_MOD5272)
-        volatile unsigned char  *pivrp;
-
         /* Set base of device vectors to be 64 */
-        pivrp = (volatile unsigned char *) (MCF_MBAR + MCFSIM_PIVR);
-        *pivrp = 0x40;
+        writeb(0x40, MCFSIM_PIVR);
 #endif
 
 #if defined(CONFIG_NETtel) || defined(CONFIG_SCALES)
diff --git a/arch/m68k/platform/coldfire/m527x.c b/arch/m68k/platform/coldfire/m527x.c
index b3cb378c5e94..1431ba03c602 100644
--- a/arch/m68k/platform/coldfire/m527x.c
+++ b/arch/m68k/platform/coldfire/m527x.c
@@ -53,9 +53,9 @@ static void __init m527x_uarts_init(void)
         /*
          * External Pin Mask Setting & Enable External Pin for Interface
          */
-        sepmask = readw(MCF_IPSBAR + MCF_GPIO_PAR_UART);
+        sepmask = readw(MCFGPIO_PAR_UART);
         sepmask |= UART0_ENABLE_MASK | UART1_ENABLE_MASK | UART2_ENABLE_MASK;
-        writew(sepmask, MCF_IPSBAR + MCF_GPIO_PAR_UART);
+        writew(sepmask, MCFGPIO_PAR_UART);
 }
 
 /***************************************************************************/
@@ -67,19 +67,19 @@ static void __init m527x_fec_init(void)
 
         /* Set multi-function pins to ethernet mode for fec0 */
 #if defined(CONFIG_M5271)
-        v = readb(MCF_IPSBAR + 0x100047);
-        writeb(v | 0xf0, MCF_IPSBAR + 0x100047);
+        v = readb(MCFGPIO_PAR_FECI2C);
+        writeb(v | 0xf0, MCFGPIO_PAR_FECI2C);
 #else
-        par = readw(MCF_IPSBAR + 0x100082);
-        writew(par | 0xf00, MCF_IPSBAR + 0x100082);
-        v = readb(MCF_IPSBAR + 0x100078);
-        writeb(v | 0xc0, MCF_IPSBAR + 0x100078);
+        par = readw(MCFGPIO_PAR_FECI2C);
+        writew(par | 0xf00, MCFGPIO_PAR_FECI2C);
+        v = readb(MCFGPIO_PAR_FEC0HL);
+        writeb(v | 0xc0, MCFGPIO_PAR_FEC0HL);
 
         /* Set multi-function pins to ethernet mode for fec1 */
-        par = readw(MCF_IPSBAR + 0x100082);
-        writew(par | 0xa0, MCF_IPSBAR + 0x100082);
-        v = readb(MCF_IPSBAR + 0x100079);
-        writeb(v | 0xc0, MCF_IPSBAR + 0x100079);
+        par = readw(MCFGPIO_PAR_FECI2C);
+        writew(par | 0xa0, MCFGPIO_PAR_FECI2C);
+        v = readb(MCFGPIO_PAR_FEC1HL);
+        writeb(v | 0xc0, MCFGPIO_PAR_FEC1HL);
 #endif
 }
 
diff --git a/arch/m68k/platform/coldfire/m528x.c b/arch/m68k/platform/coldfire/m528x.c
index f1319e5d2546..f9f7e6a13d04 100644
--- a/arch/m68k/platform/coldfire/m528x.c
+++ b/arch/m68k/platform/coldfire/m528x.c
@@ -53,9 +53,9 @@ static void __init m528x_fec_init(void)
         u16 v16;
 
         /* Set multi-function pins to ethernet mode for fec0 */
-        v16 = readw(MCF_IPSBAR + 0x100056);
-        writew(v16 | 0xf00, MCF_IPSBAR + 0x100056);
-        writeb(0xc0, MCF_IPSBAR + 0x100058);
+        v16 = readw(MCFGPIO_PASPAR);
+        writew(v16 | 0xf00, MCFGPIO_PASPAR);
+        writeb(0xc0, MCFGPIO_PEHLPAR);
 }
 
 /***************************************************************************/
diff --git a/arch/m68k/platform/coldfire/m532x.c b/arch/m68k/platform/coldfire/m532x.c
index 4819a44991ed..7951d1d43357 100644
--- a/arch/m68k/platform/coldfire/m532x.c
+++ b/arch/m68k/platform/coldfire/m532x.c
@@ -172,7 +172,7 @@ static void __init m532x_clk_init(void)
 static void __init m532x_qspi_init(void)
 {
         /* setup QSPS pins for QSPI with gpio CS control */
-        writew(0x01f0, MCF_GPIO_PAR_QSPI);
+        writew(0x01f0, MCFGPIO_PAR_QSPI);
 }
 
 #endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
@@ -182,18 +182,24 @@ static void __init m532x_qspi_init(void)
 static void __init m532x_uarts_init(void)
 {
         /* UART GPIO initialization */
-        MCF_GPIO_PAR_UART |= 0x0FFF;
+        writew(readw(MCFGPIO_PAR_UART) | 0x0FFF, MCFGPIO_PAR_UART);
 }
 
 /***************************************************************************/
 
 static void __init m532x_fec_init(void)
 {
+        u8 v;
+
         /* Set multi-function pins to ethernet mode for fec0 */
-        MCF_GPIO_PAR_FECI2C |= (MCF_GPIO_PAR_FECI2C_PAR_MDC_EMDC |
-                MCF_GPIO_PAR_FECI2C_PAR_MDIO_EMDIO);
-        MCF_GPIO_PAR_FEC = (MCF_GPIO_PAR_FEC_PAR_FEC_7W_FEC |
-                MCF_GPIO_PAR_FEC_PAR_FEC_MII_FEC);
+        v = readb(MCFGPIO_PAR_FECI2C);
+        v |= MCF_GPIO_PAR_FECI2C_PAR_MDC_EMDC |
+                MCF_GPIO_PAR_FECI2C_PAR_MDIO_EMDIO;
+        writeb(v, MCFGPIO_PAR_FECI2C);
+
+        v = readb(MCFGPIO_PAR_FEC);
+        v = MCF_GPIO_PAR_FEC_PAR_FEC_7W_FEC | MCF_GPIO_PAR_FEC_PAR_FEC_MII_FEC;
+        writeb(v, MCFGPIO_PAR_FEC);
 }
 
 /***************************************************************************/
@@ -298,7 +304,7 @@ asmlinkage void __init sysinit(void)
 void wtm_init(void)
 {
         /* Disable watchdog timer */
-        MCF_WTM_WCR = 0;
+        writew(0, MCF_WTM_WCR);
 }
 
 #define MCF_SCM_BCR_GBW         (0x00000100)
@@ -307,53 +313,53 @@ void wtm_init(void)
 void scm_init(void)
 {
         /* All masters are trusted */
-        MCF_SCM_MPR = 0x77777777;
+        writel(0x77777777, MCF_SCM_MPR);
     
         /* Allow supervisor/user, read/write, and trusted/untrusted
            access to all slaves */
-        MCF_SCM_PACRA = 0;
-        MCF_SCM_PACRB = 0;
-        MCF_SCM_PACRC = 0;
-        MCF_SCM_PACRD = 0;
-        MCF_SCM_PACRE = 0;
-        MCF_SCM_PACRF = 0;
+        writel(0, MCF_SCM_PACRA);
+        writel(0, MCF_SCM_PACRB);
+        writel(0, MCF_SCM_PACRC);
+        writel(0, MCF_SCM_PACRD);
+        writel(0, MCF_SCM_PACRE);
+        writel(0, MCF_SCM_PACRF);
 
         /* Enable bursts */
-        MCF_SCM_BCR = (MCF_SCM_BCR_GBR | MCF_SCM_BCR_GBW);
+        writel(MCF_SCM_BCR_GBR | MCF_SCM_BCR_GBW, MCF_SCM_BCR);
 }
 
 
 void fbcs_init(void)
 {
-        MCF_GPIO_PAR_CS = 0x0000003E;
+        writeb(0x3E, MCFGPIO_PAR_CS);
 
         /* Latch chip select */
-        MCF_FBCS1_CSAR = 0x10080000;
+        writel(0x10080000, MCF_FBCS1_CSAR);
 
-        MCF_FBCS1_CSCR = 0x002A3780;
-        MCF_FBCS1_CSMR = (MCF_FBCS_CSMR_BAM_2M | MCF_FBCS_CSMR_V);
+        writel(0x002A3780, MCF_FBCS1_CSCR);
+        writel(MCF_FBCS_CSMR_BAM_2M | MCF_FBCS_CSMR_V, MCF_FBCS1_CSMR);
 
         /* Initialize latch to drive signals to inactive states */
-        *((u16 *)(0x10080000)) = 0xFFFF;
+        writew(0xffff, 0x10080000);
 
         /* External SRAM */
-        MCF_FBCS1_CSAR = EXT_SRAM_ADDRESS;
-        MCF_FBCS1_CSCR = (MCF_FBCS_CSCR_PS_16
-                        | MCF_FBCS_CSCR_AA
-                        | MCF_FBCS_CSCR_SBM
-                        | MCF_FBCS_CSCR_WS(1));
-        MCF_FBCS1_CSMR = (MCF_FBCS_CSMR_BAM_512K
-                        | MCF_FBCS_CSMR_V);
+        writel(EXT_SRAM_ADDRESS, MCF_FBCS1_CSAR);
+        writel(MCF_FBCS_CSCR_PS_16 |
+                MCF_FBCS_CSCR_AA |
+                MCF_FBCS_CSCR_SBM |
+                MCF_FBCS_CSCR_WS(1),
+                MCF_FBCS1_CSCR);
+        writel(MCF_FBCS_CSMR_BAM_512K | MCF_FBCS_CSMR_V, MCF_FBCS1_CSMR);
 
         /* Boot Flash connected to FBCS0 */
-        MCF_FBCS0_CSAR = FLASH_ADDRESS;
-        MCF_FBCS0_CSCR = (MCF_FBCS_CSCR_PS_16
-                        | MCF_FBCS_CSCR_BEM
-                        | MCF_FBCS_CSCR_AA
-                        | MCF_FBCS_CSCR_SBM
-                        | MCF_FBCS_CSCR_WS(7));
-        MCF_FBCS0_CSMR = (MCF_FBCS_CSMR_BAM_32M
-                        | MCF_FBCS_CSMR_V);
+        writel(FLASH_ADDRESS, MCF_FBCS0_CSAR);
+        writel(MCF_FBCS_CSCR_PS_16 |
+                MCF_FBCS_CSCR_BEM |
+                MCF_FBCS_CSCR_AA |
+                MCF_FBCS_CSCR_SBM |
+                MCF_FBCS_CSCR_WS(7),
+                MCF_FBCS0_CSCR);
+        writel(MCF_FBCS_CSMR_BAM_32M | MCF_FBCS_CSMR_V, MCF_FBCS0_CSMR);
 }
 
 void sdramc_init(void)
@@ -362,102 +368,102 @@ void sdramc_init(void)
          * Check to see if the SDRAM has already been initialized
          * by a run control tool
          */
-        if (!(MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF)) {
+        if (!(readl(MCF_SDRAMC_SDCR) & MCF_SDRAMC_SDCR_REF)) {
                 /* SDRAM chip select initialization */
                 
                 /* Initialize SDRAM chip select */
-                MCF_SDRAMC_SDCS0 = (0
-                        | MCF_SDRAMC_SDCS_BA(SDRAM_ADDRESS)
-                        | MCF_SDRAMC_SDCS_CSSZ(MCF_SDRAMC_SDCS_CSSZ_32MBYTE));
+                writel(MCF_SDRAMC_SDCS_BA(SDRAM_ADDRESS) |
+                        MCF_SDRAMC_SDCS_CSSZ(MCF_SDRAMC_SDCS_CSSZ_32MBYTE),
+                        MCF_SDRAMC_SDCS0);
 
         /*
          * Basic configuration and initialization
          */
-        MCF_SDRAMC_SDCFG1 = (0
-                | MCF_SDRAMC_SDCFG1_SRD2RW((int)((SDRAM_CASL + 2) + 0.5 ))
-                | MCF_SDRAMC_SDCFG1_SWT2RD(SDRAM_TWR + 1)
-                | MCF_SDRAMC_SDCFG1_RDLAT((int)((SDRAM_CASL*2) + 2))
-                | MCF_SDRAMC_SDCFG1_ACT2RW((int)((SDRAM_TRCD ) + 0.5))
-                | MCF_SDRAMC_SDCFG1_PRE2ACT((int)((SDRAM_TRP ) + 0.5))
-                | MCF_SDRAMC_SDCFG1_REF2ACT((int)(((SDRAM_TRFC) ) + 0.5))
-                | MCF_SDRAMC_SDCFG1_WTLAT(3));
-        MCF_SDRAMC_SDCFG2 = (0
-                | MCF_SDRAMC_SDCFG2_BRD2PRE(SDRAM_BL/2 + 1)
-                | MCF_SDRAMC_SDCFG2_BWT2RW(SDRAM_BL/2 + SDRAM_TWR)
-                | MCF_SDRAMC_SDCFG2_BRD2WT((int)((SDRAM_CASL+SDRAM_BL/2-1.0)+0.5))
-                | MCF_SDRAMC_SDCFG2_BL(SDRAM_BL-1));
+        writel(MCF_SDRAMC_SDCFG1_SRD2RW((int)((SDRAM_CASL + 2) + 0.5)) |
+                MCF_SDRAMC_SDCFG1_SWT2RD(SDRAM_TWR + 1) |
+                MCF_SDRAMC_SDCFG1_RDLAT((int)((SDRAM_CASL * 2) + 2)) |
+                MCF_SDRAMC_SDCFG1_ACT2RW((int)(SDRAM_TRCD + 0.5)) |
+                MCF_SDRAMC_SDCFG1_PRE2ACT((int)(SDRAM_TRP + 0.5)) |
+                MCF_SDRAMC_SDCFG1_REF2ACT((int)(SDRAM_TRFC + 0.5)) |
+                MCF_SDRAMC_SDCFG1_WTLAT(3),
+                MCF_SDRAMC_SDCFG1);
+        writel(MCF_SDRAMC_SDCFG2_BRD2PRE(SDRAM_BL / 2 + 1) |
+                MCF_SDRAMC_SDCFG2_BWT2RW(SDRAM_BL / 2 + SDRAM_TWR) |
+                MCF_SDRAMC_SDCFG2_BRD2WT((int)((SDRAM_CASL + SDRAM_BL / 2 - 1.0) + 0.5)) |
+                MCF_SDRAMC_SDCFG2_BL(SDRAM_BL - 1),
+                MCF_SDRAMC_SDCFG2);
 
             
         /*
          * Precharge and enable write to SDMR
          */
-        MCF_SDRAMC_SDCR = (0
-                | MCF_SDRAMC_SDCR_MODE_EN
-                | MCF_SDRAMC_SDCR_CKE
-                | MCF_SDRAMC_SDCR_DDR
-                | MCF_SDRAMC_SDCR_MUX(1)
-                | MCF_SDRAMC_SDCR_RCNT((int)(((SDRAM_TREFI/(SYSTEM_PERIOD*64)) - 1) + 0.5))
-                | MCF_SDRAMC_SDCR_PS_16
-                | MCF_SDRAMC_SDCR_IPALL);            
+        writel(MCF_SDRAMC_SDCR_MODE_EN |
+                MCF_SDRAMC_SDCR_CKE |
+                MCF_SDRAMC_SDCR_DDR |
+                MCF_SDRAMC_SDCR_MUX(1) |
+                MCF_SDRAMC_SDCR_RCNT((int)(((SDRAM_TREFI / (SYSTEM_PERIOD * 64)) - 1) + 0.5)) |
+                MCF_SDRAMC_SDCR_PS_16 |
+                MCF_SDRAMC_SDCR_IPALL,
+                MCF_SDRAMC_SDCR);
 
         /*
          * Write extended mode register
          */
-        MCF_SDRAMC_SDMR = (0
-                | MCF_SDRAMC_SDMR_BNKAD_LEMR
-                | MCF_SDRAMC_SDMR_AD(0x0)
-                | MCF_SDRAMC_SDMR_CMD);
+        writel(MCF_SDRAMC_SDMR_BNKAD_LEMR |
+                MCF_SDRAMC_SDMR_AD(0x0) |
+                MCF_SDRAMC_SDMR_CMD,
+                MCF_SDRAMC_SDMR);
 
         /*
          * Write mode register and reset DLL
          */
-        MCF_SDRAMC_SDMR = (0
-                | MCF_SDRAMC_SDMR_BNKAD_LMR
-                | MCF_SDRAMC_SDMR_AD(0x163)
-                | MCF_SDRAMC_SDMR_CMD);
+        writel(MCF_SDRAMC_SDMR_BNKAD_LMR |
+                MCF_SDRAMC_SDMR_AD(0x163) |
+                MCF_SDRAMC_SDMR_CMD,
+                MCF_SDRAMC_SDMR);
 
         /*
          * Execute a PALL command
          */
-        MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IPALL;
+        writel(readl(MCF_SDRAMC_SDCR) | MCF_SDRAMC_SDCR_IPALL, MCF_SDRAMC_SDCR);
 
         /*
          * Perform two REF cycles
          */
-        MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IREF;
-        MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IREF;
+        writel(readl(MCF_SDRAMC_SDCR) | MCF_SDRAMC_SDCR_IREF, MCF_SDRAMC_SDCR);
+        writel(readl(MCF_SDRAMC_SDCR) | MCF_SDRAMC_SDCR_IREF, MCF_SDRAMC_SDCR);
 
         /*
          * Write mode register and clear reset DLL
          */
-        MCF_SDRAMC_SDMR = (0
-                | MCF_SDRAMC_SDMR_BNKAD_LMR
-                | MCF_SDRAMC_SDMR_AD(0x063)
-                | MCF_SDRAMC_SDMR_CMD);
+        writel(MCF_SDRAMC_SDMR_BNKAD_LMR |
+                MCF_SDRAMC_SDMR_AD(0x063) |
+                MCF_SDRAMC_SDMR_CMD,
+                MCF_SDRAMC_SDMR);
                                 
         /*
          * Enable auto refresh and lock SDMR
          */
-        MCF_SDRAMC_SDCR &= ~MCF_SDRAMC_SDCR_MODE_EN;
-        MCF_SDRAMC_SDCR |= (0
-                | MCF_SDRAMC_SDCR_REF
-                | MCF_SDRAMC_SDCR_DQS_OE(0xC));
+        writel(readl(MCF_SDRAMC_SDCR) & ~MCF_SDRAMC_SDCR_MODE_EN,
+                MCF_SDRAMC_SDCR);
+        writel(MCF_SDRAMC_SDCR_REF | MCF_SDRAMC_SDCR_DQS_OE(0xC),
+                MCF_SDRAMC_SDCR);
         }
 }
 
 void gpio_init(void)
 {
         /* Enable UART0 pins */
-        MCF_GPIO_PAR_UART = ( 0
-                | MCF_GPIO_PAR_UART_PAR_URXD0
-                | MCF_GPIO_PAR_UART_PAR_UTXD0);
-
-        /* Initialize TIN3 as a GPIO output to enable the write
-           half of the latch */
-        MCF_GPIO_PAR_TIMER = 0x00;
-        __raw_writeb(0x08, MCFGPIO_PDDR_TIMER);
-        __raw_writeb(0x00, MCFGPIO_PCLRR_TIMER);
+        writew(MCF_GPIO_PAR_UART_PAR_URXD0 | MCF_GPIO_PAR_UART_PAR_UTXD0,
+                MCFGPIO_PAR_UART);
 
+        /*
+         * Initialize TIN3 as a GPIO output to enable the write
+         * half of the latch.
+         */
+        writeb(0x00, MCFGPIO_PAR_TIMER);
+        writeb(0x08, MCFGPIO_PDDR_TIMER);
+        writeb(0x00, MCFGPIO_PCLRR_TIMER);
 }
 
 int clock_pll(int fsys, int flags)
@@ -469,7 +475,7 @@ int clock_pll(int fsys, int flags)
         
         if (fsys == 0) {
                 /* Return current PLL output */
-                mfd = MCF_PLL_PFDR;
+                mfd = readb(MCF_PLL_PFDR);
 
                 return (fref * mfd / (BUSDIV * 4));
         }
@@ -495,9 +501,10 @@ int clock_pll(int fsys, int flags)
          * If it has then the SDRAM needs to be put into self refresh
          * mode before reprogramming the PLL.
          */
-        if (MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF)
+        if (readl(MCF_SDRAMC_SDCR) & MCF_SDRAMC_SDCR_REF)
                 /* Put SDRAM into self refresh mode */
-                MCF_SDRAMC_SDCR &= ~MCF_SDRAMC_SDCR_CKE;
+                writel(readl(MCF_SDRAMC_SDCR) & ~MCF_SDRAMC_SDCR_CKE,
+                        MCF_SDRAMC_SDCR);
 
         /*
          * Initialize the PLL to generate the new system clock frequency.
@@ -508,11 +515,10 @@ int clock_pll(int fsys, int flags)
         clock_limp(DEFAULT_LPD);
                                         
         /* Reprogram PLL for desired fsys */
-        MCF_PLL_PODR = (0
-                | MCF_PLL_PODR_CPUDIV(BUSDIV/3)
-                | MCF_PLL_PODR_BUSDIV(BUSDIV));
+        writeb(MCF_PLL_PODR_CPUDIV(BUSDIV/3) | MCF_PLL_PODR_BUSDIV(BUSDIV),
+                MCF_PLL_PODR);
                                                 
-        MCF_PLL_PFDR = mfd;
+        writeb(mfd, MCF_PLL_PFDR);
                 
         /* Exit LIMP mode */
         clock_exit_limp();
@@ -520,12 +526,13 @@ int clock_pll(int fsys, int flags)
         /*
          * Return the SDRAM to normal operation if it is in use.
          */
-        if (MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF)
+        if (readl(MCF_SDRAMC_SDCR) & MCF_SDRAMC_SDCR_REF)
                 /* Exit self refresh mode */
-                MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_CKE;
+                writel(readl(MCF_SDRAMC_SDCR) | MCF_SDRAMC_SDCR_CKE,
+                        MCF_SDRAMC_SDCR);
 
         /* Errata - workaround for SDRAM opeartion after exiting LIMP mode */
-        MCF_SDRAMC_LIMP_FIX = MCF_SDRAMC_REFRESH;
+        writel(MCF_SDRAMC_REFRESH, MCF_SDRAMC_LIMP_FIX);
 
         /* wait for DQS logic to relock */
         for (i = 0; i < 0x200; i++)
@@ -546,14 +553,12 @@ int clock_limp(int div)
     
         /* Save of the current value of the SSIDIV so we don't
            overwrite the value*/
-        temp = (MCF_CCM_CDR & MCF_CCM_CDR_SSIDIV(0xF));
+        temp = readw(MCF_CCM_CDR) & MCF_CCM_CDR_SSIDIV(0xF);
       
         /* Apply the divider to the system clock */
-        MCF_CCM_CDR = ( 0
-                | MCF_CCM_CDR_LPDIV(div)
-                | MCF_CCM_CDR_SSIDIV(temp));
+        writew(MCF_CCM_CDR_LPDIV(div) | MCF_CCM_CDR_SSIDIV(temp), MCF_CCM_CDR);
     
-        MCF_CCM_MISCCR |= MCF_CCM_MISCCR_LIMP;
+        writew(readw(MCF_CCM_MISCCR) | MCF_CCM_MISCCR_LIMP, MCF_CCM_MISCCR);
     
         return (FREF/(3*(1 << div)));
 }
@@ -563,10 +568,10 @@ int clock_exit_limp(void)
         int fout;
         
         /* Exit LIMP mode */
-        MCF_CCM_MISCCR = (MCF_CCM_MISCCR & ~ MCF_CCM_MISCCR_LIMP);
+        writew(readw(MCF_CCM_MISCCR) & ~MCF_CCM_MISCCR_LIMP, MCF_CCM_MISCCR);
 
         /* Wait for PLL to lock */
-        while (!(MCF_CCM_MISCCR & MCF_CCM_MISCCR_PLL_LOCK))
+        while (!(readw(MCF_CCM_MISCCR) & MCF_CCM_MISCCR_PLL_LOCK))
                 ;
         
         fout = get_sys_clock();
@@ -579,10 +584,10 @@ int get_sys_clock(void)
         int divider;
         
         /* Test to see if device is in LIMP mode */
-        if (MCF_CCM_MISCCR & MCF_CCM_MISCCR_LIMP) {
-                divider = MCF_CCM_CDR & MCF_CCM_CDR_LPDIV(0xF);
+        if (readw(MCF_CCM_MISCCR) & MCF_CCM_MISCCR_LIMP) {
+                divider = readw(MCF_CCM_CDR) & MCF_CCM_CDR_LPDIV(0xF);
                 return (FREF/(2 << divider));
         }
         else
-                return ((FREF * MCF_PLL_PFDR) / (BUSDIV * 4));
+                return (FREF * readb(MCF_PLL_PFDR)) / (BUSDIV * 4);
 }
diff --git a/arch/m68k/platform/coldfire/m54xx.c b/arch/m68k/platform/coldfire/m54xx.c
index 2081c6cbb3de..b587bf35175b 100644
--- a/arch/m68k/platform/coldfire/m54xx.c
+++ b/arch/m68k/platform/coldfire/m54xx.c
@@ -30,14 +30,12 @@
 static void __init m54xx_uarts_init(void)
 {
         /* enable io pins */
-        __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD,
-                MCF_MBAR + MCF_PAR_PSC(0));
+        __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD, MCFGPIO_PAR_PSC0);
         __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD | MCF_PAR_PSC_RTS_RTS,
-                MCF_MBAR + MCF_PAR_PSC(1));
+                MCFGPIO_PAR_PSC1);
         __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD | MCF_PAR_PSC_RTS_RTS |
-                MCF_PAR_PSC_CTS_CTS, MCF_MBAR + MCF_PAR_PSC(2));
-        __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD,
-                MCF_MBAR + MCF_PAR_PSC(3));
+                MCF_PAR_PSC_CTS_CTS, MCFGPIO_PAR_PSC2);
+        __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD, MCFGPIO_PAR_PSC3);
 }
 
 /***************************************************************************/
@@ -46,10 +44,10 @@ static void mcf54xx_reset(void)
 {
         /* disable interrupts and enable the watchdog */
         asm("movew #0x2700, %sr\n");
-        __raw_writel(0, MCF_MBAR + MCF_GPT_GMS0);
-        __raw_writel(MCF_GPT_GCIR_CNT(1), MCF_MBAR + MCF_GPT_GCIR0);
+        __raw_writel(0, MCF_GPT_GMS0);
+        __raw_writel(MCF_GPT_GCIR_CNT(1), MCF_GPT_GCIR0);
         __raw_writel(MCF_GPT_GMS_WDEN | MCF_GPT_GMS_CE | MCF_GPT_GMS_TMS(4),
-                                                MCF_MBAR + MCF_GPT_GMS0);
+                MCF_GPT_GMS0);
 }
 
 /***************************************************************************/
diff --git a/arch/m68k/platform/coldfire/nettel.c b/arch/m68k/platform/coldfire/nettel.c
index e925ea4602f8..ddc48ec1b800 100644
--- a/arch/m68k/platform/coldfire/nettel.c
+++ b/arch/m68k/platform/coldfire/nettel.c
@@ -121,14 +121,14 @@ static void __init nettel_smc91x_setmac(unsigned int ioaddr, unsigned int flasha
 
 static void __init nettel_smc91x_init(void)
 {
-        writew(0x00ec, MCF_MBAR + MCFSIM_PADDR);
+        writew(0x00ec, MCFSIM_PADDR);
         mcf_setppdata(0, 0x0080);
         writew(1, NETTEL_SMC0_ADDR + SMC91xx_BANKSELECT);
         writew(0x0067, NETTEL_SMC0_ADDR + SMC91xx_BASEADDR);
         mcf_setppdata(0x0080, 0);
 
         /* Set correct chip select timing for SMC9196 accesses */
-        writew(0x1180, MCF_MBAR + MCFSIM_CSCR3);
+        writew(0x1180, MCFSIM_CSCR3);
 
         /* Set the SMC interrupts to be auto-vectored */
         mcf_autovector(NETTEL_SMC0_IRQ);
diff --git a/arch/m68k/platform/coldfire/pci.c b/arch/m68k/platform/coldfire/pci.c
index 553210d3d4c1..8572246db84d 100644
--- a/arch/m68k/platform/coldfire/pci.c
+++ b/arch/m68k/platform/coldfire/pci.c
@@ -272,8 +272,8 @@ static int __init mcf_pci_init(void)
                 PACR_EXTMINTE(0x1f), PACR);
 
         /* Set required multi-function pins for PCI bus use */
-        __raw_writew(0x3ff, MCF_PAR_PCIBG);
-        __raw_writew(0x3ff, MCF_PAR_PCIBR);
+        __raw_writew(0x3ff, MCFGPIO_PAR_PCIBG);
+        __raw_writew(0x3ff, MCFGPIO_PAR_PCIBR);
 
         /* Set up config space for local host bus controller */
         __raw_writel(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
diff --git a/arch/m68k/platform/coldfire/reset.c b/arch/m68k/platform/coldfire/reset.c
index 933e54eacc69..f30952f0cbe6 100644
--- a/arch/m68k/platform/coldfire/reset.c
+++ b/arch/m68k/platform/coldfire/reset.c
@@ -27,7 +27,7 @@ static void mcf_cpu_reset(void)
 {
         local_irq_disable();
         /* Set watchdog to soft reset, and enabled */
-        __raw_writeb(0xc0, MCF_MBAR + MCFSIM_SYPCR);
+        __raw_writeb(0xc0, MCFSIM_SYPCR);
         for (;;)
                 /* wait for watchdog to timeout */;
 }
diff --git a/arch/m68k/platform/coldfire/sltimers.c b/arch/m68k/platform/coldfire/sltimers.c
index 2027fc20b876..bb5a25ada848 100644
--- a/arch/m68k/platform/coldfire/sltimers.c
+++ b/arch/m68k/platform/coldfire/sltimers.c
@@ -32,7 +32,7 @@
 /*
  *      By default use Slice Timer 1 as the profiler clock timer.
  */
-#define PA(a)   (MCF_MBAR + MCFSLT_TIMER1 + (a))
+#define PA(a)   (MCFSLT_TIMER1 + (a))
 
 /*
  *      Choose a reasonably fast profile timer. Make it an odd value to
@@ -76,7 +76,7 @@ void mcfslt_profile_init(void)
 /*
  *      By default use Slice Timer 0 as the system clock timer.
  */
-#define TA(a)   (MCF_MBAR + MCFSLT_TIMER0 + (a))
+#define TA(a)   (MCFSLT_TIMER0 + (a))
 
 static u32 mcfslt_cycles_per_jiffy;
 static u32 mcfslt_cnt;
diff --git a/arch/m68k/platform/coldfire/timers.c b/arch/m68k/platform/coldfire/timers.c
index 0a273e75408c..51f6d2af807f 100644
--- a/arch/m68k/platform/coldfire/timers.c
+++ b/arch/m68k/platform/coldfire/timers.c
@@ -56,13 +56,13 @@ static void init_timer_irq(void)
 #ifdef MCFSIM_ICR_AUTOVEC
         /* Timer1 is always used as system timer */
         writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3,
-                MCF_MBAR + MCFSIM_TIMER1ICR);
+                MCFSIM_TIMER1ICR);
         mcf_mapirq2imr(MCF_IRQ_TIMER, MCFINTC_TIMER1);
 
 #ifdef CONFIG_HIGHPROFILE
         /* Timer2 is to be used as a high speed profile timer  */
         writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3,
-                MCF_MBAR + MCFSIM_TIMER2ICR);
+                MCFSIM_TIMER2ICR);
         mcf_mapirq2imr(MCF_IRQ_PROFILER, MCFINTC_TIMER2);
 #endif
 #endif /* MCFSIM_ICR_AUTOVEC */