diff options
Diffstat (limited to 'arch/m68k/platform/coldfire/intc-simr.c')
-rw-r--r-- | arch/m68k/platform/coldfire/intc-simr.c | 26 |
1 files changed, 18 insertions, 8 deletions
diff --git a/arch/m68k/platform/coldfire/intc-simr.c b/arch/m68k/platform/coldfire/intc-simr.c index 650d52e2927e..7cf2c156f72d 100644 --- a/arch/m68k/platform/coldfire/intc-simr.c +++ b/arch/m68k/platform/coldfire/intc-simr.c | |||
@@ -59,16 +59,18 @@ static unsigned int inline irq2ebit(unsigned int irq) | |||
59 | #endif | 59 | #endif |
60 | 60 | ||
61 | /* | 61 | /* |
62 | * There maybe one or two interrupt control units, each has 64 | 62 | * There maybe one, two or three interrupt control units, each has 64 |
63 | * interrupts. If there is no second unit then MCFINTC1_* defines | 63 | * interrupts. If there is no second or third unit then MCFINTC1_* or |
64 | * will be 0 (and code for them optimized away). | 64 | * MCFINTC2_* defines will be 0 (and code for them optimized away). |
65 | */ | 65 | */ |
66 | 66 | ||
67 | static void intc_irq_mask(struct irq_data *d) | 67 | static void intc_irq_mask(struct irq_data *d) |
68 | { | 68 | { |
69 | unsigned int irq = d->irq - MCFINT_VECBASE; | 69 | unsigned int irq = d->irq - MCFINT_VECBASE; |
70 | 70 | ||
71 | if (MCFINTC1_SIMR && (irq > 64)) | 71 | if (MCFINTC2_SIMR && (irq > 128)) |
72 | __raw_writeb(irq - 128, MCFINTC2_SIMR); | ||
73 | else if (MCFINTC1_SIMR && (irq > 64)) | ||
72 | __raw_writeb(irq - 64, MCFINTC1_SIMR); | 74 | __raw_writeb(irq - 64, MCFINTC1_SIMR); |
73 | else | 75 | else |
74 | __raw_writeb(irq, MCFINTC0_SIMR); | 76 | __raw_writeb(irq, MCFINTC0_SIMR); |
@@ -78,7 +80,9 @@ static void intc_irq_unmask(struct irq_data *d) | |||
78 | { | 80 | { |
79 | unsigned int irq = d->irq - MCFINT_VECBASE; | 81 | unsigned int irq = d->irq - MCFINT_VECBASE; |
80 | 82 | ||
81 | if (MCFINTC1_CIMR && (irq > 64)) | 83 | if (MCFINTC2_CIMR && (irq > 128)) |
84 | __raw_writeb(irq - 128, MCFINTC2_CIMR); | ||
85 | else if (MCFINTC1_CIMR && (irq > 64)) | ||
82 | __raw_writeb(irq - 64, MCFINTC1_CIMR); | 86 | __raw_writeb(irq - 64, MCFINTC1_CIMR); |
83 | else | 87 | else |
84 | __raw_writeb(irq, MCFINTC0_CIMR); | 88 | __raw_writeb(irq, MCFINTC0_CIMR); |
@@ -99,9 +103,11 @@ static unsigned int intc_irq_startup(struct irq_data *d) | |||
99 | unsigned int ebit = irq2ebit(irq); | 103 | unsigned int ebit = irq2ebit(irq); |
100 | u8 v; | 104 | u8 v; |
101 | 105 | ||
106 | #if defined(MCFEPORT_EPDDR) | ||
102 | /* Set EPORT line as input */ | 107 | /* Set EPORT line as input */ |
103 | v = __raw_readb(MCFEPORT_EPDDR); | 108 | v = __raw_readb(MCFEPORT_EPDDR); |
104 | __raw_writeb(v & ~(0x1 << ebit), MCFEPORT_EPDDR); | 109 | __raw_writeb(v & ~(0x1 << ebit), MCFEPORT_EPDDR); |
110 | #endif | ||
105 | 111 | ||
106 | /* Set EPORT line as interrupt source */ | 112 | /* Set EPORT line as interrupt source */ |
107 | v = __raw_readb(MCFEPORT_EPIER); | 113 | v = __raw_readb(MCFEPORT_EPIER); |
@@ -109,12 +115,13 @@ static unsigned int intc_irq_startup(struct irq_data *d) | |||
109 | } | 115 | } |
110 | 116 | ||
111 | irq -= MCFINT_VECBASE; | 117 | irq -= MCFINT_VECBASE; |
112 | if (MCFINTC1_ICR0 && (irq > 64)) | 118 | if (MCFINTC2_ICR0 && (irq > 128)) |
119 | __raw_writeb(5, MCFINTC2_ICR0 + irq - 128); | ||
120 | else if (MCFINTC1_ICR0 && (irq > 64)) | ||
113 | __raw_writeb(5, MCFINTC1_ICR0 + irq - 64); | 121 | __raw_writeb(5, MCFINTC1_ICR0 + irq - 64); |
114 | else | 122 | else |
115 | __raw_writeb(5, MCFINTC0_ICR0 + irq); | 123 | __raw_writeb(5, MCFINTC0_ICR0 + irq); |
116 | 124 | ||
117 | |||
118 | intc_irq_unmask(d); | 125 | intc_irq_unmask(d); |
119 | return 0; | 126 | return 0; |
120 | } | 127 | } |
@@ -175,8 +182,11 @@ void __init init_IRQ(void) | |||
175 | __raw_writeb(0xff, MCFINTC0_SIMR); | 182 | __raw_writeb(0xff, MCFINTC0_SIMR); |
176 | if (MCFINTC1_SIMR) | 183 | if (MCFINTC1_SIMR) |
177 | __raw_writeb(0xff, MCFINTC1_SIMR); | 184 | __raw_writeb(0xff, MCFINTC1_SIMR); |
185 | if (MCFINTC2_SIMR) | ||
186 | __raw_writeb(0xff, MCFINTC2_SIMR); | ||
178 | 187 | ||
179 | eirq = MCFINT_VECBASE + 64 + (MCFINTC1_ICR0 ? 64 : 0); | 188 | eirq = MCFINT_VECBASE + 64 + (MCFINTC1_ICR0 ? 64 : 0) + |
189 | (MCFINTC2_ICR0 ? 64 : 0); | ||
180 | for (irq = MCFINT_VECBASE; (irq < eirq); irq++) { | 190 | for (irq = MCFINT_VECBASE; (irq < eirq); irq++) { |
181 | if ((irq >= EINT1) && (irq <= EINT7)) | 191 | if ((irq >= EINT1) && (irq <= EINT7)) |
182 | irq_set_chip(irq, &intc_irq_chip_edge_port); | 192 | irq_set_chip(irq, &intc_irq_chip_edge_port); |