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-rw-r--r--arch/m68k/include/asm/m520xsim.h9
-rw-r--r--arch/m68k/include/asm/m523xsim.h9
-rw-r--r--arch/m68k/include/asm/m527xsim.h9
-rw-r--r--arch/m68k/include/asm/m528xsim.h8
-rw-r--r--arch/m68k/include/asm/m532xsim.h12
-rw-r--r--arch/m68k/include/asm/processor_no.h8
-rw-r--r--arch/m68k/include/asm/swab.h2
-rw-r--r--arch/m68k/include/asm/system_no.h107
8 files changed, 52 insertions, 112 deletions
diff --git a/arch/m68k/include/asm/m520xsim.h b/arch/m68k/include/asm/m520xsim.h
index 49d016e6391a..83bbcfd6e8f2 100644
--- a/arch/m68k/include/asm/m520xsim.h
+++ b/arch/m68k/include/asm/m520xsim.h
@@ -59,5 +59,14 @@
59#define MCFPIT_IMR MCFINTC_IMRL 59#define MCFPIT_IMR MCFINTC_IMRL
60#define MCFPIT_IMR_IBIT (1 << MCFINT_PIT1) 60#define MCFPIT_IMR_IBIT (1 << MCFINT_PIT1)
61 61
62/*
63 * Reset Controll Unit.
64 */
65#define MCF_RCR 0xFC0A0000
66#define MCF_RSR 0xFC0A0001
67
68#define MCF_RCR_SWRESET 0x80 /* Software reset bit */
69#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */
70
62/****************************************************************************/ 71/****************************************************************************/
63#endif /* m520xsim_h */ 72#endif /* m520xsim_h */
diff --git a/arch/m68k/include/asm/m523xsim.h b/arch/m68k/include/asm/m523xsim.h
index bf397313e93f..55183b5df1b8 100644
--- a/arch/m68k/include/asm/m523xsim.h
+++ b/arch/m68k/include/asm/m523xsim.h
@@ -41,5 +41,14 @@
41#define MCFSIM_DACR1 0x50 /* SDRAM base address 1 */ 41#define MCFSIM_DACR1 0x50 /* SDRAM base address 1 */
42#define MCFSIM_DMR1 0x54 /* SDRAM address mask 1 */ 42#define MCFSIM_DMR1 0x54 /* SDRAM address mask 1 */
43 43
44/*
45 * Reset Controll Unit (relative to IPSBAR).
46 */
47#define MCF_RCR 0x110000
48#define MCF_RSR 0x110001
49
50#define MCF_RCR_SWRESET 0x80 /* Software reset bit */
51#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */
52
44/****************************************************************************/ 53/****************************************************************************/
45#endif /* m523xsim_h */ 54#endif /* m523xsim_h */
diff --git a/arch/m68k/include/asm/m527xsim.h b/arch/m68k/include/asm/m527xsim.h
index 1f63ab3fb3e6..95f4f8ee8f7c 100644
--- a/arch/m68k/include/asm/m527xsim.h
+++ b/arch/m68k/include/asm/m527xsim.h
@@ -70,5 +70,14 @@
70#define UART2_ENABLE_MASK 0x3f00 70#define UART2_ENABLE_MASK 0x3f00
71#endif 71#endif
72 72
73/*
74 * Reset Controll Unit (relative to IPSBAR).
75 */
76#define MCF_RCR 0x110000
77#define MCF_RSR 0x110001
78
79#define MCF_RCR_SWRESET 0x80 /* Software reset bit */
80#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */
81
73/****************************************************************************/ 82/****************************************************************************/
74#endif /* m527xsim_h */ 83#endif /* m527xsim_h */
diff --git a/arch/m68k/include/asm/m528xsim.h b/arch/m68k/include/asm/m528xsim.h
index 28bf783a5d6d..d79c49f8134a 100644
--- a/arch/m68k/include/asm/m528xsim.h
+++ b/arch/m68k/include/asm/m528xsim.h
@@ -56,6 +56,14 @@
56#define MCF5282_INTC0_ICR17 (volatile u8 *) (MCF_IPSBAR + 0x0C51) 56#define MCF5282_INTC0_ICR17 (volatile u8 *) (MCF_IPSBAR + 0x0C51)
57 57
58 58
59/*
60 * Reset Control Unit (relative to IPSBAR).
61 */
62#define MCF_RCR 0x110000
63#define MCF_RSR 0x110001
64
65#define MCF_RCR_SWRESET 0x80 /* Software reset bit */
66#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */
59 67
60/********************************************************************* 68/*********************************************************************
61* 69*
diff --git a/arch/m68k/include/asm/m532xsim.h b/arch/m68k/include/asm/m532xsim.h
index ce603451b55e..eb7fd4448947 100644
--- a/arch/m68k/include/asm/m532xsim.h
+++ b/arch/m68k/include/asm/m532xsim.h
@@ -127,6 +127,18 @@
127 127
128/********************************************************************* 128/*********************************************************************
129 * 129 *
130 * Reset Controller Module
131 *
132 *********************************************************************/
133
134#define MCF_RCR 0xFC0A0000
135#define MCF_RSR 0xFC0A0001
136
137#define MCF_RCR_SWRESET 0x80 /* Software reset bit */
138#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */
139
140/*********************************************************************
141 *
130 * Inter-IC (I2C) Module 142 * Inter-IC (I2C) Module
131 * 143 *
132 *********************************************************************/ 144 *********************************************************************/
diff --git a/arch/m68k/include/asm/processor_no.h b/arch/m68k/include/asm/processor_no.h
index 91cba18acdd3..7a1e0ba35f5a 100644
--- a/arch/m68k/include/asm/processor_no.h
+++ b/arch/m68k/include/asm/processor_no.h
@@ -72,10 +72,10 @@ struct thread_struct {
72 unsigned char fpstate[FPSTATESIZE]; /* floating point state */ 72 unsigned char fpstate[FPSTATESIZE]; /* floating point state */
73}; 73};
74 74
75#define INIT_THREAD { \ 75#define INIT_THREAD { \
76 sizeof(init_stack) + (unsigned long) init_stack, 0, \ 76 .ksp = sizeof(init_stack) + (unsigned long) init_stack, \
77 PS_S, __KERNEL_DS, \ 77 .sr = PS_S, \
78 {0, 0}, 0, {0,}, {0, 0, 0}, {0,}, \ 78 .fs = __KERNEL_DS, \
79} 79}
80 80
81/* 81/*
diff --git a/arch/m68k/include/asm/swab.h b/arch/m68k/include/asm/swab.h
index 9e3054ea59e9..5b754aace744 100644
--- a/arch/m68k/include/asm/swab.h
+++ b/arch/m68k/include/asm/swab.h
@@ -1,7 +1,7 @@
1#ifndef _M68K_SWAB_H 1#ifndef _M68K_SWAB_H
2#define _M68K_SWAB_H 2#define _M68K_SWAB_H
3 3
4#include <asm/types.h> 4#include <linux/types.h>
5#include <linux/compiler.h> 5#include <linux/compiler.h>
6 6
7#define __SWAB_64_THRU_32__ 7#define __SWAB_64_THRU_32__
diff --git a/arch/m68k/include/asm/system_no.h b/arch/m68k/include/asm/system_no.h
index 4496c0aa8379..3c0718d74398 100644
--- a/arch/m68k/include/asm/system_no.h
+++ b/arch/m68k/include/asm/system_no.h
@@ -203,113 +203,6 @@ static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int siz
203#include <asm-generic/cmpxchg.h> 203#include <asm-generic/cmpxchg.h>
204#endif 204#endif
205 205
206#if defined( CONFIG_M68328 ) || defined( CONFIG_M68EZ328 ) || \
207 defined (CONFIG_M68360) || defined( CONFIG_M68VZ328 )
208#define HARD_RESET_NOW() ({ \
209 local_irq_disable(); \
210 asm(" \
211 moveal #0x10c00000, %a0; \
212 moveb #0, 0xFFFFF300; \
213 moveal 0(%a0), %sp; \
214 moveal 4(%a0), %a0; \
215 jmp (%a0); \
216 "); \
217})
218#endif
219
220#ifdef CONFIG_COLDFIRE
221#if defined(CONFIG_M5272) && defined(CONFIG_NETtel)
222/*
223 * Need to account for broken early mask of 5272 silicon. So don't
224 * jump through the original start address. Jump strait into the
225 * known start of the FLASH code.
226 */
227#define HARD_RESET_NOW() ({ \
228 asm(" \
229 movew #0x2700, %sr; \
230 jmp 0xf0000400; \
231 "); \
232})
233#elif defined(CONFIG_NETtel) || \
234 defined(CONFIG_SECUREEDGEMP3) || defined(CONFIG_CLEOPATRA)
235#define HARD_RESET_NOW() ({ \
236 asm(" \
237 movew #0x2700, %sr; \
238 moveal #0x10000044, %a0; \
239 movel #0xffffffff, (%a0); \
240 moveal #0x10000001, %a0; \
241 moveb #0x00, (%a0); \
242 moveal #0xf0000004, %a0; \
243 moveal (%a0), %a0; \
244 jmp (%a0); \
245 "); \
246})
247#elif defined(CONFIG_M5272)
248/*
249 * Retrieve the boot address in flash using CSBR0 and CSOR0
250 * find the reset vector at flash_address + 4 (e.g. 0x400)
251 * remap it in the flash's current location (e.g. 0xf0000400)
252 * and jump there.
253 */
254#define HARD_RESET_NOW() ({ \
255 asm(" \
256 movew #0x2700, %%sr; \
257 move.l %0+0x40,%%d0; \
258 and.l %0+0x44,%%d0; \
259 andi.l #0xfffff000,%%d0; \
260 mov.l %%d0,%%a0; \
261 or.l 4(%%a0),%%d0; \
262 mov.l %%d0,%%a0; \
263 jmp (%%a0);" \
264 : /* No output */ \
265 : "o" (*(char *)MCF_MBAR) ); \
266})
267#elif defined(CONFIG_M528x)
268/*
269 * The MCF528x has a bit (SOFTRST) in memory (Reset Control Register RCR),
270 * that when set, resets the MCF528x.
271 */
272#define HARD_RESET_NOW() \
273({ \
274 unsigned char volatile *reset; \
275 asm("move.w #0x2700, %sr"); \
276 reset = ((volatile unsigned char *)(MCF_IPSBAR + 0x110000)); \
277 while(1) \
278 *reset |= (0x01 << 7);\
279})
280#elif defined(CONFIG_M523x)
281#define HARD_RESET_NOW() ({ \
282 asm(" \
283 movew #0x2700, %sr; \
284 movel #0x01000000, %sp; \
285 moveal #0x40110000, %a0; \
286 moveb #0x80, (%a0); \
287 "); \
288})
289#elif defined(CONFIG_M520x)
290 /*
291 * The MCF5208 has a bit (SOFTRST) in memory (Reset Control Register
292 * RCR), that when set, resets the MCF5208.
293 */
294#define HARD_RESET_NOW() \
295({ \
296 unsigned char volatile *reset; \
297 asm("move.w #0x2700, %sr"); \
298 reset = ((volatile unsigned char *)(MCF_IPSBAR + 0xA0000)); \
299 while(1) \
300 *reset |= 0x80; \
301})
302#else
303#define HARD_RESET_NOW() ({ \
304 asm(" \
305 movew #0x2700, %sr; \
306 moveal #0x4, %a0; \
307 moveal (%a0), %a0; \
308 jmp (%a0); \
309 "); \
310})
311#endif
312#endif
313#define arch_align_stack(x) (x) 206#define arch_align_stack(x) (x)
314 207
315 208
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-20 20:45:31 -0500