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-rw-r--r--arch/m68k/include/asm/m520xsim.h1
-rw-r--r--arch/m68k/include/asm/m523xsim.h5
-rw-r--r--arch/m68k/include/asm/m5249sim.h2
-rw-r--r--arch/m68k/include/asm/m527xsim.h7
-rw-r--r--arch/m68k/include/asm/m528xsim.h67
-rw-r--r--arch/m68k/include/asm/m532xsim.h1
-rw-r--r--arch/m68k/include/asm/mcfqspi.h64
-rw-r--r--arch/m68k/include/asm/mcfsmc.h187
-rw-r--r--arch/m68k/include/asm/processor.h4
9 files changed, 85 insertions, 253 deletions
diff --git a/arch/m68k/include/asm/m520xsim.h b/arch/m68k/include/asm/m520xsim.h
index ed2b69b96805..db824a4b136e 100644
--- a/arch/m68k/include/asm/m520xsim.h
+++ b/arch/m68k/include/asm/m520xsim.h
@@ -113,6 +113,7 @@
113 113
114#define MCF_GPIO_PAR_UART (0xA4036) 114#define MCF_GPIO_PAR_UART (0xA4036)
115#define MCF_GPIO_PAR_FECI2C (0xA4033) 115#define MCF_GPIO_PAR_FECI2C (0xA4033)
116#define MCF_GPIO_PAR_QSPI (0xA4034)
116#define MCF_GPIO_PAR_FEC (0xA4038) 117#define MCF_GPIO_PAR_FEC (0xA4038)
117 118
118#define MCF_GPIO_PAR_UART_PAR_URXD0 (0x0001) 119#define MCF_GPIO_PAR_UART_PAR_URXD0 (0x0001)
diff --git a/arch/m68k/include/asm/m523xsim.h b/arch/m68k/include/asm/m523xsim.h
index a34894cf8e6f..e8d06b24a48e 100644
--- a/arch/m68k/include/asm/m523xsim.h
+++ b/arch/m68k/include/asm/m523xsim.h
@@ -127,5 +127,10 @@
127#define MCFGPIO_IRQ_MAX 8 127#define MCFGPIO_IRQ_MAX 8
128#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE 128#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
129 129
130/*
131 * Pin Assignment
132*/
133#define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10004A)
134#define MCFGPIO_PAR_TIMER (MCF_IPSBAR + 0x10004C)
130/****************************************************************************/ 135/****************************************************************************/
131#endif /* m523xsim_h */ 136#endif /* m523xsim_h */
diff --git a/arch/m68k/include/asm/m5249sim.h b/arch/m68k/include/asm/m5249sim.h
index 14bce877ed88..79b7b402f3c9 100644
--- a/arch/m68k/include/asm/m5249sim.h
+++ b/arch/m68k/include/asm/m5249sim.h
@@ -69,10 +69,12 @@
69#define MCFSIM_DMA1ICR MCFSIM_ICR7 /* DMA 1 ICR */ 69#define MCFSIM_DMA1ICR MCFSIM_ICR7 /* DMA 1 ICR */
70#define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */ 70#define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */
71#define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */ 71#define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */
72#define MCFSIM_QSPIICR MCFSIM_ICR10 /* QSPI ICR */
72 73
73/* 74/*
74 * Define system peripheral IRQ usage. 75 * Define system peripheral IRQ usage.
75 */ 76 */
77#define MCF_IRQ_QSPI 28 /* QSPI, Level 4 */
76#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */ 78#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */
77#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */ 79#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */
78 80
diff --git a/arch/m68k/include/asm/m527xsim.h b/arch/m68k/include/asm/m527xsim.h
index 453356d72d80..1feb46f108ce 100644
--- a/arch/m68k/include/asm/m527xsim.h
+++ b/arch/m68k/include/asm/m527xsim.h
@@ -31,6 +31,7 @@
31#define MCFINT_UART0 13 /* Interrupt number for UART0 */ 31#define MCFINT_UART0 13 /* Interrupt number for UART0 */
32#define MCFINT_UART1 14 /* Interrupt number for UART1 */ 32#define MCFINT_UART1 14 /* Interrupt number for UART1 */
33#define MCFINT_UART2 15 /* Interrupt number for UART2 */ 33#define MCFINT_UART2 15 /* Interrupt number for UART2 */
34#define MCFINT_QSPI 18 /* Interrupt number for QSPI */
34#define MCFINT_PIT1 36 /* Interrupt number for PIT1 */ 35#define MCFINT_PIT1 36 /* Interrupt number for PIT1 */
35 36
36/* 37/*
@@ -120,6 +121,9 @@
120#define MCFGPIO_PIN_MAX 100 121#define MCFGPIO_PIN_MAX 100
121#define MCFGPIO_IRQ_MAX 8 122#define MCFGPIO_IRQ_MAX 8
122#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE 123#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
124
125#define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10004A)
126#define MCFGPIO_PAR_TIMER (MCF_IPSBAR + 0x10004C)
123#endif 127#endif
124 128
125#ifdef CONFIG_M5275 129#ifdef CONFIG_M5275
@@ -212,6 +216,8 @@
212#define MCFGPIO_PIN_MAX 148 216#define MCFGPIO_PIN_MAX 148
213#define MCFGPIO_IRQ_MAX 8 217#define MCFGPIO_IRQ_MAX 8
214#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE 218#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
219
220#define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10007E)
215#endif 221#endif
216 222
217/* 223/*
@@ -223,6 +229,7 @@
223#define MCFEPORT_EPPDR (MCF_IPSBAR + 0x130005) 229#define MCFEPORT_EPPDR (MCF_IPSBAR + 0x130005)
224 230
225 231
232
226/* 233/*
227 * GPIO pins setups to enable the UARTs. 234 * GPIO pins setups to enable the UARTs.
228 */ 235 */
diff --git a/arch/m68k/include/asm/m528xsim.h b/arch/m68k/include/asm/m528xsim.h
index e2ad1f42b657..891cbedad972 100644
--- a/arch/m68k/include/asm/m528xsim.h
+++ b/arch/m68k/include/asm/m528xsim.h
@@ -29,6 +29,7 @@
29 29
30#define MCFINT_VECBASE 64 /* Vector base number */ 30#define MCFINT_VECBASE 64 /* Vector base number */
31#define MCFINT_UART0 13 /* Interrupt number for UART0 */ 31#define MCFINT_UART0 13 /* Interrupt number for UART0 */
32#define MCFINT_QSPI 18 /* Interrupt number for QSPI */
32#define MCFINT_PIT1 55 /* Interrupt number for PIT1 */ 33#define MCFINT_PIT1 55 /* Interrupt number for PIT1 */
33 34
34/* 35/*
@@ -249,70 +250,4 @@
249#define MCF5282_I2C_I2SR_RXAK (0x01) // received acknowledge 250#define MCF5282_I2C_I2SR_RXAK (0x01) // received acknowledge
250 251
251 252
252
253/*********************************************************************
254*
255* Queued Serial Peripheral Interface (QSPI) Module
256*
257*********************************************************************/
258/* Derek - 21 Feb 2005 */
259/* change to the format used in I2C */
260/* Read/Write access macros for general use */
261#define MCF5282_QSPI_QMR MCF_IPSBAR + 0x0340
262#define MCF5282_QSPI_QDLYR MCF_IPSBAR + 0x0344
263#define MCF5282_QSPI_QWR MCF_IPSBAR + 0x0348
264#define MCF5282_QSPI_QIR MCF_IPSBAR + 0x034C
265#define MCF5282_QSPI_QAR MCF_IPSBAR + 0x0350
266#define MCF5282_QSPI_QDR MCF_IPSBAR + 0x0354
267#define MCF5282_QSPI_QCR MCF_IPSBAR + 0x0354
268
269/* Bit level definitions and macros */
270#define MCF5282_QSPI_QMR_MSTR (0x8000)
271#define MCF5282_QSPI_QMR_DOHIE (0x4000)
272#define MCF5282_QSPI_QMR_BITS_16 (0x0000)
273#define MCF5282_QSPI_QMR_BITS_8 (0x2000)
274#define MCF5282_QSPI_QMR_BITS_9 (0x2400)
275#define MCF5282_QSPI_QMR_BITS_10 (0x2800)
276#define MCF5282_QSPI_QMR_BITS_11 (0x2C00)
277#define MCF5282_QSPI_QMR_BITS_12 (0x3000)
278#define MCF5282_QSPI_QMR_BITS_13 (0x3400)
279#define MCF5282_QSPI_QMR_BITS_14 (0x3800)
280#define MCF5282_QSPI_QMR_BITS_15 (0x3C00)
281#define MCF5282_QSPI_QMR_CPOL (0x0200)
282#define MCF5282_QSPI_QMR_CPHA (0x0100)
283#define MCF5282_QSPI_QMR_BAUD(x) (((x)&0x00FF))
284
285#define MCF5282_QSPI_QDLYR_SPE (0x80)
286#define MCF5282_QSPI_QDLYR_QCD(x) (((x)&0x007F)<<8)
287#define MCF5282_QSPI_QDLYR_DTL(x) (((x)&0x00FF))
288
289#define MCF5282_QSPI_QWR_HALT (0x8000)
290#define MCF5282_QSPI_QWR_WREN (0x4000)
291#define MCF5282_QSPI_QWR_WRTO (0x2000)
292#define MCF5282_QSPI_QWR_CSIV (0x1000)
293#define MCF5282_QSPI_QWR_ENDQP(x) (((x)&0x000F)<<8)
294#define MCF5282_QSPI_QWR_CPTQP(x) (((x)&0x000F)<<4)
295#define MCF5282_QSPI_QWR_NEWQP(x) (((x)&0x000F))
296
297#define MCF5282_QSPI_QIR_WCEFB (0x8000)
298#define MCF5282_QSPI_QIR_ABRTB (0x4000)
299#define MCF5282_QSPI_QIR_ABRTL (0x1000)
300#define MCF5282_QSPI_QIR_WCEFE (0x0800)
301#define MCF5282_QSPI_QIR_ABRTE (0x0400)
302#define MCF5282_QSPI_QIR_SPIFE (0x0100)
303#define MCF5282_QSPI_QIR_WCEF (0x0008)
304#define MCF5282_QSPI_QIR_ABRT (0x0004)
305#define MCF5282_QSPI_QIR_SPIF (0x0001)
306
307#define MCF5282_QSPI_QAR_ADDR(x) (((x)&0x003F))
308
309#define MCF5282_QSPI_QDR_COMMAND(x) (((x)&0xFF00))
310#define MCF5282_QSPI_QCR_DATA(x) (((x)&0x00FF)<<8)
311#define MCF5282_QSPI_QCR_CONT (0x8000)
312#define MCF5282_QSPI_QCR_BITSE (0x4000)
313#define MCF5282_QSPI_QCR_DT (0x2000)
314#define MCF5282_QSPI_QCR_DSCK (0x1000)
315#define MCF5282_QSPI_QCR_CS (((x)&0x000F)<<8)
316
317/****************************************************************************/
318#endif /* m528xsim_h */ 253#endif /* m528xsim_h */
diff --git a/arch/m68k/include/asm/m532xsim.h b/arch/m68k/include/asm/m532xsim.h
index 36bf15aec9ae..c4bf1c81e3cf 100644
--- a/arch/m68k/include/asm/m532xsim.h
+++ b/arch/m68k/include/asm/m532xsim.h
@@ -17,6 +17,7 @@
17#define MCFINT_UART0 26 /* Interrupt number for UART0 */ 17#define MCFINT_UART0 26 /* Interrupt number for UART0 */
18#define MCFINT_UART1 27 /* Interrupt number for UART1 */ 18#define MCFINT_UART1 27 /* Interrupt number for UART1 */
19#define MCFINT_UART2 28 /* Interrupt number for UART2 */ 19#define MCFINT_UART2 28 /* Interrupt number for UART2 */
20#define MCFINT_QSPI 31 /* Interrupt number for QSPI */
20 21
21#define MCF_WTM_WCR MCF_REG16(0xFC098000) 22#define MCF_WTM_WCR MCF_REG16(0xFC098000)
22 23
diff --git a/arch/m68k/include/asm/mcfqspi.h b/arch/m68k/include/asm/mcfqspi.h
new file mode 100644
index 000000000000..39d90d51111d
--- /dev/null
+++ b/arch/m68k/include/asm/mcfqspi.h
@@ -0,0 +1,64 @@
1/*
2 * Definitions for Freescale Coldfire QSPI module
3 *
4 * Copyright 2010 Steven King <sfking@fdwdc.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2
8 * as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19*/
20
21#ifndef mcfqspi_h
22#define mcfqspi_h
23
24#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x)
25#define MCFQSPI_IOBASE (MCF_IPSBAR + 0x340)
26#elif defined(CONFIG_M5249)
27#define MCFQSPI_IOBASE (MCF_MBAR + 0x300)
28#elif defined(CONFIG_M520x) || defined(CONFIG_M532x)
29#define MCFQSPI_IOBASE 0xFC058000
30#endif
31#define MCFQSPI_IOSIZE 0x40
32
33/**
34 * struct mcfqspi_cs_control - chip select control for the coldfire qspi driver
35 * @setup: setup the control; allocate gpio's, etc. May be NULL.
36 * @teardown: finish with the control; free gpio's, etc. May be NULL.
37 * @select: output the signals to select the device. Can not be NULL.
38 * @deselect: output the signals to deselect the device. Can not be NULL.
39 *
40 * The QSPI module has 4 hardware chip selects. We don't use them. Instead
41 * platforms are required to supply a mcfqspi_cs_control as a part of the
42 * platform data for each QSPI master controller. Only the select and
43 * deselect functions are required.
44*/
45struct mcfqspi_cs_control {
46 int (*setup)(struct mcfqspi_cs_control *);
47 void (*teardown)(struct mcfqspi_cs_control *);
48 void (*select)(struct mcfqspi_cs_control *, u8, bool);
49 void (*deselect)(struct mcfqspi_cs_control *, u8, bool);
50};
51
52/**
53 * struct mcfqspi_platform_data - platform data for the coldfire qspi driver
54 * @bus_num: board specific identifier for this qspi driver.
55 * @num_chipselects: number of chip selects supported by this qspi driver.
56 * @cs_control: platform dependent chip select control.
57*/
58struct mcfqspi_platform_data {
59 s16 bus_num;
60 u16 num_chipselect;
61 struct mcfqspi_cs_control *cs_control;
62};
63
64#endif /* mcfqspi_h */
diff --git a/arch/m68k/include/asm/mcfsmc.h b/arch/m68k/include/asm/mcfsmc.h
deleted file mode 100644
index 527bea5d6788..000000000000
--- a/arch/m68k/include/asm/mcfsmc.h
+++ /dev/null
@@ -1,187 +0,0 @@
1/****************************************************************************/
2
3/*
4 * mcfsmc.h -- SMC ethernet support for ColdFire environments.
5 *
6 * (C) Copyright 1999-2002, Greg Ungerer (gerg@snapgear.com)
7 * (C) Copyright 2000, Lineo Inc. (www.lineo.com)
8 */
9
10/****************************************************************************/
11#ifndef mcfsmc_h
12#define mcfsmc_h
13/****************************************************************************/
14
15/*
16 * None of the current ColdFire targets that use the SMC91x111
17 * allow 8 bit accesses. So this code is 16bit access only.
18 */
19
20
21#undef outb
22#undef inb
23#undef outw
24#undef outwd
25#undef inw
26#undef outl
27#undef inl
28
29#undef outsb
30#undef outsw
31#undef outsl
32#undef insb
33#undef insw
34#undef insl
35
36/*
37 * Re-defines for ColdFire environment... The SMC part is
38 * mapped into memory space, so remap the PC-style in/out
39 * routines to handle that.
40 */
41#define outb smc_outb
42#define inb smc_inb
43#define outw smc_outw
44#define outwd smc_outwd
45#define inw smc_inw
46#define outl smc_outl
47#define inl smc_inl
48
49#define outsb smc_outsb
50#define outsw smc_outsw
51#define outsl smc_outsl
52#define insb smc_insb
53#define insw smc_insw
54#define insl smc_insl
55
56
57static inline int smc_inb(unsigned int addr)
58{
59 register unsigned short w;
60 w = *((volatile unsigned short *) (addr & ~0x1));
61 return(((addr & 0x1) ? w : (w >> 8)) & 0xff);
62}
63
64static inline void smc_outw(unsigned int val, unsigned int addr)
65{
66 *((volatile unsigned short *) addr) = (val << 8) | (val >> 8);
67}
68
69static inline int smc_inw(unsigned int addr)
70{
71 register unsigned short w;
72 w = *((volatile unsigned short *) addr);
73 return(((w << 8) | (w >> 8)) & 0xffff);
74}
75
76static inline void smc_outl(unsigned long val, unsigned int addr)
77{
78 *((volatile unsigned long *) addr) =
79 ((val << 8) & 0xff000000) | ((val >> 8) & 0x00ff0000) |
80 ((val << 8) & 0x0000ff00) | ((val >> 8) & 0x000000ff);
81}
82
83static inline void smc_outwd(unsigned int val, unsigned int addr)
84{
85 *((volatile unsigned short *) addr) = val;
86}
87
88
89/*
90 * The rep* functions are used to feed the data port with
91 * raw data. So we do not byte swap them when copying.
92 */
93
94static inline void smc_insb(unsigned int addr, void *vbuf, int unsigned long len)
95{
96 volatile unsigned short *rp;
97 unsigned short *buf, *ebuf;
98
99 buf = (unsigned short *) vbuf;
100 rp = (volatile unsigned short *) addr;
101
102 /* Copy as words for as long as possible */
103 for (ebuf = buf + (len >> 1); (buf < ebuf); )
104 *buf++ = *rp;
105
106 /* Lastly, handle left over byte */
107 if (len & 0x1)
108 *((unsigned char *) buf) = (*rp >> 8) & 0xff;
109}
110
111static inline void smc_insw(unsigned int addr, void *vbuf, unsigned long len)
112{
113 volatile unsigned short *rp;
114 unsigned short *buf, *ebuf;
115
116 buf = (unsigned short *) vbuf;
117 rp = (volatile unsigned short *) addr;
118 for (ebuf = buf + len; (buf < ebuf); )
119 *buf++ = *rp;
120}
121
122static inline void smc_insl(unsigned int addr, void *vbuf, unsigned long len)
123{
124 volatile unsigned long *rp;
125 unsigned long *buf, *ebuf;
126
127 buf = (unsigned long *) vbuf;
128 rp = (volatile unsigned long *) addr;
129 for (ebuf = buf + len; (buf < ebuf); )
130 *buf++ = *rp;
131}
132
133static inline void smc_outsw(unsigned int addr, const void *vbuf, unsigned long len)
134{
135 volatile unsigned short *rp;
136 unsigned short *buf, *ebuf;
137
138 buf = (unsigned short *) vbuf;
139 rp = (volatile unsigned short *) addr;
140 for (ebuf = buf + len; (buf < ebuf); )
141 *rp = *buf++;
142}
143
144static inline void smc_outsl(unsigned int addr, void *vbuf, unsigned long len)
145{
146 volatile unsigned long *rp;
147 unsigned long *buf, *ebuf;
148
149 buf = (unsigned long *) vbuf;
150 rp = (volatile unsigned long *) addr;
151 for (ebuf = buf + len; (buf < ebuf); )
152 *rp = *buf++;
153}
154
155
156#ifdef CONFIG_NETtel
157/*
158 * Re-map the address space of at least one of the SMC ethernet
159 * parts. Both parts power up decoding the same address, so we
160 * need to move one of them first, before doing enything else.
161 *
162 * We also increase the number of wait states for this part by one.
163 */
164
165void smc_remap(unsigned int ioaddr)
166{
167 static int once = 0;
168 extern unsigned short ppdata;
169 if (once++ == 0) {
170 *((volatile unsigned short *)MCFSIM_PADDR) = 0x00ec;
171 ppdata |= 0x0080;
172 *((volatile unsigned short *)MCFSIM_PADAT) = ppdata;
173 outw(0x0001, ioaddr + BANK_SELECT);
174 outw(0x0001, ioaddr + BANK_SELECT);
175 outw(0x0067, ioaddr + BASE);
176
177 ppdata &= ~0x0080;
178 *((volatile unsigned short *)MCFSIM_PADAT) = ppdata;
179 }
180
181 *((volatile unsigned short *)(MCF_MBAR+MCFSIM_CSCR3)) = 0x1180;
182}
183
184#endif
185
186/****************************************************************************/
187#endif /* mcfsmc_h */
diff --git a/arch/m68k/include/asm/processor.h b/arch/m68k/include/asm/processor.h
index cbd3d4751dd2..7a6a7590cc02 100644
--- a/arch/m68k/include/asm/processor.h
+++ b/arch/m68k/include/asm/processor.h
@@ -44,11 +44,15 @@ static inline void wrusp(unsigned long usp)
44 * User space process size: 3.75GB. This is hardcoded into a few places, 44 * User space process size: 3.75GB. This is hardcoded into a few places,
45 * so don't change it unless you know what you are doing. 45 * so don't change it unless you know what you are doing.
46 */ 46 */
47#ifdef CONFIG_MMU
47#ifndef CONFIG_SUN3 48#ifndef CONFIG_SUN3
48#define TASK_SIZE (0xF0000000UL) 49#define TASK_SIZE (0xF0000000UL)
49#else 50#else
50#define TASK_SIZE (0x0E000000UL) 51#define TASK_SIZE (0x0E000000UL)
51#endif 52#endif
53#else
54#define TASK_SIZE (0xFFFFFFFFUL)
55#endif
52 56
53#ifdef __KERNEL__ 57#ifdef __KERNEL__
54#define STACK_TOP TASK_SIZE 58#define STACK_TOP TASK_SIZE
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