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-rw-r--r--arch/m68k/include/asm/atariints.h2
-rw-r--r--arch/m68k/include/asm/bootstd.h2
-rw-r--r--arch/m68k/include/asm/commproc.h4
-rw-r--r--arch/m68k/include/asm/delay_no.h2
-rw-r--r--arch/m68k/include/asm/gpio.h2
-rw-r--r--arch/m68k/include/asm/m520xsim.h2
-rw-r--r--arch/m68k/include/asm/m523xsim.h2
-rw-r--r--arch/m68k/include/asm/m527xsim.h2
-rw-r--r--arch/m68k/include/asm/m5307sim.h2
-rw-r--r--arch/m68k/include/asm/m5407sim.h2
-rw-r--r--arch/m68k/include/asm/m68360_quicc.h2
-rw-r--r--arch/m68k/include/asm/mac_oss.h2
-rw-r--r--arch/m68k/include/asm/mac_via.h2
-rw-r--r--arch/m68k/include/asm/macintosh.h2
-rw-r--r--arch/m68k/include/asm/mcftimer.h2
15 files changed, 16 insertions, 16 deletions
diff --git a/arch/m68k/include/asm/atariints.h b/arch/m68k/include/asm/atariints.h
index f597892e43a0..656bbbf5a6ff 100644
--- a/arch/m68k/include/asm/atariints.h
+++ b/arch/m68k/include/asm/atariints.h
@@ -146,7 +146,7 @@ static inline void clear_mfp_bit( unsigned irq, int type )
146 146
147/* 147/*
148 * {en,dis}able_irq have the usual semantics of temporary blocking the 148 * {en,dis}able_irq have the usual semantics of temporary blocking the
149 * interrupt, but not loosing requests that happen between disabling and 149 * interrupt, but not losing requests that happen between disabling and
150 * enabling. This is done with the MFP mask registers. 150 * enabling. This is done with the MFP mask registers.
151 */ 151 */
152 152
diff --git a/arch/m68k/include/asm/bootstd.h b/arch/m68k/include/asm/bootstd.h
index bdc1a4ac4fe9..e518f5a575b7 100644
--- a/arch/m68k/include/asm/bootstd.h
+++ b/arch/m68k/include/asm/bootstd.h
@@ -31,7 +31,7 @@
31#define __BN_flash_write_range 20 31#define __BN_flash_write_range 20
32 32
33/* Calling conventions compatible to (uC)linux/68k 33/* Calling conventions compatible to (uC)linux/68k
34 * We use simmilar macros to call into the bootloader as for uClinux 34 * We use similar macros to call into the bootloader as for uClinux
35 */ 35 */
36 36
37#define __bsc_return(type, res) \ 37#define __bsc_return(type, res) \
diff --git a/arch/m68k/include/asm/commproc.h b/arch/m68k/include/asm/commproc.h
index edf5eb6c08d2..a73998528d26 100644
--- a/arch/m68k/include/asm/commproc.h
+++ b/arch/m68k/include/asm/commproc.h
@@ -88,7 +88,7 @@ typedef struct cpm_buf_desc {
88 88
89 89
90/* rx bd status/control bits */ 90/* rx bd status/control bits */
91#define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */ 91#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */
92#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor in table */ 92#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor in table */
93#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */ 93#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
94#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame OR control char */ 94#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame OR control char */
@@ -96,7 +96,7 @@ typedef struct cpm_buf_desc {
96#define BD_SC_FIRST ((ushort)0x0400) /* 1st buffer in an HDLC frame */ 96#define BD_SC_FIRST ((ushort)0x0400) /* 1st buffer in an HDLC frame */
97#define BD_SC_ADDR ((ushort)0x0400) /* 1st byte is a multidrop address */ 97#define BD_SC_ADDR ((ushort)0x0400) /* 1st byte is a multidrop address */
98 98
99#define BD_SC_CM ((ushort)0x0200) /* Continous mode */ 99#define BD_SC_CM ((ushort)0x0200) /* Continuous mode */
100#define BD_SC_ID ((ushort)0x0100) /* Received too many idles */ 100#define BD_SC_ID ((ushort)0x0100) /* Received too many idles */
101 101
102#define BD_SC_AM ((ushort)0x0080) /* Multidrop address match */ 102#define BD_SC_AM ((ushort)0x0080) /* Multidrop address match */
diff --git a/arch/m68k/include/asm/delay_no.h b/arch/m68k/include/asm/delay_no.h
index 55cbd6294ab6..c3a0edc90f21 100644
--- a/arch/m68k/include/asm/delay_no.h
+++ b/arch/m68k/include/asm/delay_no.h
@@ -16,7 +16,7 @@ static inline void __delay(unsigned long loops)
16 * long word alignment which is the faster version. 16 * long word alignment which is the faster version.
17 * The 0x4a8e is of course a 'tstl %fp' instruction. This is better 17 * The 0x4a8e is of course a 'tstl %fp' instruction. This is better
18 * than using a NOP (0x4e71) instruction because it executes in one 18 * than using a NOP (0x4e71) instruction because it executes in one
19 * cycle not three and doesn't allow for an arbitary delay waiting 19 * cycle not three and doesn't allow for an arbitrary delay waiting
20 * for bus cycles to finish. Also fp/a6 isn't likely to cause a 20 * for bus cycles to finish. Also fp/a6 isn't likely to cause a
21 * stall waiting for the register to become valid if such is added 21 * stall waiting for the register to become valid if such is added
22 * to the coldfire at some stage. 22 * to the coldfire at some stage.
diff --git a/arch/m68k/include/asm/gpio.h b/arch/m68k/include/asm/gpio.h
index c64c7b74cf86..b2046839f4b2 100644
--- a/arch/m68k/include/asm/gpio.h
+++ b/arch/m68k/include/asm/gpio.h
@@ -31,7 +31,7 @@
31 * GPIOs in a single control area, others have some GPIOs implemented in 31 * GPIOs in a single control area, others have some GPIOs implemented in
32 * different modules. 32 * different modules.
33 * 33 *
34 * This implementation attempts accomodate the differences while presenting 34 * This implementation attempts accommodate the differences while presenting
35 * a generic interface that will optimize to as few instructions as possible. 35 * a generic interface that will optimize to as few instructions as possible.
36 */ 36 */
37#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \ 37#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
diff --git a/arch/m68k/include/asm/m520xsim.h b/arch/m68k/include/asm/m520xsim.h
index 55d5a4c5fe0b..b6bf2c518bac 100644
--- a/arch/m68k/include/asm/m520xsim.h
+++ b/arch/m68k/include/asm/m520xsim.h
@@ -157,7 +157,7 @@
157#define MCFFEC_SIZE 0x800 /* Register set size */ 157#define MCFFEC_SIZE 0x800 /* Register set size */
158 158
159/* 159/*
160 * Reset Controll Unit. 160 * Reset Control Unit.
161 */ 161 */
162#define MCF_RCR 0xFC0A0000 162#define MCF_RCR 0xFC0A0000
163#define MCF_RSR 0xFC0A0001 163#define MCF_RSR 0xFC0A0001
diff --git a/arch/m68k/include/asm/m523xsim.h b/arch/m68k/include/asm/m523xsim.h
index 8996df62ede4..6235921eca4e 100644
--- a/arch/m68k/include/asm/m523xsim.h
+++ b/arch/m68k/include/asm/m523xsim.h
@@ -48,7 +48,7 @@
48#define MCFSIM_DMR1 (MCF_IPSBAR + 0x54) /* Address mask 1 */ 48#define MCFSIM_DMR1 (MCF_IPSBAR + 0x54) /* Address mask 1 */
49 49
50/* 50/*
51 * Reset Controll Unit (relative to IPSBAR). 51 * Reset Control Unit (relative to IPSBAR).
52 */ 52 */
53#define MCF_RCR 0x110000 53#define MCF_RCR 0x110000
54#define MCF_RSR 0x110001 54#define MCF_RSR 0x110001
diff --git a/arch/m68k/include/asm/m527xsim.h b/arch/m68k/include/asm/m527xsim.h
index 74855a66c050..758810ef91ec 100644
--- a/arch/m68k/include/asm/m527xsim.h
+++ b/arch/m68k/include/asm/m527xsim.h
@@ -283,7 +283,7 @@
283#endif 283#endif
284 284
285/* 285/*
286 * Reset Controll Unit (relative to IPSBAR). 286 * Reset Control Unit (relative to IPSBAR).
287 */ 287 */
288#define MCF_RCR 0x110000 288#define MCF_RCR 0x110000
289#define MCF_RSR 0x110001 289#define MCF_RSR 0x110001
diff --git a/arch/m68k/include/asm/m5307sim.h b/arch/m68k/include/asm/m5307sim.h
index 4c94c01f36c4..8f8609fcc9b8 100644
--- a/arch/m68k/include/asm/m5307sim.h
+++ b/arch/m68k/include/asm/m5307sim.h
@@ -29,7 +29,7 @@
29#define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */ 29#define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */
30#define MCFSIM_PAR 0x04 /* Pin Assignment reg (r/w) */ 30#define MCFSIM_PAR 0x04 /* Pin Assignment reg (r/w) */
31#define MCFSIM_IRQPAR 0x06 /* Interrupt Assignment reg (r/w) */ 31#define MCFSIM_IRQPAR 0x06 /* Interrupt Assignment reg (r/w) */
32#define MCFSIM_PLLCR 0x08 /* PLL Controll Reg*/ 32#define MCFSIM_PLLCR 0x08 /* PLL Control Reg*/
33#define MCFSIM_MPARK 0x0C /* BUS Master Control Reg*/ 33#define MCFSIM_MPARK 0x0C /* BUS Master Control Reg*/
34#define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */ 34#define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */
35#define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */ 35#define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */
diff --git a/arch/m68k/include/asm/m5407sim.h b/arch/m68k/include/asm/m5407sim.h
index 762c58c89050..51e00b00b8a6 100644
--- a/arch/m68k/include/asm/m5407sim.h
+++ b/arch/m68k/include/asm/m5407sim.h
@@ -29,7 +29,7 @@
29#define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */ 29#define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */
30#define MCFSIM_PAR 0x04 /* Pin Assignment reg (r/w) */ 30#define MCFSIM_PAR 0x04 /* Pin Assignment reg (r/w) */
31#define MCFSIM_IRQPAR 0x06 /* Interrupt Assignment reg (r/w) */ 31#define MCFSIM_IRQPAR 0x06 /* Interrupt Assignment reg (r/w) */
32#define MCFSIM_PLLCR 0x08 /* PLL Controll Reg*/ 32#define MCFSIM_PLLCR 0x08 /* PLL Control Reg*/
33#define MCFSIM_MPARK 0x0C /* BUS Master Control Reg*/ 33#define MCFSIM_MPARK 0x0C /* BUS Master Control Reg*/
34#define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */ 34#define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */
35#define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */ 35#define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */
diff --git a/arch/m68k/include/asm/m68360_quicc.h b/arch/m68k/include/asm/m68360_quicc.h
index 6d40f4d18e10..59414cc108d3 100644
--- a/arch/m68k/include/asm/m68360_quicc.h
+++ b/arch/m68k/include/asm/m68360_quicc.h
@@ -32,7 +32,7 @@ struct user_data {
32 /* BASE + 0x000: user data memory */ 32 /* BASE + 0x000: user data memory */
33 volatile unsigned char udata_bd_ucode[0x400]; /*user data bd's Ucode*/ 33 volatile unsigned char udata_bd_ucode[0x400]; /*user data bd's Ucode*/
34 volatile unsigned char udata_bd[0x200]; /*user data Ucode */ 34 volatile unsigned char udata_bd[0x200]; /*user data Ucode */
35 volatile unsigned char ucode_ext[0x100]; /*Ucode Extention ram */ 35 volatile unsigned char ucode_ext[0x100]; /*Ucode Extension ram */
36 volatile unsigned char RESERVED1[0x500]; /* Reserved area */ 36 volatile unsigned char RESERVED1[0x500]; /* Reserved area */
37}; 37};
38#else 38#else
diff --git a/arch/m68k/include/asm/mac_oss.h b/arch/m68k/include/asm/mac_oss.h
index 7221f7251934..3cf2b6ed685a 100644
--- a/arch/m68k/include/asm/mac_oss.h
+++ b/arch/m68k/include/asm/mac_oss.h
@@ -61,7 +61,7 @@
61/* 61/*
62 * OSS Interrupt levels for various sub-systems 62 * OSS Interrupt levels for various sub-systems
63 * 63 *
64 * This mapping is layed out with two things in mind: first, we try to keep 64 * This mapping is laid out with two things in mind: first, we try to keep
65 * things on their own levels to avoid having to do double-dispatches. Second, 65 * things on their own levels to avoid having to do double-dispatches. Second,
66 * the levels match as closely as possible the alternate IRQ mapping mode (aka 66 * the levels match as closely as possible the alternate IRQ mapping mode (aka
67 * "A/UX mode") available on some VIA machines. 67 * "A/UX mode") available on some VIA machines.
diff --git a/arch/m68k/include/asm/mac_via.h b/arch/m68k/include/asm/mac_via.h
index 39afb438b656..a59665e1d41b 100644
--- a/arch/m68k/include/asm/mac_via.h
+++ b/arch/m68k/include/asm/mac_via.h
@@ -204,7 +204,7 @@
204#define vT2CL 0x1000 /* [VIA only] Timer two counter low. */ 204#define vT2CL 0x1000 /* [VIA only] Timer two counter low. */
205#define vT2CH 0x1200 /* [VIA only] Timer two counter high. */ 205#define vT2CH 0x1200 /* [VIA only] Timer two counter high. */
206#define vSR 0x1400 /* [VIA only] Shift register. */ 206#define vSR 0x1400 /* [VIA only] Shift register. */
207#define vACR 0x1600 /* [VIA only] Auxilary control register. */ 207#define vACR 0x1600 /* [VIA only] Auxiliary control register. */
208#define vPCR 0x1800 /* [VIA only] Peripheral control register. */ 208#define vPCR 0x1800 /* [VIA only] Peripheral control register. */
209 /* CHRP sez never ever to *write* this. 209 /* CHRP sez never ever to *write* this.
210 * Mac family says never to *change* this. 210 * Mac family says never to *change* this.
diff --git a/arch/m68k/include/asm/macintosh.h b/arch/m68k/include/asm/macintosh.h
index 50db3591ca15..c2a1c5eac1a6 100644
--- a/arch/m68k/include/asm/macintosh.h
+++ b/arch/m68k/include/asm/macintosh.h
@@ -14,7 +14,7 @@ extern void mac_init_IRQ(void);
14extern int mac_irq_pending(unsigned int); 14extern int mac_irq_pending(unsigned int);
15 15
16/* 16/*
17 * Floppy driver magic hook - probably shouldnt be here 17 * Floppy driver magic hook - probably shouldn't be here
18 */ 18 */
19 19
20extern void via1_set_head(int); 20extern void via1_set_head(int);
diff --git a/arch/m68k/include/asm/mcftimer.h b/arch/m68k/include/asm/mcftimer.h
index 92b276fe8240..351c27237874 100644
--- a/arch/m68k/include/asm/mcftimer.h
+++ b/arch/m68k/include/asm/mcftimer.h
@@ -27,7 +27,7 @@
27 27
28/* 28/*
29 * Bit definitions for the Timer Mode Register (TMR). 29 * Bit definitions for the Timer Mode Register (TMR).
30 * Register bit flags are common accross ColdFires. 30 * Register bit flags are common across ColdFires.
31 */ 31 */
32#define MCFTIMER_TMR_PREMASK 0xff00 /* Prescalar mask */ 32#define MCFTIMER_TMR_PREMASK 0xff00 /* Prescalar mask */
33#define MCFTIMER_TMR_DISCE 0x0000 /* Disable capture */ 33#define MCFTIMER_TMR_DISCE 0x0000 /* Disable capture */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-29 14:12:45 -0500