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-rw-r--r--arch/m68k/include/asm/cacheflush_mm.h41
-rw-r--r--arch/m68k/include/asm/dma.h8
-rw-r--r--arch/m68k/include/asm/gpio.h179
-rw-r--r--arch/m68k/include/asm/io_mm.h50
-rw-r--r--arch/m68k/include/asm/m520xsim.h14
-rw-r--r--arch/m68k/include/asm/m523xsim.h1
-rw-r--r--arch/m68k/include/asm/m525xsim.h194
-rw-r--r--arch/m68k/include/asm/m527xsim.h1
-rw-r--r--arch/m68k/include/asm/m528xsim.h2
-rw-r--r--arch/m68k/include/asm/m532xsim.h17
-rw-r--r--arch/m68k/include/asm/m5441xsim.h276
-rw-r--r--arch/m68k/include/asm/m54xxacr.h4
-rw-r--r--arch/m68k/include/asm/m54xxpci.h138
-rw-r--r--arch/m68k/include/asm/m54xxsim.h3
-rw-r--r--arch/m68k/include/asm/mcf8390.h (renamed from arch/m68k/include/asm/mcfne.h)137
-rw-r--r--arch/m68k/include/asm/mcfclk.h43
-rw-r--r--arch/m68k/include/asm/mcfgpio.h343
-rw-r--r--arch/m68k/include/asm/mcfsim.h5
-rw-r--r--arch/m68k/include/asm/mcftimer.h2
-rw-r--r--arch/m68k/include/asm/mcfuart.h4
-rw-r--r--arch/m68k/include/asm/pci.h6
-rw-r--r--arch/m68k/include/asm/pinmux.h30
22 files changed, 1103 insertions, 395 deletions
diff --git a/arch/m68k/include/asm/cacheflush_mm.h b/arch/m68k/include/asm/cacheflush_mm.h
index 8104bd874649..fa2c3d681d84 100644
--- a/arch/m68k/include/asm/cacheflush_mm.h
+++ b/arch/m68k/include/asm/cacheflush_mm.h
@@ -16,7 +16,48 @@
16#define DCACHE_MAX_ADDR 0 16#define DCACHE_MAX_ADDR 0
17#define DCACHE_SETMASK 0 17#define DCACHE_SETMASK 0
18#endif 18#endif
19#ifndef CACHE_MODE
20#define CACHE_MODE 0
21#define CACR_ICINVA 0
22#define CACR_DCINVA 0
23#define CACR_BCINVA 0
24#endif
25
26/*
27 * ColdFire architecture has no way to clear individual cache lines, so we
28 * are stuck invalidating all the cache entries when we want a clear operation.
29 */
30static inline void clear_cf_icache(unsigned long start, unsigned long end)
31{
32 __asm__ __volatile__ (
33 "movec %0,%%cacr\n\t"
34 "nop"
35 :
36 : "r" (CACHE_MODE | CACR_ICINVA | CACR_BCINVA));
37}
38
39static inline void clear_cf_dcache(unsigned long start, unsigned long end)
40{
41 __asm__ __volatile__ (
42 "movec %0,%%cacr\n\t"
43 "nop"
44 :
45 : "r" (CACHE_MODE | CACR_DCINVA));
46}
19 47
48static inline void clear_cf_bcache(unsigned long start, unsigned long end)
49{
50 __asm__ __volatile__ (
51 "movec %0,%%cacr\n\t"
52 "nop"
53 :
54 : "r" (CACHE_MODE | CACR_ICINVA | CACR_BCINVA | CACR_DCINVA));
55}
56
57/*
58 * Use the ColdFire cpushl instruction to push (and invalidate) cache lines.
59 * The start and end addresses are cache line numbers not memory addresses.
60 */
20static inline void flush_cf_icache(unsigned long start, unsigned long end) 61static inline void flush_cf_icache(unsigned long start, unsigned long end)
21{ 62{
22 unsigned long set; 63 unsigned long set;
diff --git a/arch/m68k/include/asm/dma.h b/arch/m68k/include/asm/dma.h
index 6fbdfe895104..0ff3fc6a6d9a 100644
--- a/arch/m68k/include/asm/dma.h
+++ b/arch/m68k/include/asm/dma.h
@@ -33,7 +33,9 @@
33 * Set number of channels of DMA on ColdFire for different implementations. 33 * Set number of channels of DMA on ColdFire for different implementations.
34 */ 34 */
35#if defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407) || \ 35#if defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407) || \
36 defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) 36 defined(CONFIG_M523x) || defined(CONFIG_M527x) || \
37 defined(CONFIG_M528x) || defined(CONFIG_M525x)
38
37#define MAX_M68K_DMA_CHANNELS 4 39#define MAX_M68K_DMA_CHANNELS 4
38#elif defined(CONFIG_M5272) 40#elif defined(CONFIG_M5272)
39#define MAX_M68K_DMA_CHANNELS 1 41#define MAX_M68K_DMA_CHANNELS 1
@@ -486,6 +488,10 @@ static __inline__ int get_dma_residue(unsigned int dmanr)
486extern int request_dma(unsigned int dmanr, const char * device_id); /* reserve a DMA channel */ 488extern int request_dma(unsigned int dmanr, const char * device_id); /* reserve a DMA channel */
487extern void free_dma(unsigned int dmanr); /* release it again */ 489extern void free_dma(unsigned int dmanr); /* release it again */
488 490
491#ifdef CONFIG_PCI
492extern int isa_dma_bridge_buggy;
493#else
489#define isa_dma_bridge_buggy (0) 494#define isa_dma_bridge_buggy (0)
495#endif
490 496
491#endif /* _M68K_DMA_H */ 497#endif /* _M68K_DMA_H */
diff --git a/arch/m68k/include/asm/gpio.h b/arch/m68k/include/asm/gpio.h
index 00d0071de4c3..4395ffc51fdb 100644
--- a/arch/m68k/include/asm/gpio.h
+++ b/arch/m68k/include/asm/gpio.h
@@ -17,170 +17,9 @@
17#define coldfire_gpio_h 17#define coldfire_gpio_h
18 18
19#include <linux/io.h> 19#include <linux/io.h>
20#include <asm-generic/gpio.h>
21#include <asm/coldfire.h> 20#include <asm/coldfire.h>
22#include <asm/mcfsim.h> 21#include <asm/mcfsim.h>
23 22#include <asm/mcfgpio.h>
24/*
25 * The Freescale Coldfire family is quite varied in how they implement GPIO.
26 * Some parts have 8 bit ports, some have 16bit and some have 32bit; some have
27 * only one port, others have multiple ports; some have a single data latch
28 * for both input and output, others have a separate pin data register to read
29 * input; some require a read-modify-write access to change an output, others
30 * have set and clear registers for some of the outputs; Some have all the
31 * GPIOs in a single control area, others have some GPIOs implemented in
32 * different modules.
33 *
34 * This implementation attempts accommodate the differences while presenting
35 * a generic interface that will optimize to as few instructions as possible.
36 */
37#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
38 defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
39 defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
40 defined(CONFIG_M532x) || defined(CONFIG_M54xx)
41
42/* These parts have GPIO organized by 8 bit ports */
43
44#define MCFGPIO_PORTTYPE u8
45#define MCFGPIO_PORTSIZE 8
46#define mcfgpio_read(port) __raw_readb(port)
47#define mcfgpio_write(data, port) __raw_writeb(data, port)
48
49#elif defined(CONFIG_M5307) || defined(CONFIG_M5407) || defined(CONFIG_M5272)
50
51/* These parts have GPIO organized by 16 bit ports */
52
53#define MCFGPIO_PORTTYPE u16
54#define MCFGPIO_PORTSIZE 16
55#define mcfgpio_read(port) __raw_readw(port)
56#define mcfgpio_write(data, port) __raw_writew(data, port)
57
58#elif defined(CONFIG_M5249)
59
60/* These parts have GPIO organized by 32 bit ports */
61
62#define MCFGPIO_PORTTYPE u32
63#define MCFGPIO_PORTSIZE 32
64#define mcfgpio_read(port) __raw_readl(port)
65#define mcfgpio_write(data, port) __raw_writel(data, port)
66
67#endif
68
69#define mcfgpio_bit(gpio) (1 << ((gpio) % MCFGPIO_PORTSIZE))
70#define mcfgpio_port(gpio) ((gpio) / MCFGPIO_PORTSIZE)
71
72#if defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
73 defined(CONFIG_M527x) || defined(CONFIG_M528x) || defined(CONFIG_M532x)
74/*
75 * These parts have an 'Edge' Port module (external interrupt/GPIO) which uses
76 * read-modify-write to change an output and a GPIO module which has separate
77 * set/clr registers to directly change outputs with a single write access.
78 */
79#if defined(CONFIG_M528x)
80/*
81 * The 528x also has GPIOs in other modules (GPT, QADC) which use
82 * read-modify-write as well as those controlled by the EPORT and GPIO modules.
83 */
84#define MCFGPIO_SCR_START 40
85#else
86#define MCFGPIO_SCR_START 8
87#endif
88
89#define MCFGPIO_SETR_PORT(gpio) (MCFGPIO_SETR + \
90 mcfgpio_port(gpio - MCFGPIO_SCR_START))
91
92#define MCFGPIO_CLRR_PORT(gpio) (MCFGPIO_CLRR + \
93 mcfgpio_port(gpio - MCFGPIO_SCR_START))
94#else
95
96#define MCFGPIO_SCR_START MCFGPIO_PIN_MAX
97/* with MCFGPIO_SCR == MCFGPIO_PIN_MAX, these will be optimized away */
98#define MCFGPIO_SETR_PORT(gpio) 0
99#define MCFGPIO_CLRR_PORT(gpio) 0
100
101#endif
102/*
103 * Coldfire specific helper functions
104 */
105
106/* return the port pin data register for a gpio */
107static inline u32 __mcf_gpio_ppdr(unsigned gpio)
108{
109#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
110 defined(CONFIG_M5307) || defined(CONFIG_M5407)
111 return MCFSIM_PADAT;
112#elif defined(CONFIG_M5272)
113 if (gpio < 16)
114 return MCFSIM_PADAT;
115 else if (gpio < 32)
116 return MCFSIM_PBDAT;
117 else
118 return MCFSIM_PCDAT;
119#elif defined(CONFIG_M5249)
120 if (gpio < 32)
121 return MCFSIM2_GPIOREAD;
122 else
123 return MCFSIM2_GPIO1READ;
124#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
125 defined(CONFIG_M527x) || defined(CONFIG_M528x) || defined(CONFIG_M532x)
126 if (gpio < 8)
127 return MCFEPORT_EPPDR;
128#if defined(CONFIG_M528x)
129 else if (gpio < 16)
130 return MCFGPTA_GPTPORT;
131 else if (gpio < 24)
132 return MCFGPTB_GPTPORT;
133 else if (gpio < 32)
134 return MCFQADC_PORTQA;
135 else if (gpio < 40)
136 return MCFQADC_PORTQB;
137#endif
138 else
139 return MCFGPIO_PPDR + mcfgpio_port(gpio - MCFGPIO_SCR_START);
140#else
141 return 0;
142#endif
143}
144
145/* return the port output data register for a gpio */
146static inline u32 __mcf_gpio_podr(unsigned gpio)
147{
148#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
149 defined(CONFIG_M5307) || defined(CONFIG_M5407)
150 return MCFSIM_PADAT;
151#elif defined(CONFIG_M5272)
152 if (gpio < 16)
153 return MCFSIM_PADAT;
154 else if (gpio < 32)
155 return MCFSIM_PBDAT;
156 else
157 return MCFSIM_PCDAT;
158#elif defined(CONFIG_M5249)
159 if (gpio < 32)
160 return MCFSIM2_GPIOWRITE;
161 else
162 return MCFSIM2_GPIO1WRITE;
163#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
164 defined(CONFIG_M527x) || defined(CONFIG_M528x) || defined(CONFIG_M532x)
165 if (gpio < 8)
166 return MCFEPORT_EPDR;
167#if defined(CONFIG_M528x)
168 else if (gpio < 16)
169 return MCFGPTA_GPTPORT;
170 else if (gpio < 24)
171 return MCFGPTB_GPTPORT;
172 else if (gpio < 32)
173 return MCFQADC_PORTQA;
174 else if (gpio < 40)
175 return MCFQADC_PORTQB;
176#endif
177 else
178 return MCFGPIO_PODR + mcfgpio_port(gpio - MCFGPIO_SCR_START);
179#else
180 return 0;
181#endif
182}
183
184/* 23/*
185 * The Generic GPIO functions 24 * The Generic GPIO functions
186 * 25 *
@@ -191,7 +30,7 @@ static inline u32 __mcf_gpio_podr(unsigned gpio)
191static inline int gpio_get_value(unsigned gpio) 30static inline int gpio_get_value(unsigned gpio)
192{ 31{
193 if (__builtin_constant_p(gpio) && gpio < MCFGPIO_PIN_MAX) 32 if (__builtin_constant_p(gpio) && gpio < MCFGPIO_PIN_MAX)
194 return mcfgpio_read(__mcf_gpio_ppdr(gpio)) & mcfgpio_bit(gpio); 33 return mcfgpio_read(__mcfgpio_ppdr(gpio)) & mcfgpio_bit(gpio);
195 else 34 else
196 return __gpio_get_value(gpio); 35 return __gpio_get_value(gpio);
197} 36}
@@ -204,12 +43,12 @@ static inline void gpio_set_value(unsigned gpio, int value)
204 MCFGPIO_PORTTYPE data; 43 MCFGPIO_PORTTYPE data;
205 44
206 local_irq_save(flags); 45 local_irq_save(flags);
207 data = mcfgpio_read(__mcf_gpio_podr(gpio)); 46 data = mcfgpio_read(__mcfgpio_podr(gpio));
208 if (value) 47 if (value)
209 data |= mcfgpio_bit(gpio); 48 data |= mcfgpio_bit(gpio);
210 else 49 else
211 data &= ~mcfgpio_bit(gpio); 50 data &= ~mcfgpio_bit(gpio);
212 mcfgpio_write(data, __mcf_gpio_podr(gpio)); 51 mcfgpio_write(data, __mcfgpio_podr(gpio));
213 local_irq_restore(flags); 52 local_irq_restore(flags);
214 } else { 53 } else {
215 if (value) 54 if (value)
@@ -225,8 +64,14 @@ static inline void gpio_set_value(unsigned gpio, int value)
225 64
226static inline int gpio_to_irq(unsigned gpio) 65static inline int gpio_to_irq(unsigned gpio)
227{ 66{
228 return (gpio < MCFGPIO_IRQ_MAX) ? gpio + MCFGPIO_IRQ_VECBASE 67#if defined(MCFGPIO_IRQ_MIN)
229 : __gpio_to_irq(gpio); 68 if ((gpio >= MCFGPIO_IRQ_MIN) && (gpio < MCFGPIO_IRQ_MAX))
69#else
70 if (gpio < MCFGPIO_IRQ_MAX)
71#endif
72 return gpio + MCFGPIO_IRQ_VECBASE;
73 else
74 return __gpio_to_irq(gpio);
230} 75}
231 76
232static inline int irq_to_gpio(unsigned irq) 77static inline int irq_to_gpio(unsigned irq)
diff --git a/arch/m68k/include/asm/io_mm.h b/arch/m68k/include/asm/io_mm.h
index fa4324bcf566..a6686d26fe17 100644
--- a/arch/m68k/include/asm/io_mm.h
+++ b/arch/m68k/include/asm/io_mm.h
@@ -65,7 +65,53 @@
65 65
66 66
67 67
68#ifdef CONFIG_ISA 68#if defined(CONFIG_PCI) && defined(CONFIG_COLDFIRE)
69
70#define HAVE_ARCH_PIO_SIZE
71#define PIO_OFFSET 0
72#define PIO_MASK 0xffff
73#define PIO_RESERVED 0x10000
74
75u8 mcf_pci_inb(u32 addr);
76u16 mcf_pci_inw(u32 addr);
77u32 mcf_pci_inl(u32 addr);
78void mcf_pci_insb(u32 addr, u8 *buf, u32 len);
79void mcf_pci_insw(u32 addr, u16 *buf, u32 len);
80void mcf_pci_insl(u32 addr, u32 *buf, u32 len);
81
82void mcf_pci_outb(u8 v, u32 addr);
83void mcf_pci_outw(u16 v, u32 addr);
84void mcf_pci_outl(u32 v, u32 addr);
85void mcf_pci_outsb(u32 addr, const u8 *buf, u32 len);
86void mcf_pci_outsw(u32 addr, const u16 *buf, u32 len);
87void mcf_pci_outsl(u32 addr, const u32 *buf, u32 len);
88
89#define inb mcf_pci_inb
90#define inb_p mcf_pci_inb
91#define inw mcf_pci_inw
92#define inw_p mcf_pci_inw
93#define inl mcf_pci_inl
94#define inl_p mcf_pci_inl
95#define insb mcf_pci_insb
96#define insw mcf_pci_insw
97#define insl mcf_pci_insl
98
99#define outb mcf_pci_outb
100#define outb_p mcf_pci_outb
101#define outw mcf_pci_outw
102#define outw_p mcf_pci_outw
103#define outl mcf_pci_outl
104#define outl_p mcf_pci_outl
105#define outsb mcf_pci_outsb
106#define outsw mcf_pci_outsw
107#define outsl mcf_pci_outsl
108
109#define readb(addr) in_8(addr)
110#define writeb(v, addr) out_8((addr), (v))
111#define readw(addr) in_le16(addr)
112#define writew(v, addr) out_le16((addr), (v))
113
114#elif defined(CONFIG_ISA)
69 115
70#if MULTI_ISA == 0 116#if MULTI_ISA == 0
71#undef MULTI_ISA 117#undef MULTI_ISA
@@ -340,4 +386,6 @@ static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int
340 */ 386 */
341#define xlate_dev_kmem_ptr(p) p 387#define xlate_dev_kmem_ptr(p) p
342 388
389#define ioport_map(port, nr) ((void __iomem *)(port))
390
343#endif /* _IO_H */ 391#endif /* _IO_H */
diff --git a/arch/m68k/include/asm/m520xsim.h b/arch/m68k/include/asm/m520xsim.h
index 17f2aab9cf97..db3f8ee4a6c6 100644
--- a/arch/m68k/include/asm/m520xsim.h
+++ b/arch/m68k/include/asm/m520xsim.h
@@ -42,6 +42,9 @@
42#define MCFINTC1_SIMR (0) 42#define MCFINTC1_SIMR (0)
43#define MCFINTC1_CIMR (0) 43#define MCFINTC1_CIMR (0)
44#define MCFINTC1_ICR0 (0) 44#define MCFINTC1_ICR0 (0)
45#define MCFINTC2_SIMR (0)
46#define MCFINTC2_CIMR (0)
47#define MCFINTC2_ICR0 (0)
45 48
46#define MCFINT_VECBASE 64 49#define MCFINT_VECBASE 64
47#define MCFINT_UART0 26 /* Interrupt number for UART0 */ 50#define MCFINT_UART0 26 /* Interrupt number for UART0 */
@@ -62,6 +65,7 @@
62#define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0) 65#define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0)
63 66
64#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI) 67#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
68#define MCF_IRQ_PIT1 (MCFINT_VECBASE + MCFINT_PIT1)
65 69
66/* 70/*
67 * SDRAM configuration registers. 71 * SDRAM configuration registers.
@@ -186,5 +190,15 @@
186#define MCF_RCR_SWRESET 0x80 /* Software reset bit */ 190#define MCF_RCR_SWRESET 0x80 /* Software reset bit */
187#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */ 191#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */
188 192
193/*
194 * Power Management.
195 */
196#define MCFPM_WCR 0xfc040013
197#define MCFPM_PPMSR0 0xfc04002c
198#define MCFPM_PPMCR0 0xfc04002d
199#define MCFPM_PPMHR0 0xfc040030
200#define MCFPM_PPMLR0 0xfc040034
201#define MCFPM_LPCR 0xfc0a0007
202
189/****************************************************************************/ 203/****************************************************************************/
190#endif /* m520xsim_h */ 204#endif /* m520xsim_h */
diff --git a/arch/m68k/include/asm/m523xsim.h b/arch/m68k/include/asm/m523xsim.h
index 075062d4eecd..91d3abc3f2a5 100644
--- a/arch/m68k/include/asm/m523xsim.h
+++ b/arch/m68k/include/asm/m523xsim.h
@@ -52,6 +52,7 @@
52#define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0) 52#define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0)
53 53
54#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI) 54#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
55#define MCF_IRQ_PIT1 (MCFINT_VECBASE + MCFINT_PIT1)
55 56
56/* 57/*
57 * SDRAM configuration registers. 58 * SDRAM configuration registers.
diff --git a/arch/m68k/include/asm/m525xsim.h b/arch/m68k/include/asm/m525xsim.h
new file mode 100644
index 000000000000..6da24f653902
--- /dev/null
+++ b/arch/m68k/include/asm/m525xsim.h
@@ -0,0 +1,194 @@
1/****************************************************************************/
2
3/*
4 * m525xsim.h -- ColdFire 525x System Integration Module support.
5 *
6 * (C) Copyright 2012, Steven king <sfking@fdwdc.com>
7 * (C) Copyright 2002, Greg Ungerer (gerg@snapgear.com)
8 */
9
10/****************************************************************************/
11#ifndef m525xsim_h
12#define m525xsim_h
13/****************************************************************************/
14
15#define CPU_NAME "COLDFIRE(m525x)"
16#define CPU_INSTR_PER_JIFFY 3
17#define MCF_BUSCLK (MCF_CLK / 2)
18
19#include <asm/m52xxacr.h>
20
21/*
22 * The 525x has a second MBAR region, define its address.
23 */
24#define MCF_MBAR2 0x80000000
25
26/*
27 * Define the 525x SIM register set addresses.
28 */
29#define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */
30#define MCFSIM_SYPCR 0x01 /* System Protection reg (r/w)*/
31#define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */
32#define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */
33#define MCFSIM_MPARK 0x0C /* BUS Master Control Reg*/
34#define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */
35#define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */
36#define MCFSIM_ICR0 0x4c /* Intr Ctrl reg 0 (r/w) */
37#define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */
38#define MCFSIM_ICR2 0x4e /* Intr Ctrl reg 2 (r/w) */
39#define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */
40#define MCFSIM_ICR4 0x50 /* Intr Ctrl reg 4 (r/w) */
41#define MCFSIM_ICR5 0x51 /* Intr Ctrl reg 5 (r/w) */
42#define MCFSIM_ICR6 0x52 /* Intr Ctrl reg 6 (r/w) */
43#define MCFSIM_ICR7 0x53 /* Intr Ctrl reg 7 (r/w) */
44#define MCFSIM_ICR8 0x54 /* Intr Ctrl reg 8 (r/w) */
45#define MCFSIM_ICR9 0x55 /* Intr Ctrl reg 9 (r/w) */
46#define MCFSIM_ICR10 0x56 /* Intr Ctrl reg 10 (r/w) */
47#define MCFSIM_ICR11 0x57 /* Intr Ctrl reg 11 (r/w) */
48
49#define MCFSIM_CSAR0 0x80 /* CS 0 Address 0 reg (r/w) */
50#define MCFSIM_CSMR0 0x84 /* CS 0 Mask 0 reg (r/w) */
51#define MCFSIM_CSCR0 0x8a /* CS 0 Control reg (r/w) */
52#define MCFSIM_CSAR1 0x8c /* CS 1 Address reg (r/w) */
53#define MCFSIM_CSMR1 0x90 /* CS 1 Mask reg (r/w) */
54#define MCFSIM_CSCR1 0x96 /* CS 1 Control reg (r/w) */
55#define MCFSIM_CSAR2 0x98 /* CS 2 Address reg (r/w) */
56#define MCFSIM_CSMR2 0x9c /* CS 2 Mask reg (r/w) */
57#define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */
58#define MCFSIM_CSAR3 0xa4 /* CS 3 Address reg (r/w) */
59#define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */
60#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */
61#define MCFSIM_CSAR4 0xb0 /* CS 4 Address reg (r/w) */
62#define MCFSIM_CSMR4 0xb4 /* CS 4 Mask reg (r/w) */
63#define MCFSIM_CSCR4 0xba /* CS 4 Control reg (r/w) */
64
65#define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */
66#define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM 0 Addr/Ctrl */
67#define MCFSIM_DMR0 (MCF_MBAR + 0x10c) /* DRAM 0 Mask */
68
69/*
70 * Secondary Interrupt Controller (in MBAR2)
71*/
72#define MCFINTC2_INTBASE (MCF_MBAR2 + 0x168) /* Base Vector Reg */
73#define MCFINTC2_INTPRI1 (MCF_MBAR2 + 0x140) /* 0-7 priority */
74#define MCFINTC2_INTPRI2 (MCF_MBAR2 + 0x144) /* 8-15 priority */
75#define MCFINTC2_INTPRI3 (MCF_MBAR2 + 0x148) /* 16-23 priority */
76#define MCFINTC2_INTPRI4 (MCF_MBAR2 + 0x14c) /* 24-31 priority */
77#define MCFINTC2_INTPRI5 (MCF_MBAR2 + 0x150) /* 32-39 priority */
78#define MCFINTC2_INTPRI6 (MCF_MBAR2 + 0x154) /* 40-47 priority */
79#define MCFINTC2_INTPRI7 (MCF_MBAR2 + 0x158) /* 48-55 priority */
80#define MCFINTC2_INTPRI8 (MCF_MBAR2 + 0x15c) /* 56-63 priority */
81
82#define MCFINTC2_INTPRI_REG(i) (MCFINTC2_INTPRI1 + \
83 ((((i) - MCFINTC2_VECBASE) / 8) * 4))
84#define MCFINTC2_INTPRI_BITS(b, i) ((b) << (((i) % 8) * 4))
85
86/*
87 * Timer module.
88 */
89#define MCFTIMER_BASE1 (MCF_MBAR + 0x140) /* Base of TIMER1 */
90#define MCFTIMER_BASE2 (MCF_MBAR + 0x180) /* Base of TIMER2 */
91
92/*
93 * UART module.
94 */
95#define MCFUART_BASE0 (MCF_MBAR + 0x1c0) /* Base address UART0 */
96#define MCFUART_BASE1 (MCF_MBAR + 0x200) /* Base address UART1 */
97
98/*
99 * QSPI module.
100 */
101#define MCFQSPI_BASE (MCF_MBAR + 0x300) /* Base address QSPI */
102#define MCFQSPI_SIZE 0x40 /* Register set size */
103
104
105#define MCFQSPI_CS0 15
106#define MCFQSPI_CS1 16
107#define MCFQSPI_CS2 24
108#define MCFQSPI_CS3 28
109
110/*
111 * I2C module.
112 */
113#define MCFI2C_BASE0 (MCF_MBAR + 0x280) /* Base addreess I2C0 */
114#define MCFI2C_SIZE0 0x20 /* Register set size */
115
116#define MCFI2C_BASE1 (MCF_MBAR2 + 0x440) /* Base addreess I2C1 */
117#define MCFI2C_SIZE1 0x20 /* Register set size */
118/*
119 * DMA unit base addresses.
120 */
121#define MCFDMA_BASE0 (MCF_MBAR + 0x300) /* Base address DMA 0 */
122#define MCFDMA_BASE1 (MCF_MBAR + 0x340) /* Base address DMA 1 */
123#define MCFDMA_BASE2 (MCF_MBAR + 0x380) /* Base address DMA 2 */
124#define MCFDMA_BASE3 (MCF_MBAR + 0x3C0) /* Base address DMA 3 */
125
126/*
127 * Some symbol defines for the above...
128 */
129#define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */
130#define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */
131#define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */
132#define MCFSIM_I2CICR MCFSIM_ICR3 /* I2C ICR */
133#define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */
134#define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */
135#define MCFSIM_DMA0ICR MCFSIM_ICR6 /* DMA 0 ICR */
136#define MCFSIM_DMA1ICR MCFSIM_ICR7 /* DMA 1 ICR */
137#define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */
138#define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */
139#define MCFSIM_QSPIICR MCFSIM_ICR10 /* QSPI ICR */
140
141/*
142 * Define system peripheral IRQ usage.
143 */
144#define MCF_IRQ_QSPI 28 /* QSPI, Level 4 */
145#define MCF_IRQ_I2C0 29
146#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */
147#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */
148
149#define MCF_IRQ_UART0 73 /* UART0 */
150#define MCF_IRQ_UART1 74 /* UART1 */
151
152/*
153 * Define the base interrupt for the second interrupt controller.
154 * We set it to 128, out of the way of the base interrupts, and plenty
155 * of room for its 64 interrupts.
156 */
157#define MCFINTC2_VECBASE 128
158
159#define MCF_IRQ_GPIO0 (MCFINTC2_VECBASE + 32)
160#define MCF_IRQ_GPIO1 (MCFINTC2_VECBASE + 33)
161#define MCF_IRQ_GPIO2 (MCFINTC2_VECBASE + 34)
162#define MCF_IRQ_GPIO3 (MCFINTC2_VECBASE + 35)
163#define MCF_IRQ_GPIO4 (MCFINTC2_VECBASE + 36)
164#define MCF_IRQ_GPIO5 (MCFINTC2_VECBASE + 37)
165#define MCF_IRQ_GPIO6 (MCFINTC2_VECBASE + 38)
166
167#define MCF_IRQ_USBWUP (MCFINTC2_VECBASE + 40)
168#define MCF_IRQ_I2C1 (MCFINTC2_VECBASE + 62)
169
170/*
171 * General purpose IO registers (in MBAR2).
172 */
173#define MCFSIM2_GPIOREAD (MCF_MBAR2 + 0x000) /* GPIO read values */
174#define MCFSIM2_GPIOWRITE (MCF_MBAR2 + 0x004) /* GPIO write values */
175#define MCFSIM2_GPIOENABLE (MCF_MBAR2 + 0x008) /* GPIO enabled */
176#define MCFSIM2_GPIOFUNC (MCF_MBAR2 + 0x00C) /* GPIO function */
177#define MCFSIM2_GPIO1READ (MCF_MBAR2 + 0x0B0) /* GPIO1 read values */
178#define MCFSIM2_GPIO1WRITE (MCF_MBAR2 + 0x0B4) /* GPIO1 write values */
179#define MCFSIM2_GPIO1ENABLE (MCF_MBAR2 + 0x0B8) /* GPIO1 enabled */
180#define MCFSIM2_GPIO1FUNC (MCF_MBAR2 + 0x0BC) /* GPIO1 function */
181
182#define MCFSIM2_GPIOINTSTAT (MCF_MBAR2 + 0xc0) /* GPIO intr status */
183#define MCFSIM2_GPIOINTCLEAR (MCF_MBAR2 + 0xc0) /* GPIO intr clear */
184#define MCFSIM2_GPIOINTENABLE (MCF_MBAR2 + 0xc4) /* GPIO intr enable */
185
186/*
187 * Generic GPIO support
188 */
189#define MCFGPIO_PIN_MAX 64
190#define MCFGPIO_IRQ_MAX 7
191#define MCFGPIO_IRQ_VECBASE MCF_IRQ_GPIO0
192
193/****************************************************************************/
194#endif /* m525xsim_h */
diff --git a/arch/m68k/include/asm/m527xsim.h b/arch/m68k/include/asm/m527xsim.h
index 83db8106f50a..71aa5104d3d6 100644
--- a/arch/m68k/include/asm/m527xsim.h
+++ b/arch/m68k/include/asm/m527xsim.h
@@ -60,6 +60,7 @@
60#define MCF_IRQ_FECENTC1 (MCFINT2_VECBASE + MCFINT2_FECENTC1) 60#define MCF_IRQ_FECENTC1 (MCFINT2_VECBASE + MCFINT2_FECENTC1)
61 61
62#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI) 62#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
63#define MCF_IRQ_PIT1 (MCFINT_VECBASE + MCFINT_PIT1)
63 64
64/* 65/*
65 * SDRAM configuration registers. 66 * SDRAM configuration registers.
diff --git a/arch/m68k/include/asm/m528xsim.h b/arch/m68k/include/asm/m528xsim.h
index 497c31c803ff..4acb3c0a642e 100644
--- a/arch/m68k/include/asm/m528xsim.h
+++ b/arch/m68k/include/asm/m528xsim.h
@@ -52,7 +52,7 @@
52#define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0) 52#define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0)
53 53
54#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI) 54#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
55 55#define MCF_IRQ_PIT1 (MCFINT_VECBASE + MCFINT_PIT1)
56/* 56/*
57 * SDRAM configuration registers. 57 * SDRAM configuration registers.
58 */ 58 */
diff --git a/arch/m68k/include/asm/m532xsim.h b/arch/m68k/include/asm/m532xsim.h
index 29b66e21413a..5ca7b298c6eb 100644
--- a/arch/m68k/include/asm/m532xsim.h
+++ b/arch/m68k/include/asm/m532xsim.h
@@ -82,6 +82,9 @@
82#define MCFINTC1_SIMR 0xFC04C01C 82#define MCFINTC1_SIMR 0xFC04C01C
83#define MCFINTC1_CIMR 0xFC04C01D 83#define MCFINTC1_CIMR 0xFC04C01D
84#define MCFINTC1_ICR0 0xFC04C040 84#define MCFINTC1_ICR0 0xFC04C040
85#define MCFINTC2_SIMR (0)
86#define MCFINTC2_CIMR (0)
87#define MCFINTC2_ICR0 (0)
85 88
86#define MCFSIM_ICR_TIMER1 (0xFC048040+32) 89#define MCFSIM_ICR_TIMER1 (0xFC048040+32)
87#define MCFSIM_ICR_TIMER2 (0xFC048040+33) 90#define MCFSIM_ICR_TIMER2 (0xFC048040+33)
@@ -135,6 +138,20 @@
135#define MCF_RCR_SWRESET 0x80 /* Software reset bit */ 138#define MCF_RCR_SWRESET 0x80 /* Software reset bit */
136#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */ 139#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */
137 140
141
142/*
143 * Power Management
144 */
145#define MCFPM_WCR 0xfc040013
146#define MCFPM_PPMSR0 0xfc04002c
147#define MCFPM_PPMCR0 0xfc04002d
148#define MCFPM_PPMSR1 0xfc04002e
149#define MCFPM_PPMCR1 0xfc04002f
150#define MCFPM_PPMHR0 0xfc040030
151#define MCFPM_PPMLR0 0xfc040034
152#define MCFPM_PPMHR1 0xfc040038
153#define MCFPM_LPCR 0xec090007
154
138/********************************************************************* 155/*********************************************************************
139 * 156 *
140 * Inter-IC (I2C) Module 157 * Inter-IC (I2C) Module
diff --git a/arch/m68k/include/asm/m5441xsim.h b/arch/m68k/include/asm/m5441xsim.h
new file mode 100644
index 000000000000..cc798ab9524b
--- /dev/null
+++ b/arch/m68k/include/asm/m5441xsim.h
@@ -0,0 +1,276 @@
1/*
2 * m5441xsim.h -- Coldfire 5441x register definitions
3 *
4 * (C) Copyright 2012, Steven King <sfking@fdwdc.com>
5*/
6
7#ifndef m5441xsim_h
8#define m5441xsim_h
9
10#define CPU_NAME "COLDFIRE(m5441x)"
11#define CPU_INSTR_PER_JIFFY 2
12#define MCF_BUSCLK (MCF_CLK / 2)
13
14#include <asm/m54xxacr.h>
15
16/*
17 * Reset Controller Module.
18 */
19
20#define MCF_RCR 0xec090000
21#define MCF_RSR 0xec090001
22
23#define MCF_RCR_SWRESET 0x80 /* Software reset bit */
24#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */
25
26/*
27 * Interrupt Controller Modules.
28 */
29/* the 5441x have 3 interrupt controllers, each control 64 interrupts */
30#define MCFINT_VECBASE 64
31#define MCFINT0_VECBASE MCFINT_VECBASE
32#define MCFINT1_VECBASE (MCFINT0_VECBASE + 64)
33#define MCFINT2_VECBASE (MCFINT1_VECBASE + 64)
34
35/* interrupt controller 0 */
36#define MCFINTC0_SIMR 0xfc04801c
37#define MCFINTC0_CIMR 0xfc04801d
38#define MCFINTC0_ICR0 0xfc048040
39/* interrupt controller 1 */
40#define MCFINTC1_SIMR 0xfc04c01c
41#define MCFINTC1_CIMR 0xfc04c01d
42#define MCFINTC1_ICR0 0xfc04c040
43/* interrupt controller 2 */
44#define MCFINTC2_SIMR 0xfc05001c
45#define MCFINTC2_CIMR 0xfc05001d
46#define MCFINTC2_ICR0 0xfc050040
47
48/* on interrupt controller 0 */
49#define MCFINT0_EPORT0 1
50#define MCFINT0_UART0 26
51#define MCFINT0_UART1 27
52#define MCFINT0_UART2 28
53#define MCFINT0_UART3 29
54#define MCFINT0_I2C0 30
55#define MCFINT0_DSPI0 31
56
57#define MCFINT0_TIMER0 32
58#define MCFINT0_TIMER1 33
59#define MCFINT0_TIMER2 34
60#define MCFINT0_TIMER3 35
61
62#define MCFINT0_FECRX0 36
63#define MCFINT0_FECTX0 40
64#define MCFINT0_FECENTC0 42
65
66#define MCFINT0_FECRX1 49
67#define MCFINT0_FECTX1 53
68#define MCFINT0_FECENTC1 55
69
70/* on interrupt controller 1 */
71#define MCFINT1_UART4 48
72#define MCFINT1_UART5 49
73#define MCFINT1_UART6 50
74#define MCFINT1_UART7 51
75#define MCFINT1_UART8 52
76#define MCFINT1_UART9 53
77#define MCFINT1_DSPI1 54
78#define MCFINT1_DSPI2 55
79#define MCFINT1_DSPI3 56
80#define MCFINT1_I2C1 57
81#define MCFINT1_I2C2 58
82#define MCFINT1_I2C3 59
83#define MCFINT1_I2C4 60
84#define MCFINT1_I2C5 61
85
86/* on interrupt controller 2 */
87#define MCFINT2_PIT0 13
88#define MCFINT2_PIT1 14
89#define MCFINT2_PIT2 15
90#define MCFINT2_PIT3 16
91#define MCFINT2_RTC 26
92
93/*
94 * PIT timer module.
95 */
96#define MCFPIT_BASE0 0xFC080000 /* Base address of TIMER0 */
97#define MCFPIT_BASE1 0xFC084000 /* Base address of TIMER1 */
98#define MCFPIT_BASE2 0xFC088000 /* Base address of TIMER2 */
99#define MCFPIT_BASE3 0xFC08C000 /* Base address of TIMER3 */
100
101
102#define MCF_IRQ_PIT1 (MCFINT2_VECBASE + MCFINT2_PIT1)
103
104/*
105 * Power Management
106 */
107#define MCFPM_WCR 0xfc040013
108#define MCFPM_PPMSR0 0xfc04002c
109#define MCFPM_PPMCR0 0xfc04002d
110#define MCFPM_PPMSR1 0xfc04002e
111#define MCFPM_PPMCR1 0xfc04002f
112#define MCFPM_PPMHR0 0xfc040030
113#define MCFPM_PPMLR0 0xfc040034
114#define MCFPM_PPMHR1 0xfc040038
115#define MCFPM_PPMLR1 0xfc04003c
116#define MCFPM_LPCR 0xec090007
117/*
118 * UART module.
119 */
120#define MCFUART_BASE0 0xfc060000 /* Base address of UART0 */
121#define MCFUART_BASE1 0xfc064000 /* Base address of UART1 */
122#define MCFUART_BASE2 0xfc068000 /* Base address of UART2 */
123#define MCFUART_BASE3 0xfc06c000 /* Base address of UART3 */
124#define MCFUART_BASE4 0xec060000 /* Base address of UART4 */
125#define MCFUART_BASE5 0xec064000 /* Base address of UART5 */
126#define MCFUART_BASE6 0xec068000 /* Base address of UART6 */
127#define MCFUART_BASE7 0xec06c000 /* Base address of UART7 */
128#define MCFUART_BASE8 0xec070000 /* Base address of UART8 */
129#define MCFUART_BASE9 0xec074000 /* Base address of UART9 */
130
131#define MCF_IRQ_UART0 (MCFINT0_VECBASE + MCFINT0_UART0)
132#define MCF_IRQ_UART1 (MCFINT0_VECBASE + MCFINT0_UART1)
133#define MCF_IRQ_UART2 (MCFINT0_VECBASE + MCFINT0_UART2)
134#define MCF_IRQ_UART3 (MCFINT0_VECBASE + MCFINT0_UART3)
135#define MCF_IRQ_UART4 (MCFINT1_VECBASE + MCFINT1_UART4)
136#define MCF_IRQ_UART5 (MCFINT1_VECBASE + MCFINT1_UART5)
137#define MCF_IRQ_UART6 (MCFINT1_VECBASE + MCFINT1_UART6)
138#define MCF_IRQ_UART7 (MCFINT1_VECBASE + MCFINT1_UART7)
139#define MCF_IRQ_UART8 (MCFINT1_VECBASE + MCFINT1_UART8)
140#define MCF_IRQ_UART9 (MCFINT1_VECBASE + MCFINT1_UART9)
141/*
142 * FEC modules.
143 */
144#define MCFFEC_BASE0 0xfc0d4000
145#define MCFFEC_SIZE0 0x800
146#define MCF_IRQ_FECRX0 (MCFINT0_VECBASE + MCFINT0_FECRX0)
147#define MCF_IRQ_FECTX0 (MCFINT0_VECBASE + MCFINT0_FECTX0)
148#define MCF_IRQ_FECENTC0 (MCFINT0_VECBASE + MCFINT0_FECENTC0)
149
150#define MCFFEC_BASE1 0xfc0d8000
151#define MCFFEC_SIZE1 0x800
152#define MCF_IRQ_FECRX1 (MCFINT0_VECBASE + MCFINT0_FECRX1)
153#define MCF_IRQ_FECTX1 (MCFINT0_VECBASE + MCFINT0_FECTX1)
154#define MCF_IRQ_FECENTC1 (MCFINT0_VECBASE + MCFINT0_FECENTC1)
155/*
156 * I2C modules.
157 */
158#define MCFI2C_BASE0 0xfc058000
159#define MCFI2C_SIZE0 0x20
160#define MCFI2C_BASE1 0xfc038000
161#define MCFI2C_SIZE1 0x20
162#define MCFI2C_BASE2 0xec010000
163#define MCFI2C_SIZE2 0x20
164#define MCFI2C_BASE3 0xec014000
165#define MCFI2C_SIZE3 0x20
166#define MCFI2C_BASE4 0xec018000
167#define MCFI2C_SIZE4 0x20
168#define MCFI2C_BASE5 0xec01c000
169#define MCFI2C_SIZE5 0x20
170
171#define MCF_IRQ_I2C0 (MCFINT0_VECBASE + MCFINT0_I2C0)
172#define MCF_IRQ_I2C1 (MCFINT1_VECBASE + MCFINT1_I2C1)
173#define MCF_IRQ_I2C2 (MCFINT1_VECBASE + MCFINT1_I2C2)
174#define MCF_IRQ_I2C3 (MCFINT1_VECBASE + MCFINT1_I2C3)
175#define MCF_IRQ_I2C4 (MCFINT1_VECBASE + MCFINT1_I2C4)
176#define MCF_IRQ_I2C5 (MCFINT1_VECBASE + MCFINT1_I2C5)
177/*
178 * EPORT Module.
179 */
180#define MCFEPORT_EPPAR 0xfc090000
181#define MCFEPORT_EPIER 0xfc090003
182#define MCFEPORT_EPFR 0xfc090006
183/*
184 * RTC Module.
185 */
186#define MCFRTC_BASE 0xfc0a8000
187#define MCFRTC_SIZE (0xfc0a8840 - 0xfc0a8000)
188#define MCF_IRQ_RTC (MCFINT2_VECBASE + MCFINT2_RTC)
189
190/*
191 * GPIO Module.
192 */
193#define MCFGPIO_PODR_A 0xec094000
194#define MCFGPIO_PODR_B 0xec094001
195#define MCFGPIO_PODR_C 0xec094002
196#define MCFGPIO_PODR_D 0xec094003
197#define MCFGPIO_PODR_E 0xec094004
198#define MCFGPIO_PODR_F 0xec094005
199#define MCFGPIO_PODR_G 0xec094006
200#define MCFGPIO_PODR_H 0xec094007
201#define MCFGPIO_PODR_I 0xec094008
202#define MCFGPIO_PODR_J 0xec094009
203#define MCFGPIO_PODR_K 0xec09400a
204
205#define MCFGPIO_PDDR_A 0xec09400c
206#define MCFGPIO_PDDR_B 0xec09400d
207#define MCFGPIO_PDDR_C 0xec09400e
208#define MCFGPIO_PDDR_D 0xec09400f
209#define MCFGPIO_PDDR_E 0xec094010
210#define MCFGPIO_PDDR_F 0xec094011
211#define MCFGPIO_PDDR_G 0xec094012
212#define MCFGPIO_PDDR_H 0xec094013
213#define MCFGPIO_PDDR_I 0xec094014
214#define MCFGPIO_PDDR_J 0xec094015
215#define MCFGPIO_PDDR_K 0xec094016
216
217#define MCFGPIO_PPDSDR_A 0xec094018
218#define MCFGPIO_PPDSDR_B 0xec094019
219#define MCFGPIO_PPDSDR_C 0xec09401a
220#define MCFGPIO_PPDSDR_D 0xec09401b
221#define MCFGPIO_PPDSDR_E 0xec09401c
222#define MCFGPIO_PPDSDR_F 0xec09401d
223#define MCFGPIO_PPDSDR_G 0xec09401e
224#define MCFGPIO_PPDSDR_H 0xec09401f
225#define MCFGPIO_PPDSDR_I 0xec094020
226#define MCFGPIO_PPDSDR_J 0xec094021
227#define MCFGPIO_PPDSDR_K 0xec094022
228
229#define MCFGPIO_PCLRR_A 0xec094024
230#define MCFGPIO_PCLRR_B 0xec094025
231#define MCFGPIO_PCLRR_C 0xec094026
232#define MCFGPIO_PCLRR_D 0xec094027
233#define MCFGPIO_PCLRR_E 0xec094028
234#define MCFGPIO_PCLRR_F 0xec094029
235#define MCFGPIO_PCLRR_G 0xec09402a
236#define MCFGPIO_PCLRR_H 0xec09402b
237#define MCFGPIO_PCLRR_I 0xec09402c
238#define MCFGPIO_PCLRR_J 0xec09402d
239#define MCFGPIO_PCLRR_K 0xec09402e
240
241#define MCFGPIO_PAR_FBCTL 0xec094048
242#define MCFGPIO_PAR_BE 0xec094049
243#define MCFGPIO_PAR_CS 0xec09404a
244#define MCFGPIO_PAR_CANI2C 0xec09404b
245#define MCFGPIO_PAR_IRQ0H 0xec09404c
246#define MCFGPIO_PAR_IRQ0L 0xec09404d
247#define MCFGPIO_PAR_DSPIOWH 0xec09404e
248#define MCFGPIO_PAR_DSPIOWL 0xec09404f
249#define MCFGPIO_PAR_TIMER 0xec094050
250#define MCFGPIO_PAR_UART2 0xec094051
251#define MCFGPIO_PAR_UART1 0xec094052
252#define MCFGPIO_PAR_UART0 0xec094053
253#define MCFGPIO_PAR_SDHCH 0xec094054
254#define MCFGPIO_PAR_SDHCL 0xec094055
255#define MCFGPIO_PAR_SIMP0H 0xec094056
256#define MCFGPIO_PAR_SIMP0L 0xec094057
257#define MCFGPIO_PAR_SSI0H 0xec094058
258#define MCFGPIO_PAR_SSI0L 0xec094059
259#define MCFGPIO_PAR_DEBUGH1 0xec09405a
260#define MCFGPIO_PAR_DEBUGH0 0xec09405b
261#define MCFGPIO_PAR_DEBUGl 0xec09405c
262#define MCFGPIO_PAR_FEC 0xec09405e
263
264/* generalization for generic gpio support */
265#define MCFGPIO_PODR MCFGPIO_PODR_A
266#define MCFGPIO_PDDR MCFGPIO_PDDR_A
267#define MCFGPIO_PPDR MCFGPIO_PPDSDR_A
268#define MCFGPIO_SETR MCFGPIO_PPDSDR_A
269#define MCFGPIO_CLRR MCFGPIO_PCLRR_A
270
271#define MCFGPIO_IRQ_MIN 17
272#define MCFGPIO_IRQ_MAX 24
273#define MCFGPIO_IRQ_VECBASE (MCFINT_VECBASE - MCFGPIO_IRQ_MIN)
274#define MCFGPIO_PIN_MAX 87
275
276#endif /* m5441xsim_h */
diff --git a/arch/m68k/include/asm/m54xxacr.h b/arch/m68k/include/asm/m54xxacr.h
index 47906aafbf67..192bbfeabf70 100644
--- a/arch/m68k/include/asm/m54xxacr.h
+++ b/arch/m68k/include/asm/m54xxacr.h
@@ -55,6 +55,10 @@
55#define ICACHE_SIZE 0x8000 /* instruction - 32k */ 55#define ICACHE_SIZE 0x8000 /* instruction - 32k */
56#define DCACHE_SIZE 0x8000 /* data - 32k */ 56#define DCACHE_SIZE 0x8000 /* data - 32k */
57 57
58#elif defined(CONFIG_M5441x)
59
60#define ICACHE_SIZE 0x2000 /* instruction - 8k */
61#define DCACHE_SIZE 0x2000 /* data - 8k */
58#endif 62#endif
59 63
60#define CACHE_LINE_SIZE 0x0010 /* 16 bytes */ 64#define CACHE_LINE_SIZE 0x0010 /* 16 bytes */
diff --git a/arch/m68k/include/asm/m54xxpci.h b/arch/m68k/include/asm/m54xxpci.h
new file mode 100644
index 000000000000..6fbf54f72f2e
--- /dev/null
+++ b/arch/m68k/include/asm/m54xxpci.h
@@ -0,0 +1,138 @@
1/****************************************************************************/
2
3/*
4 * m54xxpci.h -- ColdFire 547x and 548x PCI bus support
5 *
6 * (C) Copyright 2011, Greg Ungerer <gerg@uclinux.org>
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file COPYING in the main directory of this archive
10 * for more details.
11 */
12
13/****************************************************************************/
14#ifndef M54XXPCI_H
15#define M54XXPCI_H
16/****************************************************************************/
17
18/*
19 * The core set of PCI support registers are mapped into the MBAR region.
20 */
21#define PCIIDR (CONFIG_MBAR + 0xb00) /* PCI device/vendor ID */
22#define PCISCR (CONFIG_MBAR + 0xb04) /* PCI status/command */
23#define PCICCRIR (CONFIG_MBAR + 0xb08) /* PCI class/revision */
24#define PCICR1 (CONFIG_MBAR + 0xb0c) /* PCI configuration 1 */
25#define PCIBAR0 (CONFIG_MBAR + 0xb10) /* PCI base address 0 */
26#define PCIBAR1 (CONFIG_MBAR + 0xb14) /* PCI base address 1 */
27#define PCICCPR (CONFIG_MBAR + 0xb28) /* PCI cardbus CIS pointer */
28#define PCISID (CONFIG_MBAR + 0xb2c) /* PCI subsystem IDs */
29#define PCIERBAR (CONFIG_MBAR + 0xb30) /* PCI expansion ROM */
30#define PCICPR (CONFIG_MBAR + 0xb34) /* PCI capabilities pointer */
31#define PCICR2 (CONFIG_MBAR + 0xb3c) /* PCI configuration 2 */
32
33#define PCIGSCR (CONFIG_MBAR + 0xb60) /* Global status/control */
34#define PCITBATR0 (CONFIG_MBAR + 0xb64) /* Target base translation 0 */
35#define PCITBATR1 (CONFIG_MBAR + 0xb68) /* Target base translation 1 */
36#define PCITCR (CONFIG_MBAR + 0xb6c) /* Target control */
37#define PCIIW0BTAR (CONFIG_MBAR + 0xb70) /* Initiator window 0 */
38#define PCIIW1BTAR (CONFIG_MBAR + 0xb74) /* Initiator window 1 */
39#define PCIIW2BTAR (CONFIG_MBAR + 0xb78) /* Initiator window 2 */
40#define PCIIWCR (CONFIG_MBAR + 0xb80) /* Initiator window config */
41#define PCIICR (CONFIG_MBAR + 0xb84) /* Initiator control */
42#define PCIISR (CONFIG_MBAR + 0xb88) /* Initiator status */
43#define PCICAR (CONFIG_MBAR + 0xbf8) /* Configuration address */
44
45#define PCITPSR (CONFIG_MBAR + 0x8400) /* TX packet size */
46#define PCITSAR (CONFIG_MBAR + 0x8404) /* TX start address */
47#define PCITTCR (CONFIG_MBAR + 0x8408) /* TX transaction control */
48#define PCITER (CONFIG_MBAR + 0x840c) /* TX enables */
49#define PCITNAR (CONFIG_MBAR + 0x8410) /* TX next address */
50#define PCITLWR (CONFIG_MBAR + 0x8414) /* TX last word */
51#define PCITDCR (CONFIG_MBAR + 0x8418) /* TX done counts */
52#define PCITSR (CONFIG_MBAR + 0x841c) /* TX status */
53#define PCITFDR (CONFIG_MBAR + 0x8440) /* TX FIFO data */
54#define PCITFSR (CONFIG_MBAR + 0x8444) /* TX FIFO status */
55#define PCITFCR (CONFIG_MBAR + 0x8448) /* TX FIFO control */
56#define PCITFAR (CONFIG_MBAR + 0x844c) /* TX FIFO alarm */
57#define PCITFRPR (CONFIG_MBAR + 0x8450) /* TX FIFO read pointer */
58#define PCITFWPR (CONFIG_MBAR + 0x8454) /* TX FIFO write pointer */
59
60#define PCIRPSR (CONFIG_MBAR + 0x8480) /* RX packet size */
61#define PCIRSAR (CONFIG_MBAR + 0x8484) /* RX start address */
62#define PCIRTCR (CONFIG_MBAR + 0x8488) /* RX transaction control */
63#define PCIRER (CONFIG_MBAR + 0x848c) /* RX enables */
64#define PCIRNAR (CONFIG_MBAR + 0x8490) /* RX next address */
65#define PCIRDCR (CONFIG_MBAR + 0x8498) /* RX done counts */
66#define PCIRSR (CONFIG_MBAR + 0x849c) /* RX status */
67#define PCIRFDR (CONFIG_MBAR + 0x84c0) /* RX FIFO data */
68#define PCIRFSR (CONFIG_MBAR + 0x84c4) /* RX FIFO status */
69#define PCIRFCR (CONFIG_MBAR + 0x84c8) /* RX FIFO control */
70#define PCIRFAR (CONFIG_MBAR + 0x84cc) /* RX FIFO alarm */
71#define PCIRFRPR (CONFIG_MBAR + 0x84d0) /* RX FIFO read pointer */
72#define PCIRFWPR (CONFIG_MBAR + 0x84d4) /* RX FIFO write pointer */
73
74#define PACR (CONFIG_MBAR + 0xc00) /* PCI arbiter control */
75#define PASR (COFNIG_MBAR + 0xc04) /* PCI arbiter status */
76
77/*
78 * Definitions for the Global status and control register.
79 */
80#define PCIGSCR_PE 0x20000000 /* Parity error detected */
81#define PCIGSCR_SE 0x10000000 /* System error detected */
82#define PCIGSCR_XCLKBIN 0x07000000 /* XLB2CLKIN mask */
83#define PCIGSCR_PEE 0x00002000 /* Parity error intr enable */
84#define PCIGSCR_SEE 0x00001000 /* System error intr enable */
85#define PCIGSCR_RESET 0x00000001 /* Reset bit */
86
87/*
88 * Bit definitions for the PCICAR configuration address register.
89 */
90#define PCICAR_E 0x80000000 /* Enable config space */
91#define PCICAR_BUSN 16 /* Move bus bits */
92#define PCICAR_DEVFNN 8 /* Move devfn bits */
93#define PCICAR_DWORDN 0 /* Move dword bits */
94
95/*
96 * The initiator windows hold the memory and IO mapping information.
97 * This macro creates the register values from the desired addresses.
98 */
99#define WXBTAR(hostaddr, pciaddr, size) \
100 (((hostaddr) & 0xff000000) | \
101 ((((size) - 1) & 0xff000000) >> 8) | \
102 (((pciaddr) & 0xff000000) >> 16))
103
104#define PCIIWCR_W0_MEM 0x00000000 /* Window 0 is memory */
105#define PCIIWCR_W0_IO 0x08000000 /* Window 0 is IO */
106#define PCIIWCR_W0_MRD 0x00000000 /* Window 0 memory read */
107#define PCIIWCR_W0_MRDL 0x02000000 /* Window 0 memory read line */
108#define PCIIWCR_W0_MRDM 0x04000000 /* Window 0 memory read mult */
109#define PCIIWCR_W0_E 0x01000000 /* Window 0 enable */
110
111#define PCIIWCR_W1_MEM 0x00000000 /* Window 0 is memory */
112#define PCIIWCR_W1_IO 0x00080000 /* Window 0 is IO */
113#define PCIIWCR_W1_MRD 0x00000000 /* Window 0 memory read */
114#define PCIIWCR_W1_MRDL 0x00020000 /* Window 0 memory read line */
115#define PCIIWCR_W1_MRDM 0x00040000 /* Window 0 memory read mult */
116#define PCIIWCR_W1_E 0x00010000 /* Window 0 enable */
117
118/*
119 * Bit definitions for the PCIBATR registers.
120 */
121#define PCITBATR0_E 0x00000001 /* Enable window 0 */
122#define PCITBATR1_E 0x00000001 /* Enable window 1 */
123
124/*
125 * PCI arbiter support definitions and macros.
126 */
127#define PACR_INTMPRI 0x00000001
128#define PACR_EXTMPRI(x) (((x) & 0x1f) << 1)
129#define PACR_INTMINTE 0x00010000
130#define PACR_EXTMINTE(x) (((x) & 0x1f) << 17)
131#define PACR_PKMD 0x40000000
132#define PACR_DS 0x80000000
133
134#define PCICR1_CL(x) ((x) & 0xf) /* Cacheline size field */
135#define PCICR1_LT(x) (((x) & 0xff) << 8) /* Latency timer field */
136
137/****************************************************************************/
138#endif /* M54XXPCI_H */
diff --git a/arch/m68k/include/asm/m54xxsim.h b/arch/m68k/include/asm/m54xxsim.h
index ae56b8848a9d..d3c5e0dbdadf 100644
--- a/arch/m68k/include/asm/m54xxsim.h
+++ b/arch/m68k/include/asm/m54xxsim.h
@@ -81,4 +81,7 @@
81#define MCF_PAR_PSC_RTS_RTS (0x30) 81#define MCF_PAR_PSC_RTS_RTS (0x30)
82#define MCF_PAR_PSC_CANRX (0x40) 82#define MCF_PAR_PSC_CANRX (0x40)
83 83
84#define MCF_PAR_PCIBG (CONFIG_MBAR + 0xa48) /* PCI bus grant */
85#define MCF_PAR_PCIBR (CONFIG_MBAR + 0xa4a) /* PCI */
86
84#endif /* m54xxsim_h */ 87#endif /* m54xxsim_h */
diff --git a/arch/m68k/include/asm/mcfne.h b/arch/m68k/include/asm/mcf8390.h
index bf638be0958c..a72a20819a54 100644
--- a/arch/m68k/include/asm/mcfne.h
+++ b/arch/m68k/include/asm/mcf8390.h
@@ -1,7 +1,7 @@
1/****************************************************************************/ 1/****************************************************************************/
2 2
3/* 3/*
4 * mcfne.h -- NE2000 in ColdFire eval boards. 4 * mcf8390.h -- NS8390 support for ColdFire eval boards.
5 * 5 *
6 * (C) Copyright 1999-2000, Greg Ungerer (gerg@snapgear.com) 6 * (C) Copyright 1999-2000, Greg Ungerer (gerg@snapgear.com)
7 * (C) Copyright 2000, Lineo (www.lineo.com) 7 * (C) Copyright 2000, Lineo (www.lineo.com)
@@ -14,8 +14,8 @@
14 */ 14 */
15 15
16/****************************************************************************/ 16/****************************************************************************/
17#ifndef mcfne_h 17#ifndef mcf8390_h
18#define mcfne_h 18#define mcf8390_h
19/****************************************************************************/ 19/****************************************************************************/
20 20
21 21
@@ -37,6 +37,7 @@
37#if defined(CONFIG_ARN5206) 37#if defined(CONFIG_ARN5206)
38#define NE2000_ADDR 0x40000300 38#define NE2000_ADDR 0x40000300
39#define NE2000_ODDOFFSET 0x00010000 39#define NE2000_ODDOFFSET 0x00010000
40#define NE2000_ADDRSIZE 0x00020000
40#define NE2000_IRQ_VECTOR 0xf0 41#define NE2000_IRQ_VECTOR 0xf0
41#define NE2000_IRQ_PRIORITY 2 42#define NE2000_IRQ_PRIORITY 2
42#define NE2000_IRQ_LEVEL 4 43#define NE2000_IRQ_LEVEL 4
@@ -46,6 +47,7 @@
46#if defined(CONFIG_M5206eC3) 47#if defined(CONFIG_M5206eC3)
47#define NE2000_ADDR 0x40000300 48#define NE2000_ADDR 0x40000300
48#define NE2000_ODDOFFSET 0x00010000 49#define NE2000_ODDOFFSET 0x00010000
50#define NE2000_ADDRSIZE 0x00020000
49#define NE2000_IRQ_VECTOR 0x1c 51#define NE2000_IRQ_VECTOR 0x1c
50#define NE2000_IRQ_PRIORITY 2 52#define NE2000_IRQ_PRIORITY 2
51#define NE2000_IRQ_LEVEL 4 53#define NE2000_IRQ_LEVEL 4
@@ -54,6 +56,7 @@
54 56
55#if defined(CONFIG_M5206e) && defined(CONFIG_NETtel) 57#if defined(CONFIG_M5206e) && defined(CONFIG_NETtel)
56#define NE2000_ADDR 0x30000300 58#define NE2000_ADDR 0x30000300
59#define NE2000_ADDRSIZE 0x00001000
57#define NE2000_IRQ_VECTOR 25 60#define NE2000_IRQ_VECTOR 25
58#define NE2000_IRQ_PRIORITY 1 61#define NE2000_IRQ_PRIORITY 1
59#define NE2000_IRQ_LEVEL 3 62#define NE2000_IRQ_LEVEL 3
@@ -63,6 +66,7 @@
63#if defined(CONFIG_M5307C3) 66#if defined(CONFIG_M5307C3)
64#define NE2000_ADDR 0x40000300 67#define NE2000_ADDR 0x40000300
65#define NE2000_ODDOFFSET 0x00010000 68#define NE2000_ODDOFFSET 0x00010000
69#define NE2000_ADDRSIZE 0x00020000
66#define NE2000_IRQ_VECTOR 0x1b 70#define NE2000_IRQ_VECTOR 0x1b
67#define NE2000_BYTE volatile unsigned short 71#define NE2000_BYTE volatile unsigned short
68#endif 72#endif
@@ -70,6 +74,7 @@
70#if defined(CONFIG_M5272) && defined(CONFIG_NETtel) 74#if defined(CONFIG_M5272) && defined(CONFIG_NETtel)
71#define NE2000_ADDR 0x30600300 75#define NE2000_ADDR 0x30600300
72#define NE2000_ODDOFFSET 0x00008000 76#define NE2000_ODDOFFSET 0x00008000
77#define NE2000_ADDRSIZE 0x00010000
73#define NE2000_IRQ_VECTOR 67 78#define NE2000_IRQ_VECTOR 67
74#undef BSWAP 79#undef BSWAP
75#define BSWAP(w) (w) 80#define BSWAP(w) (w)
@@ -82,6 +87,7 @@
82#define NE2000_ADDR0 0x30600300 87#define NE2000_ADDR0 0x30600300
83#define NE2000_ADDR1 0x30800300 88#define NE2000_ADDR1 0x30800300
84#define NE2000_ODDOFFSET 0x00008000 89#define NE2000_ODDOFFSET 0x00008000
90#define NE2000_ADDRSIZE 0x00010000
85#define NE2000_IRQ_VECTOR0 27 91#define NE2000_IRQ_VECTOR0 27
86#define NE2000_IRQ_VECTOR1 29 92#define NE2000_IRQ_VECTOR1 29
87#undef BSWAP 93#undef BSWAP
@@ -94,6 +100,7 @@
94#if defined(CONFIG_M5307) && defined(CONFIG_SECUREEDGEMP3) 100#if defined(CONFIG_M5307) && defined(CONFIG_SECUREEDGEMP3)
95#define NE2000_ADDR 0x30600300 101#define NE2000_ADDR 0x30600300
96#define NE2000_ODDOFFSET 0x00008000 102#define NE2000_ODDOFFSET 0x00008000
103#define NE2000_ADDRSIZE 0x00010000
97#define NE2000_IRQ_VECTOR 27 104#define NE2000_IRQ_VECTOR 27
98#undef BSWAP 105#undef BSWAP
99#define BSWAP(w) (w) 106#define BSWAP(w) (w)
@@ -105,6 +112,7 @@
105#if defined(CONFIG_ARN5307) 112#if defined(CONFIG_ARN5307)
106#define NE2000_ADDR 0xfe600300 113#define NE2000_ADDR 0xfe600300
107#define NE2000_ODDOFFSET 0x00010000 114#define NE2000_ODDOFFSET 0x00010000
115#define NE2000_ADDRSIZE 0x00020000
108#define NE2000_IRQ_VECTOR 0x1b 116#define NE2000_IRQ_VECTOR 0x1b
109#define NE2000_IRQ_PRIORITY 2 117#define NE2000_IRQ_PRIORITY 2
110#define NE2000_IRQ_LEVEL 3 118#define NE2000_IRQ_LEVEL 3
@@ -114,129 +122,10 @@
114#if defined(CONFIG_M5407C3) 122#if defined(CONFIG_M5407C3)
115#define NE2000_ADDR 0x40000300 123#define NE2000_ADDR 0x40000300
116#define NE2000_ODDOFFSET 0x00010000 124#define NE2000_ODDOFFSET 0x00010000
125#define NE2000_ADDRSIZE 0x00020000
117#define NE2000_IRQ_VECTOR 0x1b 126#define NE2000_IRQ_VECTOR 0x1b
118#define NE2000_BYTE volatile unsigned short 127#define NE2000_BYTE volatile unsigned short
119#endif 128#endif
120 129
121/****************************************************************************/ 130/****************************************************************************/
122 131#endif /* mcf8390_h */
123/*
124 * Side-band address space for odd address requires re-mapping
125 * many of the standard ISA access functions.
126 */
127#ifdef NE2000_ODDOFFSET
128
129#undef outb
130#undef outb_p
131#undef inb
132#undef inb_p
133#undef outsb
134#undef outsw
135#undef insb
136#undef insw
137
138#define outb ne2000_outb
139#define inb ne2000_inb
140#define outb_p ne2000_outb
141#define inb_p ne2000_inb
142#define outsb ne2000_outsb
143#define outsw ne2000_outsw
144#define insb ne2000_insb
145#define insw ne2000_insw
146
147
148#ifndef COLDFIRE_NE2000_FUNCS
149
150void ne2000_outb(unsigned int val, unsigned int addr);
151int ne2000_inb(unsigned int addr);
152void ne2000_insb(unsigned int addr, void *vbuf, int unsigned long len);
153void ne2000_insw(unsigned int addr, void *vbuf, unsigned long len);
154void ne2000_outsb(unsigned int addr, void *vbuf, unsigned long len);
155void ne2000_outsw(unsigned int addr, void *vbuf, unsigned long len);
156
157#else
158
159/*
160 * This macro converts a conventional register address into the
161 * real memory pointer of the mapped NE2000 device.
162 * On most NE2000 implementations on ColdFire boards the chip is
163 * mapped in kinda funny, due to its ISA heritage.
164 */
165#define NE2000_PTR(addr) ((addr&0x1)?(NE2000_ODDOFFSET+addr-1):(addr))
166#define NE2000_DATA_PTR(addr) (addr)
167
168
169void ne2000_outb(unsigned int val, unsigned int addr)
170{
171 NE2000_BYTE *rp;
172
173 rp = (NE2000_BYTE *) NE2000_PTR(addr);
174 *rp = RSWAP(val);
175}
176
177int ne2000_inb(unsigned int addr)
178{
179 NE2000_BYTE *rp, val;
180
181 rp = (NE2000_BYTE *) NE2000_PTR(addr);
182 val = *rp;
183 return((int) ((NE2000_BYTE) RSWAP(val)));
184}
185
186void ne2000_insb(unsigned int addr, void *vbuf, int unsigned long len)
187{
188 NE2000_BYTE *rp, val;
189 unsigned char *buf;
190
191 buf = (unsigned char *) vbuf;
192 rp = (NE2000_BYTE *) NE2000_DATA_PTR(addr);
193 for (; (len > 0); len--) {
194 val = *rp;
195 *buf++ = RSWAP(val);
196 }
197}
198
199void ne2000_insw(unsigned int addr, void *vbuf, unsigned long len)
200{
201 volatile unsigned short *rp;
202 unsigned short w, *buf;
203
204 buf = (unsigned short *) vbuf;
205 rp = (volatile unsigned short *) NE2000_DATA_PTR(addr);
206 for (; (len > 0); len--) {
207 w = *rp;
208 *buf++ = BSWAP(w);
209 }
210}
211
212void ne2000_outsb(unsigned int addr, const void *vbuf, unsigned long len)
213{
214 NE2000_BYTE *rp, val;
215 unsigned char *buf;
216
217 buf = (unsigned char *) vbuf;
218 rp = (NE2000_BYTE *) NE2000_DATA_PTR(addr);
219 for (; (len > 0); len--) {
220 val = *buf++;
221 *rp = RSWAP(val);
222 }
223}
224
225void ne2000_outsw(unsigned int addr, const void *vbuf, unsigned long len)
226{
227 volatile unsigned short *rp;
228 unsigned short w, *buf;
229
230 buf = (unsigned short *) vbuf;
231 rp = (volatile unsigned short *) NE2000_DATA_PTR(addr);
232 for (; (len > 0); len--) {
233 w = *buf++;
234 *rp = BSWAP(w);
235 }
236}
237
238#endif /* COLDFIRE_NE2000_FUNCS */
239#endif /* NE2000_OFFOFFSET */
240
241/****************************************************************************/
242#endif /* mcfne_h */
diff --git a/arch/m68k/include/asm/mcfclk.h b/arch/m68k/include/asm/mcfclk.h
new file mode 100644
index 000000000000..b676a02bb392
--- /dev/null
+++ b/arch/m68k/include/asm/mcfclk.h
@@ -0,0 +1,43 @@
1/*
2 * mcfclk.h -- coldfire specific clock structure
3 */
4
5
6#ifndef mcfclk_h
7#define mcfclk_h
8
9struct clk;
10
11#ifdef MCFPM_PPMCR0
12struct clk_ops {
13 void (*enable)(struct clk *);
14 void (*disable)(struct clk *);
15};
16
17struct clk {
18 const char *name;
19 struct clk_ops *clk_ops;
20 unsigned long rate;
21 unsigned long enabled;
22 u8 slot;
23};
24
25extern struct clk *mcf_clks[];
26extern struct clk_ops clk_ops0;
27#ifdef MCFPM_PPMCR1
28extern struct clk_ops clk_ops1;
29#endif /* MCFPM_PPMCR1 */
30
31#define DEFINE_CLK(clk_bank, clk_name, clk_slot, clk_rate) \
32static struct clk __clk_##clk_bank##_##clk_slot = { \
33 .name = clk_name, \
34 .clk_ops = &clk_ops##clk_bank, \
35 .rate = clk_rate, \
36 .slot = clk_slot, \
37}
38
39void __clk_init_enabled(struct clk *);
40void __clk_init_disabled(struct clk *);
41#endif /* MCFPM_PPMCR0 */
42
43#endif /* mcfclk_h */
diff --git a/arch/m68k/include/asm/mcfgpio.h b/arch/m68k/include/asm/mcfgpio.h
index fe468eaa51e0..fa1059f50dfc 100644
--- a/arch/m68k/include/asm/mcfgpio.h
+++ b/arch/m68k/include/asm/mcfgpio.h
@@ -16,82 +16,289 @@
16#ifndef mcfgpio_h 16#ifndef mcfgpio_h
17#define mcfgpio_h 17#define mcfgpio_h
18 18
19#include <linux/io.h> 19#ifdef CONFIG_GPIOLIB
20#include <asm-generic/gpio.h> 20#include <asm-generic/gpio.h>
21#else
22
23int __mcfgpio_get_value(unsigned gpio);
24void __mcfgpio_set_value(unsigned gpio, int value);
25int __mcfgpio_direction_input(unsigned gpio);
26int __mcfgpio_direction_output(unsigned gpio, int value);
27int __mcfgpio_request(unsigned gpio);
28void __mcfgpio_free(unsigned gpio);
29
30/* our alternate 'gpiolib' functions */
31static inline int __gpio_get_value(unsigned gpio)
32{
33 if (gpio < MCFGPIO_PIN_MAX)
34 return __mcfgpio_get_value(gpio);
35 else
36 return -EINVAL;
37}
38
39static inline void __gpio_set_value(unsigned gpio, int value)
40{
41 if (gpio < MCFGPIO_PIN_MAX)
42 __mcfgpio_set_value(gpio, value);
43}
44
45static inline int __gpio_cansleep(unsigned gpio)
46{
47 if (gpio < MCFGPIO_PIN_MAX)
48 return 0;
49 else
50 return -EINVAL;
51}
52
53static inline int __gpio_to_irq(unsigned gpio)
54{
55 return -EINVAL;
56}
57
58static inline int gpio_direction_input(unsigned gpio)
59{
60 if (gpio < MCFGPIO_PIN_MAX)
61 return __mcfgpio_direction_input(gpio);
62 else
63 return -EINVAL;
64}
65
66static inline int gpio_direction_output(unsigned gpio, int value)
67{
68 if (gpio < MCFGPIO_PIN_MAX)
69 return __mcfgpio_direction_output(gpio, value);
70 else
71 return -EINVAL;
72}
73
74static inline int gpio_request(unsigned gpio, const char *label)
75{
76 if (gpio < MCFGPIO_PIN_MAX)
77 return __mcfgpio_request(gpio);
78 else
79 return -EINVAL;
80}
81
82static inline void gpio_free(unsigned gpio)
83{
84 if (gpio < MCFGPIO_PIN_MAX)
85 __mcfgpio_free(gpio);
86}
87
88#endif /* CONFIG_GPIOLIB */
21 89
22struct mcf_gpio_chip {
23 struct gpio_chip gpio_chip;
24 void __iomem *pddr;
25 void __iomem *podr;
26 void __iomem *ppdr;
27 void __iomem *setr;
28 void __iomem *clrr;
29 const u8 *gpio_to_pinmux;
30};
31
32extern struct mcf_gpio_chip mcf_gpio_chips[];
33extern unsigned int mcf_gpio_chips_size;
34
35int mcf_gpio_direction_input(struct gpio_chip *, unsigned);
36int mcf_gpio_get_value(struct gpio_chip *, unsigned);
37int mcf_gpio_direction_output(struct gpio_chip *, unsigned, int);
38void mcf_gpio_set_value(struct gpio_chip *, unsigned, int);
39void mcf_gpio_set_value_fast(struct gpio_chip *, unsigned, int);
40int mcf_gpio_request(struct gpio_chip *, unsigned);
41void mcf_gpio_free(struct gpio_chip *, unsigned);
42 90
43/* 91/*
44 * Define macros to ease the pain of setting up the GPIO tables. There 92 * The Freescale Coldfire family is quite varied in how they implement GPIO.
45 * are two cases we need to deal with here, they cover all currently 93 * Some parts have 8 bit ports, some have 16bit and some have 32bit; some have
46 * available ColdFire GPIO hardware. There are of course minor differences 94 * only one port, others have multiple ports; some have a single data latch
47 * in the layout and number of bits in each ColdFire part, but the macros 95 * for both input and output, others have a separate pin data register to read
48 * take all that in. 96 * input; some require a read-modify-write access to change an output, others
97 * have set and clear registers for some of the outputs; Some have all the
98 * GPIOs in a single control area, others have some GPIOs implemented in
99 * different modules.
49 * 100 *
50 * Firstly is the conventional GPIO registers where we toggle individual 101 * This implementation attempts accommodate the differences while presenting
51 * bits in a register, preserving the other bits in the register. For 102 * a generic interface that will optimize to as few instructions as possible.
52 * lack of a better term I have called this the slow method. 103 */
104#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
105 defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
106 defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
107 defined(CONFIG_M532x) || defined(CONFIG_M54xx) || \
108 defined(CONFIG_M5441x)
109
110/* These parts have GPIO organized by 8 bit ports */
111
112#define MCFGPIO_PORTTYPE u8
113#define MCFGPIO_PORTSIZE 8
114#define mcfgpio_read(port) __raw_readb(port)
115#define mcfgpio_write(data, port) __raw_writeb(data, port)
116
117#elif defined(CONFIG_M5307) || defined(CONFIG_M5407) || defined(CONFIG_M5272)
118
119/* These parts have GPIO organized by 16 bit ports */
120
121#define MCFGPIO_PORTTYPE u16
122#define MCFGPIO_PORTSIZE 16
123#define mcfgpio_read(port) __raw_readw(port)
124#define mcfgpio_write(data, port) __raw_writew(data, port)
125
126#elif defined(CONFIG_M5249) || defined(CONFIG_M525x)
127
128/* These parts have GPIO organized by 32 bit ports */
129
130#define MCFGPIO_PORTTYPE u32
131#define MCFGPIO_PORTSIZE 32
132#define mcfgpio_read(port) __raw_readl(port)
133#define mcfgpio_write(data, port) __raw_writel(data, port)
134
135#endif
136
137#define mcfgpio_bit(gpio) (1 << ((gpio) % MCFGPIO_PORTSIZE))
138#define mcfgpio_port(gpio) ((gpio) / MCFGPIO_PORTSIZE)
139
140#if defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
141 defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
142 defined(CONFIG_M532x) || defined(CONFIG_M5441x)
143/*
144 * These parts have an 'Edge' Port module (external interrupt/GPIO) which uses
145 * read-modify-write to change an output and a GPIO module which has separate
146 * set/clr registers to directly change outputs with a single write access.
147 */
148#if defined(CONFIG_M528x)
149/*
150 * The 528x also has GPIOs in other modules (GPT, QADC) which use
151 * read-modify-write as well as those controlled by the EPORT and GPIO modules.
53 */ 152 */
54#define MCFGPS(mlabel, mbase, mngpio, mpddr, mpodr, mppdr) \ 153#define MCFGPIO_SCR_START 40
55 { \ 154#elif defined(CONFIGM5441x)
56 .gpio_chip = { \ 155/* The m5441x EPORT doesn't have its own GPIO port, uses PORT C */
57 .label = #mlabel, \ 156#define MCFGPIO_SCR_START 0
58 .request = mcf_gpio_request, \ 157#else
59 .free = mcf_gpio_free, \ 158#define MCFGPIO_SCR_START 8
60 .direction_input = mcf_gpio_direction_input, \ 159#endif
61 .direction_output = mcf_gpio_direction_output,\
62 .get = mcf_gpio_get_value, \
63 .set = mcf_gpio_set_value, \
64 .base = mbase, \
65 .ngpio = mngpio, \
66 }, \
67 .pddr = (void __iomem *) mpddr, \
68 .podr = (void __iomem *) mpodr, \
69 .ppdr = (void __iomem *) mppdr, \
70 }
71 160
161#define MCFGPIO_SETR_PORT(gpio) (MCFGPIO_SETR + \
162 mcfgpio_port(gpio - MCFGPIO_SCR_START))
163
164#define MCFGPIO_CLRR_PORT(gpio) (MCFGPIO_CLRR + \
165 mcfgpio_port(gpio - MCFGPIO_SCR_START))
166#else
167
168#define MCFGPIO_SCR_START MCFGPIO_PIN_MAX
169/* with MCFGPIO_SCR == MCFGPIO_PIN_MAX, these will be optimized away */
170#define MCFGPIO_SETR_PORT(gpio) 0
171#define MCFGPIO_CLRR_PORT(gpio) 0
172
173#endif
72/* 174/*
73 * Secondly is the faster case, where we have set and clear registers 175 * Coldfire specific helper functions
74 * that allow us to set or clear a bit with a single write, not having
75 * to worry about preserving other bits.
76 */ 176 */
77#define MCFGPF(mlabel, mbase, mngpio) \
78 { \
79 .gpio_chip = { \
80 .label = #mlabel, \
81 .request = mcf_gpio_request, \
82 .free = mcf_gpio_free, \
83 .direction_input = mcf_gpio_direction_input, \
84 .direction_output = mcf_gpio_direction_output,\
85 .get = mcf_gpio_get_value, \
86 .set = mcf_gpio_set_value_fast, \
87 .base = mbase, \
88 .ngpio = mngpio, \
89 }, \
90 .pddr = (void __iomem *) MCFGPIO_PDDR_##mlabel, \
91 .podr = (void __iomem *) MCFGPIO_PODR_##mlabel, \
92 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_##mlabel, \
93 .setr = (void __iomem *) MCFGPIO_PPDSDR_##mlabel, \
94 .clrr = (void __iomem *) MCFGPIO_PCLRR_##mlabel, \
95 }
96 177
178/* return the port pin data register for a gpio */
179static inline u32 __mcfgpio_ppdr(unsigned gpio)
180{
181#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
182 defined(CONFIG_M5307) || defined(CONFIG_M5407)
183 return MCFSIM_PADAT;
184#elif defined(CONFIG_M5272)
185 if (gpio < 16)
186 return MCFSIM_PADAT;
187 else if (gpio < 32)
188 return MCFSIM_PBDAT;
189 else
190 return MCFSIM_PCDAT;
191#elif defined(CONFIG_M5249) || defined(CONFIG_M525x)
192 if (gpio < 32)
193 return MCFSIM2_GPIOREAD;
194 else
195 return MCFSIM2_GPIO1READ;
196#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
197 defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
198 defined(CONFIG_M532x) || defined(CONFIG_M5441x)
199#if !defined(CONFIG_M5441x)
200 if (gpio < 8)
201 return MCFEPORT_EPPDR;
202#if defined(CONFIG_M528x)
203 else if (gpio < 16)
204 return MCFGPTA_GPTPORT;
205 else if (gpio < 24)
206 return MCFGPTB_GPTPORT;
207 else if (gpio < 32)
208 return MCFQADC_PORTQA;
209 else if (gpio < 40)
210 return MCFQADC_PORTQB;
211#endif /* defined(CONFIG_M528x) */
212 else
213#endif /* !defined(CONFIG_M5441x) */
214 return MCFGPIO_PPDR + mcfgpio_port(gpio - MCFGPIO_SCR_START);
215#else
216 return 0;
97#endif 217#endif
218}
219
220/* return the port output data register for a gpio */
221static inline u32 __mcfgpio_podr(unsigned gpio)
222{
223#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
224 defined(CONFIG_M5307) || defined(CONFIG_M5407)
225 return MCFSIM_PADAT;
226#elif defined(CONFIG_M5272)
227 if (gpio < 16)
228 return MCFSIM_PADAT;
229 else if (gpio < 32)
230 return MCFSIM_PBDAT;
231 else
232 return MCFSIM_PCDAT;
233#elif defined(CONFIG_M5249) || defined(CONFIG_M525x)
234 if (gpio < 32)
235 return MCFSIM2_GPIOWRITE;
236 else
237 return MCFSIM2_GPIO1WRITE;
238#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
239 defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
240 defined(CONFIG_M532x) || defined(CONFIG_M5441x)
241#if !defined(CONFIG_M5441x)
242 if (gpio < 8)
243 return MCFEPORT_EPDR;
244#if defined(CONFIG_M528x)
245 else if (gpio < 16)
246 return MCFGPTA_GPTPORT;
247 else if (gpio < 24)
248 return MCFGPTB_GPTPORT;
249 else if (gpio < 32)
250 return MCFQADC_PORTQA;
251 else if (gpio < 40)
252 return MCFQADC_PORTQB;
253#endif /* defined(CONFIG_M528x) */
254 else
255#endif /* !defined(CONFIG_M5441x) */
256 return MCFGPIO_PODR + mcfgpio_port(gpio - MCFGPIO_SCR_START);
257#else
258 return 0;
259#endif
260}
261
262/* return the port direction data register for a gpio */
263static inline u32 __mcfgpio_pddr(unsigned gpio)
264{
265#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
266 defined(CONFIG_M5307) || defined(CONFIG_M5407)
267 return MCFSIM_PADDR;
268#elif defined(CONFIG_M5272)
269 if (gpio < 16)
270 return MCFSIM_PADDR;
271 else if (gpio < 32)
272 return MCFSIM_PBDDR;
273 else
274 return MCFSIM_PCDDR;
275#elif defined(CONFIG_M5249) || defined(CONFIG_M525x)
276 if (gpio < 32)
277 return MCFSIM2_GPIOENABLE;
278 else
279 return MCFSIM2_GPIO1ENABLE;
280#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
281 defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
282 defined(CONFIG_M532x) || defined(CONFIG_M5441x)
283#if !defined(CONFIG_M5441x)
284 if (gpio < 8)
285 return MCFEPORT_EPDDR;
286#if defined(CONFIG_M528x)
287 else if (gpio < 16)
288 return MCFGPTA_GPTDDR;
289 else if (gpio < 24)
290 return MCFGPTB_GPTDDR;
291 else if (gpio < 32)
292 return MCFQADC_DDRQA;
293 else if (gpio < 40)
294 return MCFQADC_DDRQB;
295#endif /* defined(CONFIG_M528x) */
296 else
297#endif /* !defined(CONFIG_M5441x) */
298 return MCFGPIO_PDDR + mcfgpio_port(gpio - MCFGPIO_SCR_START);
299#else
300 return 0;
301#endif
302}
303
304#endif /* mcfgpio_h */
diff --git a/arch/m68k/include/asm/mcfsim.h b/arch/m68k/include/asm/mcfsim.h
index ebd0304054ad..7a83e619e73b 100644
--- a/arch/m68k/include/asm/mcfsim.h
+++ b/arch/m68k/include/asm/mcfsim.h
@@ -27,6 +27,9 @@
27#elif defined(CONFIG_M5249) 27#elif defined(CONFIG_M5249)
28#include <asm/m5249sim.h> 28#include <asm/m5249sim.h>
29#include <asm/mcfintc.h> 29#include <asm/mcfintc.h>
30#elif defined(CONFIG_M525x)
31#include <asm/m525xsim.h>
32#include <asm/mcfintc.h>
30#elif defined(CONFIG_M527x) 33#elif defined(CONFIG_M527x)
31#include <asm/m527xsim.h> 34#include <asm/m527xsim.h>
32#elif defined(CONFIG_M5272) 35#elif defined(CONFIG_M5272)
@@ -43,6 +46,8 @@
43#include <asm/mcfintc.h> 46#include <asm/mcfintc.h>
44#elif defined(CONFIG_M54xx) 47#elif defined(CONFIG_M54xx)
45#include <asm/m54xxsim.h> 48#include <asm/m54xxsim.h>
49#elif defined(CONFIG_M5441x)
50#include <asm/m5441xsim.h>
46#endif 51#endif
47 52
48/****************************************************************************/ 53/****************************************************************************/
diff --git a/arch/m68k/include/asm/mcftimer.h b/arch/m68k/include/asm/mcftimer.h
index 351c27237874..da2fa43c2e45 100644
--- a/arch/m68k/include/asm/mcftimer.h
+++ b/arch/m68k/include/asm/mcftimer.h
@@ -19,7 +19,7 @@
19#define MCFTIMER_TRR 0x04 /* Timer Reference (r/w) */ 19#define MCFTIMER_TRR 0x04 /* Timer Reference (r/w) */
20#define MCFTIMER_TCR 0x08 /* Timer Capture reg (r/w) */ 20#define MCFTIMER_TCR 0x08 /* Timer Capture reg (r/w) */
21#define MCFTIMER_TCN 0x0C /* Timer Counter reg (r/w) */ 21#define MCFTIMER_TCN 0x0C /* Timer Counter reg (r/w) */
22#if defined(CONFIG_M532x) 22#if defined(CONFIG_M532x) || defined(CONFIG_M5441x)
23#define MCFTIMER_TER 0x03 /* Timer Event reg (r/w) */ 23#define MCFTIMER_TER 0x03 /* Timer Event reg (r/w) */
24#else 24#else
25#define MCFTIMER_TER 0x11 /* Timer Event reg (r/w) */ 25#define MCFTIMER_TER 0x11 /* Timer Event reg (r/w) */
diff --git a/arch/m68k/include/asm/mcfuart.h b/arch/m68k/include/asm/mcfuart.h
index 2d3bc774b3c5..b40c20f66647 100644
--- a/arch/m68k/include/asm/mcfuart.h
+++ b/arch/m68k/include/asm/mcfuart.h
@@ -43,8 +43,8 @@ struct mcf_platform_uart {
43#define MCFUART_UFPD 0x30 /* Frac Prec. Divider (r/w) */ 43#define MCFUART_UFPD 0x30 /* Frac Prec. Divider (r/w) */
44#endif 44#endif
45#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \ 45#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
46 defined(CONFIG_M5249) || defined(CONFIG_M5307) || \ 46 defined(CONFIG_M5249) || defined(CONFIG_M525x) || \
47 defined(CONFIG_M5407) 47 defined(CONFIG_M5307) || defined(CONFIG_M5407)
48#define MCFUART_UIVR 0x30 /* Interrupt Vector (r/w) */ 48#define MCFUART_UIVR 0x30 /* Interrupt Vector (r/w) */
49#endif 49#endif
50#define MCFUART_UIPR 0x34 /* Input Port (r) */ 50#define MCFUART_UIPR 0x34 /* Input Port (r) */
diff --git a/arch/m68k/include/asm/pci.h b/arch/m68k/include/asm/pci.h
index 4ad0aea48ab4..848c3dfaad50 100644
--- a/arch/m68k/include/asm/pci.h
+++ b/arch/m68k/include/asm/pci.h
@@ -2,6 +2,7 @@
2#define _ASM_M68K_PCI_H 2#define _ASM_M68K_PCI_H
3 3
4#include <asm-generic/pci-dma-compat.h> 4#include <asm-generic/pci-dma-compat.h>
5#include <asm-generic/pci.h>
5 6
6/* The PCI address space does equal the physical memory 7/* The PCI address space does equal the physical memory
7 * address space. The networking and block device layers use 8 * address space. The networking and block device layers use
@@ -9,4 +10,9 @@
9 */ 10 */
10#define PCI_DMA_BUS_IS_PHYS (1) 11#define PCI_DMA_BUS_IS_PHYS (1)
11 12
13#define pcibios_assign_all_busses() 1
14
15#define PCIBIOS_MIN_IO 0x00000100
16#define PCIBIOS_MIN_MEM 0x02000000
17
12#endif /* _ASM_M68K_PCI_H */ 18#endif /* _ASM_M68K_PCI_H */
diff --git a/arch/m68k/include/asm/pinmux.h b/arch/m68k/include/asm/pinmux.h
deleted file mode 100644
index 119ee686dbd1..000000000000
--- a/arch/m68k/include/asm/pinmux.h
+++ /dev/null
@@ -1,30 +0,0 @@
1/*
2 * Coldfire generic GPIO pinmux support.
3 *
4 * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#ifndef pinmux_h
17#define pinmux_h
18
19#define MCFPINMUX_NONE -1
20
21extern int mcf_pinmux_request(unsigned, unsigned);
22extern void mcf_pinmux_release(unsigned, unsigned);
23
24static inline int mcf_pinmux_is_valid(unsigned pinmux)
25{
26 return pinmux != MCFPINMUX_NONE;
27}
28
29#endif
30
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-23 21:21:08 -0500