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-rw-r--r--arch/m68k/include/asm/system.h210
1 files changed, 5 insertions, 205 deletions
diff --git a/arch/m68k/include/asm/system.h b/arch/m68k/include/asm/system.h
index a10c4d1241de..a7f40578587c 100644
--- a/arch/m68k/include/asm/system.h
+++ b/arch/m68k/include/asm/system.h
@@ -1,205 +1,5 @@
1#ifndef _M68K_SYSTEM_H 1/* FILE TO BE DELETED. DO NOT ADD STUFF HERE! */
2#define _M68K_SYSTEM_H 2#include <asm/barrier.h>
3 3#include <asm/cmpxchg.h>
4#include <linux/linkage.h> 4#include <asm/exec.h>
5#include <linux/kernel.h> 5#include <asm/switch_to.h>
6#include <linux/irqflags.h>
7#include <asm/segment.h>
8#include <asm/entry.h>
9
10#ifdef __KERNEL__
11
12/*
13 * switch_to(n) should switch tasks to task ptr, first checking that
14 * ptr isn't the current task, in which case it does nothing. This
15 * also clears the TS-flag if the task we switched to has used the
16 * math co-processor latest.
17 */
18/*
19 * switch_to() saves the extra registers, that are not saved
20 * automatically by SAVE_SWITCH_STACK in resume(), ie. d0-d5 and
21 * a0-a1. Some of these are used by schedule() and its predecessors
22 * and so we might get see unexpected behaviors when a task returns
23 * with unexpected register values.
24 *
25 * syscall stores these registers itself and none of them are used
26 * by syscall after the function in the syscall has been called.
27 *
28 * Beware that resume now expects *next to be in d1 and the offset of
29 * tss to be in a1. This saves a few instructions as we no longer have
30 * to push them onto the stack and read them back right after.
31 *
32 * 02/17/96 - Jes Sorensen (jds@kom.auc.dk)
33 *
34 * Changed 96/09/19 by Andreas Schwab
35 * pass prev in a0, next in a1
36 */
37asmlinkage void resume(void);
38#define switch_to(prev,next,last) do { \
39 register void *_prev __asm__ ("a0") = (prev); \
40 register void *_next __asm__ ("a1") = (next); \
41 register void *_last __asm__ ("d1"); \
42 __asm__ __volatile__("jbsr resume" \
43 : "=a" (_prev), "=a" (_next), "=d" (_last) \
44 : "0" (_prev), "1" (_next) \
45 : "d0", "d2", "d3", "d4", "d5"); \
46 (last) = _last; \
47} while (0)
48
49
50/*
51 * Force strict CPU ordering.
52 * Not really required on m68k...
53 */
54#define nop() do { asm volatile ("nop"); barrier(); } while (0)
55#define mb() barrier()
56#define rmb() barrier()
57#define wmb() barrier()
58#define read_barrier_depends() ((void)0)
59#define set_mb(var, value) ({ (var) = (value); wmb(); })
60
61#define smp_mb() barrier()
62#define smp_rmb() barrier()
63#define smp_wmb() barrier()
64#define smp_read_barrier_depends() ((void)0)
65
66#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
67
68struct __xchg_dummy { unsigned long a[100]; };
69#define __xg(x) ((volatile struct __xchg_dummy *)(x))
70
71extern unsigned long __invalid_xchg_size(unsigned long, volatile void *, int);
72
73#ifndef CONFIG_RMW_INSNS
74static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
75{
76 unsigned long flags, tmp;
77
78 local_irq_save(flags);
79
80 switch (size) {
81 case 1:
82 tmp = *(u8 *)ptr;
83 *(u8 *)ptr = x;
84 x = tmp;
85 break;
86 case 2:
87 tmp = *(u16 *)ptr;
88 *(u16 *)ptr = x;
89 x = tmp;
90 break;
91 case 4:
92 tmp = *(u32 *)ptr;
93 *(u32 *)ptr = x;
94 x = tmp;
95 break;
96 default:
97 tmp = __invalid_xchg_size(x, ptr, size);
98 break;
99 }
100
101 local_irq_restore(flags);
102 return x;
103}
104#else
105static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
106{
107 switch (size) {
108 case 1:
109 __asm__ __volatile__
110 ("moveb %2,%0\n\t"
111 "1:\n\t"
112 "casb %0,%1,%2\n\t"
113 "jne 1b"
114 : "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory");
115 break;
116 case 2:
117 __asm__ __volatile__
118 ("movew %2,%0\n\t"
119 "1:\n\t"
120 "casw %0,%1,%2\n\t"
121 "jne 1b"
122 : "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory");
123 break;
124 case 4:
125 __asm__ __volatile__
126 ("movel %2,%0\n\t"
127 "1:\n\t"
128 "casl %0,%1,%2\n\t"
129 "jne 1b"
130 : "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory");
131 break;
132 default:
133 x = __invalid_xchg_size(x, ptr, size);
134 break;
135 }
136 return x;
137}
138#endif
139
140#include <asm-generic/cmpxchg-local.h>
141
142#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
143
144extern unsigned long __invalid_cmpxchg_size(volatile void *,
145 unsigned long, unsigned long, int);
146
147/*
148 * Atomic compare and exchange. Compare OLD with MEM, if identical,
149 * store NEW in MEM. Return the initial value in MEM. Success is
150 * indicated by comparing RETURN with OLD.
151 */
152#ifdef CONFIG_RMW_INSNS
153#define __HAVE_ARCH_CMPXCHG 1
154
155static inline unsigned long __cmpxchg(volatile void *p, unsigned long old,
156 unsigned long new, int size)
157{
158 switch (size) {
159 case 1:
160 __asm__ __volatile__ ("casb %0,%2,%1"
161 : "=d" (old), "=m" (*(char *)p)
162 : "d" (new), "0" (old), "m" (*(char *)p));
163 break;
164 case 2:
165 __asm__ __volatile__ ("casw %0,%2,%1"
166 : "=d" (old), "=m" (*(short *)p)
167 : "d" (new), "0" (old), "m" (*(short *)p));
168 break;
169 case 4:
170 __asm__ __volatile__ ("casl %0,%2,%1"
171 : "=d" (old), "=m" (*(int *)p)
172 : "d" (new), "0" (old), "m" (*(int *)p));
173 break;
174 default:
175 old = __invalid_cmpxchg_size(p, old, new, size);
176 break;
177 }
178 return old;
179}
180
181#define cmpxchg(ptr, o, n) \
182 ((__typeof__(*(ptr)))__cmpxchg((ptr), (unsigned long)(o), \
183 (unsigned long)(n), sizeof(*(ptr))))
184#define cmpxchg_local(ptr, o, n) \
185 ((__typeof__(*(ptr)))__cmpxchg((ptr), (unsigned long)(o), \
186 (unsigned long)(n), sizeof(*(ptr))))
187#else
188
189/*
190 * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
191 * them available.
192 */
193#define cmpxchg_local(ptr, o, n) \
194 ((__typeof__(*(ptr)))__cmpxchg_local_generic((ptr), (unsigned long)(o),\
195 (unsigned long)(n), sizeof(*(ptr))))
196
197#include <asm-generic/cmpxchg.h>
198
199#endif
200
201#define arch_align_stack(x) (x)
202
203#endif /* __KERNEL__ */
204
205#endif /* _M68K_SYSTEM_H */
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