diff options
Diffstat (limited to 'arch/m68k/include/asm/mcftimer.h')
| -rw-r--r-- | arch/m68k/include/asm/mcftimer.h | 80 |
1 files changed, 80 insertions, 0 deletions
diff --git a/arch/m68k/include/asm/mcftimer.h b/arch/m68k/include/asm/mcftimer.h new file mode 100644 index 000000000000..0f90f6d2227a --- /dev/null +++ b/arch/m68k/include/asm/mcftimer.h | |||
| @@ -0,0 +1,80 @@ | |||
| 1 | /****************************************************************************/ | ||
| 2 | |||
| 3 | /* | ||
| 4 | * mcftimer.h -- ColdFire internal TIMER support defines. | ||
| 5 | * | ||
| 6 | * (C) Copyright 1999-2006, Greg Ungerer <gerg@snapgear.com> | ||
| 7 | * (C) Copyright 2000, Lineo Inc. (www.lineo.com) | ||
| 8 | */ | ||
| 9 | |||
| 10 | /****************************************************************************/ | ||
| 11 | #ifndef mcftimer_h | ||
| 12 | #define mcftimer_h | ||
| 13 | /****************************************************************************/ | ||
| 14 | |||
| 15 | |||
| 16 | /* | ||
| 17 | * Get address specific defines for this ColdFire member. | ||
| 18 | */ | ||
| 19 | #if defined(CONFIG_M5206) || defined(CONFIG_M5206e) | ||
| 20 | #define MCFTIMER_BASE1 0x100 /* Base address of TIMER1 */ | ||
| 21 | #define MCFTIMER_BASE2 0x120 /* Base address of TIMER2 */ | ||
| 22 | #elif defined(CONFIG_M5272) | ||
| 23 | #define MCFTIMER_BASE1 0x200 /* Base address of TIMER1 */ | ||
| 24 | #define MCFTIMER_BASE2 0x220 /* Base address of TIMER2 */ | ||
| 25 | #define MCFTIMER_BASE3 0x240 /* Base address of TIMER4 */ | ||
| 26 | #define MCFTIMER_BASE4 0x260 /* Base address of TIMER3 */ | ||
| 27 | #elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407) | ||
| 28 | #define MCFTIMER_BASE1 0x140 /* Base address of TIMER1 */ | ||
| 29 | #define MCFTIMER_BASE2 0x180 /* Base address of TIMER2 */ | ||
| 30 | #elif defined(CONFIG_M532x) | ||
| 31 | #define MCFTIMER_BASE1 0xfc070000 /* Base address of TIMER1 */ | ||
| 32 | #define MCFTIMER_BASE2 0xfc074000 /* Base address of TIMER2 */ | ||
| 33 | #define MCFTIMER_BASE3 0xfc078000 /* Base address of TIMER3 */ | ||
| 34 | #define MCFTIMER_BASE4 0xfc07c000 /* Base address of TIMER4 */ | ||
| 35 | #endif | ||
| 36 | |||
| 37 | |||
| 38 | /* | ||
| 39 | * Define the TIMER register set addresses. | ||
| 40 | */ | ||
| 41 | #define MCFTIMER_TMR 0x00 /* Timer Mode reg (r/w) */ | ||
| 42 | #define MCFTIMER_TRR 0x04 /* Timer Reference (r/w) */ | ||
| 43 | #define MCFTIMER_TCR 0x08 /* Timer Capture reg (r/w) */ | ||
| 44 | #define MCFTIMER_TCN 0x0C /* Timer Counter reg (r/w) */ | ||
| 45 | #if defined(CONFIG_M532x) | ||
| 46 | #define MCFTIMER_TER 0x03 /* Timer Event reg (r/w) */ | ||
| 47 | #else | ||
| 48 | #define MCFTIMER_TER 0x11 /* Timer Event reg (r/w) */ | ||
| 49 | #endif | ||
| 50 | |||
| 51 | /* | ||
| 52 | * Bit definitions for the Timer Mode Register (TMR). | ||
| 53 | * Register bit flags are common accross ColdFires. | ||
| 54 | */ | ||
| 55 | #define MCFTIMER_TMR_PREMASK 0xff00 /* Prescalar mask */ | ||
| 56 | #define MCFTIMER_TMR_DISCE 0x0000 /* Disable capture */ | ||
| 57 | #define MCFTIMER_TMR_ANYCE 0x00c0 /* Capture any edge */ | ||
| 58 | #define MCFTIMER_TMR_FALLCE 0x0080 /* Capture fallingedge */ | ||
| 59 | #define MCFTIMER_TMR_RISECE 0x0040 /* Capture rising edge */ | ||
| 60 | #define MCFTIMER_TMR_ENOM 0x0020 /* Enable output toggle */ | ||
| 61 | #define MCFTIMER_TMR_DISOM 0x0000 /* Do single output pulse */ | ||
| 62 | #define MCFTIMER_TMR_ENORI 0x0010 /* Enable ref interrupt */ | ||
| 63 | #define MCFTIMER_TMR_DISORI 0x0000 /* Disable ref interrupt */ | ||
| 64 | #define MCFTIMER_TMR_RESTART 0x0008 /* Restart counter */ | ||
| 65 | #define MCFTIMER_TMR_FREERUN 0x0000 /* Free running counter */ | ||
| 66 | #define MCFTIMER_TMR_CLKTIN 0x0006 /* Input clock is TIN */ | ||
| 67 | #define MCFTIMER_TMR_CLK16 0x0004 /* Input clock is /16 */ | ||
| 68 | #define MCFTIMER_TMR_CLK1 0x0002 /* Input clock is /1 */ | ||
| 69 | #define MCFTIMER_TMR_CLKSTOP 0x0000 /* Stop counter */ | ||
| 70 | #define MCFTIMER_TMR_ENABLE 0x0001 /* Enable timer */ | ||
| 71 | #define MCFTIMER_TMR_DISABLE 0x0000 /* Disable timer */ | ||
| 72 | |||
| 73 | /* | ||
| 74 | * Bit definitions for the Timer Event Registers (TER). | ||
| 75 | */ | ||
| 76 | #define MCFTIMER_TER_CAP 0x01 /* Capture event */ | ||
| 77 | #define MCFTIMER_TER_REF 0x02 /* Refernece event */ | ||
| 78 | |||
| 79 | /****************************************************************************/ | ||
| 80 | #endif /* mcftimer_h */ | ||
