diff options
Diffstat (limited to 'arch/m68k/include/asm/mcfmbus.h')
-rw-r--r-- | arch/m68k/include/asm/mcfmbus.h | 77 |
1 files changed, 0 insertions, 77 deletions
diff --git a/arch/m68k/include/asm/mcfmbus.h b/arch/m68k/include/asm/mcfmbus.h deleted file mode 100644 index 319899c47a2c..000000000000 --- a/arch/m68k/include/asm/mcfmbus.h +++ /dev/null | |||
@@ -1,77 +0,0 @@ | |||
1 | /****************************************************************************/ | ||
2 | |||
3 | /* | ||
4 | * mcfmbus.h -- Coldfire MBUS support defines. | ||
5 | * | ||
6 | * (C) Copyright 1999, Martin Floeer (mfloeer@axcent.de) | ||
7 | */ | ||
8 | |||
9 | /****************************************************************************/ | ||
10 | |||
11 | |||
12 | #ifndef mcfmbus_h | ||
13 | #define mcfmbus_h | ||
14 | |||
15 | |||
16 | #define MCFMBUS_BASE 0x280 | ||
17 | #define MCFMBUS_IRQ_VECTOR 0x19 | ||
18 | #define MCFMBUS_IRQ 0x1 | ||
19 | #define MCFMBUS_CLK 0x3f | ||
20 | #define MCFMBUS_IRQ_LEVEL 0x07 /*IRQ Level 1*/ | ||
21 | #define MCFMBUS_ADDRESS 0x01 | ||
22 | |||
23 | |||
24 | /* | ||
25 | * Define the 5307 MBUS register set addresses | ||
26 | */ | ||
27 | |||
28 | #define MCFMBUS_MADR 0x00 | ||
29 | #define MCFMBUS_MFDR 0x04 | ||
30 | #define MCFMBUS_MBCR 0x08 | ||
31 | #define MCFMBUS_MBSR 0x0C | ||
32 | #define MCFMBUS_MBDR 0x10 | ||
33 | |||
34 | |||
35 | #define MCFMBUS_MADR_ADDR(a) (((a)&0x7F)<<0x01) /*Slave Address*/ | ||
36 | |||
37 | #define MCFMBUS_MFDR_MBC(a) ((a)&0x3F) /*M-Bus Clock*/ | ||
38 | |||
39 | /* | ||
40 | * Define bit flags in Control Register | ||
41 | */ | ||
42 | |||
43 | #define MCFMBUS_MBCR_MEN (0x80) /* M-Bus Enable */ | ||
44 | #define MCFMBUS_MBCR_MIEN (0x40) /* M-Bus Interrupt Enable */ | ||
45 | #define MCFMBUS_MBCR_MSTA (0x20) /* Master/Slave Mode Select Bit */ | ||
46 | #define MCFMBUS_MBCR_MTX (0x10) /* Transmit/Rcv Mode Select Bit */ | ||
47 | #define MCFMBUS_MBCR_TXAK (0x08) /* Transmit Acknowledge Enable */ | ||
48 | #define MCFMBUS_MBCR_RSTA (0x04) /* Repeat Start */ | ||
49 | |||
50 | /* | ||
51 | * Define bit flags in Status Register | ||
52 | */ | ||
53 | |||
54 | #define MCFMBUS_MBSR_MCF (0x80) /* Data Transfer Complete */ | ||
55 | #define MCFMBUS_MBSR_MAAS (0x40) /* Addressed as a Slave */ | ||
56 | #define MCFMBUS_MBSR_MBB (0x20) /* Bus Busy */ | ||
57 | #define MCFMBUS_MBSR_MAL (0x10) /* Arbitration Lost */ | ||
58 | #define MCFMBUS_MBSR_SRW (0x04) /* Slave Transmit */ | ||
59 | #define MCFMBUS_MBSR_MIF (0x02) /* M-Bus Interrupt */ | ||
60 | #define MCFMBUS_MBSR_RXAK (0x01) /* No Acknowledge Received */ | ||
61 | |||
62 | /* | ||
63 | * Define bit flags in DATA I/O Register | ||
64 | */ | ||
65 | |||
66 | #define MCFMBUS_MBDR_READ (0x01) /* 1=read 0=write MBUS */ | ||
67 | |||
68 | #define MBUSIOCSCLOCK 1 | ||
69 | #define MBUSIOCGCLOCK 2 | ||
70 | #define MBUSIOCSADDR 3 | ||
71 | #define MBUSIOCGADDR 4 | ||
72 | #define MBUSIOCSSLADDR 5 | ||
73 | #define MBUSIOCGSLADDR 6 | ||
74 | #define MBUSIOCSSUBADDR 7 | ||
75 | #define MBUSIOCGSUBADDR 8 | ||
76 | |||
77 | #endif | ||