1 files changed, 23 insertions, 50 deletions
diff --git a/arch/m68k/include/asm/mcfintc.h b/arch/m68k/include/asm/mcfintc.h
index a75a001e773a..213aa6c68abb 100644
--- a/arch/m68k/include/asm/mcfintc.h
+++ b/arch/m68k/include/asm/mcfintc.h
@@ -48,59 +48,32 @@
 #define MCFSIM_ICR_PRI3         0x03            /* Priority 3 intr */
 /*
- *      Bit definitions for the ICR family of registers.
+ * IMR bit position definitions.
 */
-#define MCFSIM_ICR_AUTOVEC      0x80            /* Auto-vectored intr */
+#define MCFINTC_EINT1           1               /* External int #1 */
-#define MCFSIM_ICR_LEVEL0       0x00            /* Level 0 intr */
+#define MCFINTC_EINT2           2               /* External int #2 */
-#define MCFSIM_ICR_LEVEL1       0x04            /* Level 1 intr */
+#define MCFINTC_EINT3           3               /* External int #3 */
-#define MCFSIM_ICR_LEVEL2       0x08            /* Level 2 intr */
+#define MCFINTC_EINT4           4               /* External int #4 */
-#define MCFSIM_ICR_LEVEL3       0x0c            /* Level 3 intr */
+#define MCFINTC_EINT5           5               /* External int #5 */
-#define MCFSIM_ICR_LEVEL4       0x10            /* Level 4 intr */
+#define MCFINTC_EINT6           6               /* External int #6 */
-#define MCFSIM_ICR_LEVEL5       0x14            /* Level 5 intr */
+#define MCFINTC_EINT7           7               /* External int #7 */
-#define MCFSIM_ICR_LEVEL6       0x18            /* Level 6 intr */
+#define MCFINTC_SWT             8               /* Software Watchdog */
-#define MCFSIM_ICR_LEVEL7       0x1c            /* Level 7 intr */
+#define MCFINTC_TIMER1          9
+#define MCFINTC_TIMER2          10
+#define MCFINTC_I2C             11              /* I2C / MBUS */
+#define MCFINTC_UART0           12
+#define MCFINTC_UART1           13
+#define MCFINTC_DMA0            14
+#define MCFINTC_DMA1            15
+#define MCFINTC_DMA2            16
+#define MCFINTC_DMA3            17
+#define MCFINTC_QSPI            18
-#define MCFSIM_ICR_PRI0         0x00            /* Priority 0 intr */
+#ifndef __ASSEMBLER__
-#define MCFSIM_ICR_PRI1         0x01            /* Priority 1 intr */
+void mcf_autovector(int irq);
-#define MCFSIM_ICR_PRI2         0x02            /* Priority 2 intr */
+void mcf_setimr(int index);
-#define MCFSIM_ICR_PRI3         0x03            /* Priority 3 intr */
+void mcf_clrimr(int index);
-/*
- *      Bit definitions for the Interrupt Mask register (IMR).
- */
-#define MCFSIM_IMR_EINT1        0x0002          /* External intr # 1 */
-#define MCFSIM_IMR_EINT2        0x0004          /* External intr # 2 */
-#define MCFSIM_IMR_EINT3        0x0008          /* External intr # 3 */
-#define MCFSIM_IMR_EINT4        0x0010          /* External intr # 4 */
-#define MCFSIM_IMR_EINT5        0x0020          /* External intr # 5 */
-#define MCFSIM_IMR_EINT6        0x0040          /* External intr # 6 */
-#define MCFSIM_IMR_EINT7        0x0080          /* External intr # 7 */
-#define MCFSIM_IMR_SWD          0x0100          /* Software Watchdog intr */
-#define MCFSIM_IMR_TIMER1       0x0200          /* TIMER 1 intr */
-#define MCFSIM_IMR_TIMER2       0x0400          /* TIMER 2 intr */
-#define MCFSIM_IMR_MBUS         0x0800          /* MBUS intr    */
-#define MCFSIM_IMR_UART1        0x1000          /* UART 1 intr */
-#define MCFSIM_IMR_UART2        0x2000          /* UART 2 intr */
-#if defined(CONFIG_M5206e)
-#define MCFSIM_IMR_DMA1         0x4000          /* DMA 1 intr */
-#define MCFSIM_IMR_DMA2         0x8000          /* DMA 2 intr */
-#elif defined(CONFIG_M5249) || defined(CONFIG_M5307)
-#define MCFSIM_IMR_DMA0         0x4000          /* DMA 0 intr */
-#define MCFSIM_IMR_DMA1         0x8000          /* DMA 1 intr */
-#define MCFSIM_IMR_DMA2         0x10000         /* DMA 2 intr */
-#define MCFSIM_IMR_DMA3         0x20000         /* DMA 3 intr */
 #endif
-/*
- *      Mask for all of the SIM devices. Some parts have more or less
- *      SIM devices. This is a catchall for the sandard set.
- */
-#ifndef MCFSIM_IMR_MASKALL
-#define MCFSIM_IMR_MASKALL      0x3ffe          /* All intr sources */
-#endif
 /****************************************************************************/
 #endif  /* mcfintc_h */

diff --git a/arch/m68k/include/asm/mcfintc.h b/arch/m68k/include/asm/mcfintc.h index a75a001e773a..213aa6c68abb 100644 --- a/arch/m68k/include/asm/mcfintc.h +++ b/arch/m68k/include/asm/mcfintc.h
@@ -48,59 +48,32 @@
48	#define MCFSIM_ICR_PRI3 0x03 /* Priority 3 intr */	48	#define MCFSIM_ICR_PRI3 0x03 /* Priority 3 intr */
49		49
50	/*	50	/*
51	* Bit definitions for the ICR family of registers.	51	* IMR bit position definitions.
52	*/	52	*/
53	#define MCFSIM_ICR_AUTOVEC 0x80 /* Auto-vectored intr */	53	#define MCFINTC_EINT1 1 /* External int #1 */
54	#define MCFSIM_ICR_LEVEL0 0x00 /* Level 0 intr */	54	#define MCFINTC_EINT2 2 /* External int #2 */
55	#define MCFSIM_ICR_LEVEL1 0x04 /* Level 1 intr */	55	#define MCFINTC_EINT3 3 /* External int #3 */
56	#define MCFSIM_ICR_LEVEL2 0x08 /* Level 2 intr */	56	#define MCFINTC_EINT4 4 /* External int #4 */
57	#define MCFSIM_ICR_LEVEL3 0x0c /* Level 3 intr */	57	#define MCFINTC_EINT5 5 /* External int #5 */
58	#define MCFSIM_ICR_LEVEL4 0x10 /* Level 4 intr */	58	#define MCFINTC_EINT6 6 /* External int #6 */
59	#define MCFSIM_ICR_LEVEL5 0x14 /* Level 5 intr */	59	#define MCFINTC_EINT7 7 /* External int #7 */
60	#define MCFSIM_ICR_LEVEL6 0x18 /* Level 6 intr */	60	#define MCFINTC_SWT 8 /* Software Watchdog */
61	#define MCFSIM_ICR_LEVEL7 0x1c /* Level 7 intr */	61	#define MCFINTC_TIMER1 9
		62	#define MCFINTC_TIMER2 10
		63	#define MCFINTC_I2C 11 /* I2C / MBUS */
		64	#define MCFINTC_UART0 12
		65	#define MCFINTC_UART1 13
		66	#define MCFINTC_DMA0 14
		67	#define MCFINTC_DMA1 15
		68	#define MCFINTC_DMA2 16
		69	#define MCFINTC_DMA3 17
		70	#define MCFINTC_QSPI 18
62		71
63	#define MCFSIM_ICR_PRI0 0x00 /* Priority 0 intr */	72	#ifndef __ASSEMBLER__
64	#define MCFSIM_ICR_PRI1 0x01 /* Priority 1 intr */	73	void mcf_autovector(int irq);
65	#define MCFSIM_ICR_PRI2 0x02 /* Priority 2 intr */	74	void mcf_setimr(int index);
66	#define MCFSIM_ICR_PRI3 0x03 /* Priority 3 intr */	75	void mcf_clrimr(int index);
67
68	/*
69	* Bit definitions for the Interrupt Mask register (IMR).
70	*/
71	#define MCFSIM_IMR_EINT1 0x0002 /* External intr # 1 */
72	#define MCFSIM_IMR_EINT2 0x0004 /* External intr # 2 */
73	#define MCFSIM_IMR_EINT3 0x0008 /* External intr # 3 */
74	#define MCFSIM_IMR_EINT4 0x0010 /* External intr # 4 */
75	#define MCFSIM_IMR_EINT5 0x0020 /* External intr # 5 */
76	#define MCFSIM_IMR_EINT6 0x0040 /* External intr # 6 */
77	#define MCFSIM_IMR_EINT7 0x0080 /* External intr # 7 */
78
79	#define MCFSIM_IMR_SWD 0x0100 /* Software Watchdog intr */
80	#define MCFSIM_IMR_TIMER1 0x0200 /* TIMER 1 intr */
81	#define MCFSIM_IMR_TIMER2 0x0400 /* TIMER 2 intr */
82	#define MCFSIM_IMR_MBUS 0x0800 /* MBUS intr */
83	#define MCFSIM_IMR_UART1 0x1000 /* UART 1 intr */
84	#define MCFSIM_IMR_UART2 0x2000 /* UART 2 intr */
85
86	#if defined(CONFIG_M5206e)
87	#define MCFSIM_IMR_DMA1 0x4000 /* DMA 1 intr */
88	#define MCFSIM_IMR_DMA2 0x8000 /* DMA 2 intr */
89	#elif defined(CONFIG_M5249) \|\| defined(CONFIG_M5307)
90	#define MCFSIM_IMR_DMA0 0x4000 /* DMA 0 intr */
91	#define MCFSIM_IMR_DMA1 0x8000 /* DMA 1 intr */
92	#define MCFSIM_IMR_DMA2 0x10000 /* DMA 2 intr */
93	#define MCFSIM_IMR_DMA3 0x20000 /* DMA 3 intr */
94	#endif	76	#endif
95		77
96	/*
97	* Mask for all of the SIM devices. Some parts have more or less
98	* SIM devices. This is a catchall for the sandard set.
99	*/
100	#ifndef MCFSIM_IMR_MASKALL
101	#define MCFSIM_IMR_MASKALL 0x3ffe /* All intr sources */
102	#endif
103
104
105	/****************************************************************************/	78	/****************************************************************************/
106	#endif /* mcfintc_h */	79	#endif /* mcfintc_h */