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-rw-r--r--arch/m68k/include/asm/mcfgpio.h329
1 files changed, 261 insertions, 68 deletions
diff --git a/arch/m68k/include/asm/mcfgpio.h b/arch/m68k/include/asm/mcfgpio.h
index fe468eaa51e0..67ba20ffedbe 100644
--- a/arch/m68k/include/asm/mcfgpio.h
+++ b/arch/m68k/include/asm/mcfgpio.h
@@ -16,82 +16,275 @@
16#ifndef mcfgpio_h 16#ifndef mcfgpio_h
17#define mcfgpio_h 17#define mcfgpio_h
18 18
19#include <linux/io.h> 19#ifdef CONFIG_GPIOLIB
20#include <asm-generic/gpio.h> 20#include <asm-generic/gpio.h>
21#else
22
23int __mcfgpio_get_value(unsigned gpio);
24void __mcfgpio_set_value(unsigned gpio, int value);
25int __mcfgpio_direction_input(unsigned gpio);
26int __mcfgpio_direction_output(unsigned gpio, int value);
27int __mcfgpio_request(unsigned gpio);
28void __mcfgpio_free(unsigned gpio);
29
30/* our alternate 'gpiolib' functions */
31static inline int __gpio_get_value(unsigned gpio)
32{
33 if (gpio < MCFGPIO_PIN_MAX)
34 return __mcfgpio_get_value(gpio);
35 else
36 return -EINVAL;
37}
38
39static inline void __gpio_set_value(unsigned gpio, int value)
40{
41 if (gpio < MCFGPIO_PIN_MAX)
42 __mcfgpio_set_value(gpio, value);
43}
44
45static inline int __gpio_cansleep(unsigned gpio)
46{
47 if (gpio < MCFGPIO_PIN_MAX)
48 return 0;
49 else
50 return -EINVAL;
51}
52
53static inline int __gpio_to_irq(unsigned gpio)
54{
55 return -EINVAL;
56}
57
58static inline int gpio_direction_input(unsigned gpio)
59{
60 if (gpio < MCFGPIO_PIN_MAX)
61 return __mcfgpio_direction_input(gpio);
62 else
63 return -EINVAL;
64}
65
66static inline int gpio_direction_output(unsigned gpio, int value)
67{
68 if (gpio < MCFGPIO_PIN_MAX)
69 return __mcfgpio_direction_output(gpio, value);
70 else
71 return -EINVAL;
72}
73
74static inline int gpio_request(unsigned gpio, const char *label)
75{
76 if (gpio < MCFGPIO_PIN_MAX)
77 return __mcfgpio_request(gpio);
78 else
79 return -EINVAL;
80}
81
82static inline void gpio_free(unsigned gpio)
83{
84 if (gpio < MCFGPIO_PIN_MAX)
85 __mcfgpio_free(gpio);
86}
87
88#endif /* CONFIG_GPIOLIB */
21 89
22struct mcf_gpio_chip {
23 struct gpio_chip gpio_chip;
24 void __iomem *pddr;
25 void __iomem *podr;
26 void __iomem *ppdr;
27 void __iomem *setr;
28 void __iomem *clrr;
29 const u8 *gpio_to_pinmux;
30};
31
32extern struct mcf_gpio_chip mcf_gpio_chips[];
33extern unsigned int mcf_gpio_chips_size;
34
35int mcf_gpio_direction_input(struct gpio_chip *, unsigned);
36int mcf_gpio_get_value(struct gpio_chip *, unsigned);
37int mcf_gpio_direction_output(struct gpio_chip *, unsigned, int);
38void mcf_gpio_set_value(struct gpio_chip *, unsigned, int);
39void mcf_gpio_set_value_fast(struct gpio_chip *, unsigned, int);
40int mcf_gpio_request(struct gpio_chip *, unsigned);
41void mcf_gpio_free(struct gpio_chip *, unsigned);
42 90
43/* 91/*
44 * Define macros to ease the pain of setting up the GPIO tables. There 92 * The Freescale Coldfire family is quite varied in how they implement GPIO.
45 * are two cases we need to deal with here, they cover all currently 93 * Some parts have 8 bit ports, some have 16bit and some have 32bit; some have
46 * available ColdFire GPIO hardware. There are of course minor differences 94 * only one port, others have multiple ports; some have a single data latch
47 * in the layout and number of bits in each ColdFire part, but the macros 95 * for both input and output, others have a separate pin data register to read
48 * take all that in. 96 * input; some require a read-modify-write access to change an output, others
97 * have set and clear registers for some of the outputs; Some have all the
98 * GPIOs in a single control area, others have some GPIOs implemented in
99 * different modules.
49 * 100 *
50 * Firstly is the conventional GPIO registers where we toggle individual 101 * This implementation attempts accommodate the differences while presenting
51 * bits in a register, preserving the other bits in the register. For 102 * a generic interface that will optimize to as few instructions as possible.
52 * lack of a better term I have called this the slow method.
53 */ 103 */
54#define MCFGPS(mlabel, mbase, mngpio, mpddr, mpodr, mppdr) \ 104#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
55 { \ 105 defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
56 .gpio_chip = { \ 106 defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
57 .label = #mlabel, \ 107 defined(CONFIG_M532x) || defined(CONFIG_M54xx)
58 .request = mcf_gpio_request, \ 108
59 .free = mcf_gpio_free, \ 109/* These parts have GPIO organized by 8 bit ports */
60 .direction_input = mcf_gpio_direction_input, \ 110
61 .direction_output = mcf_gpio_direction_output,\ 111#define MCFGPIO_PORTTYPE u8
62 .get = mcf_gpio_get_value, \ 112#define MCFGPIO_PORTSIZE 8
63 .set = mcf_gpio_set_value, \ 113#define mcfgpio_read(port) __raw_readb(port)
64 .base = mbase, \ 114#define mcfgpio_write(data, port) __raw_writeb(data, port)
65 .ngpio = mngpio, \ 115
66 }, \ 116#elif defined(CONFIG_M5307) || defined(CONFIG_M5407) || defined(CONFIG_M5272)
67 .pddr = (void __iomem *) mpddr, \ 117
68 .podr = (void __iomem *) mpodr, \ 118/* These parts have GPIO organized by 16 bit ports */
69 .ppdr = (void __iomem *) mppdr, \ 119
70 } 120#define MCFGPIO_PORTTYPE u16
121#define MCFGPIO_PORTSIZE 16
122#define mcfgpio_read(port) __raw_readw(port)
123#define mcfgpio_write(data, port) __raw_writew(data, port)
124
125#elif defined(CONFIG_M5249)
126
127/* These parts have GPIO organized by 32 bit ports */
128
129#define MCFGPIO_PORTTYPE u32
130#define MCFGPIO_PORTSIZE 32
131#define mcfgpio_read(port) __raw_readl(port)
132#define mcfgpio_write(data, port) __raw_writel(data, port)
133
134#endif
71 135
136#define mcfgpio_bit(gpio) (1 << ((gpio) % MCFGPIO_PORTSIZE))
137#define mcfgpio_port(gpio) ((gpio) / MCFGPIO_PORTSIZE)
138
139#if defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
140 defined(CONFIG_M527x) || defined(CONFIG_M528x) || defined(CONFIG_M532x)
141/*
142 * These parts have an 'Edge' Port module (external interrupt/GPIO) which uses
143 * read-modify-write to change an output and a GPIO module which has separate
144 * set/clr registers to directly change outputs with a single write access.
145 */
146#if defined(CONFIG_M528x)
72/* 147/*
73 * Secondly is the faster case, where we have set and clear registers 148 * The 528x also has GPIOs in other modules (GPT, QADC) which use
74 * that allow us to set or clear a bit with a single write, not having 149 * read-modify-write as well as those controlled by the EPORT and GPIO modules.
75 * to worry about preserving other bits.
76 */ 150 */
77#define MCFGPF(mlabel, mbase, mngpio) \ 151#define MCFGPIO_SCR_START 40
78 { \ 152#else
79 .gpio_chip = { \ 153#define MCFGPIO_SCR_START 8
80 .label = #mlabel, \ 154#endif
81 .request = mcf_gpio_request, \ 155
82 .free = mcf_gpio_free, \ 156#define MCFGPIO_SETR_PORT(gpio) (MCFGPIO_SETR + \
83 .direction_input = mcf_gpio_direction_input, \ 157 mcfgpio_port(gpio - MCFGPIO_SCR_START))
84 .direction_output = mcf_gpio_direction_output,\ 158
85 .get = mcf_gpio_get_value, \ 159#define MCFGPIO_CLRR_PORT(gpio) (MCFGPIO_CLRR + \
86 .set = mcf_gpio_set_value_fast, \ 160 mcfgpio_port(gpio - MCFGPIO_SCR_START))
87 .base = mbase, \ 161#else
88 .ngpio = mngpio, \ 162
89 }, \ 163#define MCFGPIO_SCR_START MCFGPIO_PIN_MAX
90 .pddr = (void __iomem *) MCFGPIO_PDDR_##mlabel, \ 164/* with MCFGPIO_SCR == MCFGPIO_PIN_MAX, these will be optimized away */
91 .podr = (void __iomem *) MCFGPIO_PODR_##mlabel, \ 165#define MCFGPIO_SETR_PORT(gpio) 0
92 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_##mlabel, \ 166#define MCFGPIO_CLRR_PORT(gpio) 0
93 .setr = (void __iomem *) MCFGPIO_PPDSDR_##mlabel, \
94 .clrr = (void __iomem *) MCFGPIO_PCLRR_##mlabel, \
95 }
96 167
97#endif 168#endif
169/*
170 * Coldfire specific helper functions
171 */
172
173/* return the port pin data register for a gpio */
174static inline u32 __mcfgpio_ppdr(unsigned gpio)
175{
176#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
177 defined(CONFIG_M5307) || defined(CONFIG_M5407)
178 return MCFSIM_PADAT;
179#elif defined(CONFIG_M5272)
180 if (gpio < 16)
181 return MCFSIM_PADAT;
182 else if (gpio < 32)
183 return MCFSIM_PBDAT;
184 else
185 return MCFSIM_PCDAT;
186#elif defined(CONFIG_M5249)
187 if (gpio < 32)
188 return MCFSIM2_GPIOREAD;
189 else
190 return MCFSIM2_GPIO1READ;
191#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
192 defined(CONFIG_M527x) || defined(CONFIG_M528x) || defined(CONFIG_M532x)
193 if (gpio < 8)
194 return MCFEPORT_EPPDR;
195#if defined(CONFIG_M528x)
196 else if (gpio < 16)
197 return MCFGPTA_GPTPORT;
198 else if (gpio < 24)
199 return MCFGPTB_GPTPORT;
200 else if (gpio < 32)
201 return MCFQADC_PORTQA;
202 else if (gpio < 40)
203 return MCFQADC_PORTQB;
204#endif
205 else
206 return MCFGPIO_PPDR + mcfgpio_port(gpio - MCFGPIO_SCR_START);
207#else
208 return 0;
209#endif
210}
211
212/* return the port output data register for a gpio */
213static inline u32 __mcfgpio_podr(unsigned gpio)
214{
215#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
216 defined(CONFIG_M5307) || defined(CONFIG_M5407)
217 return MCFSIM_PADAT;
218#elif defined(CONFIG_M5272)
219 if (gpio < 16)
220 return MCFSIM_PADAT;
221 else if (gpio < 32)
222 return MCFSIM_PBDAT;
223 else
224 return MCFSIM_PCDAT;
225#elif defined(CONFIG_M5249)
226 if (gpio < 32)
227 return MCFSIM2_GPIOWRITE;
228 else
229 return MCFSIM2_GPIO1WRITE;
230#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
231 defined(CONFIG_M527x) || defined(CONFIG_M528x) || defined(CONFIG_M532x)
232 if (gpio < 8)
233 return MCFEPORT_EPDR;
234#if defined(CONFIG_M528x)
235 else if (gpio < 16)
236 return MCFGPTA_GPTPORT;
237 else if (gpio < 24)
238 return MCFGPTB_GPTPORT;
239 else if (gpio < 32)
240 return MCFQADC_PORTQA;
241 else if (gpio < 40)
242 return MCFQADC_PORTQB;
243#endif
244 else
245 return MCFGPIO_PODR + mcfgpio_port(gpio - MCFGPIO_SCR_START);
246#else
247 return 0;
248#endif
249}
250
251/* return the port direction data register for a gpio */
252static inline u32 __mcfgpio_pddr(unsigned gpio)
253{
254#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
255 defined(CONFIG_M5307) || defined(CONFIG_M5407)
256 return MCFSIM_PADDR;
257#elif defined(CONFIG_M5272)
258 if (gpio < 16)
259 return MCFSIM_PADDR;
260 else if (gpio < 32)
261 return MCFSIM_PBDDR;
262 else
263 return MCFSIM_PCDDR;
264#elif defined(CONFIG_M5249)
265 if (gpio < 32)
266 return MCFSIM2_GPIOENABLE;
267 else
268 return MCFSIM2_GPIO1ENABLE;
269#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
270 defined(CONFIG_M527x) || defined(CONFIG_M528x) || defined(CONFIG_M532x)
271 if (gpio < 8)
272 return MCFEPORT_EPDDR;
273#if defined(CONFIG_M528x)
274 else if (gpio < 16)
275 return MCFGPTA_GPTDDR;
276 else if (gpio < 24)
277 return MCFGPTB_GPTDDR;
278 else if (gpio < 32)
279 return MCFQADC_DDRQA;
280 else if (gpio < 40)
281 return MCFQADC_DDRQB;
282#endif
283 else
284 return MCFGPIO_PDDR + mcfgpio_port(gpio - MCFGPIO_SCR_START);
285#else
286 return 0;
287#endif
288}
289
290#endif /* mcfgpio_h */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-21 03:17:00 -0500