1 files changed, 275 insertions, 68 deletions
diff --git a/arch/m68k/include/asm/mcfgpio.h b/arch/m68k/include/asm/mcfgpio.h
index fe468eaa51e0..fa1059f50dfc 100644
--- a/arch/m68k/include/asm/mcfgpio.h
+++ b/arch/m68k/include/asm/mcfgpio.h
@@ -16,82 +16,289 @@
 #ifndef mcfgpio_h
 #define mcfgpio_h
-#include <linux/io.h>
+#ifdef CONFIG_GPIOLIB
 #include <asm-generic/gpio.h>
+#else
+int __mcfgpio_get_value(unsigned gpio);
+void __mcfgpio_set_value(unsigned gpio, int value);
+int __mcfgpio_direction_input(unsigned gpio);
+int __mcfgpio_direction_output(unsigned gpio, int value);
+int __mcfgpio_request(unsigned gpio);
+void __mcfgpio_free(unsigned gpio);
+/* our alternate 'gpiolib' functions */
+static inline int __gpio_get_value(unsigned gpio)
+{
+        if (gpio < MCFGPIO_PIN_MAX)
+                return __mcfgpio_get_value(gpio);
+        else
+                return -EINVAL;
+}
+static inline void __gpio_set_value(unsigned gpio, int value)
+{
+        if (gpio < MCFGPIO_PIN_MAX)
+                __mcfgpio_set_value(gpio, value);
+}
+static inline int __gpio_cansleep(unsigned gpio)
+{
+        if (gpio < MCFGPIO_PIN_MAX)
+                return 0;
+        else
+                return -EINVAL;
+}
+static inline int __gpio_to_irq(unsigned gpio)
+{
+        return -EINVAL;
+}
+static inline int gpio_direction_input(unsigned gpio)
+{
+        if (gpio < MCFGPIO_PIN_MAX)
+                return __mcfgpio_direction_input(gpio);
+        else
+                return -EINVAL;
+}
+static inline int gpio_direction_output(unsigned gpio, int value)
+{
+        if (gpio < MCFGPIO_PIN_MAX)
+                return __mcfgpio_direction_output(gpio, value);
+        else
+                return -EINVAL;
+}
+static inline int gpio_request(unsigned gpio, const char *label)
+{
+        if (gpio < MCFGPIO_PIN_MAX)
+                return __mcfgpio_request(gpio);
+        else
+                return -EINVAL;
+}
+static inline void gpio_free(unsigned gpio)
+{
+        if (gpio < MCFGPIO_PIN_MAX)
+                __mcfgpio_free(gpio);
+}
+#endif /* CONFIG_GPIOLIB */
-struct mcf_gpio_chip {
-        struct gpio_chip gpio_chip;
-        void __iomem *pddr;
-        void __iomem *podr;
-        void __iomem *ppdr;
-        void __iomem *setr;
-        void __iomem *clrr;
-        const u8 *gpio_to_pinmux;
-};
-extern struct mcf_gpio_chip mcf_gpio_chips[];
-extern unsigned int mcf_gpio_chips_size;
-int mcf_gpio_direction_input(struct gpio_chip *, unsigned);
-int mcf_gpio_get_value(struct gpio_chip *, unsigned);
-int mcf_gpio_direction_output(struct gpio_chip *, unsigned, int);
-void mcf_gpio_set_value(struct gpio_chip *, unsigned, int);
-void mcf_gpio_set_value_fast(struct gpio_chip *, unsigned, int);
-int mcf_gpio_request(struct gpio_chip *, unsigned);
-void mcf_gpio_free(struct gpio_chip *, unsigned);
 /*
- *      Define macros to ease the pain of setting up the GPIO tables. There
+ * The Freescale Coldfire family is quite varied in how they implement GPIO.
- *      are two cases we need to deal with here, they cover all currently
+ * Some parts have 8 bit ports, some have 16bit and some have 32bit; some have
- *      available ColdFire GPIO hardware. There are of course minor differences
+ * only one port, others have multiple ports; some have a single data latch
- *      in the layout and number of bits in each ColdFire part, but the macros
+ * for both input and output, others have a separate pin data register to read
- *      take all that in.
+ * input; some require a read-modify-write access to change an output, others
+ * have set and clear registers for some of the outputs; Some have all the
+ * GPIOs in a single control area, others have some GPIOs implemented in
+ * different modules.
 *
- *      Firstly is the conventional GPIO registers where we toggle individual
+ * This implementation attempts accommodate the differences while presenting
- *      bits in a register, preserving the other bits in the register. For
+ * a generic interface that will optimize to as few instructions as possible.
- *      lack of a better term I have called this the slow method.
+ */
+#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
+    defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
+    defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
+    defined(CONFIG_M532x) || defined(CONFIG_M54xx) || \
+    defined(CONFIG_M5441x)
+/* These parts have GPIO organized by 8 bit ports */
+#define MCFGPIO_PORTTYPE                u8
+#define MCFGPIO_PORTSIZE                8
+#define mcfgpio_read(port)              __raw_readb(port)
+#define mcfgpio_write(data, port)       __raw_writeb(data, port)
+#elif defined(CONFIG_M5307) || defined(CONFIG_M5407) || defined(CONFIG_M5272)
+/* These parts have GPIO organized by 16 bit ports */
+#define MCFGPIO_PORTTYPE                u16
+#define MCFGPIO_PORTSIZE                16
+#define mcfgpio_read(port)              __raw_readw(port)
+#define mcfgpio_write(data, port)       __raw_writew(data, port)
+#elif defined(CONFIG_M5249) || defined(CONFIG_M525x)
+/* These parts have GPIO organized by 32 bit ports */
+#define MCFGPIO_PORTTYPE                u32
+#define MCFGPIO_PORTSIZE                32
+#define mcfgpio_read(port)              __raw_readl(port)
+#define mcfgpio_write(data, port)       __raw_writel(data, port)
+#endif
+#define mcfgpio_bit(gpio)               (1 << ((gpio) %  MCFGPIO_PORTSIZE))
+#define mcfgpio_port(gpio)              ((gpio) / MCFGPIO_PORTSIZE)
+#if defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
+    defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
+    defined(CONFIG_M532x) || defined(CONFIG_M5441x)
+/*
+ * These parts have an 'Edge' Port module (external interrupt/GPIO) which uses
+ * read-modify-write to change an output and a GPIO module which has separate
+ * set/clr registers to directly change outputs with a single write access.
+ */
+#if defined(CONFIG_M528x)
+/*
+ * The 528x also has GPIOs in other modules (GPT, QADC) which use
+ * read-modify-write as well as those controlled by the EPORT and GPIO modules.
 */
-#define MCFGPS(mlabel, mbase, mngpio, mpddr, mpodr, mppdr)                  \
+#define MCFGPIO_SCR_START               40
-        {                                                                   \
+#elif defined(CONFIGM5441x)
-                .gpio_chip                      = {                         \
+/* The m5441x EPORT doesn't have its own GPIO port, uses PORT C */
-                        .label                  = #mlabel,                  \
+#define MCFGPIO_SCR_START               0
-                        .request                = mcf_gpio_request,         \
+#else
-                        .free                   = mcf_gpio_free,            \
+#define MCFGPIO_SCR_START               8
-                        .direction_input        = mcf_gpio_direction_input, \
+#endif
-                        .direction_output       = mcf_gpio_direction_output,\
-                        .get                    = mcf_gpio_get_value,       \
-                        .set                    = mcf_gpio_set_value,       \
-                        .base                   = mbase,                    \
-                        .ngpio                  = mngpio,                   \
-                },                                                          \
-                .pddr           = (void __iomem *) mpddr,                   \
-                .podr           = (void __iomem *) mpodr,                   \
-                .ppdr           = (void __iomem *) mppdr,                   \
-        }
+#define MCFGPIO_SETR_PORT(gpio)         (MCFGPIO_SETR + \
+                                        mcfgpio_port(gpio - MCFGPIO_SCR_START))
+#define MCFGPIO_CLRR_PORT(gpio)         (MCFGPIO_CLRR + \
+                                        mcfgpio_port(gpio - MCFGPIO_SCR_START))
+#else
+#define MCFGPIO_SCR_START               MCFGPIO_PIN_MAX
+/* with MCFGPIO_SCR == MCFGPIO_PIN_MAX, these will be optimized away */
+#define MCFGPIO_SETR_PORT(gpio)         0
+#define MCFGPIO_CLRR_PORT(gpio)         0
+#endif
 /*
- *      Secondly is the faster case, where we have set and clear registers
+ * Coldfire specific helper functions
- *      that allow us to set or clear a bit with a single write, not having
- *      to worry about preserving other bits.
 */
-#define MCFGPF(mlabel, mbase, mngpio)                                       \
-        {                                                                   \
-                .gpio_chip                      = {                         \
-                        .label                  = #mlabel,                  \
-                        .request                = mcf_gpio_request,         \
-                        .free                   = mcf_gpio_free,            \
-                        .direction_input        = mcf_gpio_direction_input, \
-                        .direction_output       = mcf_gpio_direction_output,\
-                        .get                    = mcf_gpio_get_value,       \
-                        .set                    = mcf_gpio_set_value_fast,  \
-                        .base                   = mbase,                    \
-                        .ngpio                  = mngpio,                   \
-                },                                                          \
-                .pddr           = (void __iomem *) MCFGPIO_PDDR_##mlabel,   \
-                .podr           = (void __iomem *) MCFGPIO_PODR_##mlabel,   \
-                .ppdr           = (void __iomem *) MCFGPIO_PPDSDR_##mlabel, \
-                .setr           = (void __iomem *) MCFGPIO_PPDSDR_##mlabel, \
-                .clrr           = (void __iomem *) MCFGPIO_PCLRR_##mlabel,  \
-        }
+/* return the port pin data register for a gpio */
+static inline u32 __mcfgpio_ppdr(unsigned gpio)
+{
+#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
+    defined(CONFIG_M5307) || defined(CONFIG_M5407)
+        return MCFSIM_PADAT;
+#elif defined(CONFIG_M5272)
+        if (gpio < 16)
+                return MCFSIM_PADAT;
+        else if (gpio < 32)
+                return MCFSIM_PBDAT;
+        else
+                return MCFSIM_PCDAT;
+#elif defined(CONFIG_M5249) || defined(CONFIG_M525x)
+        if (gpio < 32)
+                return MCFSIM2_GPIOREAD;
+        else
+                return MCFSIM2_GPIO1READ;
+#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
+      defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
+      defined(CONFIG_M532x) || defined(CONFIG_M5441x)
+#if !defined(CONFIG_M5441x)
+        if (gpio < 8)
+                return MCFEPORT_EPPDR;
+#if defined(CONFIG_M528x)
+        else if (gpio < 16)
+                return MCFGPTA_GPTPORT;
+        else if (gpio < 24)
+                return MCFGPTB_GPTPORT;
+        else if (gpio < 32)
+                return MCFQADC_PORTQA;
+        else if (gpio < 40)
+                return MCFQADC_PORTQB;
+#endif /* defined(CONFIG_M528x) */
+        else
+#endif /* !defined(CONFIG_M5441x) */
+                return MCFGPIO_PPDR + mcfgpio_port(gpio - MCFGPIO_SCR_START);
+#else
+        return 0;
 #endif
+}
+/* return the port output data register for a gpio */
+static inline u32 __mcfgpio_podr(unsigned gpio)
+{
+#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
+    defined(CONFIG_M5307) || defined(CONFIG_M5407)
+        return MCFSIM_PADAT;
+#elif defined(CONFIG_M5272)
+        if (gpio < 16)
+                return MCFSIM_PADAT;
+        else if (gpio < 32)
+                return MCFSIM_PBDAT;
+        else
+                return MCFSIM_PCDAT;
+#elif defined(CONFIG_M5249) || defined(CONFIG_M525x)
+        if (gpio < 32)
+                return MCFSIM2_GPIOWRITE;
+        else
+                return MCFSIM2_GPIO1WRITE;
+#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
+      defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
+      defined(CONFIG_M532x) || defined(CONFIG_M5441x)
+#if !defined(CONFIG_M5441x)
+        if (gpio < 8)
+                return MCFEPORT_EPDR;
+#if defined(CONFIG_M528x)
+        else if (gpio < 16)
+                return MCFGPTA_GPTPORT;
+        else if (gpio < 24)
+                return MCFGPTB_GPTPORT;
+        else if (gpio < 32)
+                return MCFQADC_PORTQA;
+        else if (gpio < 40)
+                return MCFQADC_PORTQB;
+#endif /* defined(CONFIG_M528x) */
+        else
+#endif /* !defined(CONFIG_M5441x) */
+                return MCFGPIO_PODR + mcfgpio_port(gpio - MCFGPIO_SCR_START);
+#else
+        return 0;
+#endif
+}
+/* return the port direction data register for a gpio */
+static inline u32 __mcfgpio_pddr(unsigned gpio)
+{
+#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
+    defined(CONFIG_M5307) || defined(CONFIG_M5407)
+        return MCFSIM_PADDR;
+#elif defined(CONFIG_M5272)
+        if (gpio < 16)
+                return MCFSIM_PADDR;
+        else if (gpio < 32)
+                return MCFSIM_PBDDR;
+        else
+                return MCFSIM_PCDDR;
+#elif defined(CONFIG_M5249) || defined(CONFIG_M525x)
+        if (gpio < 32)
+                return MCFSIM2_GPIOENABLE;
+        else
+                return MCFSIM2_GPIO1ENABLE;
+#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
+      defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
+      defined(CONFIG_M532x) || defined(CONFIG_M5441x)
+#if !defined(CONFIG_M5441x)
+        if (gpio < 8)
+                return MCFEPORT_EPDDR;
+#if defined(CONFIG_M528x)
+        else if (gpio < 16)
+                return MCFGPTA_GPTDDR;
+        else if (gpio < 24)
+                return MCFGPTB_GPTDDR;
+        else if (gpio < 32)
+                return MCFQADC_DDRQA;
+        else if (gpio < 40)
+                return MCFQADC_DDRQB;
+#endif /* defined(CONFIG_M528x) */
+        else
+#endif /* !defined(CONFIG_M5441x) */
+                return MCFGPIO_PDDR + mcfgpio_port(gpio - MCFGPIO_SCR_START);
+#else
+        return 0;
+#endif
+}
+#endif /* mcfgpio_h */

diff --git a/arch/m68k/include/asm/mcfgpio.h b/arch/m68k/include/asm/mcfgpio.h index fe468eaa51e0..fa1059f50dfc 100644 --- a/arch/m68k/include/asm/mcfgpio.h +++ b/arch/m68k/include/asm/mcfgpio.h
@@ -16,82 +16,289 @@
16	#ifndef mcfgpio_h	16	#ifndef mcfgpio_h
17	#define mcfgpio_h	17	#define mcfgpio_h
18		18
19	#include <linux/io.h>	19	#ifdef CONFIG_GPIOLIB
20	#include <asm-generic/gpio.h>	20	#include <asm-generic/gpio.h>
		21	#else
		22
		23	int __mcfgpio_get_value(unsigned gpio);
		24	void __mcfgpio_set_value(unsigned gpio, int value);
		25	int __mcfgpio_direction_input(unsigned gpio);
		26	int __mcfgpio_direction_output(unsigned gpio, int value);
		27	int __mcfgpio_request(unsigned gpio);
		28	void __mcfgpio_free(unsigned gpio);
		29
		30	/* our alternate 'gpiolib' functions */
		31	static inline int __gpio_get_value(unsigned gpio)
		32	{
		33	if (gpio < MCFGPIO_PIN_MAX)
		34	return __mcfgpio_get_value(gpio);
		35	else
		36	return -EINVAL;
		37	}
		38
		39	static inline void __gpio_set_value(unsigned gpio, int value)
		40	{
		41	if (gpio < MCFGPIO_PIN_MAX)
		42	__mcfgpio_set_value(gpio, value);
		43	}
		44
		45	static inline int __gpio_cansleep(unsigned gpio)
		46	{
		47	if (gpio < MCFGPIO_PIN_MAX)
		48	return 0;
		49	else
		50	return -EINVAL;
		51	}
		52
		53	static inline int __gpio_to_irq(unsigned gpio)
		54	{
		55	return -EINVAL;
		56	}
		57
		58	static inline int gpio_direction_input(unsigned gpio)
		59	{
		60	if (gpio < MCFGPIO_PIN_MAX)
		61	return __mcfgpio_direction_input(gpio);
		62	else
		63	return -EINVAL;
		64	}
		65
		66	static inline int gpio_direction_output(unsigned gpio, int value)
		67	{
		68	if (gpio < MCFGPIO_PIN_MAX)
		69	return __mcfgpio_direction_output(gpio, value);
		70	else
		71	return -EINVAL;
		72	}
		73
		74	static inline int gpio_request(unsigned gpio, const char *label)
		75	{
		76	if (gpio < MCFGPIO_PIN_MAX)
		77	return __mcfgpio_request(gpio);
		78	else
		79	return -EINVAL;
		80	}
		81
		82	static inline void gpio_free(unsigned gpio)
		83	{
		84	if (gpio < MCFGPIO_PIN_MAX)
		85	__mcfgpio_free(gpio);
		86	}
		87
		88	#endif /* CONFIG_GPIOLIB */
21		89
22	struct mcf_gpio_chip {
23	struct gpio_chip gpio_chip;
24	void __iomem *pddr;
25	void __iomem *podr;
26	void __iomem *ppdr;
27	void __iomem *setr;
28	void __iomem *clrr;
29	const u8 *gpio_to_pinmux;
30	};
31
32	extern struct mcf_gpio_chip mcf_gpio_chips[];
33	extern unsigned int mcf_gpio_chips_size;
34
35	int mcf_gpio_direction_input(struct gpio_chip *, unsigned);
36	int mcf_gpio_get_value(struct gpio_chip *, unsigned);
37	int mcf_gpio_direction_output(struct gpio_chip *, unsigned, int);
38	void mcf_gpio_set_value(struct gpio_chip *, unsigned, int);
39	void mcf_gpio_set_value_fast(struct gpio_chip *, unsigned, int);
40	int mcf_gpio_request(struct gpio_chip *, unsigned);
41	void mcf_gpio_free(struct gpio_chip *, unsigned);
42		90
43	/*	91	/*
44	* Define macros to ease the pain of setting up the GPIO tables. There	92	* The Freescale Coldfire family is quite varied in how they implement GPIO.
45	* are two cases we need to deal with here, they cover all currently	93	* Some parts have 8 bit ports, some have 16bit and some have 32bit; some have
46	* available ColdFire GPIO hardware. There are of course minor differences	94	* only one port, others have multiple ports; some have a single data latch
47	* in the layout and number of bits in each ColdFire part, but the macros	95	* for both input and output, others have a separate pin data register to read
48	* take all that in.	96	* input; some require a read-modify-write access to change an output, others
		97	* have set and clear registers for some of the outputs; Some have all the
		98	* GPIOs in a single control area, others have some GPIOs implemented in
		99	* different modules.
49	*	100	*
50	* Firstly is the conventional GPIO registers where we toggle individual	101	* This implementation attempts accommodate the differences while presenting
51	* bits in a register, preserving the other bits in the register. For	102	* a generic interface that will optimize to as few instructions as possible.
52	* lack of a better term I have called this the slow method.	103	*/
		104	#if defined(CONFIG_M5206) \|\| defined(CONFIG_M5206e) \|\| \
		105	defined(CONFIG_M520x) \|\| defined(CONFIG_M523x) \|\| \
		106	defined(CONFIG_M527x) \|\| defined(CONFIG_M528x) \|\| \
		107	defined(CONFIG_M532x) \|\| defined(CONFIG_M54xx) \|\| \
		108	defined(CONFIG_M5441x)
		109
		110	/* These parts have GPIO organized by 8 bit ports */
		111
		112	#define MCFGPIO_PORTTYPE u8
		113	#define MCFGPIO_PORTSIZE 8
		114	#define mcfgpio_read(port) __raw_readb(port)
		115	#define mcfgpio_write(data, port) __raw_writeb(data, port)
		116
		117	#elif defined(CONFIG_M5307) \|\| defined(CONFIG_M5407) \|\| defined(CONFIG_M5272)
		118
		119	/* These parts have GPIO organized by 16 bit ports */
		120
		121	#define MCFGPIO_PORTTYPE u16
		122	#define MCFGPIO_PORTSIZE 16
		123	#define mcfgpio_read(port) __raw_readw(port)
		124	#define mcfgpio_write(data, port) __raw_writew(data, port)
		125
		126	#elif defined(CONFIG_M5249) \|\| defined(CONFIG_M525x)
		127
		128	/* These parts have GPIO organized by 32 bit ports */
		129
		130	#define MCFGPIO_PORTTYPE u32
		131	#define MCFGPIO_PORTSIZE 32
		132	#define mcfgpio_read(port) __raw_readl(port)
		133	#define mcfgpio_write(data, port) __raw_writel(data, port)
		134
		135	#endif
		136
		137	#define mcfgpio_bit(gpio) (1 << ((gpio) % MCFGPIO_PORTSIZE))
		138	#define mcfgpio_port(gpio) ((gpio) / MCFGPIO_PORTSIZE)
		139
		140	#if defined(CONFIG_M520x) \|\| defined(CONFIG_M523x) \|\| \
		141	defined(CONFIG_M527x) \|\| defined(CONFIG_M528x) \|\| \
		142	defined(CONFIG_M532x) \|\| defined(CONFIG_M5441x)
		143	/*
		144	* These parts have an 'Edge' Port module (external interrupt/GPIO) which uses
		145	* read-modify-write to change an output and a GPIO module which has separate
		146	* set/clr registers to directly change outputs with a single write access.
		147	*/
		148	#if defined(CONFIG_M528x)
		149	/*
		150	* The 528x also has GPIOs in other modules (GPT, QADC) which use
		151	* read-modify-write as well as those controlled by the EPORT and GPIO modules.
53	*/	152	*/
54	#define MCFGPS(mlabel, mbase, mngpio, mpddr, mpodr, mppdr) \	153	#define MCFGPIO_SCR_START 40
55	{ \	154	#elif defined(CONFIGM5441x)
56	.gpio_chip = { \	155	/* The m5441x EPORT doesn't have its own GPIO port, uses PORT C */
57	.label = #mlabel, \	156	#define MCFGPIO_SCR_START 0
58	.request = mcf_gpio_request, \	157	#else
59	.free = mcf_gpio_free, \	158	#define MCFGPIO_SCR_START 8
60	.direction_input = mcf_gpio_direction_input, \	159	#endif
61	.direction_output = mcf_gpio_direction_output,\
62	.get = mcf_gpio_get_value, \
63	.set = mcf_gpio_set_value, \
64	.base = mbase, \
65	.ngpio = mngpio, \
66	}, \
67	.pddr = (void __iomem *) mpddr, \
68	.podr = (void __iomem *) mpodr, \
69	.ppdr = (void __iomem *) mppdr, \
70	}
71		160
		161	#define MCFGPIO_SETR_PORT(gpio) (MCFGPIO_SETR + \
		162	mcfgpio_port(gpio - MCFGPIO_SCR_START))
		163
		164	#define MCFGPIO_CLRR_PORT(gpio) (MCFGPIO_CLRR + \
		165	mcfgpio_port(gpio - MCFGPIO_SCR_START))
		166	#else
		167
		168	#define MCFGPIO_SCR_START MCFGPIO_PIN_MAX
		169	/* with MCFGPIO_SCR == MCFGPIO_PIN_MAX, these will be optimized away */
		170	#define MCFGPIO_SETR_PORT(gpio) 0
		171	#define MCFGPIO_CLRR_PORT(gpio) 0
		172
		173	#endif
72	/*	174	/*
73	* Secondly is the faster case, where we have set and clear registers	175	* Coldfire specific helper functions
74	* that allow us to set or clear a bit with a single write, not having
75	* to worry about preserving other bits.
76	*/	176	*/
77	#define MCFGPF(mlabel, mbase, mngpio) \
78	{ \
79	.gpio_chip = { \
80	.label = #mlabel, \
81	.request = mcf_gpio_request, \
82	.free = mcf_gpio_free, \
83	.direction_input = mcf_gpio_direction_input, \
84	.direction_output = mcf_gpio_direction_output,\
85	.get = mcf_gpio_get_value, \
86	.set = mcf_gpio_set_value_fast, \
87	.base = mbase, \
88	.ngpio = mngpio, \
89	}, \
90	.pddr = (void __iomem *) MCFGPIO_PDDR_##mlabel, \
91	.podr = (void __iomem *) MCFGPIO_PODR_##mlabel, \
92	.ppdr = (void __iomem *) MCFGPIO_PPDSDR_##mlabel, \
93	.setr = (void __iomem *) MCFGPIO_PPDSDR_##mlabel, \
94	.clrr = (void __iomem *) MCFGPIO_PCLRR_##mlabel, \
95	}
96		177
		178	/* return the port pin data register for a gpio */
		179	static inline u32 __mcfgpio_ppdr(unsigned gpio)
		180	{
		181	#if defined(CONFIG_M5206) \|\| defined(CONFIG_M5206e) \|\| \
		182	defined(CONFIG_M5307) \|\| defined(CONFIG_M5407)
		183	return MCFSIM_PADAT;
		184	#elif defined(CONFIG_M5272)
		185	if (gpio < 16)
		186	return MCFSIM_PADAT;
		187	else if (gpio < 32)
		188	return MCFSIM_PBDAT;
		189	else
		190	return MCFSIM_PCDAT;
		191	#elif defined(CONFIG_M5249) \|\| defined(CONFIG_M525x)
		192	if (gpio < 32)
		193	return MCFSIM2_GPIOREAD;
		194	else
		195	return MCFSIM2_GPIO1READ;
		196	#elif defined(CONFIG_M520x) \|\| defined(CONFIG_M523x) \|\| \
		197	defined(CONFIG_M527x) \|\| defined(CONFIG_M528x) \|\| \
		198	defined(CONFIG_M532x) \|\| defined(CONFIG_M5441x)
		199	#if !defined(CONFIG_M5441x)
		200	if (gpio < 8)
		201	return MCFEPORT_EPPDR;
		202	#if defined(CONFIG_M528x)
		203	else if (gpio < 16)
		204	return MCFGPTA_GPTPORT;
		205	else if (gpio < 24)
		206	return MCFGPTB_GPTPORT;
		207	else if (gpio < 32)
		208	return MCFQADC_PORTQA;
		209	else if (gpio < 40)
		210	return MCFQADC_PORTQB;
		211	#endif /* defined(CONFIG_M528x) */
		212	else
		213	#endif /* !defined(CONFIG_M5441x) */
		214	return MCFGPIO_PPDR + mcfgpio_port(gpio - MCFGPIO_SCR_START);
		215	#else
		216	return 0;
97	#endif	217	#endif
		218	}
		219
		220	/* return the port output data register for a gpio */
		221	static inline u32 __mcfgpio_podr(unsigned gpio)
		222	{
		223	#if defined(CONFIG_M5206) \|\| defined(CONFIG_M5206e) \|\| \
		224	defined(CONFIG_M5307) \|\| defined(CONFIG_M5407)
		225	return MCFSIM_PADAT;
		226	#elif defined(CONFIG_M5272)
		227	if (gpio < 16)
		228	return MCFSIM_PADAT;
		229	else if (gpio < 32)
		230	return MCFSIM_PBDAT;
		231	else
		232	return MCFSIM_PCDAT;
		233	#elif defined(CONFIG_M5249) \|\| defined(CONFIG_M525x)
		234	if (gpio < 32)
		235	return MCFSIM2_GPIOWRITE;
		236	else
		237	return MCFSIM2_GPIO1WRITE;
		238	#elif defined(CONFIG_M520x) \|\| defined(CONFIG_M523x) \|\| \
		239	defined(CONFIG_M527x) \|\| defined(CONFIG_M528x) \|\| \
		240	defined(CONFIG_M532x) \|\| defined(CONFIG_M5441x)
		241	#if !defined(CONFIG_M5441x)
		242	if (gpio < 8)
		243	return MCFEPORT_EPDR;
		244	#if defined(CONFIG_M528x)
		245	else if (gpio < 16)
		246	return MCFGPTA_GPTPORT;
		247	else if (gpio < 24)
		248	return MCFGPTB_GPTPORT;
		249	else if (gpio < 32)
		250	return MCFQADC_PORTQA;
		251	else if (gpio < 40)
		252	return MCFQADC_PORTQB;
		253	#endif /* defined(CONFIG_M528x) */
		254	else
		255	#endif /* !defined(CONFIG_M5441x) */
		256	return MCFGPIO_PODR + mcfgpio_port(gpio - MCFGPIO_SCR_START);
		257	#else
		258	return 0;
		259	#endif
		260	}
		261
		262	/* return the port direction data register for a gpio */
		263	static inline u32 __mcfgpio_pddr(unsigned gpio)
		264	{
		265	#if defined(CONFIG_M5206) \|\| defined(CONFIG_M5206e) \|\| \
		266	defined(CONFIG_M5307) \|\| defined(CONFIG_M5407)
		267	return MCFSIM_PADDR;
		268	#elif defined(CONFIG_M5272)
		269	if (gpio < 16)
		270	return MCFSIM_PADDR;
		271	else if (gpio < 32)
		272	return MCFSIM_PBDDR;
		273	else
		274	return MCFSIM_PCDDR;
		275	#elif defined(CONFIG_M5249) \|\| defined(CONFIG_M525x)
		276	if (gpio < 32)
		277	return MCFSIM2_GPIOENABLE;
		278	else
		279	return MCFSIM2_GPIO1ENABLE;
		280	#elif defined(CONFIG_M520x) \|\| defined(CONFIG_M523x) \|\| \
		281	defined(CONFIG_M527x) \|\| defined(CONFIG_M528x) \|\| \
		282	defined(CONFIG_M532x) \|\| defined(CONFIG_M5441x)
		283	#if !defined(CONFIG_M5441x)
		284	if (gpio < 8)
		285	return MCFEPORT_EPDDR;
		286	#if defined(CONFIG_M528x)
		287	else if (gpio < 16)
		288	return MCFGPTA_GPTDDR;
		289	else if (gpio < 24)
		290	return MCFGPTB_GPTDDR;
		291	else if (gpio < 32)
		292	return MCFQADC_DDRQA;
		293	else if (gpio < 40)
		294	return MCFQADC_DDRQB;
		295	#endif /* defined(CONFIG_M528x) */
		296	else
		297	#endif /* !defined(CONFIG_M5441x) */
		298	return MCFGPIO_PDDR + mcfgpio_port(gpio - MCFGPIO_SCR_START);
		299	#else
		300	return 0;
		301	#endif
		302	}
		303
		304	#endif /* mcfgpio_h */