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-rw-r--r--arch/m68k/include/asm/m54xxacr.h7
1 files changed, 3 insertions, 4 deletions
diff --git a/arch/m68k/include/asm/m54xxacr.h b/arch/m68k/include/asm/m54xxacr.h
index 29d4713f796b..16a1835f9b2a 100644
--- a/arch/m68k/include/asm/m54xxacr.h
+++ b/arch/m68k/include/asm/m54xxacr.h
@@ -81,15 +81,14 @@
81#define INSN_CACHE_MODE (ACR_ENABLE+ACR_ANY) 81#define INSN_CACHE_MODE (ACR_ENABLE+ACR_ANY)
82 82
83#define CACHE_INIT (CACR_DCINVA+CACR_BCINVA+CACR_ICINVA) 83#define CACHE_INIT (CACR_DCINVA+CACR_BCINVA+CACR_ICINVA)
84#define CACHE_INVALIDATE (CACHE_MODE+CACR_DCINVA+CACR_BCINVA+CACR_ICINVA) 84#define CACHE_INVALIDATE (CACHE_MODE+CACR_DCINVA+CACR_BCINVA+CACR_ICINVA)
85#define CACHE_INVALIDATEI (CACHE_MODE+CACR_BCINVA+CACR_ICINVA)
86#define CACHE_INVALIDATED (CACHE_MODE+CACR_DCINVA)
85#define ACR0_MODE (0x000f0000+DATA_CACHE_MODE) 87#define ACR0_MODE (0x000f0000+DATA_CACHE_MODE)
86#define ACR1_MODE 0 88#define ACR1_MODE 0
87#define ACR2_MODE (0x000f0000+INSN_CACHE_MODE) 89#define ACR2_MODE (0x000f0000+INSN_CACHE_MODE)
88#define ACR3_MODE 0 90#define ACR3_MODE 0
89 91
90#if ((DATA_CACHE_MODE & ACR_CM) == ACR_CM_WT)
91#define flush_dcache_range(a, l) do { asm("nop"); } while (0)
92#endif
93#if ((DATA_CACHE_MODE & ACR_CM) == ACR_CM_CP) 92#if ((DATA_CACHE_MODE & ACR_CM) == ACR_CM_CP)
94/* Copyback cache mode must push dirty cache lines first */ 93/* Copyback cache mode must push dirty cache lines first */
95#define CACHE_PUSH 94#define CACHE_PUSH