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-rw-r--r--arch/m68k/include/asm/m53xxacr.h8
1 files changed, 7 insertions, 1 deletions
diff --git a/arch/m68k/include/asm/m53xxacr.h b/arch/m68k/include/asm/m53xxacr.h
index 74c81c9b177e..d8b8dd68368f 100644
--- a/arch/m68k/include/asm/m53xxacr.h
+++ b/arch/m68k/include/asm/m53xxacr.h
@@ -53,6 +53,12 @@
53 * CACR is cache inhibited, we use the ACR register to set cacheing 53 * CACR is cache inhibited, we use the ACR register to set cacheing
54 * enabled on the regions we want (eg RAM). 54 * enabled on the regions we want (eg RAM).
55 */ 55 */
56#if defined(CONFIG_CACHE_COPYBACK)
57#define CACHE_TYPE ACR_CM_CB
58#else
59#define CACHE_TYPE ACR_CM_WT
60#endif
61
56#ifdef CONFIG_COLDFIRE_SW_A7 62#ifdef CONFIG_COLDFIRE_SW_A7
57#define CACHE_MODE (CACR_EC + CACR_ESB + CACR_DCM_PRE) 63#define CACHE_MODE (CACR_EC + CACR_ESB + CACR_DCM_PRE)
58#else 64#else
@@ -63,7 +69,7 @@
63 69
64#define ACR0_MODE ((CONFIG_RAMBASE & 0xff000000) + \ 70#define ACR0_MODE ((CONFIG_RAMBASE & 0xff000000) + \
65 (0x000f0000) + \ 71 (0x000f0000) + \
66 (ACR_ENABLE + ACR_ANY + ACR_CM_CB)) 72 (ACR_ENABLE + ACR_ANY + CACHE_TYPE))
67#define ACR1_MODE 0 73#define ACR1_MODE 0
68 74
69/****************************************************************************/ 75/****************************************************************************/