diff options
Diffstat (limited to 'arch/m68k/include/asm/m5307sim.h')
| -rw-r--r-- | arch/m68k/include/asm/m5307sim.h | 136 |
1 files changed, 68 insertions, 68 deletions
diff --git a/arch/m68k/include/asm/m5307sim.h b/arch/m68k/include/asm/m5307sim.h index 3bc3adaa7ee0..5d0bb7ec31f8 100644 --- a/arch/m68k/include/asm/m5307sim.h +++ b/arch/m68k/include/asm/m5307sim.h | |||
| @@ -23,71 +23,71 @@ | |||
| 23 | /* | 23 | /* |
| 24 | * Define the 5307 SIM register set addresses. | 24 | * Define the 5307 SIM register set addresses. |
| 25 | */ | 25 | */ |
| 26 | #define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */ | 26 | #define MCFSIM_RSR (MCF_MBAR + 0x00) /* Reset Status reg */ |
| 27 | #define MCFSIM_SYPCR 0x01 /* System Protection reg (r/w)*/ | 27 | #define MCFSIM_SYPCR (MCF_MBAR + 0x01) /* System Protection */ |
| 28 | #define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */ | 28 | #define MCFSIM_SWIVR (MCF_MBAR + 0x02) /* SW Watchdog intr */ |
| 29 | #define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */ | 29 | #define MCFSIM_SWSR (MCF_MBAR + 0x03) /* SW Watchdog service*/ |
| 30 | #define MCFSIM_PAR 0x04 /* Pin Assignment reg (r/w) */ | 30 | #define MCFSIM_PAR (MCF_MBAR + 0x04) /* Pin Assignment */ |
| 31 | #define MCFSIM_IRQPAR 0x06 /* Interrupt Assignment reg (r/w) */ | 31 | #define MCFSIM_IRQPAR (MCF_MBAR + 0x06) /* Itr Assignment */ |
| 32 | #define MCFSIM_PLLCR 0x08 /* PLL Control Reg*/ | 32 | #define MCFSIM_PLLCR (MCF_MBAR + 0x08) /* PLL Ctrl Reg */ |
| 33 | #define MCFSIM_MPARK 0x0C /* BUS Master Control Reg*/ | 33 | #define MCFSIM_MPARK (MCF_MBAR + 0x0C) /* BUS Master Ctrl */ |
| 34 | #define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */ | 34 | #define MCFSIM_IPR (MCF_MBAR + 0x40) /* Interrupt Pend */ |
| 35 | #define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */ | 35 | #define MCFSIM_IMR (MCF_MBAR + 0x44) /* Interrupt Mask */ |
| 36 | #define MCFSIM_AVR 0x4b /* Autovector Ctrl reg (r/w) */ | 36 | #define MCFSIM_AVR (MCF_MBAR + 0x4b) /* Autovector Ctrl */ |
| 37 | #define MCFSIM_ICR0 0x4c /* Intr Ctrl reg 0 (r/w) */ | 37 | #define MCFSIM_ICR0 (MCF_MBAR + 0x4c) /* Intr Ctrl reg 0 */ |
| 38 | #define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */ | 38 | #define MCFSIM_ICR1 (MCF_MBAR + 0x4d) /* Intr Ctrl reg 1 */ |
| 39 | #define MCFSIM_ICR2 0x4e /* Intr Ctrl reg 2 (r/w) */ | 39 | #define MCFSIM_ICR2 (MCF_MBAR + 0x4e) /* Intr Ctrl reg 2 */ |
| 40 | #define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */ | 40 | #define MCFSIM_ICR3 (MCF_MBAR + 0x4f) /* Intr Ctrl reg 3 */ |
| 41 | #define MCFSIM_ICR4 0x50 /* Intr Ctrl reg 4 (r/w) */ | 41 | #define MCFSIM_ICR4 (MCF_MBAR + 0x50) /* Intr Ctrl reg 4 */ |
| 42 | #define MCFSIM_ICR5 0x51 /* Intr Ctrl reg 5 (r/w) */ | 42 | #define MCFSIM_ICR5 (MCF_MBAR + 0x51) /* Intr Ctrl reg 5 */ |
| 43 | #define MCFSIM_ICR6 0x52 /* Intr Ctrl reg 6 (r/w) */ | 43 | #define MCFSIM_ICR6 (MCF_MBAR + 0x52) /* Intr Ctrl reg 6 */ |
| 44 | #define MCFSIM_ICR7 0x53 /* Intr Ctrl reg 7 (r/w) */ | 44 | #define MCFSIM_ICR7 (MCF_MBAR + 0x53) /* Intr Ctrl reg 7 */ |
| 45 | #define MCFSIM_ICR8 0x54 /* Intr Ctrl reg 8 (r/w) */ | 45 | #define MCFSIM_ICR8 (MCF_MBAR + 0x54) /* Intr Ctrl reg 8 */ |
| 46 | #define MCFSIM_ICR9 0x55 /* Intr Ctrl reg 9 (r/w) */ | 46 | #define MCFSIM_ICR9 (MCF_MBAR + 0x55) /* Intr Ctrl reg 9 */ |
| 47 | #define MCFSIM_ICR10 0x56 /* Intr Ctrl reg 10 (r/w) */ | 47 | #define MCFSIM_ICR10 (MCF_MBAR + 0x56) /* Intr Ctrl reg 10 */ |
| 48 | #define MCFSIM_ICR11 0x57 /* Intr Ctrl reg 11 (r/w) */ | 48 | #define MCFSIM_ICR11 (MCF_MBAR + 0x57) /* Intr Ctrl reg 11 */ |
| 49 | 49 | ||
| 50 | #define MCFSIM_CSAR0 0x80 /* CS 0 Address 0 reg (r/w) */ | 50 | #define MCFSIM_CSAR0 (MCF_MBAR + 0x80) /* CS 0 Address reg */ |
| 51 | #define MCFSIM_CSMR0 0x84 /* CS 0 Mask 0 reg (r/w) */ | 51 | #define MCFSIM_CSMR0 (MCF_MBAR + 0x84) /* CS 0 Mask reg */ |
| 52 | #define MCFSIM_CSCR0 0x8a /* CS 0 Control reg (r/w) */ | 52 | #define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */ |
| 53 | #define MCFSIM_CSAR1 0x8c /* CS 1 Address reg (r/w) */ | 53 | #define MCFSIM_CSAR1 (MCF_MBAR + 0x8c) /* CS 1 Address reg */ |
| 54 | #define MCFSIM_CSMR1 0x90 /* CS 1 Mask reg (r/w) */ | 54 | #define MCFSIM_CSMR1 (MCF_MBAR + 0x90) /* CS 1 Mask reg */ |
| 55 | #define MCFSIM_CSCR1 0x96 /* CS 1 Control reg (r/w) */ | 55 | #define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */ |
| 56 | 56 | ||
| 57 | #ifdef CONFIG_OLDMASK | 57 | #ifdef CONFIG_OLDMASK |
| 58 | #define MCFSIM_CSBAR 0x98 /* CS Base Address reg (r/w) */ | 58 | #define MCFSIM_CSBAR (MCF_MBAR + 0x98) /* CS Base Address */ |
| 59 | #define MCFSIM_CSBAMR 0x9c /* CS Base Mask reg (r/w) */ | 59 | #define MCFSIM_CSBAMR (MCF_MBAR + 0x9c) /* CS Base Mask */ |
| 60 | #define MCFSIM_CSMR2 0x9e /* CS 2 Mask reg (r/w) */ | 60 | #define MCFSIM_CSMR2 (MCF_MBAR + 0x9e) /* CS 2 Mask reg */ |
| 61 | #define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */ | 61 | #define MCFSIM_CSCR2 (MCF_MBAR + 0xa2) /* CS 2 Control reg */ |
| 62 | #define MCFSIM_CSMR3 0xaa /* CS 3 Mask reg (r/w) */ | 62 | #define MCFSIM_CSMR3 (MCF_MBAR + 0xaa) /* CS 3 Mask reg */ |
| 63 | #define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */ | 63 | #define MCFSIM_CSCR3 (MCF_MBAR + 0xae) /* CS 3 Control reg */ |
| 64 | #define MCFSIM_CSMR4 0xb6 /* CS 4 Mask reg (r/w) */ | 64 | #define MCFSIM_CSMR4 (MCF_MBAR + 0xb6) /* CS 4 Mask reg */ |
| 65 | #define MCFSIM_CSCR4 0xba /* CS 4 Control reg (r/w) */ | 65 | #define MCFSIM_CSCR4 (MCF_MBAR + 0xba) /* CS 4 Control reg */ |
| 66 | #define MCFSIM_CSMR5 0xc2 /* CS 5 Mask reg (r/w) */ | 66 | #define MCFSIM_CSMR5 (MCF_MBAR + 0xc2) /* CS 5 Mask reg */ |
| 67 | #define MCFSIM_CSCR5 0xc6 /* CS 5 Control reg (r/w) */ | 67 | #define MCFSIM_CSCR5 (MCF_MBAR + 0xc6) /* CS 5 Control reg */ |
| 68 | #define MCFSIM_CSMR6 0xce /* CS 6 Mask reg (r/w) */ | 68 | #define MCFSIM_CSMR6 (MCF_MBAR + 0xce) /* CS 6 Mask reg */ |
| 69 | #define MCFSIM_CSCR6 0xd2 /* CS 6 Control reg (r/w) */ | 69 | #define MCFSIM_CSCR6 (MCF_MBAR + 0xd2) /* CS 6 Control reg */ |
| 70 | #define MCFSIM_CSMR7 0xda /* CS 7 Mask reg (r/w) */ | 70 | #define MCFSIM_CSMR7 (MCF_MBAR + 0xda) /* CS 7 Mask reg */ |
| 71 | #define MCFSIM_CSCR7 0xde /* CS 7 Control reg (r/w) */ | 71 | #define MCFSIM_CSCR7 (MCF_MBAR + 0xde) /* CS 7 Control reg */ |
| 72 | #else | 72 | #else |
| 73 | #define MCFSIM_CSAR2 0x98 /* CS 2 Address reg (r/w) */ | 73 | #define MCFSIM_CSAR2 (MCF_MBAR + 0x98) /* CS 2 Address reg */ |
| 74 | #define MCFSIM_CSMR2 0x9c /* CS 2 Mask reg (r/w) */ | 74 | #define MCFSIM_CSMR2 (MCF_MBAR + 0x9c) /* CS 2 Mask reg */ |
| 75 | #define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */ | 75 | #define MCFSIM_CSCR2 (MCF_MBAR + 0xa2) /* CS 2 Control reg */ |
| 76 | #define MCFSIM_CSAR3 0xa4 /* CS 3 Address reg (r/w) */ | 76 | #define MCFSIM_CSAR3 (MCF_MBAR + 0xa4) /* CS 3 Address reg */ |
| 77 | #define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */ | 77 | #define MCFSIM_CSMR3 (MCF_MBAR + 0xa8) /* CS 3 Mask reg */ |
| 78 | #define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */ | 78 | #define MCFSIM_CSCR3 (MCF_MBAR + 0xae) /* CS 3 Control reg */ |
| 79 | #define MCFSIM_CSAR4 0xb0 /* CS 4 Address reg (r/w) */ | 79 | #define MCFSIM_CSAR4 (MCF_MBAR + 0xb0) /* CS 4 Address reg */ |
| 80 | #define MCFSIM_CSMR4 0xb4 /* CS 4 Mask reg (r/w) */ | 80 | #define MCFSIM_CSMR4 (MCF_MBAR + 0xb4) /* CS 4 Mask reg */ |
| 81 | #define MCFSIM_CSCR4 0xba /* CS 4 Control reg (r/w) */ | 81 | #define MCFSIM_CSCR4 (MCF_MBAR + 0xba) /* CS 4 Control reg */ |
| 82 | #define MCFSIM_CSAR5 0xbc /* CS 5 Address reg (r/w) */ | 82 | #define MCFSIM_CSAR5 (MCF_MBAR + 0xbc) /* CS 5 Address reg */ |
| 83 | #define MCFSIM_CSMR5 0xc0 /* CS 5 Mask reg (r/w) */ | 83 | #define MCFSIM_CSMR5 (MCF_MBAR + 0xc0) /* CS 5 Mask reg */ |
| 84 | #define MCFSIM_CSCR5 0xc6 /* CS 5 Control reg (r/w) */ | 84 | #define MCFSIM_CSCR5 (MCF_MBAR + 0xc6) /* CS 5 Control reg */ |
| 85 | #define MCFSIM_CSAR6 0xc8 /* CS 6 Address reg (r/w) */ | 85 | #define MCFSIM_CSAR6 (MCF_MBAR + 0xc8) /* CS 6 Address reg */ |
| 86 | #define MCFSIM_CSMR6 0xcc /* CS 6 Mask reg (r/w) */ | 86 | #define MCFSIM_CSMR6 (MCF_MBAR + 0xcc) /* CS 6 Mask reg */ |
| 87 | #define MCFSIM_CSCR6 0xd2 /* CS 6 Control reg (r/w) */ | 87 | #define MCFSIM_CSCR6 (MCF_MBAR + 0xd2) /* CS 6 Control reg */ |
| 88 | #define MCFSIM_CSAR7 0xd4 /* CS 7 Address reg (r/w) */ | 88 | #define MCFSIM_CSAR7 (MCF_MBAR + 0xd4) /* CS 7 Address reg */ |
| 89 | #define MCFSIM_CSMR7 0xd8 /* CS 7 Mask reg (r/w) */ | 89 | #define MCFSIM_CSMR7 (MCF_MBAR + 0xd8) /* CS 7 Mask reg */ |
| 90 | #define MCFSIM_CSCR7 0xde /* CS 7 Control reg (r/w) */ | 90 | #define MCFSIM_CSCR7 (MCF_MBAR + 0xde) /* CS 7 Control reg */ |
| 91 | #endif /* CONFIG_OLDMASK */ | 91 | #endif /* CONFIG_OLDMASK */ |
| 92 | 92 | ||
| 93 | #define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */ | 93 | #define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */ |
| @@ -127,9 +127,9 @@ | |||
| 127 | /* | 127 | /* |
| 128 | * Generic GPIO support | 128 | * Generic GPIO support |
| 129 | */ | 129 | */ |
| 130 | #define MCFGPIO_PIN_MAX 16 | 130 | #define MCFGPIO_PIN_MAX 16 |
| 131 | #define MCFGPIO_IRQ_MAX -1 | 131 | #define MCFGPIO_IRQ_MAX -1 |
| 132 | #define MCFGPIO_IRQ_VECBASE -1 | 132 | #define MCFGPIO_IRQ_VECBASE -1 |
| 133 | 133 | ||
| 134 | 134 | ||
| 135 | /* Definition offset address for CS2-7 -- old mask 5307 */ | 135 | /* Definition offset address for CS2-7 -- old mask 5307 */ |
| @@ -167,9 +167,9 @@ | |||
| 167 | /* | 167 | /* |
| 168 | * Defines for the IRQPAR Register | 168 | * Defines for the IRQPAR Register |
| 169 | */ | 169 | */ |
| 170 | #define IRQ5_LEVEL4 0x80 | 170 | #define IRQ5_LEVEL4 0x80 |
| 171 | #define IRQ3_LEVEL6 0x40 | 171 | #define IRQ3_LEVEL6 0x40 |
| 172 | #define IRQ1_LEVEL2 0x20 | 172 | #define IRQ1_LEVEL2 0x20 |
| 173 | 173 | ||
| 174 | /* | 174 | /* |
| 175 | * Define system peripheral IRQ usage. | 175 | * Define system peripheral IRQ usage. |