diff options
Diffstat (limited to 'arch/m68k/include/asm/m5307sim.h')
-rw-r--r-- | arch/m68k/include/asm/m5307sim.h | 32 |
1 files changed, 14 insertions, 18 deletions
diff --git a/arch/m68k/include/asm/m5307sim.h b/arch/m68k/include/asm/m5307sim.h index 5886728409c0..c6830e5b54ce 100644 --- a/arch/m68k/include/asm/m5307sim.h +++ b/arch/m68k/include/asm/m5307sim.h | |||
@@ -90,8 +90,15 @@ | |||
90 | #define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */ | 90 | #define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */ |
91 | #define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */ | 91 | #define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */ |
92 | 92 | ||
93 | #define MCFSIM_PADDR 0x244 /* Parallel Direction (r/w) */ | 93 | #define MCFSIM_PADDR (MCF_MBAR + 0x244) |
94 | #define MCFSIM_PADAT 0x248 /* Parallel Data (r/w) */ | 94 | #define MCFSIM_PADAT (MCF_MBAR + 0x248) |
95 | |||
96 | /* | ||
97 | * Generic GPIO support | ||
98 | */ | ||
99 | #define MCFGPIO_PIN_MAX 16 | ||
100 | #define MCFGPIO_IRQ_MAX -1 | ||
101 | #define MCFGPIO_IRQ_VECBASE -1 | ||
95 | 102 | ||
96 | 103 | ||
97 | /* Definition offset address for CS2-7 -- old mask 5307 */ | 104 | /* Definition offset address for CS2-7 -- old mask 5307 */ |
@@ -117,22 +124,6 @@ | |||
117 | #define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */ | 124 | #define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */ |
118 | #define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */ | 125 | #define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */ |
119 | 126 | ||
120 | #if defined(CONFIG_M5307) | ||
121 | #define MCFSIM_IMR_MASKALL 0x3fffe /* All SIM intr sources */ | ||
122 | #endif | ||
123 | |||
124 | /* | ||
125 | * Macro to set IMR register. It is 32 bits on the 5307. | ||
126 | */ | ||
127 | #define mcf_getimr() \ | ||
128 | *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) | ||
129 | |||
130 | #define mcf_setimr(imr) \ | ||
131 | *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) = (imr); | ||
132 | |||
133 | #define mcf_getipr() \ | ||
134 | *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IPR)) | ||
135 | |||
136 | 127 | ||
137 | /* | 128 | /* |
138 | * Some symbol defines for the Parallel Port Pin Assignment Register | 129 | * Some symbol defines for the Parallel Port Pin Assignment Register |
@@ -149,6 +140,11 @@ | |||
149 | #define IRQ3_LEVEL6 0x40 | 140 | #define IRQ3_LEVEL6 0x40 |
150 | #define IRQ1_LEVEL2 0x20 | 141 | #define IRQ1_LEVEL2 0x20 |
151 | 142 | ||
143 | /* | ||
144 | * Define system peripheral IRQ usage. | ||
145 | */ | ||
146 | #define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */ | ||
147 | #define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */ | ||
152 | 148 | ||
153 | /* | 149 | /* |
154 | * Define the Cache register flags. | 150 | * Define the Cache register flags. |